Micropower Single-Supply Rail-to-Rail Input/Output Op Amps OP191/OP291/OP491 FEATURES PIN CONFIGURATIONS Single-supply operation: 2.7 V to 12 V NC 1 8 NC OUTA 1 8 +V Wide input voltage range –INA 2 7 +V –INA 2 7 OUTB Rail-to-rail output swing OP191 OP291 +INA 3 6 OUTA +INA 3 6 –INB LWoiwde s bupanpdlyw ciudrtrhe:n 3t :M 3H00z μA/amp –V N4C = NO CONNECT5 NC 00294-001 –V 4 5 +INB 00294-002 Slew rate: 0.5 V/μs Low offset voltage: 700 μV Figure 1. 8-Lead Narrow-Body SOIC Figure 2. 8-Lead Narrow-Body SOIC No phase reversal OUTA 1 14 OUTD OUTA 1 14 OUTD –INA 2 13 –IND APPLICATIONS +INA 3 12 +IND –INA 2 - + + - 13 –IND +INA 3 12 +IND Industrial process control +V 4 OP491 11 –V +V 4 OP491 11 –V Battery-powered instrumentation +INB 5 10 +INC +INB 5 10 +INC –INB 6 9 –INC PTReoelmweceoort mesu smpeupnnslyoic crasot niotnrosl and protection OUTB 7 8 OUTC 00294-003 O–UINTBB 67 - + + - 98 –OIUNTCC 00294-004 Low voltage strain gage amplifiers Figure 3. 14-Lead Narrow-Body SOIC Figure 4. 14-Lead PDIP DAC output amplifiers OUTA 1 14 OUTD –INA 2 13 –IND +INA 3 12 +IND +V 4 OP491 11 –V +INB 5 10 +INC –INB 6 9 –INC OUTB 7 8 OUTC 00294-005 Figure 5. 14-Lead TSSOP GENERAL DESCRIPTION The OP191, OP291, and OP491 are single, dual, and quad The ability to swing rail-to-rail at both the input and output micropower, single-supply, 3 MHz bandwidth amplifiers enables designers to build multistage filters in single-supply featuring rail-to-rail inputs and outputs. All are guaranteed to systems and to maintain high signal-to-noise ratios. operate from a +3 V single supply as well as ±5 V dual supplies. The OP191/OP291/OP491 are specified over the extended Fabricated on Analog Devices CBCMOS process, the OPx91 industrial –40°C to +125°C temperature range. The OP191 family has a unique input stage that allows the input voltage to single and OP291 dual amplifiers are available in 8-lead plastic safely extend 10 V beyond either supply without any phase SOIC surface-mount packages. The OP491 quad is available in a inversion or latch-up. The output voltage swings to within 14-lead PDIP, a narrow 14-lead SOIC package, and a 14-lead millivolts of the supplies and continues to sink or source TSSOP. current all the way to the supplies. Applications for these amplifiers include portable tele- communications equipment, power supply control and protection, and interface for transducers with wide output ranges. Sensors requiring a rail-to-rail input amplifier include Hall effect, piezo electric, and resistive transducers. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©1994–2010 Analog Devices, Inc. All rights reserved.

OP191/OP291/OP491 TABLE OF CONTENTS Features .............................................................................................. 1  Overdrive Recovery ................................................................... 18  Applications ....................................................................................... 1  Applications Information .............................................................. 19  Pin Configurations ........................................................................... 1  Single 3 V Supply, Instrumentation Amplifier ....................... 19  General Description ......................................................................... 1  Single-Supply RTD Amplifier ................................................... 19  Revision History ............................................................................... 2  A 2.5 V Reference from a 3 V Supply ...................................... 20  Specifications ..................................................................................... 3  5 V Only, 12-Bit DAC Swings Rail-to-Rail ............................. 20  Electrical Specifications ............................................................... 3  A High-Side Current Monitor .................................................. 20  Absolute Maximum Ratings ............................................................ 7  A 3 V, Cold Junction Compensated Thermocouple Amplifier ....................................................................................................... 21  Thermal Resistance ...................................................................... 7  Single-Supply, Direct Access Arrangement for Modems ...... 21  ESD Caution .................................................................................. 7  3 V, 50 Hz/60 Hz Active Notch Filter with False Ground ..... 22  Typical Performance Characteristics ............................................. 8  Single-Supply, Half-Wave, and Full-Wave Rectifiers ............. 22  Theory of Operation ...................................................................... 17  Outline Dimensions ....................................................................... 23  Input Overvoltage Protection ................................................... 18  Ordering Guide .......................................................................... 24  Output Voltage Phase Reversal ................................................. 18  REVISION HISTORY 4/10—Rev. D to Rev. E 3/04—Rev. B to Rev. C. Changes to Input Voltage Parameter, Table 4 ............................... 7 Changes to OP291 SOIC Pin Configuration ................................. 1 4/06—Rev. C to Rev. D 11/03—Rev. A to Rev. B. Changes to Noise Performance, Voltage Density, Table 1 ........... 3 Edits to General Description ........................................................... 1 Changes to Noise Performance, Voltage Density, Table 2 ........... 4 Edits to Pin Configuration ............................................................... 1 Changes to Noise Performance, Voltage Density, Table 3 ........... 5 Changes to Ordering Guide ............................................................. 5 Changes to Figure 23 and Figure 24 ............................................. 10 Updated Outline Dimensions ....................................................... 19 Changes to Figure 42 ...................................................................... 13 12/02—Rev. 0 to Rev. A. Changes to Figure 43 ...................................................................... 14 Edits to General Description ........................................................... 1 Changes to Figure 57 ...................................................................... 16 Edits to Pin Configuration ............................................................... 1 Added Figure 58 .............................................................................. 16 Changes to Ordering Guide ............................................................. 5 Changed Reference from Figure 47 to Figure 12 ........................ 17 Edits to Dice Characteristics ............................................................ 5 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 24 Rev. E | Page 2 of 24

OP191/OP291/OP491 SPECIFICATIONS ELECTRICAL SPECIFICATIONS @ V = 3.0 V, V = 0.1 V, V = 1.4 V, T = 25°C, unless otherwise noted. S CM O A Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage OP191G V 80 500 μV OS −40°C ≤ T ≤ +125°C 1 mV A OP291G/OP491G V 80 700 μV OS −40°C ≤ T ≤ +125°C 1.25 mV A Input Bias Current I 30 65 nA B −40°C ≤ T ≤ +125°C 95 nA A Input Offset Current I 0.1 11 nA OS −40°C ≤ T ≤ +125°C 22 nA A Input Voltage Range 0 3 V Common-Mode Rejection Ratio CMRR V = 0 V to 2.9 V 70 90 dB CM −40°C ≤ T ≤ +125°C 65 87 dB A Large Signal Voltage Gain A R = 10 kΩ, V = 0.3 V to 2.7 V 25 70 V/mV VO L O −40°C ≤ T ≤ +125°C 50 V/mV A Offset Voltage Drift ∆V /∆T 1.1 μV/°C OS Bias Current Drift ∆I/∆T 100 pA/°C B Offset Current Drift ∆I /∆T 20 pA/°C OS OUTPUT CHARACTERISTICS Output Voltage High V R = 100 kΩ to GND 2.95 2.99 V OH L −40°C to +125°C 2.90 2.98 V R = 2 kΩ to GND 2.8 2.9 V L −40°C to +125°C 2.70 2.80 V Output Voltage Low V R = 100 kΩ to V+ 4.5 10 mV OL L −40°C to +125°C 35 mV R = 2 kΩ to V+ 40 75 mV L −40°C to +125°C 130 mV Short-Circuit Limit I Sink/source ±8.75 ±13.50 mA SC −40°C to +125°C ±6.0 ±10.5 mA Open-Loop Impedance Z f = 1 MHz, A = 1 200 Ω OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 12 V 80 110 dB S −40°C ≤ T ≤ +125°C 75 110 dB A Supply Current/Amplifier I V = 0 V 200 350 μA SY O −40°C ≤ T ≤ +125°C 330 480 μA A DYNAMIC PERFORMANCE Slew Rate +SR R = 10 kΩ 0.4 V/μs L Slew Rate –SR R = 10 kΩ 0.4 V/μs L Full-Power Bandwidth BW 1% distortion 1.2 kHz P Settling Time t To 0.01% 22 μs S Gain Bandwidth Product GBP 3 MHz Phase Margin θ 45 Degrees O Channel Separation CS f = 1 kHz, R = 10 kΩ 145 dB L NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 2 μV p-p n Voltage Noise Density e f = 1 kHz 30 nV/√Hz n Current Noise Density i 0.8 pA/√Hz n Rev. E | Page 3 of 24

OP191/OP291/OP491 @ V = 5.0 V, V = 0.1 V, V = 1.4 V, T = 25°C, unless otherwise noted. +5 V specifications are guaranteed by +3 V and ±5 V testing. S CM O A Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage OP191 V 80 500 μV OS −40°C ≤ T ≤ +125°C 1.0 mV A OP291/OP491 V 80 700 μV OS −40°C ≤ T ≤ +125°C 1.25 mV A Input Bias Current I 30 65 nA B −40°C ≤ T ≤ +125°C 95 nA A Input Offset Current I 0.1 11 nA OS −40°C ≤ T ≤ +125°C 22 nA A Input Voltage Range 0 5 V Common-Mode Rejection Ratio CMRR V = 0 V to 4.9 V 70 93 dB CM –40°C ≤ T ≤ +125°C 65 90 dB A Large Signal Voltage Gain A R = 10 kΩ, V = 0.3 V to 4.7 V 25 70 V/mV VO L O −40°C ≤ T ≤ +125°C 50 V/mV A Offset Voltage Drift ∆V /∆T −40°C ≤ T ≤ +125°C 1.1 μV/°C OS A Bias Current Drift ∆I/∆T 100 pA/°C B Offset Current Drift ∆I /∆T 20 pA/°C OS OUTPUT CHARACTERISTICS Output Voltage High V R = 100 kΩ to GND 4.95 4.99 V OH L −40°C to +125°C 4.90 4.98 V R = 2 kΩ to GND 4.8 4.85 V L −40°C to +125°C 4.65 4.75 V Output Voltage Low V R = 100 kΩ to V+ 4.5 10 mV OL L −40°C to +125°C 35 mV R = 2 kΩ to V+ 40 75 mV L −40°C to +125°C 155 mV Short-Circuit Limit I Sink/source ±8.75 ±13.5 mA SC −40°C to +125°C ±6.0 ±10.5 mA Open-Loop Impedance Z f = 1 MHz, A = 1 200 Ω OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 12 V 80 110 dB S −40°C ≤ T ≤ +125°C 75 110 dB A Supply Current/Amplifier I V = 0 V 220 400 μA SY O −40°C ≤ T ≤ +125°C 350 500 μA A DYNAMIC PERFORMANCE Slew Rate +SR R = 10 kΩ 0.4 V/μs L Slew Rate –SR R = 10 kΩ 0.4 V/μs L Full-Power Bandwidth BW 1% distortion 1.2 kHz P Settling Time t To 0.01% 22 μs S Gain Bandwidth Product GBP 3 MHz Phase Margin θ 45 Degrees O Channel Separation CS f = 1 kHz, R = 10 kΩ 145 dB L NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 2 μV p-p n Voltage Noise Density e f = 1 kHz 42 nV/√Hz n Current Noise Density i 0.8 pA/√Hz n Rev. E | Page 4 of 24

OP191/OP291/OP491 @ V = ±5.0 V, –4.9 V ≤ V ≤ +4.9 V, T = +25°C, unless otherwise noted. O CM A Table 3. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage OP191 V 80 500 μV OS −40°C ≤ T ≤ +125°C 1 mV A OP291/OP491 V 80 700 μV OS −40°C ≤ T ≤ +125°C 1.25 mV A Input Bias Current I 30 65 nA B −40°C ≤ T ≤ +125°C 95 nA A Input Offset Current I 0.1 11 nA OS −40°C ≤ T ≤ +125°C 22 nA A Input Voltage Range −5 +5 V Common-Mode Rejection Ratio CMRR V = ±5 V 75 100 dB CM −40°C ≤ T ≤ +125°C 67 97 dB A Large Signal Voltage Gain A R = +10 kΩ, V = ±4.7 V 25 70 VO L O −40°C ≤ T ≤ +125°C 50 V/mV A Offset Voltage Drift ∆V /∆T 1.1 μV/°C OS Bias Current Drift ∆I/∆T 100 pA/°C B Offset Current Drift ∆I /∆T 20 pA/°C OS OUTPUT CHARACTERISTICS Output Voltage Swing V R = 100 kΩ to GND ±4.93 ±4.99 V O L −40°C to +125°C ±4.90 ±4.98 V R = 2 kΩ to GND ±4.80 ±4.95 V L –40°C ≤ T ≤ +125°C ±4.65 ±4.75 V A Short-Circuit Limit I Sink/source ±8.75 ±16.00 mA SC −40°C to +125°C ±6 ±13 mA Open-Loop Impedance Z f = 1 MHz, A = 1 200 Ω OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR V = ±5 V 80 110 dB S −40°C ≤ T ≤ +125°C 75 100 dB A Supply Current/Amplifier I V = 0 V 260 420 μA SY O −40°C ≤ T ≤ +125°C 390 550 μA A DYNAMIC PERFORMANCE Slew Rate ±SR R = 10 kΩ 0.5 V/μs L Full-Power Bandwidth BW 1% distortion 1.2 kHz P Settling Time t To 0.01% 22 μs S Gain Bandwidth Product GBP 3 MHz Phase Margin θ 45 Degrees O Channel Separation CS f = 1 kHz 145 dB NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 2 μV p-p n Voltage Noise Density e f = 1 kHz 42 nV/√Hz n Current Noise Density i 0.8 pA/√Hz n Rev. E | Page 5 of 24

OP191/OP291/OP491 5V Vs=±5V 100 RL=2kΩ 90 AV=+1 INPUT VIN=20Vp-p OUTPUT 10 0% 5V 200μs 00294-006 Figure 6. Input and Output with Inputs Overdriven by 5 V Rev. E | Page 6 of 24

OP191/OP291/OP491 ABSOLUTE MAXIMUM RATINGS Table 4. THERMAL RESISTANCE Parameter Rating θ is specified for the worst-case conditions; that is, θ is Supply Voltage 16 V JA JA specified for device in socket for PDIP packages; θ is specified Input Voltage GND to (V + 10 V) JA S for device soldered in circuit board for TSSOP and SOIC Differential Input Voltage 7 V packages. Output Short-Circuit Duration to GND Indefinite Storage Temperature Range Table 5. Thermal Resistance N, R, RU Packages −65°C to +150°C Package Type θJA θJC Unit Operating Temperature Range 8-Lead SOIC (R) 158 43 °C/W OP191G/OP291G/OP491G −40°C to +125°C 14-Lead PDIP (N) 76 33 °C/W Junction Temperature Range 14-Lead SOIC (R) 120 36 °C/W N, R, RU Packages −65°C to +150°C 14-Lead TSSOP (RU) 180 35 °C/W Lead Temperature (Soldering, 60 sec) 300°C Stresses above those listed under Absolute Maximum Ratings ESD CAUTION may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. Rev. E | Page 7 of 24

OP191/OP291/OP491 TYPICAL PERFORMANCE CHARACTERISTICS 180 40 160 VTAS == 235V°C 30 VCM = 3V BASED ON 1200 OP AMPS 140 20 120 T (nA) 10 VCM = 2.9V N TS 100 URRE 0 VS = 3V NI C –10 U 80 S BIA –20 VCM = 0.1V 60 T U –30 P N 40 I –40 200 00294-012 ––5600 VCM = 0V 00294-015 –0.18 –0.10 –0.02 0.06 0.14 0.22 –40 25 85 125 INPUT OFFSET VOLTAGE (mV) TEMPERATURE (°C) Figure 7. OP291 Input Offset Voltage Distribution, VS = 3 V Figure 10. Input Bias Current vs. Temperature, VS = 3 V 120 0 VS = 3V –40°C < TA < +125°C –0.2 100 BASED ON 600 OP AMPS A) –0.4 VCM = 0.1V T (n VS = 3V VCM = 2.9V 80 N –0.6 RE VCM = 3V R S U –0.8 T C NI 60 T U SE –1.0 40 T OFF –1.2 VCM = 0V U P N –1.4 20 I 0 00294-013 ––11..68 00294-016 0 1 2 3 4 5 6 7 –40 25 85 125 INPUT OFFSET VOLTAGE (µV/°C) TEMPERATURE (°C) Figure 8. OP291 Input Offset Voltage Drift Distribution, VS = 3 V Figure 11. Input Offset Current vs. Temperature, VS = 3 V 0 36 VS = 3V VS = 3V 30 –0.02 V) VCM = 0.1V 24 m E ( –0.04 nA) 18 OLTAG –0.06 VCM = 0V RENT ( 162 SET V –0.08 VCM = 3V S CUR 0 F A –6 INPUT OF –0.10 VCM = 2.9V INPUT BI ––1182 –0.12 –24 –0.14 00294-014 ––3360 00294-017 –40 25 85 125 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 TEMPERATURE (°C) INPUT COMMON-MODE VOLTAGE (V) Figure 9. Input Offset Voltage vs. Temperature, VS = 3 V Figure 12. Input Bias Current vs. Input Common-Mode Voltage, VS = 3 V Rev. E | Page 8 of 24

OP191/OP291/OP491 3.00 50 +VO @ RL = 100kΩ 40 VS = 3V TA = 25°C V) 2.95 30 WING ( N (dB) 20 S 2.90 AI 10 E G VOLTAG 2.85 +VO @ RL = 2kΩ D-LOOP –100 UTPUT CLOSE –20 O 2.80 –30 2.75 VS = 3V 00294-018 ––5400 00294-021 –40 25 85 125 10 100 1k 10k 100k 1M 10M TEMPERATURE (°C) FREQUENCY (Hz) Figure 13. Output Voltage Swing vs. Temperature, VS = 3 V Figure 16. Closed-Loop Gain vs. Frequency, VS = 3 V 160 160 140 VTAS==235V°C 140 CVSM =R R3V TA = 25°C 120 s) 120 e N-LOOP GAIN (dB) 168040000 90 HASE SHIFT (Degre CMRR (dB) 106840000 E P OP 20 45 EN 20 P 0 0 O 0 ––4200100 1k F1R0EkQUENCY1(0H0zk) 1M 10M––9405 00294-019 ––4200100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M00294-022 Figure 14. Open-Loop Gain and Phase vs. Frequency, VS = 3 V Figure 17. CMRR vs. Frequency, VS = 3 V 90 1200 VS = 3V RL = 100kΩ, VCM = 2.9V 89 1000 mV) RL = 100kΩ, 88 V/ 800 VCM = 0.1V GAIN ( R (dB) 87 OOP 600 CMR EN-L 400 86 P O 85 2000 VS = 3V, VO = 0.3V/2.7V 00294-020 84–40 25 85 12500294-023 –40 25 85 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Open-Loop Gain vs. Temperature, VS = 3 V Figure 18. CMRR vs. Temperature, VS = 3 V Rev. E | Page 9 of 24

OP191/OP291/OP491 160 0.35 ±PSRR VS = 3V 140 VS = 3V TA = 25°C A) 0.30 120 m R ( 100 FIE 0.25 LI B) 80 MP d +PSRR A PSRR ( 6400 –PSRR RRENT/ 0.20 U C 0.15 20 Y L P 0 P U 0.10 S ––4200 00294-024 0.05 00294-027 100 1k 10k 100k 1M 10M –40 25 85 125 FREQUENCY (Hz) TEMPERATURE (°C) Figure 19. PSRR vs. Frequency, VS = 3 V Figure 22. Supply Current vs. Temperature, VS = +3 V, +5 V, ±5 V 113 3.0 VS = 3V VIN = 2.8V p-p VS = 3V 112 2.5 AV = +1 G (V) RL = 100kΩ N 111 WI 2.0 S R (dB) 110 TPUT 1.5 R U S O P M 109 MU 1.0 XI A M 108 0.5 107 00294-025 0 00294-028 –40 25 85 125 100 1k 10k 100k 1M TEMPERATURE (°C) FREQUENCY (Hz) Figure 20. PSRR vs. Temperature, VS = 3 V Figure 23. Maximum Output Swing vs. Frequency, VS = 3 V 1.6 1k VS = 3V 1.4 Hz) 1.2 +SR nV/ s) TY ( V/µ 1.0 NSI ATE ( 0.8 E DE 100 R S W OI LE 0.6 E N S G A 0.4 T L O –SR V 0.02 00294-026 10 00294-029 –40 25 85 125 10 100 1k 10k TEMPERATURE (°C) FREQUENCY (Hz) Figure 21. Slew Rate vs. Temperature, VS = 3 V Figure 24. Voltage Noise Density, VS = 5 V or ±5 V Rev. E | Page 10 of 24

OP191/OP291/OP491 70 40 60 VTBOASAP S ==A E 25MD5VP °OCSN 600 30 VS = 5V VCM = 5V +IB–IB 20 50 10 S 40 A) UNIT 30 I (nB 0 –10 20 –20 VCM = 0V 10 –IB 0 00294-030 ––3400 +IB 00294-033 –0.50 –0.30 –0.10 0.10 0.30 0.50 –40 25 85 125 INPUT OFFSET VOLTAGE (mV) TEMPERATURE (°C) Figure 25. OP291 Input Offset Voltage Distribution, VS = 5 V Figure 28. Input Bias Current vs. Temperature, VS = 5 V 120 1.6 VS=5V V–4S0 =°C 5 V< TA < +125°C 1.4 100 BASED ON 600 OP AMPS A) 1.2 n T ( 80 EN 1.0 RR VCM=0V S U 0.8 T C NI 60 T U SE 0.6 F F 40 T O 0.4 U P N 0.2 I 20 0 00294-031 –00.2 VCM=5V 00294-034 0 1 2 3 4 5 6 7 –40 25 85 125 INPUT OFFSET VOLTAGE (µV/°C) TEMPERATURE(°C) Figure 26. OP291 Input Offset Voltage Drift Distribution, VS = 5 V Figure 29. Input Offset Current vs. Temperature, VS = 5 V 0.15 36 VS = 5V 30 VS = 5V 24 0.10 A) 18 VCM = 0V T (n 12 N (mV)OS 0.05 S CURRE 06 V 0 BIA –6 T –12 U P –0.05 VCM = 5V IN –18 –24 –0.10 00294-032 ––3360 00294-035 –40 25 85 125 0 1 2 3 4 5 TEMPERATURE (°C) COMMON-MODE INPUT VOLTAGE (V) Figure 27. Input Offset Voltage vs. Temperature, VS = 5 V Figure 30. Input Bias Current vs. Common-Mode Input Voltage, VS = 5 V Rev. E | Page 11 of 24

OP191/OP291/OP491 5.00 50 RL = 100kΩ 40 VS = 5V TA = 25°C V) 4.95 30 WING ( 4.90 N (dB) 20 S AI 10 E G VOLTAG 4.85 RL = 2kΩ D-LOOP –100 PUT 4.80 OSE –20 UT CL O –30 4.75 4.70 VS = 5V 00294-036 ––5400 00294-039 –40 25 85 125 10 100 1k 10k 100k 1M 10M TEMPERATURE (°C) FREQUENCY (Hz) Figure 31. Output Voltage Swing vs. Temperature, VS = 5 V Figure 34. Closed-Loop Gain vs. Frequency, VS = 5 V 160 160 140 VTAS==255V°C 140 CVSM=RR5V TA=25°C 120 s) 120 e N-LOOP GAIN (dB) 168040000 90 HASE SHIFT (Degre CMRR (dB) 106840000 E P OP 20 45 EN 20 P 0 0 O 0 ––4200100 1k F1R0EkQUENCY1(0H0zk) 1M 10M––9405 00294-037 ––4200100 1k F1R0EkQUENCY1(0H0zk) 1M 10M00294-040 Figure 32. Open-Loop Gain and Phase vs. Frequency, VS = 5 V Figure 35. CMRR vs. Frequency, VS = 5V 96 140 VS = 5V 95 VS = 5V 120 RL = 100kΩ, VCM = 5V 94 mV) 100 93 GAIN (V/ 80 R (dB) 9921 OOP 60 CMR 90 EN-L RL = 100kΩ, VCM = 0V 89 P 40 O RL = 2kΩ, VCM = 5V 88 200 RL = 2kΩ, VCM = 0V 00294-038 8876–40 25 85 12500294-041 –40 25 85 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 33. Open-Loop Gain vs. Temperature, VS = 5 V Figure 36. CMRR vs. Temperature, VS = 5 V Rev. E | Page 12 of 24

OP191/OP291/OP491 160 20 ±PSRR 140 TVAS == 255V°C 18 +ISC, VS = ±5V 120 A) 100 NT (m 16 –ISC, VS = ±5V RE 14 R (dB) 6800 +PSRR T CUR 12 +ISC, VS = +3V R UI S C P 2400 –PSRR RT-CIR 10 –ISC, VS = +3V O 8 0 SH ––4200 00294-042 46 00294-045 100 1k 10k 100k 1M 10M –40 25 85 125 FREQUENCY (Hz) TEMPERATURE (°C) Figure 37. PSRR vs. Frequency, VS = 5 V Figure 40. Short-Circuit Current vs. Temperature, VS = +3 V, +5 V, ±5 V 0.6 80 VS = ±5V 70 0.5 60 0.4 V) 50 μ µs) +SR –SR E ( R (V/ 0.3 TAG 40 S OL V 30 0.2 20 10kΩ 1kΩ VO 0.1 A B 0 VS=5V 00294-043 100 VIN = 10V p-p @ 1kH10zkΩ 00294-046 –40 25 85 125 0 500 1000 1500 2000 2500 TEMPERATURE(°C) FREQUENCY (Hz) Figure 38. OP291 Slew Rate vs. Temperature, VS = 5 V Figure 41. Channel Separation, VS = ±5 V 0.50 5.0 0.45 VS = 5V 4.5 VVISN == 54V.8V p-p AV = +1 0.40 V) 4.0 RL = 100kΩ +SR G ( 0.35 N 3.5 –SR WI µs) 0.30 UT S 3.0 SR (V/ 00..2205 M OUTP 22..05 U 0.15 XIM 1.5 A 0.10 M 1.0 0.050 00294-044 0.50 00294-047 –40 25 85 125 100 1k 10k 100k 1M TEMPERATURE (°C) FREQUENCY (Hz) Figure 39. OP491 Slew Rate vs. Temperature, VS = 5 V Figure 42. Maximum Output Swing vs. Frequency, VS = 5 V Rev. E | Page 13 of 24

OP191/OP291/OP491 10 1.6 VIN = 9.8V p-p VS=±5V VS = ±5V 1.4 AV = +1 V) 8 RL = 100kΩ A) 1.2 NG ( T (n VCM=–5V WI EN 1.0 S 6 R PUT CUR 0.8 M OUT 4 FFSET 0.6 XIMU UT O 0.4 A P M 2 N 0.2 I VCM=+5V 00 00294-048 –0.20 00294-051 100 1k 10k 100k 1M –40 25 85 125 FREQUENCY(Hz) TEMPERATURE(°C) Figure 43. Maximum Output Swing vs. Frequency, VS = ±5 V Figure 46. Input Offset Current vs. Temperature, VS = ±5 V 0.15 36 VS=±5V VS = ±5V V) 0.10 24 T VOLTAGE (m 0.05 VCM= –5V CURRENT (nA) 102 FFSE 0 BIAS T O UT –12 INPU–0.05 VCM=+5V INP –24 –0.10 00294-049 –36 00294-052 –40 25 85 125 –5 –4 –3 –2 –1 0 1 2 3 4 5 TEMPERATURE(°C) COMMON-MODE INPUT VOLTAGE (V) Figure 44. Input Offset Voltage vs. Temperature, VS = ±5 V Figure 47. Input Bias Current vs. Common-Mode Voltage, VS = ±5 V 50 5.00 40 VS = ±5V 4.95 RL= 2kΩ +IB 4.90 3200 VCM = +5V –IB G (V) 4.85 N WI 4.80 RL= 2kΩ 10 S I (nA)B 0 LTAGE 4.750 VS = ±5V –10 VO–4.75 –20 UT –4.80 –30 VCM = –5V –IB OUTP–4.85 RL= 2kΩ –4.90 ––4500 +IB 00294-050 ––54..0905 RL= 2kΩ 00294-053 –40 25 85 125 –40 25 85 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 45. Input Bias Current vs. Temperature, VS = ±5 V Figure 48. Output Voltage Swing vs. Temperature, VS = ±5 V Rev. E | Page 14 of 24

OP191/OP291/OP491 70 160 VS = ±5V CMRR 60 TA = 25°C 140 VS = ±5V TA = 25°C 50 120 AIN (dB) 3400 405 Degrees) B) 10800 N-LOOP G 2100 91035 SE SHIFT ( CMRR (d 6400 E A OP 0 180 PH 20 –10 225 0 ––32001k 10k FREQU1E00NkCY (Hz) 1M 10M270 00294-054 ––4200100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M00294-057 Figure 49. Open-Loop Gain and Phase vs. Frequency, VS = ±5 V Figure 52. CMRR vs. Frequency, VS = ±5 V 200 102 VS = ±5V VS = ±5V 180 101 160 100 V) RL= 2kΩ m 140 99 V/ AIN ( 120 dB) 98 LOOP G 10800 CMRR ( 9967 N- PE 65 95 O 40 94 250 RL= 2kΩ 00294-055 9923 00294-058 –40 25 85 125 –40 25 85 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 50. Open-Loop Gain vs. Temperature, VS = ±5 V Figure 53. CMRR vs. Temperature, VS =± 5 V 50 160 ±PSRR 40 VTAS == 2±55°VC 140 VTAS == 2±55°VC 30 120 N (dB) 20 100 GAI 10 B) 80 +PSRR OP 0 R (d 60 O R D-L –10 PS 40 E S –PSRR LO –20 20 C –30 0 ––5400 00294-056 ––4200 00294-059 10 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 51. Closed-Loop Gain vs. Frequency, VS = ±5 V Figure 54. PSRR vs. Frequency, VS = ±5 V Rev. E | Page 15 of 24

OP191/OP291/OP491 115 1k VS = ±5V OP491 Hz) 110 V/ n OP291 Y ( T R (dB) 105 E DENSI 100 R S PS 100 NOI E G A T L 95 O V 90 00294-060 10 00294-078 –40 25 85 125 10 100 1k 10k TEMPERATURE (°C) FREQUENCY (Hz) Figure 55. OP291/OP491 PSRR vs. Temperature, VS = ±5 V Figure 58. Voltage Noise Density, VS = 3 V 0.7 VS=±5V 1.00V 0.6 100 +SR 0.5 90 –SR s) 0.4 µ V/ SR ( 0.3 INPUT 0.2 0.10 00294-061 OUTPUT 01%0 500mV 2.00µs VRSL==13200V00mkΩV –40Figure 56. Slew R2a5TtEeM vPs.E TReAmTpUeRrEa(t°uCr8)e5, VS = ±5 V 125 Figure 59. Large Signal Transient Response, VS = 3 V 00294-063 1k VS = 3V AV = +100 2.00V 100 Ω) 100 90 E ( NC AV = +10 A INPUT D MPE 10 AV = +1 T I U P T U O 1 VS=±5V 0.1 00294-062 OUTPUT 01%0 1.00V 2.00µARsLV==2+0110V0k/0VΩmV 1k 10k FREQUENCY 1(0H0zk) 1M 2M 00294-064 Figure 57. Output Impedance vs. Frequency Figure 60. Large Signal Transient Response, VS = ±5 V Rev. E | Page 16 of 24

OP191/OP291/OP491 THEORY OF OPERATION The OP191/OP291/OP491 are single-supply, micropower Notice that the input stage includes 5 kΩ series resistors and amplifiers featuring rail-to-rail inputs and outputs. To achieve differential diodes, a common practice in bipolar amplifiers to wide input and output ranges, these amplifiers employ unique protect the input transistors from large differential voltages. input and output stages. In Figure 61 , the input stage comprises These diodes turn on whenever the differential voltage exceeds two differential pairs, a PNP pair and an NPN pair. These two approximately 0.6 V. In this condition, current flows between stages do not work in parallel. Instead, only one stage is on for the input pins, limited only by the two 5 kΩ resistors. This any given input signal level. The PNP stage (Transistor Q1 and characteristic is important in circuits where the amplifier may Transistor Q2) is required to ensure that the amplifier remains be operated open-loop, such as a comparator. Evaluate each in the linear region when the input voltage approaches and circuit carefully to make sure that the increase in current does reaches the negative rail. On the other hand, the NPN stage not affect the performance. (Transistor Q5 and Transistor Q6) is needed for input voltages The output stage in OP191 devices uses a PNP and an NPN up to and including the positive rail. transistor, as do most output stages; however, Q32 and Q33, the For the majority of the input common-mode range, the PNP output transistors, are actually connected with their collectors stage is active, as is shown in Figure 12. Notice that the bias to the output pin to achieve the rail-to-rail output swing. As the current switches direction at approximately 1.2 V to 1.3 V output voltage approaches either the positive or negative rail, below the positive rail. At voltages below this, the bias current these transistors begin to saturate. Thus, the final limit on flows out of the OP291, indicating a PNP input stage. Above output voltage is the saturation voltage of these transistors, this voltage, however, the bias current enters the device, which is about 50 mV. The output stage does have inherent gain revealing the NPN stage. The actual mechanism within the arising from the collectors and any external load impedance. amplifier for switching between the input stages comprises Because of this, the open-loop gain of the amplifier is Transistor Q3, Transistor Q4, and Transistor Q7. As the input dependent on the load resistance. common-mode voltage increases, the emitters of Q1 and Q2 follow that voltage plus a diode drop. Eventually, the emitters of Q1 and Q2 are high enough to turn on Q3, which diverts the 8 μA of tail current away from the PNP input stage, turning it off. Instead, the current is mirrored through Q4 and Q7 to activate the NPN input stage. 8µA Q22 Q26 –IN Q32 Q23 Q27 5kΩ Q3 5kΩ Q20 Q30 +IN Q1 Q2 Q5 Q6 Q16 Q17 10pF Q8 Q10 Q12 Q14 Q21 Q31 VOUT Q9 Q11 Q13 Q15 Q24 Q28 Q18 Q19 Q25 Q29 Q33 Q4 Q7 00294-065 Figure 61. Simplified Schematic Rev. E | Page 17 of 24

OP191/OP291/OP491 INPUT OVERVOLTAGE PROTECTION OUTPUT VOLTAGE PHASE REVERSAL As with any semiconductor device, whenever the condition Some operational amplifiers designed for single-supply exists for the input to exceed either supply voltage, check the operation exhibit an output voltage phase reversal when their input overvoltage characteristic. When an overvoltage occurs, inputs are driven beyond their useful common-mode range. the amplifier could be damaged depending on the voltage level Typically, for single-supply bipolar op amps, the negative supply and the magnitude of the fault current. Figure 62 shows the determines the lower limit of their common-mode range. characteristics for the OP191 family. This graph was generated With these devices, external clamping diodes with the anode with the power supplies at ground and a curve tracer connected connected to ground and the cathode to the inputs prevent input signal excursions from exceeding the device’s negative to the input. When the input voltage exceeds either supply by supply (that is, GND), preventing a condition that could cause more than 0.6 V, internal PN junctions energize, allowing the output voltage to change phase. JFET input amplifiers can current to flow from the input to the supplies. As described, the also exhibit phase reversal, and, if so, a series input resistor is OP291/OP491 do have 5 kΩ resistors in series with each input usually required to prevent it. to help limit the current. Calculating the slope of the current vs. voltage in the graph confirms the 5 kΩ resistor. The OP191 is free from reasonable input voltage range IIN restrictions due to its novel input structure. In fact, the input signal can exceed the supply voltage by a significant amount +2mA without causing damage to the device. As shown in Figure 64, the OP191 family can safely handle a 20 V p-p input signal on +1mA ±5 V supplies without exhibiting any sign of output voltage phase reversal or other anomalous behavior. Thus, no external –10V –5V +5V +10V clamping diodes are required. VIN OVERDRIVE RECOVERY The overdrive recovery time of an operational amplifier is the –1mA time required for the output voltage to recover to its linear region from a saturated condition. This recovery time is –2mA 00294-066 iqmuipcokrlyta anftt einr aa plaprlgicea ttrioannssi ewnht eervee tnhte, saumchp laifsi ear cmomuspt arreactoovr.e rT he Figure 62. Input Overvoltage Characteristics circuit shown in Figure 63 was used to evaluate the OPx91 This input current is not inherently damaging to the device as overdrive recovery time. The OPx91 takes approximately 8 μs to long as it is limited to 5 mA or less. For an input of 10 V over recover from positive saturation and approximately 6.5 μs to the supply, the current is limited to 1.8 mA. If the voltage is recover from negative saturation. large enough to cause more than 5 mA of current to flow, then R1 an external series resistor should be added. The size of this 9kΩ 3 + 1/2 resistor is calculated by dividing the maximum overvoltage by VIN OP291 1 VOUT 5 mA and subtracting the internal 5 kΩ resistor. For example, if 10V STEP 2 – R2 R3 tbhee ( i1n0p0u Vt v/5o lmtaAge) c−o 5u lkdΩ re =a c1h5 1k0Ω0 .V T, hthise r eexsitsetrannacl er esshiostuolrd sbheo uld VS = ±5V 10kΩ 10kΩ 00294-068 placed in series with either or both inputs if they are subjected Figure 63. Overdrive Recovery Time Test Circuit to the overvoltages. 5µs 5µs +5V 100 100 90 90 20V pV-IpN 3 +8 V/DIV) V/DIV) 2O–P12/291 1 VOUT V (2.5IN V (2OUT 4 10 10 0% 0% –5V 20mV 20mV TIME (200µs/DIV) TIME (200µs/DIV) 00294-067 Figure 64. Output Voltage Phase Reversal Behavior Rev. E | Page 18 of 24

OP191/OP291/OP491 APPLICATIONS INFORMATION SINGLE 3 V SUPPLY, INSTRUMENTATION SINGLE-SUPPLY RTD AMPLIFIER AMPLIFIER The circuit in Figure 66 uses three op amps of the OP491 to develop a bridge configuration for an RTD amplifier that The OP291 low supply current and low voltage operation operates from a single 5 V supply. The circuit takes advantage of make it ideal for battery-powered applications, such as the the OP491 wide output swing range to generate a high bridge instrumentation amplifier shown in Figure 65. The circuit uses excitation voltage of 3.9 V. In fact, because of the rail-to-rail the classic two op amp instrumentation amplifier topology, with output swing, this circuit works with supplies as low as 4.0 V. four resistors to set the gain. The equation is simply that of a Amplifier A1 servos the bridge to create a constant excitation noninverting amplifier, as shown in Figure 65. The two resistors current in conjunction with the AD589, a 1.235 V precision labeled R1 should be closely matched both to each other and to reference. The op amp maintains the reference voltage across the two resistors labeled R2 to ensure good common-mode the parallel combination of the 6.19 kΩ and 2.55 MΩ resistors, rejection performance. Resistor networks ensure the closest which generate a 200 μA current source. This current splits matching as well as matched drifts for good temperature evenly and flows through both halves of the bridge. Thus, stability. Capacitor C1 is included to limit the bandwidth and, 100 μA flows through the RTD to generate an output voltage therefore, the noise in sensitive applications. The value of this based on its resistance. A 3-wire RTD is used to balance the line capacitor should be adjusted depending on the desired closed- resistance in both 100 Ω legs of the bridge to improve accuracy. loop bandwidth of the instrumentation amplifier. The RC combination creates a pole at a frequency equal to 1/(2π × R1C1). If AC-CMRR is critical, then a matched capacitor to C1 GAIN = 274 200Ω should be included across the second resistor labeled R1. 10 TURNS 5V 26.7kΩ 26.7kΩ 3V A3 1/4 8 100Ω A2 OP491 VOUT + 5 1/2 RTD 1/4 VIN OP291 7 VOUT 2.55MΩ 100Ω OP491 6 4 – 3 1/2 365Ω 365Ω 100kΩ OP291 1 6.19kΩ A1 2 1/4 100kΩ R1 R2 R2 R1 OP491 0.01pF ALL RESISTORS 1% OR BETTER VOUT= (1 + RR 12 ) = VIN 10C01pF 00294-069 AD589 37.4kΩ 00294-070 Figure 65. Single 3 V Supply Instrumentation Amplifier 5V Figure 66. Single-Supply RTD Amplifier Because the OP291 accepts rail-to-rail inputs, the input common-mode range includes both ground and the positive Amplifier A2 and Amplifier A3 are configured in the two op supply of 3 V. Furthermore, the rail-to-rail output range ensures amp instrumentation amplifier topology described in the Single the widest signal range possible and maximizes the dynamic 3 V Supply, Instrumentation Amplifier section. The resistors are range of the system. Also, with its low supply current of chosen to produce a gain of 274, such that each 1°C increase in 300 μA/device, this circuit consumes a quiescent current of temperature results in a 10 mV change in the output voltage, for only 600 μA yet still exhibits a gain bandwidth of 3 MHz. ease of measurement. A 0.01 μF capacitor is included in parallel with the 100 kΩ resistor on Amplifier A3 to filter out any A question may arise about other instrumentation amplifier unwanted noise from this high gain circuit. This particular RC topologies for single-supply applications. For example, a combination creates a pole at 1.6 kHz. variation on this topology adds a fifth resistor between the two inverting inputs of the op amps for gain setting. While that topology works well in dual-supply applications, it is inherently inappropriate for single-supply circuits. The same could be said for the traditional three op amp instrumentation amplifier. In both cases, the circuits simply cannot work in single-supply situations unless a false ground between the supplies is created. Rev. E | Page 19 of 24

OP191/OP291/OP491 A 2.5 V REFERENCE FROM A 3 V SUPPLY The OP291 serves two functions. First, it is required to buffer the high output impedance of the DAC V pin, which is on the In many single-supply applications, the need for a 2.5 V REF order of 10 kΩ. The op amp provides a low impedance output reference often arises. Many commercially available monolithic to drive any following circuitry. Second, the op amp amplifies 2.5 V references require a minimum operating supply voltage of the output signal to provide a rail-to-rail output swing. In this 4 V. The problem is exacerbated when the minimum operating particular case, the gain is set to 4.1 to generate a 5.0 V output system supply voltage is 3 V. The circuit illustrated in Figure 67 when the DAC is at full scale. If other output voltage ranges are is an example of a 2.5 V reference that operates from a single needed, such as 0 V to 4.095 V, the gain can easily be adjusted 3 V supply. The circuit takes advantage of the OP291 rail-to-rail by altering the value of the resistors. input and output voltage ranges to amplify an AD589 1.235 V output to 2.5 V. The OP291 low TCV of 1 μV/°C helps OS A HIGH-SIDE CURRENT MONITOR maintain an output voltage temperature coefficient of less than In the design of power supply control circuits, a great deal of 200 ppm/°C. The circuit overall temperature coefficient is design effort is focused on ensuring a pass transistor’s long- dominated by the temperature coefficient of R2 and R3. Lower term reliability over a wide range of load current conditions. temperature coefficient resistors are recommended. The entire As a result, monitoring and limiting device power dissipation circuit draws less than 420 μA from a 3 V supply at 25°C. is of prime importance in these designs. The circuit illustrated 3V in Figure 69 is an example of a 5 V, single-supply, high-side R1 3V 17.4kΩ current monitor that can be incorporated into the design of a 3 8 voltage regulator with fold-back current limiting or a high 1/2 AD589 OP291 1 2.5VREF current power supply with crowbar protection. This design uses 2 4 RESISTORS = 1%, 100ppm/°C an OP291 rail-to-rail input voltage range to sense the voltage POTENTIOMETER = 10 TURN, 100ppm/°C drop across a 0.1 Ω current shunt. A p-channel MOSFET used 10R0k3Ω 10R02kΩ 5Rk1Ω 00294-071 adsif tfheree fneteidalb iancpku etl evmolteangte i nin tthoe a c cirucrurietn cto. nTvheirst csu trhree nopt ias mthpe n Figure 67. A 2.5 V Reference that Operates on a Single 3 V Supply applied to R2 to generate a voltage that is a linear representation 5 V ONLY, 12-BIT DAC SWINGS RAIL-TO-RAIL of the load current. The transfer equation for the current monitor is given by The OPx91 family is ideal for use with a CMOS DAC to generate a digitally controlled voltage with a wide output range. MonitorOutput=R2×⎜⎛RSENSE ⎟⎞×I Figure 68 shows the DAC8043 used in conjunction with the ⎝ R1 ⎠ L AD589 to generate a voltage output from 0 V to 1.23 V. The For the element values shown, the monitor output transfer DAC is operated in voltage switching mode, where the reference characteristic is 2.5 V/A. is connected to the current output, I , and the output voltage OUT is taken from the VREF pin. This topology is inherently RSENSE IL 0.1Ω noninverting as opposed to the classic current output mode, 5V 5V which is inverting and, therefore, unsuitable for single supply. 5V R1 100Ω 3 8 5V 1/2 OP291 1 8 2 4 17.8kRΩ1 VDD RFB 2 S G 1.23V 3 IOUTGNDDACC8L0K43SR1VRLEDF 1 5V MOOUNTITPOURT 3N1RM6231 D 00294-073 AD589 4 7 6 5 3 8 2.49kΩ 1/2 D OP291 1 VOUT = –––– (5V) DIGITAL 4096 CONTROL 2 4 Figure 69. A High-Side Load Current Monitor R3 R2 R4 232Ω 32.4kΩ 100kΩ 1% 1% 1% 00294-072 Figure 68. 5 V Only, 12-Bit DAC Swings Rail-to-Rail Rev. E | Page 20 of 24

OP191/OP291/OP491 A 3 V, COLD JUNCTION COMPENSATED The transmit signal, TXA, is inverted by A2 and then reinverted THERMOCOUPLE AMPLIFIER by A3 to provide a differential drive to the transformer, where each amplifier supplies half the drive signal. This is needed The OP291 low supply operation makes it ideal for 3 V battery- because of the smaller swings associated with a single supply as powered applications such as the thermocouple amplifier opposed to a dual supply. Amplifier A1 provides some gain for shown in Figure 70. The K-type thermocouple terminates in an the received signal, and it also removes the transmit signal isothermal block where the junction ambient temperature is present at the transformer from the received signal. To do this, continuously monitored using a simple 1N914 diode. The diode the drive signal from A2 is also fed to the noninverting input of corrects the thermal EMF generated in the junctions by feeding A1 to cancel the transmit signal from the transformer. a small voltage, scaled by the 1.5 MΩ and 475 Ω resistors, to the op amp. 390pF To calibrate this circuit, immerse the thermocouple measuring 37.4kΩ junction in a 0°C ice bath and adjust the 500 Ω potentiometer 20kΩ,1% to 0 V out. Next, immerse the thermocouple in a 250°C 0.1μF A1 1/4 13 RXA 14 OP491 temperature bath or oven and adjust the scale adjust 12 potentiometer for an output voltage of 2.50 V. Within this 0.0047μF temperature range, the K-type thermocouple is accurate to 3.3kΩ 20kΩ,1% within ±3°C without linearization. 10 A2 1.235V 1/4 475Ω,1% OP491 8 AD589 10kΩ 3.0V 9 ISOTHERMAL SCALE 37.4kΩ,1% T1 B1NL9O1C4K 7.15k1Ω% 214%.3kΩ 1.33MΩA2D0JkUΩST TXA 0.1μF 20kΩ,1% 750pF 1.5MΩ 24.9kΩ 4.99kΩ 20kΩ,1% 0.033μF 1:1 ALUMEL 1% 1% 1% 8 2 20kΩ,1% AL COLD 500Ω OP1/2291 1 VOUT 5.1V TO 6.2V JUNCTIONS 10TURN 6 A3 ZENER 5 CHROMECLR 11.2mV ZAEDRJUOST 3 4 03VV==300°C0°C O1P/4491 7 475Ω 2.1kΩ 5 KT40H-T.E7YμRPVME/°OCCOUPLE 1% 1% 00294-074 3V OR 5V Figure 70. A 3 V, Cold Junction Compensated Thermocouple Amplifier 4 2 1/4 100kΩ SINGLE-SUPPLY, DIRECT ACCESS ARRANGEMENT 1 OP491 A4 11 3 FOR MODEMS 100kΩ 10μF 0.1μF Ainnte irmfapceo.r Itnan tth beu ciilrdciunigt sbhloocwkn i nin m Foigduerme s7 i1s, tah de itreelcetp ahcocneess l ine 00294-075 Figure 71. Single-Supply, Direct Access Arrangement for Modems arrangement is used to transmit and receive data from the telephone line. Amplifier A1 is the receiving amplifier; The OP491 bandwidth of 3 MHz and rail-to-rail output swings Amplifier A2 and Amplifier A3 are the transmitters. The fourth ensure that it can provide the largest possible drive to the amplifier, A4, generates a pseudo ground halfway between the transformer at the frequency of transmission. supply voltage and ground. This pseudo ground is needed for the ac-coupled bipolar input signals. Rev. E | Page 21 of 24

OP191/OP291/OP491 3 V, 50 HZ/60 HZ ACTIVE NOTCH FILTER WITH The filter section uses a pair of OP491s in a twin-T FALSE GROUND configuration whose frequency selectivity is very sensitive to the relative matching of the capacitors and resistors in To process ac signals in a single-supply system, it is often best the twin-T section. Mylar is the material of choice for the to use a false ground biasing scheme. Figure 72 illustrates a capacitors, and the relative matching of the capacitors and circuit that uses this approach. In this circuit, a false-ground resistors determines the pass band symmetry of the filter. Using circuit biases an active notch filter used to reject 50 Hz/60 Hz 1% resistors and 5% capacitors produces satisfactory results. power line interference in portable patient monitoring equipment. Notch filters are quite commonly used to reject SINGLE-SUPPLY, HALF-WAVE, AND FULL-WAVE power line frequency interference that often obscures low RECTIFIERS frequency physiological signals, such as heart rates, blood An OPx91 device configured as a voltage follower operating on pressure readings, EEGs, and EKGs. This notch filter effectively a single supply can be used as a simple half-wave rectifier in low squelches 60 Hz pickup at a filter Q of 0.75. Substituting frequency (<2 kHz) applications. A full-wave rectifier can be 3.16 kΩ resistors for the 2.67 kΩ resistors in the twin-T section configured with a pair of OP291s, as illustrated in Figure 73. (R1 through R5) configures the active filter to reject 50 Hz The circuit works in the following way. When the input signal is interference. above 0 V, the output of Amplifier A1 follows the input signal. R2 Because the noninverting input of Amplifier A2 is connected to 2.67kΩ the output of A1, op amp loop control forces the inverting input 3V R1 2.67kΩ of the A2 to the same potential. The result is that both terminals 2 11 1Cμ1F 1Cμ2F of R1 are equipotential; that is, no current flows. Because there 1/4 is no current flow in R1, the same condition exists for R2; thus, VIN OP491 1 R3 R4 5 1/4 VOUT the output of the circuit tracks the input signal. When the input 3 4 A1 2.67kΩ 2.67kΩ OP491 7 signal is below 0 V, the output voltage of A1 is forced to 0 V. 6 A2 C3 R5 This condition now forces A2 to operate as an inverting voltage R1060kΩ (1μF 2×μ 2F) 1(2.3.637kkΩΩ ÷ 2) R8 R7 follower because the noninverting terminal of A2 is also at 0 V. 1kΩ 1kΩ The output voltage at VOUTA is then a full-wave rectified version R11 of the input signal. If needed, a buffered, half-wave rectified 100kΩ version of the input signal is available at V B. C5 OUT 3V R1 R2 0.01μF 100kΩ 100kΩ R9 9 R12 1MΩ OP1/4491 8 499Ω 5V 6 C4 10 A3 C11.μ65FV 2V pV-IpN 3 1/28 OP1/2291 7 VOUTAFRUELCLT-IWFIAEDVE 1μF R10 <2kHz OP291 1 5 A2 OUTPUT 1MΩ 00294-076 2 4 A1 VOUTBHALF-WAVE Figure 72. A 3 V Single-Supply, 50 Hz/60 Hz Active Notch Filter RECTIFIED with False Ground OUTPUT 1V 500mV Amplifier A3 is the heart of the false ground bias circuit. VIN (1V/DIV) 100 It buffers the voltage developed by R9 and R10 and is the 90 reference for the active notch filter. Because the OP491 exhibits a rail-to-rail input common-mode range, R9 and R10 VOUTA (0.5V/DIV) are chosen to split the 3 V supply symmetrically. An in-the-loop compensation scheme used around the OP491 allows the op 10 amp to drive C6, a 1 μF capacitor, without oscillation. C6 VOUTB 0% mfreaqinuteanincys ara lnogwe iomf ptheed afinltceer .a c ground over the operating (0.5V/DIV) 500mV 200μs 00294-077 TIME (200μs/DIV) Figure 73. Single-Supply, Half-Wave, and Full-Wave Rectifiers Using an OP291 Rev. E | Page 22 of 24

OP191/OP291/OP491 OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA C(RINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIOARRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure 74. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) [S-Suffix] Dimensions shown in millimeters and (inches) 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 14 8 6.20 (0.2441) 3.80 (0.1496) 1 7 5.80 (0.2283) 1.27 (0.0500) 0.50 (0.0197) BSC 45° 1.75 (0.0689) 0.25 (0.0098) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) PLANE 0.25 (0.0098) 1.27 (0.0500) 0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157) COMPLIANTTO JEDEC STANDARDS MS-012-AB C(RINOEFNPETARRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 060606-A Figure 75. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) [S-Suffix] Dimensions shown in millimeters and (inches) 5.10 5.00 4.90 14 8 4.50 4.40 6.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.00 1M.2A0X 0.20 0.80 0.09 0.75 0.15 8° 0.60 0.05 0.30 SPLEAATNIENG 0° 0.45 COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 061908-A Figure 76. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Rev. E | Page 23 of 24

OP191/OP291/OP491 0.775 (19.69) 0.750 (19.05) 0.735 (18.67) 14 8 0.280 (7.11) 0.250 (6.35) 1 7 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.110 (2.79) SEATING PLANE 0.014 (0.36) PLANE 0.010 (0.25) 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.050 (1.27) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINEOFRPEANRREERENN LCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 070606-A Figure 77. 14-Lead Plastic Dual In-Line Package [PDIP] (N-14) [P-Suffix] Dimensions shown in inches and (millimeters) ORDERING GUIDE Model1 Temperature Range Package Description Package Option OP191GS −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP191GS-REEL −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP191GS-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP191GSZ −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP191GSZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP191GSZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP291GS −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP291GS-REEL −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP291GS-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP291GSZ −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP291GSZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP291GSZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP491GP −40°C to +125°C 14-Lead PDIP N-14 [P-Suffix] OP491GPZ −40°C to +125°C 14-Lead PDIP N-14 [P-Suffix] OP491GRU-REEL −40°C to +125°C 14-Lead TSSOP RU-14 OP491GRUZ-REEL −40°C to +125°C 14-Lead TSSOP RU-14 OP491GS −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix] OP491GS-REEL −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix] OP491GS-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix] OP491GSZ −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix] OP491GSZ-REEL −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix] OP491GSZ-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix] 1 Z = RoHS Compliant Part. ©1994–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00294-0-4/10(E) Rev. E | Page 24 of 24

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: OP491GSZ OP191GSZ-REEL7 OP491GSZ-REEL OP491GRUZ-REEL OP191GSZ OP291GSZ-REEL OP491GSZ-REEL7 OP291GSZ OP291GS OP491GPZ OP491GS-REEL7 OP291GS-REEL7 OP191GSZ-REEL OP291GSZ-REEL7