Dual 9 MHz Precision Operational Amplifier Data Sheet OP285 FEATURES PIN CONNECTION Low offset voltage: 250 μV OUT A 1 8 V+ Low noise: 6 nV/√Hz –IN A 2 OP285 7 OUT B Low distortion: 0.0006% +IN A 3 (Not to Scale) 6 –IN B High slew rate: 22 V/μs V– 4 5 +IN B Wide bandwidth: 9 MHz 8-Lead Narrow Body SOIC Low supply current: 5 mA Low offset current: 2 nA Unity-gain stable 8-lead SOIC_N package APPLICATIONS High performance audio Active filters Fast amplifiers Integrators GENERAL DESCRIPTION The OP285 is a precision high-speed amplifier featuring the The combination of low noise, speed and accuracy can be used Butler Amplifier front-end. This new front-end design to build high speed instrumentation systems. Circuits such as combines the accuracy and low noise performance of bipolar instrumentation amplifiers, ramp generators, bi-quad filters and transistors with the speed of JFETs. This yields an amplifier dc-coupled audio systems are all practical with the OP285. For with high slew rates, low offset and good noise performance at applications that require long term stability, the OP285 has a low supply currents. Bias currents are also low compared to guaranteed maximum long term drift specification. bipolar designs. The OP285 is specified over the XIND—extended industrial— The OP285 offers the slew rate and low power of a JFET (−40°C to +85°C) temperature range. The OP285 is available in amplifier combined with the precision, low noise and low drift an 8-lead SOIC_N surface mount package. of a bipolar amplifier. Input offset voltage is laser-trimmed and guaranteed less than 250 μV. This makes the OP285 useful in dc-coupled or summing applications without the need for special selections or the added noise of additional offset adjustment circuitry. Slew rates of 22 V/μs and a bandwidth of 9 MHz make the OP285 one of the most accurate medium speed amplifiers available. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©1992–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

OP285–SPECIFICATIONS (@ Vs = (cid:2)15.0 V, TA = 25(cid:3)C, unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V 35 250 µV OS V –40°C ≤ T ≤ +85°C 600 µV OS A Input Bias Current I V = 0 V 100 350 nA B CM I V = 0 V, –40°C ≤ T ≤ +85°C 400 nA B CM A Input Offset Current I V = 0 V 2 ±50 nA OS CM I V = 0 V, –40°C ≤ T ≤ +85°C 2 ±100 nA OS CM A Input Voltage Range V –10.5 10.5 V CM Common-Mode Rejection CMRR V = ±10.5 V, CM –40°C ≤ T ≤ +85°C 80 106 dB A Large-Signal Voltage Gain A R = 2 kΩ 250 V/mV VO L A R = 2 kΩ, –40°C ≤ T ≤ +85°C 175 V/mV VO L A A R = 600 Ω 200 V/mV VO L Common-Mode Input Capacitance 7.5 pF Differential Input Capacitance 3.7 pF Long-Term Offset Voltage ∆V Note 1 300 µV OS Offset Voltage Drift ∆V /∆T 1 µV/°C OS OUTPUT CHARACTERISTICS Output Voltage Swing V RL = 2 kΩ –13.5 +13.9 +13.5 V O V RL = 2 kΩ, –40°C ≤ T ≤ +85°C –13 +13.9 +13 V O A RL = 600 Ω, V = ±18 V –16/+14 V S POWER SUPPLY Power Supply Rejection Ratio PSRR V = ±4.5 V to ±18 V 85 111 dB S PSRR V = ±4.5 V to ±18 V, S –40°C ≤ T ≤ +85°C 80 dB A Supply Current ISY VS = ±4.5 V to ± 18 V, VO = 0 V, –40°C ≤ T ≤ +85°C 4 5 mA A ISY VS = ±22 V, VO = 0 V, –40°C ≤ T ≤ +85°C 5.5 mA A Supply Voltage Range VS ±4.5 ±22 V DYNAMIC PERFORMANCE Slew Rate SR R = 2 kΩ 15 22 V/µs L Gain Bandwidth Product GBP 9 MHz Phase Margin (cid:1)o 62 Degrees Settling Time t To 0.1%, 10 V Step 625 ns s t To 0.01%, 10 V Step 750 ns s Distortion A = 1, V = 8.5 V p-p, V OUT f = 1 kHz, R = 2 kΩ –104 dB L Voltage Noise Density e f = 30 Hz 7 nV/√Hz n e f = 1 kHz 6 nV/√Hz n Current Noise Density i f = 1 kHz 0.9 pA/√Hz n Headroom THD + Noise ≤ 0.01%, R = 2 kΩ, V = ±18 V >12.9 dBu L S NOTE 1Long-term offset voltage is guaranteed by a 1,000 hour life test performed on three independent wafer lots at 125°C, with an LTPD of 1.3. Specifications subject to change without notice. –2– REV. C

OP285 ABSOLUTE MAXIMUM RATINGS1 Package Type (cid:4) 4 (cid:4) Unit Supp ly Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V JA JC Inpu t Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V 8- L e a d SOIC _N 158 43 °C/W Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . ±7.5 V Outp ut Short-Circuit Duration to Gnd3 . . . . . . . . . Indefinite NOTES 1 Absolute Maximum Ratings apply to packaged parts, unless otherwise noted. Stora ge Temperature Range 2For supply voltages less than ±7.5 V, the absolute maximum input voltage is SOIC _N P ackage . . . . . . . . . . . . . . . . . . . –65°C to +150°C equal to the supply voltage. Operating Temperature Range 3Shorts to either supply may destroy the device. See data sheet for full details. OP 285G . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C 4 (cid:1)JA is specified for the worst case conditions, i.e., (cid:1)JA is specified for device Junction Temperature Range soldered in circuit board for SOIC package. SOIC _N Package . . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 60 Sec) . . . . . . . . 300°C ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. REV. C –3–

OP285 2205 TRAL == 225k(cid:3)(cid:6)C 1500 VVSO == (cid:2)(cid:2)1150VV 30 VRSL == (cid:2)2k1(cid:6)5V – V 15 +VOM 1250 25 PUT VOLTAGE SWING –11–00505 EN-LOOP GAIN – V/MV1750500000 RL =+ 6G0A0I(cid:6)N +RGL A= I–R2NGLk A(cid:6)= I2Nk(cid:6) (cid:1)SLEW RATE – V/s 121005 +SR –SR UT–15 –VOM OP O 250 –GAIN 5 –20 RL = 600(cid:6) –250 (cid:2)5 (cid:2)10 (cid:2)15 (cid:2)20 (cid:2)25 0 0 –50 –25 0 25 50 75 100 0 0.2 0.4 0.6 0.8 1.0 SUPPLY VOLTAGE – V TEMPERATURE – C DIFFERENTIAL INPUT VOLTAGE – V TPC 1. Output Voltage Swing vs. TPC 2. Open-Loop Gain TPC 3. Slew Rate vs. Differential Supply Voltage vs. Temperature Input Voltage 50 45 VVRRSSLL ==== (cid:2)(cid:2)22kk11(cid:6)(cid:6)55VV 5400 VTAS == +(cid:2)2155(cid:3)VC 60 VTAS == 2(cid:2)51(cid:3)5CV –SR AVCL = +100 50 B (cid:1)SLEW RATE – V/s 334500 +SR SED-LOOP GAIN – d 1230000 AAVVCCLL == + +110 (cid:6)IMPEDANCE – 324000 AVCL = +10A0VCL = +A1V0CL = +1 O L–10 25 C 10 –20 20 –30 0 –50 –25 0 25 50 75 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M TEMPERATURE – (cid:3)C FREQUENCY – Hz FREQUENCY – Hz TPC 4. Slew Rate vs. Temperature TPC 5. Closed-Loop Gain TPC 6. Closed-Loop Output Imped vs. Frequency ance vs. Frequency 120 120 100 DE REJECTION – dB 1806000 VTAS == 2(cid:2)51(cid:3)5CV LY REJECTION – dB1680000 VTAS == 2(cid:2)51(cid:3)5CV –PSRR +PSRR OOP G– dB MIN 46820000 PHASEGAIN VTRASL === 2(cid:2)25k1(cid:3)05CNV = 58(cid:3) 19403055 E – Degrees MMON MO 4200 WER SUPP 40 OPEN-L–200 128205PHAS CO PO 20 –40 270 0100 1k 10k 100k 1M 10M 010 100 1k 10k 100k 1M –601k 10k 100k 1M 10M 100M FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz TPC 7. Common-Mode Rejection TPC 8. Power Supply Rejection TPC 9. Open-Loop Gain, Phase vs. Frequency vs. Frequency vs. Frequency –4– REV. C

Typical Performance Characteristics–OP285 11 65 100 16 AIN BANDWIDTH PRODUCT – MHz1908 GBW øM 556050PHASE MARGIN – Degrees OVERSHOOT – % 3264578900000000 ANE V CG L A =T I+V1EVVR ISLEN == DAP= G 2O V1 1k CES0 5 L0I VT=m I+VV1E p E-pDGE MAXIMUM OUTPUT SWING – Volts1110426284 –VOM +VOM TVAS == 251(cid:3)5CV G 10 7 40 0 0 –50 –25 0 25 50 75 100 0 100 200 300 400 500 100 1k 10k TEMPERATURE – (cid:3)C LOAD CAPACITANCE – pF LOAD RESISTANCE – (cid:6) TPC 10. Gain Bandwidth Product, TPC 11. Small-Signal Overshoot vs.| TPC 12. Maximum Output Voltage Phase Margin vs. Temperature Load Capacitance vs. Load Resistance 30 5.0 120 A110 VS = 15V m UT SWING – V 2205 ENT – mA 4.5 TA = +85(cid:3)C T CURRENT – 1890000 SINK OUTP 15 CURR 4.0 TA = +25(cid:3)C UTPU 6700 MAXIMUM 105 VRTAASVL C===L 22 =51k (cid:3)5(cid:6)+CV1 SUPPLY 3.5 TA = –40(cid:3)C ABSOLUTE O 534000 SOURCE 0 3.0 20 1k 10k 100k 1M 10M 0 5 10 15 25 –50 –25 0 25 50 75 100 FREQUENCY – Hz SUPPLY VOLTAGE – V TEMPERATURE – (cid:3)C TPC 13. Maximum Output Swing TPC 14. Supply Current vs. TPC 15. Short Circuit Current vs. vs. Frequency Supply Voltage Temperature 300 5 250 RRENT – nA 225000 VS = 15V SITY – pA/Hz 34 VTAS == 251(cid:3)5CV S 125000 4–0420 (cid:3)OC P ATMAP S +85(cid:3)C INPUT BIAS CU 11055000 RENT NOISE DEN 21 UNIT 15000 R U C 0 0 –50 –25 0 25 50 75 100 10 100 1k 100k 0 1 2 3 4 5 6 7 8 9 10 TEMPERATURE – (cid:3)C FREQUENCY – Hz TC VOS – (cid:1)V/ (cid:3)C TPC 16. Input Bias Current vs. TPC 17. Current Noise Density vs. TPC 18. tC VOS Distribution Temperature Frequency REV. C –5–

OP285 250 10 50 TA= 25(cid:3)C 8 TA = 25(cid:3)C 200 402 (cid:7) OP AMPS 6 +0.1% +0.01% 45 –SR VS = 15V 4 S UNITS150 P SIZE – V 20 (cid:1)RATE – V/ 3450 100 TE –2 W S –4 SLE 30 +SR 50 –6 –0.1% –0.01% 25 –8 0 –10 20 –250–200–150–100–50 0 50 100150200250 0 100 200 300 400 500 600 700 800 900 0 100 200 300 400 500 INPUT OFFSET – (cid:1)V SETTLING TIME – ns CAPACITIVE LOAD – pF TPC 19. Input Offset (V ) TPC 20. Settling Time vs. Step Size TPC 21. Slew Rate vs. OS Distribution Capacitive Load 100 100 100 90 90 90 10 10 10 0% 0% 0% 5V 200nS 5V 200nS 50mV 100nS TPC 22. Negative Slew Rate TPC 23. Positive Slew Rate TPC 24. Small Signal Response RL =2 kΩ, VS = ±15 V, AV = +1 RL = 2 kΩ, VS = ±15 V, AV = +1 RL =2 kΩ, VS = ±15 V, AV = +1 CH A: 80.0 (cid:1)V FS 10.0 (cid:1)V/DIV MKR: 6.23 (cid:1)V/ Hz 0 Hz 2.5 KHz MKR: 1 000 Hz BW: 15.0 MHz TPC 25. OP285 Voltage Noise Density vs. Frequency V = ±15 V, A = 1000 S V –6– REV. C

OP285 APPLICATIONS applications, the fix is a simple one and is illustrated in Figure 3. Short-Circuit Protection A 3.92 kΩ resistor in series with the noninverting input of the The OP285 has been designed with inherent short-circuit OP285 cures the problem. protection to ground. An internal 30 Ω resistor, in series with the output, limits the output current at room temperature to RFB* I + = 40 mA and I - = –90 mA, typically, with ±15 V supplies. SC SC However, shorts to either supply may destroy the device when – VOUT excessive voltages or current are applied. If it is possible for a VIN + upusetr c tuor rsehnotr to fa nth oeu OtpPu2t8 t5o sah souupldp lby,e fdoer ssiagfne- loimpeirteadti otno ,± th30e omuAt-, 3.9R2Sk(cid:6) 2RkL(cid:6) as shown in Figure 1. *RFB IS OPTIONAL RFB Figure 3. Output Voltage Phase Reversal Fix FEEDBACK Overload or Overdrive Recovery – 33R2X(cid:6) Overload or overdrive recovery time of an operational amplifier A1 is the time required for the output voltage to recover to a rated + VOUT output voltage from a saturated condition. This recovery time is A1 = 1/2 OP285 important in applications where the amplifier must recover quickly Figure 1. Recommended Output Short-Circuit Protection after a large abnormal transient event. The circuit shown in Figure 4 was used to evaluate the OP285’s overload recovery time. The ITnhpeu tm Oaxviemr uCmur irnepnut tP drioffteercetniotnial voltage that can be applied OanPd2 a8p5p traokxeims aapteplyro 1x.i5m µast etloy r1e.c2o vµesr t too rVecove r= t –o1 V0O VU.T = +10 V to the OP285 is determined by a pair of internal Zener diodes OUT connected across the inputs. They limit the maximum differ- R1 R2 ential input voltage to ±7.5 V. This is to prevent emitter-base 1k(cid:6) 10k(cid:6) junction breakdown from occurring in the input stage of the 2 OP285 when very large differential voltages are applied. How- 1 VOUT A1 ever, in order to preserve the OP285’s low input noise 3 vuoseltda gteo, liinmteitr nthael rceusrisretannt cien itnh ese crliaems wp idthio tdhees .i nIpnu stms awlel-rsei gnnoatl 4VV IpN-p 90R9S(cid:6) 2R.L43k(cid:6) applications, this is not an issue; however, in industrial appli- @100 Hz A1 = 1/2 OP285 cations, where large differential voltages can be inadvertently applied to the device, large transient currents can be made to Figure 4. Overload Recovery Time Test Circuit flow through these diodes. The diodes have been designed to carry a current of ±8 mA; and, in applications where the Driving the Analog Input of an A/D Converter OP285’s differential voltage were to exceed ±7.5 V, the resis- Settling characteristics of operational amplifiers also include the tor values shown in Figure 2 safely limit the diode current to amplifier’s ability to recover, i.e., settle, from a transient output ±8 mA. current load condition. When driving the input of an A/D converter, especially successive-approximation converters, the amplifier must maintain a constant output voltage under 909(cid:6) dynamically changing load current conditions. In these types of – converters, the comparison point is usually diode clamped, but A1 it may deviate several hundred millivolts resulting in high 909(cid:6) frequency modulation of the A/D input current. Amplifiers that + exhibit high closed-loop output impedances and/or low unity-gain A1 = 1/2 crossover frequencies recover very slowly from output load current transients. This slow recovery leads to linearity errors or missing codes because of errors in the instantaneous input voltage. Figure 2. OP285 Input Over Current Protection Therefore, the amplifier chosen for this type of application should Output Voltage Phase Reversal exhibit low output impedance and high unity-gain bandwidth so Since the OP285’s input stage combines bipolar transistors that its output has had a chance to settle to its nominal value for low noise and p-channel JFETs for high speed performance, before the converter makes its comparison. the output voltage of the OP285 may exhibit phase reversal if The circuit in Figure 5 illustrates a settling measurement circuit either of its inputs exceed its negative common-mode input for evaluating the recovery time of an amplifier from an output voltage. This might occur in very severe industrial applications load current transient. The amplifier is configured as a follower where a sensor or system fault might apply very large voltages on with a very high speed current generator connected to its output. the inputs of the OP285. Even though the input voltage range of In this test, a 1 mA transient current was used. As shown in the OP285 is ±10.5 V, an input voltage of approximately –13.5 V Figure 6, the OP285 exhibits an extremely fast recovery time of will cause output voltage phase reversal. In inverting amplifier 139 ns to 0.01%. Because of its high gain-bandwidth product, configurations, the OP285’s internal 7.5 V input clamping high open-loop gain, and low output impedance, the OP285 is diodes will prevent phase reversal; however, they will not prevent ideally suited to drive high speed A/D converters. this effect from occurring in noninverting applications. For these REV. C –7–

OP285 +15V Measuring Settling Time 0.1(cid:1)F The design of OP285 combines high slew rate and wide gain- 3 + 1/82 1 bfoarn 8d-w ainddth 1 p2-rboidt uacptp tloic aptrioondsu.c Te hae f taesstt- sceirtctluinitg d (etssi g<n el dµ st)o ammepalsiufireer OP285 + 7A13 PLUG-IN 2 – 0.1(cid:1)F the settling time of the OP285 is shown in Figure 7. This test 4 method has advantages over false-sum node techniques in that * –15V the actual output of the amplifier is measured, instead of an – 7A13 PLUG-IN error voltage at the sum node. Common-mode settling effects 300pF 1k(cid:6) are exercised in this circuit in addition to the slew rate and bandwidth effects measured by the false-sum-node method. Of TTL 15V (cid:8)IOUT |V1RkE(cid:6)F| course, a reasonably flat-top pulse is required as the stimulus. INPUT 1.5k(cid:6) 2N3904 The output waveform of the OP285 under test is clamped by Schottky diodes and buffered by the JFET source follower. 1N4148 2N2907 10(cid:1)F 1k(cid:6) + The signal is amplified by a factor of ten by the OP260 and 1.8k(cid:6) then Schottky-clamped at the output to prevent overloading 15V 220(cid:6) the oscilloscope’s input amplifier. The OP41 is configured as a fast integrator which provides overall dc offset nulling. 0.47(cid:1)F 0.1(cid:1)F High Speed Operation 0.01(cid:1)F As with most high speed amplifiers, care should be taken with *NOTE DECOUPLE CLOSE VREF supply decoupling, lead dress, and component placement. Rec- TOGETHER ON GROUND PLAN (–1V) ommended circuit configurations for inverting and noninverting WITH SHORT LEAD LENGTHS. applications are shown in Figures 8 and Figure 9. Figure 5. Transient Output Load Current Test Fixture +15V 10(cid:1)F + A1 1,2 V T 138.9NS 0.1(cid:1)F 100 TTL CTRL 90 (5V/ DIV) 2 8 – 1/2 1 VOUT 10V OP285 VIN 3 (2MV/V DOIUVT) 100% + 4 1R5Lk(cid:6) 5V 2MV 50NS 0.1(cid:1)F 10(cid:1)F Figure 6. OP285’s Output Load Current Recovery Time –15V Figure 8. Unity Gain Follower 16–20V – + +15V 1k(cid:6) OUTPUT 0.1(cid:1)F (TO SCOPE) V+ RL D3 D4 1k(cid:6) DUT 2N4416 1/2 OP260AJ V– D1 D2 1(cid:1)F 0.1(cid:1)F RF 2k(cid:6) 10k(cid:6) + – RG IC2 16–20V 222(cid:6) 10k(cid:6) (cid:2)5V 2N2222A 750(cid:6) 1N4148 15k(cid:6) SCHOTTKY DIODES D1–D4 ARE HEWLETT-PACKARD HP5082-2835 IC1 IS 1/2 OP260AJ –15V IC2 IS PMI OP41EJ Figure 7. OP285’s Settling Time Test Fixture –8– REV. C

OP285 +15V 10(cid:1)F + R3 2k(cid:6) 0.1(cid:1)F 2 R9 1 50(cid:6) VO1 10pF 3 A2 VIN 4.99k(cid:6) 2 –4.99k8(cid:6) VIN 3 2kR(cid:6)1 R2k4(cid:6) 2Rk7(cid:6) 1Rk1(cid:6)1 VO2 – VO1 = VIN 1/2 1 VOUT 1 3 OP285 2 A1 10kP(cid:6)1 + 4 2k(cid:6) R5 2.49k(cid:6) 2k(cid:6) R6 0.1(cid:1)F R2 2k(cid:6) 2k(cid:6) R12 6 R10 1k(cid:6) 10(cid:1)F 7 50(cid:6) VO2 + 5 A3 R8 2k(cid:6) –15V A1 = 1/2OP285 Figure 9. Unity-Gain Inverter A2, A3 = 1/2 OP285 GAIN = SET R2, R4, R5 = R1 AND R, R7, R8 = R2 In inverting and noninverting applications, the feedback resis- tance forms a pole with the source resistance and capacitance Figure 11. High-Speed, Low-Noise Differential Line Driver (R and C ) and the OP285’s input capacitance (C ), as S S IN shown in Figure 10. With RS and RF in the kilohm range, this Low Phase Error Amplifier pole can create excess phase shift and even oscillation. A small The simple amplifier configuration of Figure 12 uses the OP285 capacitor, CFB, in parallel with RFB eliminates this problem. By and resistors to reduce phase error substantially over a wide setting RS (CS + CIN) = RFBCFB, the effect of the feedback pole frequency range when compared to conventional amplifier designs. is completely removed. This technique relies on the matched frequency characteristics of the two amplifiers in the OP285. Each amplifier in the circuit CFB has the same feedback network which produces a circuit gain of 10.Since the two amplifiers are set to the same gain and are RFB matched due to the monolithic construction of the OP285, they will exhibit identical frequency response. Recall from feedback theory that a pole of a feedback network becomes a zero in the VOUT loop gain response. By using this technique, the dominant pole RS CS CIN of the amplifier in the feedback loop compensates for the domi- nant pole of the main amplifier, R2 Figure 10. Compensating the Feedback Pole 4.99k(cid:6) R1 549(cid:6) 2 1 High-Speed, Low-Noise Differential Line Driver 3 A1 R5 The circuit of Figure 11 is a unique line driver widely used in 549(cid:6) industrial applications. With ±18 V supplies, the line driver can deliver a differential signal of 30 V p-p into a 2.5 kΩ load. The 6 R4.499(cid:6) 7 high slew rate and wide bandwidth of the OP285 combine to 5 A2 VOUT yield a full power bandwidth of 130 kHz while the low noise VIN R3 A1, A2 = 1/2 OP285 front end produces a referred-to-input noise voltage spectral 499(cid:6) density of 10 nV/√Hz. The design is a transformerless, balanced Figure 12. Cancellation of A2’s Dominant Pole by A1 transmission system where output common-mode rejection of noise is of paramount importance. Like the transformer-based design, either output can be shorted to ground for unbalanced line driver applications without changing the circuit gain of 1. Other circuit gains can be set according to the equation in the diagram. This allows the design to be easily set to noninverting, inverting, or differential operation. REV. C –9–

OP285 thereby reducing phase error dramatically. This is shown in A Low Noise, High Speed Instrumentation Amplifier Figure 13 where the 10x composite amplifier’s phase response A high speed, low noise instrumentation amplifier, constructed exhibits less than 1.5° phase shift through 500 kHz. On the other with a single OP285, is illustrated in Figure 15. The circuit exhibits hand, the single gain stage amplifier exhibits 25° of phase shift less than 1.2 µV p-p noise (RTI) in the 0.1 Hz to 10 Hz band over the same frequency range. An additional benefit of the low and an input noise voltage spectral density of 9 nV/√Hz (1 kHz) phase error configuration is constant group delay, by virtue of at a gain of 1000. The gain of the amplifier is easily set by RG constant phase shift at all frequencies below 500 kHz. Although according to the formula: this technique is valid for minimum circuit gains of 10, actual closed-loop magnitude response must be optimized for the VOUT = 9.98kΩ +2 amplifier chosen. VIN RG The advantages of a two op amp instrumentation amplifier based on a dual op amp is that the errors in the individual am- LOW PHASE ERROR 0 AMPLIFIER RESPONSE plifiers tend to cancel one another. For example, the circuit’s input offset voltage is determined by the input offset voltage –5 matching of the OP285, which is typically less than 250 µV. –10 s e E – Degre ––2105 AMPSLIINFGIELRE RSETSAPGOENSE V+–IN 32 A1 1 56 A2 7 VOUT AS –25 AC CMRR TRIM R3 H 4.99k(cid:6) P –30 C1 4.R992(cid:6) 4.9R94k(cid:6) –35 5pF–40pF –40 DC CMRR TRIM R4.199k(cid:6) RG AG1A, INA 2= =9 .19/82k O(cid:6)P+2285 RQ –4510k 100k 1M 10M GAIN RG((cid:6)) START 10,000.000Hz STOP 10,000,000.000Hz P5010(cid:6) 120 O1.P2E4kN 100 102 Figure 13. Phase Error Comparison 1000 10 For a more detailed treatment on the design of low phase error Figure 15. A High-Speed Instrumentation Amplifier amplifiers, see Application Note AN-107. Common-mode rejection of the circuit is limited by the matching Fast Current Pump of resistors R1 to R4. For good common-mode rejection, these A fast, 30 mA current source, illustrated in Figure 14, takes resistors ought to be matched to better than 1%. The circuit was advantage of the OP285’s speed and high output current drive. constructed with 1% resistors and included potentiometer P1 This is a variation of the Howland current source where a sec- for trimming the CMRR and a capacitor C1 for trimming the ond amplifier, A2, is used to increase load current accuracy and CMRR. With these two trims, the circuit’s common-mode output voltage compliance. With supply voltages of ±15 V, the rejection was better than 95 dB at 60 Hz and better than 65 dB output voltage compliance of the current pump is ±8 V. To at 10 kHz. For the best common-mode rejection performance, keep the output resistance in the MΩ range requires that 0.1% use a matched (better than 0.1%) thin-film resistor network for or better resistors be used in the circuit. The gain of the current R1 through R4 and use the variable capacitor to optimize the pump can be easily changed according to the equations shown circuit’s CMR. in the diagram. The instrumentation amplifier exhibits very wide small- and R1 R2 large-signal bandwidths regardless of the gain setting, as shown 2k(cid:6) 2k(cid:6) VIN1 in the table. Because of its low noise, wide gain-bandwidth 2 R5 product, and high slew rate, the OP285 is ideally suited for high R3 1 50(cid:6) 2k(cid:6) 3 A1 speed signal conditioning applications. VIN2 2Rk4(cid:6) 7 5 IOUT =VIN2 R–5 VIN1=(cid:8)RV5IN Circuit R Circuit Bandwidth A2 6 IOUT = (MAX) = (cid:2)30mA Gain ((cid:6)G) V = 100 mV p-p V = 20 V p-p A1, A2 = 1/2 OP285 OUT OUT GAIN = R 2 , R4 = R2, R3 = R1 R1 2 Open 5 MHz 780 kHz 10 1.24 k 1 MHz 460 kHz Figure 14. A Fast Current Pump 100 102 90 kHz 85 kHz 1000 10 10 kHz 10 kHz –10– REV. C

OP285 R1 95.3k(cid:6) 2 1 22C001pF 78R72(cid:6) 4.1R26k(cid:6) 5 A1 VIN 3 2200CpF2 5 2200CpF4 100kR(cid:6)7 6 A4 7 VOUT 7 A3 6 R3 1.82k(cid:6) R9 1Rk8(cid:6) 2 1k(cid:6) 1 A2 3 C3 2200pF R4 1.87k(cid:6) A1, A4 = 1/2 OP285 A2, A3 = 1/2 OP285 R5 1.82k(cid:6) Figure 16. A 3-Pole, 40 kHz Low-Pass Filter A 3-Pole, 40 kHz Low-Pass Filter The closely matched and uniform ac characteristics of the OP285 Driving Capacitive Loads make it ideal for use in GIC (Generalized Impedance Converter) The OP285 was designed to drive both resistive loads to 600 Ω and FDNR (Frequency Dependent Negative Resistor) filter appli- and capacitive loads of over 1000 pF and maintain stability. While cations. The circuit in Figure 16 illustrates a linear-phase, there is a degradation in bandwidth when driving capacitive loads, 3-pole, 40 kHz low-pass filter using an OP285 as an inductance the designer need not worry about device stability. The graph in simulator (gyrator). The circuit uses one OP285 (A2 and A3) Figure 18 shows the 0 dB bandwidth of the OP285 with capacitive for the FDNR and one OP285 (Al and A4) as an input buffer loads from 10 pF to 1000 pF. and bias current source for A3. Amplifier A4 is configured in a gain of 2 to set the pass band magnitude response to 0 dB. The 10 benefits of this filter topology over classical approaches are 9 that the op amp used in the FDNR is not in the signal path and 8 that the filter’s performance is relatively insensitive to compo- nent variations. Also, the configuration is such that large signal z 7 H levels can be handled without overloading any of the filter’s – M 6 internal nodes. As shown in Figure 17, the OP285’s symmetric DTH 5 slew rate and low distortion produce a clean, well-behaved WI transient response. ND 4 A B 3 2 1 100 90 0 0 200 400 600 800 1000 CLOAD – pF VOUT 10V p-p Figure 18. Bandwidth vs. C 10kHz LOAD 10 0% SCALE: VERTICAL – 2V/ DIV HORIZONTAL – 10(cid:1)S/ DIV Figure 17. Low-Pass Filter Transient Response REV. C –11–

OP285 OP285 SPICE Model *Node assignments *POLE/ZERO PAIR AT 1.5MHz/2.7MHz * noninverting input * * inverting input R8 21 98 1E3 * positive supply R9 21 22 1.25E3 * negative supply C4 22 98 47.2E-12 * output G2 98 21 18 28 1E-3 * * * * POLE AT 100 MHZ .SUBCKT OP285 1 2 99 50 34 * * R10 23 98 1 * INPUT STAGE & POLE AT 100 MHZ C5 23 98 1.59E-9 * G3 98 23 21 28 1 R3 5 51 2.188 * R4 6 51 2.188 * POLE AT 100 MHZ CIN 1 2 1.5E-12 * C2 5 6 364E-12 R11 24 98 l I1 97 4 100E-3 C6 24 98 1.59E-9 IOS 1 2 1E-9 G4 98 24 23 28 1 EOS 9 3 POLY(1) 26 28 35E-6 1 * Q1 5 2 7 QX * COMMON-MODE GAIN NETWORK WITH ZERO AT Q2 6 9 8 QX 1 kHZ * R5 7 4 1.672 R12 25 26 1E6 R6 8 4 1.672 C7 25 26 1.59E-12 D1 2 36 DZ R13 26 98 1 D2 1 36 DZ E2 25 98 POLY(2) 1 98 2 98 0 2.506 2.506 EN 3 1 100 1 * GN1 0 2 13 0 1 * POLE AT 100 MHZ GN20 1 16 0 1 * * R14 27 98 1 EREF 98 0 28 0 1 C8 27 98 1.59E-9 EP 97 0 99 0 l G5 98 27 24 28 1 EM 510 50 0 1 * * * OUTPUT STAGE * VOLTAGE NOISE SOURCE * * Rl5 28 99 100E3 DN1 35 10 DEN R16 28 50 100E3 DN2 10 11 DEN C9 28 50 1 E-6 VN1 35 0 DC 2 ISY 99 50 1.85E-3 VN2 0 11 DC 2 R17 29 99 100 * R18 29 50 100 * CURRENT NOISE SOURCE L2 29 34 1E-9 * G6 32 50 27 29 10E-3 DN3 12 13 DIN G7 33 50 29 27 10E-3 DN4 13 14 DIN G8 29 99 99 27 10E-3 VN3 12 0 DC 2 G9 50 29 27 50 10E-3 VN4 0 14 DC 2 V4 30 29 1.3 CN1 13 0 7.53E-3 V5 29 31 3.8 * F1 29 0 V4 1 * CURRENT NOISE SOURCE F2 0 29 V5 1 * D5 27 30 DX DN5 15 16 DIN D6 31 27 DX DN6 16 17 DIN D7 99 32 DX VN5 15 0 DC 2 D8 99 33 DX VN6 0 17 DC2 D9 50 32 DY CN2 16 0 7.53E-3 D10 50 33 DY * * * GAIN STAGE & DOMINANT POLE AT 32 HZ * * MODELS USED R7 18 98 1.09E6 * C3 18 98 4.55E-9 .MODEL QX PNP(BF = 5E5) G1 98 18 5 6 4.57E-1 .MODEL DX D(IS = lE-12) V2 97 19 1.4 .MODEL DY D(IS = lE-15 BV = 50) V3 20 51 1.4 .MODEL DZ D(IS = lE-15 BV = 7.0) D3 18 19 DX .MODEL DEN D(IS = lE-12 RS = 4.35K KF = 1.95E-15 D4 20 18 DX AF = l) .MODEL DIN D(IS = lE-12 RS = 77.3E-6 * KF = 3.38E-15 AF = 1) .ENDS OP-285 –12– REV. C

OP285 97 EP I1 4 R5 R6 7 8 2 9 35 12 15 –IN Q1 Q2 CIN D1 VN1 DN1 VN3 DN3 VN5 DN5 IOS 36 10 13 CN1 16 CN2 +IN1 D2 EN 3 EOS VN2 DN2 VN4 DN4 VN6 DN6 11 14 17 5 6 C2 R3 R4 EM Figure 19a. Spice Diagram 97 V2 19 C7 D3 21 23 24 25 26 R12 R9 G1 C3 G2 G3 C5 G4 C6 E2 R7 R8 R10 R11 R13 C4 D4 20 V3 51 Figure 19b. Spice Diagram 99 D7 D8 R15 G8 R17 ISY 28 D5 30 V4 27 F1 29 L2 34 OUTPUT D6 V5 G5 R14 C8 31 98 F2 R16 32 33 G3 R18 C9 D9 D10 G6 G7 50 Figure 19c. Spice Diagram REV. C –13–

OP285 Data Sheet OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA C(RINEOFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1 Temperature Range Package Description Package Option OP285GS −40°C to +85°C 8-lead SOIC_N R-8 OP285GS-REEL −40°C to +85°C 8-lead SOIC_N R-8 OP285GS-REEL7 −40°C to +85°C 8-lead SOIC_N R-8 OP285GSZ −40°C to +85°C 8-lead SOIC_N R-8 OP285GSZ-REEL −40°C to +85°C 8-lead SOIC_N R-8 OP285GSZ-REEL7 −40°C to +85°C 8-lead SOIC_N R-8 1 Z = RoHS Compliant Part. Rev. C | Page 14 of 15

Data Sheet OP285 REVISION HISTORY 1/2018—Rev. B to Rev. C Changes to Figure 1 ........................................................................... 1 10/2017—Rev. A to Rev. B Changes to General Description Section and Pin Connection ... 1 Changes to Supply Current Parameter, Specifications Section ... 2 Changes to Absolute Maximum Ratings Section .......................... 3 Updated Outline Dimensions ........................................................ 14 Moved Ordering Guide .................................................................. 14 Changes to Ordering Guide ........................................................... 14 1/2002—Rev. 0 to Rev. A Edits to Ordering Guide ................................................................... 3 Deleted Wafer Test Limits ................................................................ 3 Deleted Dice Characteristics ............................................................ 3 7/1992—Revision 0: Initial Version ©1992–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00306-0-1/18(C) Rev. C | Page 15 of 15