a Rail-to-Rail High Output Current Operational Amplifiers OP179/OP279 FEATURES PIN CONFIGURATIONS Rail-to-Rail Inputs and Outputs 5-Lead SOT-23-5 High Output Current: (cid:2)60 mA (RT-5) Single Supply: 5 V to 12 V Wide Bandwidth: 5 MHz High Slew Rate: 3 V/(cid:3)s OP179 OUT A 1 5 V– Low Distortion: 0.01% V+ 2 Unity-Gain Stable No Phase Reversal +IN A 3 4 (cid:1)IN A Short-Circuit Protected Drives Capacitive Loads: 10 nF 8-Lead SOIC APPLICATIONS (S Suffix) Multimedia Telecom DAA Transformer Driver OP179 NC 1 8 NC LCD Driver (cid:1)IN A 2 7 V+ Low Voltage Servo Control +IN A 3 6 OUT A Modems V(cid:1) 4 5 NC FET Drivers NC = NO CONNECT 8-Lead SOIC and TSSOP GENERAL DESCRIPTION SO-8 (S) and RU-8 The OP179 and OP279 are rail-to-rail, high output current, single-supply amplifiers. They are designed for low voltage applications that require either current or capacitive load drive OUT A 1 8 V+ capability. The OP179/OP279 can sink and source currents of (cid:1)IN A 2 OP279 7 OUT B ±60 mA (typical) and are stable with capacitive loads to 10 nF. +IN A 3 6 (cid:1)IN B Applications that benefit from the high output current of the V(cid:1) 4 5 +IN B OP179/OP279 include driving headphones, displays, transform- ers and power transistors. The powerful output is combined with a unique input stage that maintains very low distortion with wide common-mode range, even in single supply designs. Very good audio performance can be attained when using the OP179/OP279 in 5 volt systems. THD is below 0.01% with a The OP179/OP279 can be used as a buffer to provide much 600Ω load, and noise is a respectable 21nV/√Hz. Supply current greater drive capability than can usually be provided by CMOS is less than 3.5 mA per amplifier. outputs. CMOS ASICs and DAC often have outputs that can swing to both the positive supply and ground, but cannot drive The single OP179 is available in the 5-lead SOT-23-5 package. more than a few milliamps. It is specified over the industrial (–40°C to +85°C) tempera- Bandwidth is typically 5 MHz and the slew rate is 3 V/µs, making ture range. these amplifiers well suited for single supply applications that The OP279 is available in 8-lead TSSOP and SO-8 surface require audio bandwidths when used in high gain configurations. mount packages. They are specified over the industrial (–40°C Operation is guaranteed from voltages as low as 4.5 V, up to 12 V. to +85°C) temperature range. REV.G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002

OP179/OP279–SPECIFICATIONS ELECTRICAL SPECIFICATIONS (@ V = 5.0 V, V = 2.5 V, –40(cid:4)C ≤ T ≤ +85(cid:4)C unless otherwise noted.) S CM A Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage OP179 V V = 2.5 V ±5 mV OS OUT OP279 V V = 2.5 V ±4 mV OS OUT Input Bias Current I V = 2.5 V, T = 25°C ±300 nA B OUT A V = 2.5 V ±700 nA OUT Input Offset Current I V = 2.5 V, T = 25°C ±50 nA OS OUT A V = 2.5 V ±100 nA OUT Input Voltage Range V 0 5 V CM Common-Mode Rejection Ratio CMRR V = 0 V to 5 V 56 66 dB CM Large Signal Voltage Gain A R = 1 kΩ, 0.3 V ≤ V ≤ 4.7 V 20 V/mV VO L OUT Offset Voltage Drift ∆V /∆T 4 µV/°C OS OUTPUT CHARACTERISTICS Output Voltage High V I = 10 mA Source +4.8 V OH L Output Voltage Low V I = 10 mA Sink, T = 25°C 75 mV OL L A I = 10 mA Sink 100 mV L Short-Circuit Limit I T = 25°C ±40 mA SC A Output Impedance Z f = 1 MHz, A = 1 22 Ω OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR V = 4.5 V to 12 V 70 88 dB S Supply Current/Amplifier I V = 2.5 V 3.5 mA SY OUT Supply Voltage Range V +4.5 +12 V S DYNAMIC PERFORMANCE Slew Rate SR R = 1 kΩ, 1 nF 3 V/µs L Gain Bandwidth Product GBP 5 MHz Phase Margin φm 60 Degrees Capacitive Load Drive No Oscillation 10 nF AUDIO PERFORMANCE Total Harmonic Distortion THD 0.01 % Voltage Noise Density en f = 1 kHz 22 nV/√Hz ELECTRICAL SPECIFICATIONS (@ V = (cid:2)5.0 V, –40(cid:4)C ≤ T ≤ +85(cid:4)C unless otherwise noted.) S A Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage OP179 V V = 0 ±5 mV OS OUT OP279 V V = 0 ±4 mV OS OUT Input Bias Current I T = 25°C ±300 nA B A ±700 nA Input Offset Current I T = 25°C ±50 nA OS A ±100 nA Input Voltage Range V –5 +5 V CM Common-Mode Rejection Ratio CMRR V = –5 V to +5 V 56 66 dB CM Large Signal Voltage Gain A R = 1 kΩ, –4.7 V ≤ V ≤ 4.7 V 20 V/mV VO L OUT Offset Voltage Drift ∆V /∆T 3 µV/°C OS OUTPUT CHARACTERISTICS Output Voltage High V I = 10 mA Source +4.8 V OH L Output Voltage Low V I = 10 mA Sink –4.85 V OL L Short Circuit Limit I T = 25°C ±50 mA SC A Open-Loop Output Impedance Z f = 1 MHz, A = +1 22 Ω OUT V POWER SUPPLY Supply Current/Amplifier I V = ±6 V, V = 0 V 3.75 mA SY S OUT DYNAMIC PERFORMANCE Slew Rate SR R = 1 kΩ, 1 nF 3 V/µs L Full-Power Bandwidth BWp 1% Distortion kHz Gain Bandwidth Product GBP 5 MHz Phase Margin φm 69 Degrees NOISE PERFORMANCE Voltage Noise en p-p 0.1 Hz to 10 Hz 2 µV p-p Voltage Noise Density en f = 1 kHz 22 nV/√Hz Current Noise Density in 1 pA/√Hz Specifications subject to change without notice. –2– REV. G

OP179/OP279 ABSOLUTE MAXIMUM RATINGS Package Types (cid:5) 2 (cid:5) Unit JA JC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 V 5-Lead SOT-23 (RT) 256 81 °C/W Differential Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . .±1 V 8-Lead SOIC (S) 158 43 °C/W Output Short-Circuit Duration to GND . . . . . . . . . .Indefinite 8-Lead TSSOP (RU) 240 43 °C/W Storage Temperature Range NOTES S, RT, RU Package . . . . . . . . . . . . . . . . . .–65°C to +150°C 1The inputs are clamped with back-to-back diodes. If the differential input voltage Operating Temperature Range exceeds 1 volt, the input current should be limited to 5 mA. OP179G/OP279G . . . . . . . . . . . . . . . . . . . .–40°C to +85°C 2θJA is specified for the worst-case conditions, i.e., θJA is specified for device soldered in circuit board for SOIC packages. Junction Temperature Range S, RT, RU Package . . . . . . . . . . . . . . . . . . .–65°C to +150°C Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C ORDERING GUIDE Package Temperature Range Package Description Package Option Brand Code OP179GRT –40°C to +85°C 5-Lead SOT-23 RT-5 A2G OP279GS –40°C to +85°C 8-Lead SOIC SO-8 OP279GRU –40°C to +85°C 8-Lead TSSOP RU-8 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the OP179/OP279 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. G –3–

OP179/OP279–Typical Performance Characteristics 160 90 400 VS (cid:6) 5V VS (cid:6) 5V 140 6T2A0 (cid:6) (cid:7) 2 O5(cid:4)PC AMPS mA80 A 300 –40(cid:4)C 120 T – – n 200 100 REN –ISC ENT 100 +25(cid:4)C R70 R S U R NIT 80 T C +ISC CU 0 +85(cid:4)C U CUI60 AS 60 R BI –100 CI T 4200 SHORT-50 VVSC M(cid:6) (cid:6) 5 V2.5V INPU ––230000 0 40 –400 –2.5 –1.5 –0.5 0.5 1.5 2.5 –50 –25 0 25 50 75 100 0 1 2 3 4 5 INPUT OFFSET – mV TEMPERATURE – (cid:4)C COMMON-MODE VOLTAGE – Volts TPC 1.Input Offset Distribution TPC 2.Short-Circuit Current vs. TPC 3.Input Bias Current Temperature vs. Common-Mode Voltage 3.0 100 7 AGE – mV 22..50 VTAS (cid:6)(cid:6) 255V(cid:4)C URRENT – mA8900 –ISC H – MHz645 VTAS (cid:6)(cid:6) 255V(cid:4)C VOLT 1.5 UIT C +ISC WIDT3 FFSET 1.0 T-CIRC70 BAND2 O R O60 0.5 SH VS (cid:6) (cid:2)5V 1 0 50 0 0 1 2 3 4 5 –50 –25 0 25 50 75 100 0 1 2 3 4 5 COMMON-MODE VOLTAGE – Volts TEMPERATURE – (cid:4)C COMMON-MODE VOLTAGE – Volts TPC 4.Offset Voltage vs. TPC 5.Short-Circuit Current vs. TPC 6.Bandwidth vs. Common-Mode Voltage Temperature Common-Mode Voltage 1000 5 120 270 RL (cid:6) 2k(cid:8) 100 TVAS –(cid:2)420.5(cid:4)CV 225 mV800 4 +EDGE B 80 RL (cid:6) 2k(cid:8) 180 OPEN-LOOP GAIN – V/624000000 V0.S3 (cid:6) 1V5OVUT 4.7RVL (cid:6) 1k(cid:8) (cid:9)(cid:3)SLEW RATE – Vs312 VRSL (cid:6)(cid:6) 51Vk(cid:8) –EDGE OPEN-LOOP GAIN – d 4620000 PHGAASIEN 94100535PHASE – Degrees CL (cid:6) +1nF –20 –45 0 0 –40 –90 –50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 100 1k 10k 100k 1M 10M TEMPERATURE – (cid:4)C TEMPERATURE – (cid:4)C FREQUENCY – Hz TPC 7.Open-Loop Gain vs. TPC 8.Slew Rate vs. TPC 9.Open-Loop Gain and Temperature Temperature Phase vs. Frequency –4– REV. G

OP179/OP279 6.5 5 120 270 +EDGE 100 TVAS –(cid:2)420.5(cid:4)CV 225 SUPPLY CURRENT – mA 5456....5500 VVVVSSSC M(cid:6)(cid:6)(cid:6) (cid:6) (cid:2)(cid:2)5 V562VV.5V (cid:3)SLEW RATE – V/s3124 VRSL (cid:6)(cid:6) (cid:2)1k5(cid:8)V –EDGE OPEN-LOOP GAIN – dB 468200000 PGHAAISNE RCLL (cid:6)(cid:6) 25k0(cid:8)0pF 91410805305PHASE – Degrees CL (cid:6) +1nF –20 –45 4.0 0 –40 –90 –50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 100 1k 10k 100k 1M 10M TEMPERATURE – (cid:4)C TEMPERATURE – (cid:4)C FREQUENCY – Hz TPC 10.Supply Current vs. TPC 11.Slew Rate vs. Temperature TPC 12.Open-Loop Gain and Temperature Phase vs. Frequency 120 6 180 PLY REJECTION – dB1680000 +PSRR – TVPASS R(cid:6)R 2(cid:2)52(cid:4).C5V M OUTPUT SWING – Volts3245 VATRASVL C(cid:6)(cid:6)L (cid:2)21(cid:6)5k2 (cid:4)(cid:8)+.C51V (cid:8)EDANCE – 11118462000000 VTAS (cid:6)(cid:6) 2(cid:2)52(cid:4).C5AVV OCRL (cid:6)(cid:2) 51V0 OR 100 R SUP 40 AXIMU1 IMP 60 E M 40 W PO 20 01k 10kFREQU1E0N0CkY – Hz1M 10M 20 AVCL (cid:6) 1 0 0 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M FREQUENCY – Hz FREQUENCY – Hz TPC 13.Power Supply Rejection vs. TPC 14.Maximum Output TPC 15.Closed-Loop Output Frequency Swing vs. Frequency Impedance vs. Frequency 12 50 80 XIMUM OUTPUT SWING – Volts16480 ATVRASVL C(cid:6)(cid:6)L (cid:2)21(cid:6)5k5 (cid:4)(cid:8)+VC1 CLOSED-LOOP GAIN – dB–12341000000 AAAVVVCCCLLL (cid:6)(cid:6)(cid:6) +++111000 TRVASL (cid:6) 2(cid:2)15k2(cid:4)(cid:8).C5V OVERSHOOT – %243567000000 ATRVVASIVLN C(cid:6) (cid:6)L 2 (cid:2)1(cid:6)15k20 (cid:4)(cid:8)+.0CPN51mVOEVGS IpAT-TIpVIVEE E EDDGGEE AND A 2 M –20 10 0 –30 0 1k 10k 100k 1M 10M 1k 10k 100k 1M 10M 100M 0 2k 4k 6k 8k 10k FREQUENCY – Hz FREQUENCY – Hz LOAD CAPACITANCE – pF TPC 16.Maximum Output Swing vs. TPC 17.Closed-Loop Gain vs. TPC 18.Small Signal Overshoot vs. Frequency Frequency Load Capacitance REV. G –5–

OP179/OP279 100 60 120 (cid:1)VOLTAGE NOISE DENSITY – nV/Hz64280000 VTAS (cid:6)(cid:6) 255V(cid:4)C (cid:1)VOLTAGE NOISE DENSITY – nV/Hz 3125400000 FVTARS E(cid:6)(cid:6)Q 25U5VE(cid:4)CNCY (cid:6) 1kHz COMMON-MODE REJECTION – dB16428000000 TVAS (cid:6) 2(cid:2)52(cid:4).C5V 0 0 0 1 10 100 1k 10k 0 1 2 3 4 5 100 1k 10k 100k 1M FREQUENCY – Hz COMMON-MODE VOLTAGE – Volts FREQUENCY – Hz TPC 19.Voltage Noise Density vs. TPC 20.Voltage Noise Density vs. TPC 21.Common-Mode Frequency Common-Mode Voltage Rejection vs. Frequency THEORY OF OPERATION VPOS The OP179/OP279 is the latest entry in Analog Devices’ expand- ing family of single-supply devices, designed for the multimedia R1 R2 and telecom marketplaces. It is a high output current drive, 6k(cid:8) 3k(cid:8) rail-to-rail input /output operational amplifier, powered from a Q2 Q3 single 5 V supply. It is also intended for other low supply voltage applications where low distortion and high output current drive Q4 are needed. To combine the attributes of high output current R3 R4 2.5k(cid:8) 2.5k(cid:8) and low distortion in rail-to-rail input/output operation, novel circuit design techniques are used. D5 D6 Q1 Q5 Q6 Q9 For example, TPC 1 illustrates a simplified equivalent circuit for IN+ IN– the OP179/OP279’s input stage. It is comprised of two PNP D7 D8 D1 D3 differential pairs, Q5-Q6 and Q7-Q8, operating in parallel, with D2 D4 R5 R6 diode protection networks. Diode networks D5-D6 and D7-D8 Q7 4k(cid:8) 4k(cid:8) Q8 serve to clamp the applied differential input voltage to the OP179/OP279, thereby protecting the input transistors against I1 I2 – VO + avalanche damage. The fundamental differences between these R2.72k(cid:8) 2.2kR(cid:8)8 I3 two PNP gain stages are that the Q7-Q8 pair are normally OFF and that their inputs are buffered from the operational amplifier VNEG inputs by Q1-D1-D2 and Q9-D3-D4. Operation is best under- Figure 1.OP179/OP279 Equivalent Input Circuit stood as a function of the applied common-mode voltage: When the inputs of the OP179/OP279 are biased midway between the The key issue here is the behavior of the input bias currents supplies, the differential signal path gain is controlled by the in this stage. The input bias currents of the OP179/OP279 over resistively loaded (via R7, R8) Q5-Q6. As the input common-mode the range of common-mode voltages from (V + 1V) to NEG level is reduced toward the negative supply (V or GND), the (V – 1V) are the arithmetic sum of the base currents in Q1-Q5 NEG POS input transistor current sources, I1 and I3, are forced into satura- and Q9-Q6. Outside of this range, the input bias currents are tion, thereby forcing the Q1-D1-D2 and Q9-D3-D4 networks dominated by the base current sum of Q5-Q6 for input signals into cutoff; however, Q5-Q6 remain active, providing input stage close to V , and of Q1-Q5 (Q9-Q6) for input signals close to NEG gain. On the other hand, when the common-mode input voltage V . As a result of this design approach, the input bias currents POS is increased toward the positive supply, Q5-Q6 are driven into in the OP179/OP279 not only exhibit different amplitudes, but cutoff, Q3 is driven into saturation, and Q4 becomes active, also exhibit different polarities. This input bias current behavior providing bias to the Q7-Q8 differential pair. The point at which is best illustrated in TPC 3. It is, therefore, of paramount the Q7-Q8 differential pair becomes active is approximately equal importance that the effective source impedances connected to to (V – 1 V). the OP179/OP279’s inputs are balanced for optimum dc and POS ac performance. –6– REV. G

OP179/OP279 In order to achieve rail-to-rail output behavior, the OP179/OP279 ance levels. For more information on general overvoltage charac- design employs a complementary common-emitter (or g R ) teristics of amplifiers refer to the 1993 Seminar Applications Guide, m L output stage (Q15-Q16), as illustrated in Figure 2. These available from the Analog Devices Literature Center. amplifiers provide output current until they are forced into 5 saturation, which occurs at approximately 50 mV from either supply rail. Thus, their saturation voltage is the limit on the 4 maximum output voltage swing in the OP179/OP279. The 3 output stage also exhibits voltage gain, by virtue of the use of A 2 m cthoem omuotpnu-et mstiatgteer (athmupsl,i ftiheers o; paennd-,l oaos pa greasinu lot,f tthhee vdoelvtaicgee) geaxihni bo-f NT – 1 E its a strong dependence to the total load resistance at the output RR 0 U of the OP179/OP279 as illustrated in TPC 7. C–1 T U P–2 N VPOS I–3 –4 105(cid:8) Q13 –5 –2.0 –1.0 0 1.0 2.0 I1 Q3 Q7 I3 INPUT VOLTAGE – V Q15 Figure 3.OP179/OP279 Input Overvoltage Characteristic Q4 Q8 Output Phase Reversal Q1 150(cid:8) Q11 Some operational amplifiers designed for single-supply operation VOUT exhibit an output voltage phase reversal when their inputs are Q2 Q12 Q5 Q9 driven beyond their useful common-mode range. Typically for single-supply bipolar op amps, the negative supply determines Q16 the lower limit of their common-mode range. With these devices, I2 Q6 Q10 I4 external clamping diodes, with the anode connected to ground and the cathode to the inputs, input signal excursions are pre- 105(cid:8) Q14 vented from exceeding the device’s negative supply (i.e., GND), preventing a condition that could cause the output voltage to VNEG change phase. JFET input amplifiers may also exhibit phase reversal and, if so, a series input resistor is usually required to Figure 2.OP179/OP279 Equivalent Output Circuit prevent it. Input Overvoltage Protection The OP179/OP279 is free from reasonable input voltage range As with any semiconductor device, whenever the condition restrictions provided that input voltages no greater than the exists for the input to exceed either supply voltage, the device’s supply voltages are applied. Although the device’s output will input overvoltage characteristic must be considered. When an not change phase, large currents can flow through the input overvoltage occurs, the amplifier could be damaged, depending protection diodes, shown in Figure 1. Therefore, the technique on the magnitude of the applied voltage and the magnitude of recommended in the Input Overvoltage Protection section should the fault current. Figure 3 illustrates the input overvoltage char- be applied in those applications where the likelihood of input acteristic of the OP179/OP279. This graph was generated with voltages exceeding the supply voltages is possible. the power supplies at ground and a curve tracer connected to the input. As can be seen, when the input voltage exceeds either Capacitive Load Drive supply by more than 0.6 V, internal pn-junctions energize, The OP179/OP279 has excellent capacitive load driving capa- which allows current to flow from the input to the supplies. As bilities. It can drive up to 10 nF directly as the performance illustrated in the simplified equivalent input circuit (Figure 1), graph titled Small Signal Overshoot vs. Load Capacitance the OP179/OP279 does not have any internal current limiting (TPC 18) shows. However, even though the device is stable, a resistors, so fault currents can quickly rise to damaging levels. capacitive load does not come without a penalty in bandwidth. As shown in Figure 4, the bandwidth is reduced to under 1 MHz This input current is not inherently damaging to the device as for loads greater than 3 nF. A “snubber” network on the output long as it is limited to 5 mA or less. For the OP179/OP279, once will not increase the bandwidth, but it does significantly reduce the input voltage exceeds the supply by more than 0.6 V, the the amount of overshoot for a given capacitive load. A snubber input current quickly exceeds 5 mA. If this condition continues to consists of a series R-C network (R , C ), as shown in Figure 5, exist, an external series resistor should be added. The size of the S S connected from the output of the device to ground. This net- resistor is calculated by dividing the maximum overvoltage by work operates in parallel with the load capacitor, C , to provide 5mA. For example, if the input voltage could reach 100 V, the L phase lag compensation. The actual value of the resistor and external resistor should be (100 V/5 mA) = 20 kΩ. This resis- capacitor is best determined empirically. tance should be placed in series with either or both inputs if they are exposed to an overvoltage. Again, in order to ensure optimum dc and ac performance, it is important to balance source imped- REV. G –7–

OP179/OP279 7 Table I. Snubber Networks for Large Capacitive Loads VS (cid:6) (cid:2)5V 6 RL (cid:6) 1k(cid:8) Load Capacitance (CL) Snubber Network (RS, CS) TA (cid:6) 25(cid:4)C 10 nF 20 Ω, 1 µF z 5 100 nF 5 Ω, 10 µF H – M 4 1 µF 0 Ω, 10 µF H T D WI 3 Overload Recovery Time D N Overload, or overdrive, recovery time of an operational amplifier A B 2 is the time required for the output voltage to recover to its linear region from a saturated condition. This recovery time is impor- 1 tant in applications where the amplifier must recover after a large transient event. The circuit in Figure 7 was used to 0 0.01 0.100 1 10 evaluate the OP179/OP279’s overload recovery time. The CAPACITIVE LOAD – nF OP179/OP279 takes approximately 1 µs to recover from positive Figure 4.OP179/OP279 Bandwidth vs. Capacitive Load saturation and approximately 1.2 µs to recover from negative saturation. 5V R2 R3 1k(cid:8) 10k(cid:8) 1/2 +5V OP279 VOUT VIN RS 100mV p-p 20V CL 1/2 C1(cid:3)SF 10nF 90R91(cid:8) OP279 VOUT RL 2V p-p 499(cid:8) @ 100Hz –5V Figure 5.Snubber Network Compensates for Capacitive Load The first step is to determine the value of the resistor, R . A Figure 7.Overload Recovery Time Test Circuit S good starting value is 100 Ω (typically, the optimum value will Output Transient Current Recovery be less than 100 Ω). This value is reduced until the small-signal In many applications, operational amplifiers are used to provide transient response is optimized. Next, CS is determined—10 µF moderate levels of output current to drive the inputs of ADCs, is a good starting point. This value is reduced to the smallest small motors, transmission lines and current sources. It is in these value for acceptable performance (typically, 1 µF). For the case applications that operational amplifiers must recover quickly to of a 10 nF load capacitor on the OP179/OP279, the optimal step changes in the load current while maintaining steady-state snubber network is a 20 Ω in series with 1 µF. The benefit is load current levels. Because of its high output current capability immediately apparent as seen in the scope photo in Figure 6. and low closed-loop output impedance, the OP179/OP279 is an The top trace was taken with a 10 nF load and the bottom trace excellent choice for these types of applications. For example, with the 20 Ω, 1 µF snubber network in place. The amount of when sourcing or sinking a 25 mA steady-state load current, the overshot and ringing is dramatically reduced. Table I illustrates a OP179/OP279 exhibits a recovery time of less than 500 ns to few sample snubber networks for large load capacitors. 0.1% for a 10 mA (i.e., 25 mA to 35 mA and 35 mA to 25 mA) step change in load current. A Precision Negative Voltage Reference 10nF LOAD In many data acquisition applications, the need for a precision ONLY 19000 negative reference is required. In general, any positive voltage reference can be converted into a negative voltage reference through the use of an operational amplifier and a pair of matched resistors in an inverting configuration. The disadvantage to that SNUBBER approach is that the largest single source of error in the circuit is IN CIRCUIT 100% the relative matching of the resistors used. 50mV 2(cid:3)s The circuit illustrated in Figure 8 avoids the need for tightly matched resistors with the use of an active integrator circuit. In Figure 6.Overshoot and Ringing Are Reduced by Adding this circuit, the output of the voltage reference provides the a “Snubber” Network in Parallel with the 10 nF Load input drive for the integrator. The integrator, to maintain circuit equilibrium, adjusts its output to establish the proper relation- ship between the reference’s V and GND. Thus, various OUT negative output voltages can be chosen simply by substituting for the appropriate reference IC (see table). To speed up the –8– REV. G

OP179/OP279 ON-OFF settling time of the circuit, R2 can be reduced to The low dropout performance of this circuit is provided by stage 50 kΩ or less. Although the integrator’s time constant chosen U2, one-half of an OP179/OP279 connected as a follower/buffer here is 1 ms, room exists to trade off circuit bandwidth and for the basic reference voltage produced by U1. The low voltage noise by increasing R3 and decreasing C2. The SHUTDOWN saturation characteristic of the OP179/OP279 allows up to 30 mA feature is maintained in the circuit with the simple addition of a of load current in the illustrated use, as a 5 V to 3.3 V converter PNP transistor and a 10 kΩ resistor. One caveat with this with high dc accuracy. In fact, the dc output voltage change for approach should be mentioned: although rail-to-rail output a 30 mA load current delta measures less than 1 mV. This amplifiers work best in the application, these operational ampli- corresponds to an equivalent output impedance of < 0.03 Ω. In fiers require a finite amount (mV) of headroom when required this application, the stable 3.3 V from U1 is applied to U2 to provide any load current. The choice for the circuit’s negative through a noise filter, R1-C1. U2 replicates the U1 voltage supply should take this issue into account. within a few mV, but at a higher current output at V , with OUT1 the ability to both sink and source output current(s)—unlike most IC references. R2 and C2 in the feedback path of U2 U1 VOUT (V) +5V REF192 2.5 provide bias compensation for lowest dc error and additional REF193 3.0 noise filtering. R5 REF196 3.3 C2 SHUTDOWN 10k(cid:8) REF194 4.5 1(cid:3)F Transient performance of the reference/regulator for a 10 mA TTL/CMOS 2N3904 2 step change in load current is also quite good and is determined U1 1Rk3(cid:8) +5V largely by the R5-C5 output network. With values as shown, the 3 6 R4 REF195 1/2 10(cid:8) transient is about 10 mV peak and settles to within 2 mV in 8 µs, GND C1 OP279 –VREF for either polarity. Although room exists for optimizing the 1(cid:3)F 4 transient response, any changes to the R5-C5 network should 10kR(cid:8)1 100kR(cid:8)2 –10V be verified by experiment to preclude the possibility of excessive ringing with some capacitor types. Figure 8.A Negative Precision Voltage Reference That To scale V to another (higher) output level, the optional OUT2 Uses No Precision Resistors Exhibits High Output Current resistor R3 (shown dotted) is added, causing the new V to OUT1 Drive become: A High Output Current, Buffered Reference/Regulator  R2 Many applications require stable voltage outputs relatively close VOUT1=VOUT2×1+ R3 in potential to an unregulated input source. This “low dropout” type of reference/regulator is readily implemented with a rail-to- As an example, for a V = 4.5 V, and V = 2.5 V from a OUT1 OUT2 rail output op amp, and is particularly useful when using a REF192, the gain required of U2 is 1.8 times, so R2 and R3 higher current device such as the OP179/OP279. A typical would be chosen for a ratio of 0.8:1, or 18 kΩ:22.5 kΩ. Note that example is the 3.3 V or 4.5 V reference voltage developed from for the lowest V dc error, the parallel combination of R2 and OUT1 a 5 V system source. Generating these voltages requires a three- R3 should be maintained equal to R1 (as here), and the R2-R3 terminal reference, such as the REF196 (3.3 V) or the REF194 resistors should be stable, close tolerance metal film types. (4.5 V), both of which feature low power, with sourcing outputs The circuit can be used as shown as either a 5 V to 3.3 V reference/ of 30mA or less. Figure 9 shows how such a reference can be regulator, or it can be used with ON/OFF control. By driving outfitted with an OP179/OP279 buffer for higher currents and/ Pin 3 of U1 with a logic control signal as noted, the output is or voltage levels, plus sink and source load capability. switched ON/OFF. Note that when ON/OFF control is used, resistor R4 should be used with U1 to speed ON-OFF switching. VS U2 5V 1/2 OP279 Direct Access Arrangement for Telephone Line Interface 0.1(cid:3)CF1 3.3VVO @UT 310 =mA Finitgeurrfea c1e0 f oilrlu 1s1tr0a tΩes tara 5n sVm oisnsliyo ntr asnyssmtemit/sr.e cIet iavlel otwelse pfuhloln deu lpinleex R2 transmission of signals on a transformer coupled 110 Ω line in R1 1 0 1k%(cid:8) a differential manner. Amplifier A1 provides gain that can be 10k(cid:8) adjusted to meet the modem output drive requirements. Both 1% C2 A1 and A2 are configured to apply the largest possible signal on a 0.1(cid:3)F R3 single supply to the transformer. Because of the OP179/OP279’s C3 0.1(cid:3)F 2 (SEE TEXT) C105(cid:3)F/25V high output current drive and low dropout voltage, the largest 6 TANTALUM signal available on a single 5 V supply is approximately 4.5 V p-p U1 VC 3 REF196 VO3U.3TV2 = R3.43k(cid:8) R5 ian dtoif afe 1re1n0c Ωe atrmanpslimfieisrs itoon e sxytsrtaecmt .t hAem rpelciefiievre A s3ig insa cl ofnrofimgu trhede as OCON/NOTFRFOL 4 C1(cid:3)4F 1(cid:8) transmission line for amplification by A4. A4’s gain can be adjusted INPUT CMOS HI (OR OPEN) = ON in the same manner as A1’s to meet the modem’s input signal LO = OFF VCSOMMON VCOOUMTMON r(Seqinugilree mIne-lnintse. PSatcaknadgaer)d f orremsiastt orre svisatloure as rpraeyrsm. Cit otuhpel eu sthe ios fw SitIhP the OP179/OP279’s 8-lead SOIC footprint and this circuit Figure 9.A High Output Current Reference/Regulator offers a compact, cost-sensitive solution. REV. G –9–

OP179/OP279 P1 The AMP04 is configured for a gain of 100, producing a circuit TAXD JGUASINT R2 sensitivity of 80 mV/Ω. Capacitor C2 is used across the AMP04’s 9.09k(cid:8) Pins 8 and 6 to provide a 16-Hz noise filter. If additional noise TO TELL1IEN:1PEHONE 5R53(cid:8) 21k(cid:8) A1 23 10Rk1(cid:8) 0.C1(cid:3)1F TRATNXSAMIT ftihltee rAinMg Pis0 r4e’qs uinirpeudt, aton porpotvioidnea ld ciaffpearceintotira,l -CmXo, dcaen n boeis eu sreedje acctiroons.s R5 ZO 6.2V 10k(cid:8) A Single-Supply, Balanced Line Driver 110(cid:8) 6.2V 5R54(cid:8) 5V DC The circuit in Figure 12 is a unique line driver circuit topology used in professional audio applications and has been modified T1 R6 10k(cid:8) 7 A2 6 R107k(cid:8) flionre a durtiovmero etixvhei baiutsd iloes asp tphlaicna 0ti.o0n2s%. O dnis tao sritniognle i n1t2o Va s6u0p0p Ωly ,l othade 5 R8 across the entire audio band (not shown). For loads greater than 10(cid:3)F 10k(cid:8) 600 Ω, distortion performance improves to where the circuit R9 R10 exhibits less than 0.002%. The design is a transformerless, balanced 10k(cid:8) 10k(cid:8) P2 RX GAIN transmission system where output common-mode rejection of 2 R13 R14 ADJUST RECEIVE noise is of paramount importance. Like the transformer-based R11 1 10k(cid:8) 9.09k(cid:8) RXA 10k(cid:8) 3 A3 6 2k(cid:8) C2 sliynset edmri,v eeirt haeprp oliucatptiuotn cs awni tbheo suht ocrhteadn gtion gg rtohuen cdir fcouri tu gnabianl aonf c1e.d R12 7 0.1(cid:3)F A1, A2 = 1/2 OP27910k(cid:8) 5 A4 Other circuit gains can be set according to the equation in the A3, A4 = 1/2 OP279 diagram. This allows the design to be easily configured for noninverting, inverting, or differential operation. Figure 10.A Single-Supply Direct Access Arrangement for Modems R3 A Single-Supply, Remote Strain Gage Signal Conditioner 10k(cid:8) C3 TOhPe2 7c9ir ccuaint ibne Fuisgeudr ein 1 a1 1il2lu Vst rsaintegsl ea swuapyp lbyy, 3w5h0ic Ωh tshtrea iOn Pg1a7g9e/ 32 A2 1 R6 5R05(cid:8) 47(cid:3)F VO1 signal conditioning circuit. In this circuit, the OP179/OP279 10k(cid:8) serves two functions: (1) By servoing the output of the REF43’s R2 10k(cid:8) R7 2.5 V output across R1, it provides a 20 mA drive to the 350 Ω 10k(cid:8) 12V strain gage. In this way, small changes in the strain gage pro- 12V 12V duce large differential output voltages across the AMP04’s C1 2 6 R8 ihnaplfu otsf. t(h2e) OTPo1 m79a/xOimPi2z7e9 t hise ccoirncfuigitu’sr eddy ansa ma iscu prapnlyg-es,p tlhitet eorther VIN 22(cid:3)F 3 A1 1 7 A1 5 100k(cid:8) 600R(cid:8)L R9 C2 connected to the AMP04’s REF terminal. Thus, tension or 100k(cid:8) 1(cid:3)F compression in the application can be measured by the circuit. A1, A2 = 1/2 OP279 10Rk1(cid:8) R101k1(cid:8) 1R01k2(cid:8) C4 12V GAIN =RR32 56 A2 7 5R01(cid:8)4 47(cid:3)F VO2 SET: R7, R10, R11 = R2 R13 10k(cid:8) 2 SET: R6, R12, R13 = R3 1 8 3 2.5V 6 REF43 0.1(cid:3)F Figure 12.A Single-Supply, Balanced Line Driver for A1 2 F+ 4 4 Automotive Applications 12V R4 C2 1k(cid:8)0.1(cid:3)F 7 20mA DRIVE 3 1 S+ 8 6 S– CX AMP04 2 4 5 80mVOV/(cid:8) R1 124(cid:8) 100-ft TWISTED PAIR 0.1%, LOW TCR VO BELDEN TYPE 9502 COMMON F– 12V 350(cid:8) 6 STRAIN GAGE R2 7 10k(cid:8) 5 A2 +6V C1 R3 10(cid:3)F 10k(cid:8) A1, A2 = 1/2 OP279 Figure 11.A Single-Supply, Remote Strain Gage Signal Conditioner –10– REV. G

OP179/OP279 A Single-Supply Headphone Amplifier UNITY-GAIN, SALLEN-KEY (VCVS) FILTERS Because of its high speed and large output drive, the OP179/P279 High Pass Configurations makes for an excellent headphone driver, as illustrated in Figure Figure 14a is the HP form of a unity-gain 2-pole SK filter 13. Its low supply operation and rail-to-rail inputs and outputs using an OP179/OP279 section. For this filter and its LP coun- give a maximum signal swing on a single 5 V supply. To ensure terpart, the gain in the passband is inherently unity, and the maximum signal swing available to drive the headphone, the signal phase is noninverting due to the follower hookup. For amplifier inputs are biased to V+/2, which is in this case 2.5 V. simplicity and practicality, capacitors C1-C2are set equal, and The 100 kΩ resistor to the positive supply is equally split into resistors R2-R1are adjusted to a ratio “N,” which provides the two 50 kΩ with their common point bypassed by 10 µF to pre- filter damping “α” as per the design expressions. An HP design vent power supply noise from contaminating the audio signal. starts with the selection of standard capacitor values for C1 and C2, and a calculation of N. R1 and R2 are then calculated as per the figure expressions. +V + 5V In these examples, α (or 1/Q) is set equal to √2, providing a 50k(cid:8) +V + 5V Butterworth (maximally flat) response characteristic. The filter corner frequency is normalized to 1 kHz, with resistor values 50k(cid:8) 10(cid:3)F 1/2 16(cid:8) 220(cid:3)F LEFT shown in both rounded and (exact) form. Various other two-pole OP279 HEADPHONE response shapes are also possible with appropriate selection of LEFT INPUT 10(cid:3)F 50k(cid:8) α. For a given response type (α), frequency can be easily scaled, 100k(cid:8) using proportional R or C values. R1 C1 11k(cid:8) +V 0.01(cid:3)F (11.254k(cid:8)) IN OUT 50k(cid:8) 0.01(cid:3)CF2 3 +VS8 OUP12A79 GIVEN: ALPHA, F 1 50k(cid:8) 10(cid:3)F 1/2 16(cid:8) 220(cid:3)F RIGHT 22kR(cid:8)2 2 4 S E T C A1L =P HCA2 == C2/(N^0.5) = 1/Q OP279 HEADPHONE (22.508k(cid:8)) N = 4/(ALPHA)^2 = R2/R1 RIGHT –VS INPUT 10(cid:3)F 50k(cid:8) R1 = 1/(2*PI*F*C* (N^0.5)) 100k(cid:8) R = R2 R2 = N*R1 1kHz BW SHOWN 0.1(cid:3)F Figure 13.A Single-Supply, Stereo Headphone Driver Zf (HIGH PASS) The audio signal is then ac-coupled to each input through a a. High Pass 10 µF capacitor. A large value is needed to ensure that the 11Rk1(cid:8) C1 20 Hz audio information is not blocked. If the input already has (11.254k(cid:8)) 0.02(cid:3)F IN OUT the proper dc bias, the ac coupling and biasing resistors are not R2 required. A 220 µF capacitor is used at the output to couple the 11k(cid:8) U1B amplifier to the headphone. This value is much larger than that (11.254k(cid:8)) 5 OP279 GIVEN: ALPHA, F 7 used for the input because of the low impedance of the head- C2 6 S E T R A1L =P HRA2 == R2/(M^0.5) = 1/Q phones, which can range from 32 Ω to 600 Ω. An additional 0.01(cid:3)F N = 4/(ALPHA)^2 = C2/C1 16 Ω resistor is used in series with the output capacitor to pro- PICK C1 C1 = M*C1 tect the op amp’s output stage by limiting capacitor discharge R = R1+R2 R = 1/(2*P1*F*C1* (M^0.5)) current. When driving a 48 Ω load, the circuit exhibits less than 1kHz BW SHOWN 0.02% THD+N at low output drive levels (not shown). The 0.1(cid:3)F OP179/OP279’s high current output stage can drive this heavy Zf (LOW PASS) load to 4 V p-p and maintain less than 1% THD+N. b. Low Pass Active Filters Several active filter topologies are useful with the OP179/OP279. Among these are two popular architectures, the familiar Sallen- Figure 14.Two-Pole Unity-Gain Sallen Key HP/LP Filters Key (SK) voltage controlled voltage source (VCVS) and the Low Pass Configurations multiple feedback (MFB) topologies. These filter types can be In the LP SK arrangement of Figure 14b, R and C elements are arranged for high pass (HP), low pass (LP), and band-pass (BP) interchanged, and the resistors are made equal. Here the C2/C1 filters. The SK filter type uses the op amp as a fixed gain voltage ratio “M” is used to set the filter α, as noted. This design is begun follower at unity or a higher gain, while the MFB structure uses with the choice of a standard capacitor value for C1 and a calcu- it as an inverting stage. Discussed here are simplified, 2-pole lation of M, which forces a value of “M × C1” for C2. Then, the forms of these filters, highly useful as system building blocks. value “R” for R1 and R2 is calculated as per the expression. For highest performance, the passive components used for tun- ing active filters deserve attention. Resistors should be 1%, low TC, metal film types of the RN55 or RN60 style, or similar. REV. G –11–

OP179/OP279 Capacitors should be 1% or 2% film types preferably, such as loading can be tempered somewhat by using a small series input polypropylene or polystyrene, or NPO (COG) ceramic for resistance of about 100 Ω, but can still be an issue. smaller values. Somewhat lesser performance is available with the use of polyester capacitors. C1 C2 0.01(cid:3)F 0.01(cid:3)F Parasitic Effects in Sallen-Key Implementations IN OUT Iune sd feosrig Rn1in-gR 2th ceasne cbier cuusietsd, tmo omdienriamteilzye ltohwe (e1ff0e cktΩs oofr Jloehssn)s ovanl- 0.0C13(cid:3)F 33R.62k(cid:8) GIVEN: ALPHA, F AND H (PASSBAND GAIN) noise when critical, with, of course, practical tradeoffs of capaci- 6 ALPHA = 1/Q troesri sstizaen caen,d u enxlepsesn bseia. sD cCur reernrot rcso wmilpl ernessautlito fno ri sl aursgeedr. vTalou easd dof R7.15k(cid:8) 5 U1B7 PCRI13C ==K ACAL1 S,P CTHD2A =/C( (C12 *1VP/AHI*LFU*CE1, )T*H(2E+N(1:/H))) bias compensation in the HP filter of Figure 14a, a feedback OP279 R2 = (H*(2+(1/H)))/(ALPHA*(2*PI*F*C1)) compensation resistor with a value equal to R2 is used, shown R = R2 1kHz BW EXAMPLE SHOWN optionally as Z. This will minimize bias induced offset, reduc- f (NOTE: SEE TEXT ON C1 LOADING ing it to the product of the OP179/OP279’s I and R2. Similar OS 0.1(cid:3)F CONSIDERATIONS) compensation is applied to the LP filter, using a Z resistance of f Zb R1 + R2. Using dc compensation and relatively low filter values, filter output dc errors using the OP179/OP279 will be domi- Figure 15.Two-Pole, High Pass Multiple Feedback Filters nated by V , which is limited to 4 mV or less. A caveat here is OS In this example, the filter gain is set to unity, the corner fre- that the additional resistors increase noise substantially—for example, an unbypassed 10 kΩ resistor generates ≈ 12 nV/√Hz quency is 1 kHz, and the response is a Butterworth type. For applications where dc output offset is critical, bias current com- of noise. However, the resistance can be ac-bypassed to elimi- nate noise with a simple shunt capacitor, such as 0.1 µF. pensation can be used for the amplifier. This is provided by network Z , where R is equal to R2, and the capacitor provides b Sallen-Key Implementations in Single-Supply Applications a noise bypass. The hookups shown illustrate a classical dual supply op amp application, which for the OP179/OP279 would use supplies up Low Pass Configurations to ±5 V. However, these filters can also use the op amp in a Figure 16 is a LP MFB 2-pole filter using an OP179/OP279 single-supply mode, with little if any alteration to the filter itself. section. For this filter, the gain in the pass band is user con- To operate single supply, the OP179/OP279 is powered from figurable over a wide range, and the pass band signal phase is 5 V at Pin 8 with Pin 4 grounded. The input dc bias for the op inverting. Given the design parameters for α, F, and H, a simplified amp must be supplied from a dc source equal to one-half supply, design process is begun by picking a standard value for C2. Then C1and resistors R1-R3are selected as per the relationships or 2.5 V in this case. noted. Optional dc bias current compensation is provided by Z, For the HP section, dc bias is applied to the common end of R2. b where R is equal to the value of R3 plus the parallel equivalent R2 is simply returned to an ac ground that is a well-bypassed value of R1and R2. 2:1 divider across the 5 V source. This can be as simple as a pair of 100 kΩ resistors with a 10 µF bypass cap. The output from R1 R2 the stage is then ac coupled, using an appropriate coupling cap 11.3k(cid:8) 11.3k(cid:8) from U1A to the next stage. For the LP section dc bias is applied IN OUT to the input end of R1, in common with the input signal. This 5.6R23k(cid:8) 0.0C12(cid:3)F G IVAELNP:HA, F AND H (PASSBAND GAIN) dc can be taken from an unbypassed dual 100 kΩ divider across ALPHA = 1/Q the supply, with the input signal ac coupled to the divider and R1. C1 5 7 PICK A STD C2 VALUE, THEN: 0.04(cid:3)F 6 C1 = C2 • (4 • (H +1))/ALPHA^2 Multiple Feedback Filters R1 = ALPHA/(4 • H • PI • F • C2) U1B R2 = H • R1 MFB filters, like their SK relatives, can be used as building OP279 R3 = ALPHA/(4 • (H + 1) • PI • F • C2) blocks as well. They feature LP and HP operation as well, but (R1 R2)+R3 1kHz BW EXAMPLE SHOWN can also be used in a band-pass BP mode. They have the property (NOTE: SEE TEXT ON C1 LOADING of inverting operation in the pass band, since they are based on CONSIDERATIONS) an inverting amplifier structure. Another useful asset is their 0.1(cid:3)F ability to be easily configured for gain. Zb High Pass Configurations Figure 16.Two-Pole, Low-Pass Multiple Feedback Filters Figure 15 shows an HP MFB 2-pole filter using an OP179/ Gain of this filter, H, is set here by resistors R2 and R1 (as in a OP279 section. For this filter, the gain in the pass band is user standard op amp inverter), and can be just as precise as these configurable, and the signal phase is inverting. The circuit uses resistors allow at low frequencies. Because of this flexible and one more tuning component than the SK types. For simplicity, accurate gain characteristic, plus a low range of component capacitors C1 and C3are set to equal standard values, and resis- value spread, this filter is perhaps the most practical of all the tors R1-R2are selected as per the relationships noted. Gain of MFB types. Capacitor ratios are best satisfied by paralleling two this filter, H, is set by capacitors C1 and C2, and this factor or more common types, as in the example, which is a 1 kHz limits both gain selectability and precision. Also, input capaci- unity-gain Butterworth filter. tance C1 makes the load seen by the driving stage highly reactive, and limits overall practicality of this filter. The dire effect of C1 –12– REV. G

OP179/OP279 Band-pass Configurations C1 R1 R3 The MFB band-pass filter using an OP179/OP279 section is 0.01(cid:3)F 31.6k(cid:8) 49.9(cid:8) shown in Figure 17. This filter provides reasonably stable medium HI Q designs for frequencies of up to a few kHz. For best pre- C2 +VS 500Hz AND UP 0.01(cid:3)F U1A dictability and stability, operation should be restricted to 3 OP279 applications where the OP179/OP279 has an open-loop gain 1 in excess of 2Q2 at the filter center frequency. R2 2 VIN 31.6k(cid:8) 4 R1 –VS 26.4k(cid:8) C1 R5 R6 R4 (264k(cid:8)) 0.1(cid:3)F 31.6k(cid:8) 31.6k(cid:8) 49.9(cid:8) IN OUT LO 0.C1(cid:3)2F 53R03k(cid:8) GIVEN: 15R.87k(cid:8) 0.0C13(cid:3)F DC – 500Hz Q, F, AND AO (PASSBAND GAIN) R2 6 ALPHA = 1/Q, H = AO/Q C4 6 1.4k(cid:8) 7 0.02(cid:3)F 7 (1.33k(cid:8)) 5 PICK A STD C1 VALUE, THEN: 5 U1B C2 = C1 U1B OP279 R1 = 1/(H*(2*PI*F*C1)) OP279 R2 = 1/(((2*Q) –H)*(2*PI*F*C1)) R = R3 R3 = Q/(PI*F*C1) +VS +5V EXAMPLE: 60Hz, Q = 10, 0.1(cid:3)F 100(cid:3)F/25V 0.1(cid:3)F AAOO == 11 0F (OORR ' (1 ))' VALUES TO U1 COM Zb 0.1(cid:3)F 100(cid:3)F/25V –VS –5V Figure 17.Two-Pole, Band-pass Multiple Feedback Filters Given the band-pass design parameters for Q, F, and pass band Figure 18.Two-Way Active Crossover Networks gain AO, the design process is begun by picking a standard value In the filter sections, component values have been selected for for C1. Then C2 and resistors R1-R3 are selected as per the good balance between reasonable physical/electrical size, and relationships noted. This filter is subject to a wide range of lowest noise and distortion. DC offset errors can be minimized component values by nature. Practical designs should attempt by using dc compensation in the feedback and bias paths, ac to restrict resistances to a 1 kΩ to 1 MΩ range, with capacitor bypassed with capacitors for low noise. Also, since the network values of 1 µF or less. When needed, dc bias current compensa- input is reactive, it should driven from a directly coupled low tion is provided by Zb, where R is equal to R3. impedance source at VIN. Two-Way Loudspeaker Crossover Networks Figure 19 shows this filter architecture adapted for single-supply Active filters are useful in loudspeaker crossover networks for operation from a 5 V dc source, along the lines discussed reasons of small size, relative freedom from parasitic effects, previously. and the ease of controlling low/high channel drive, plus the con- trolled driver damping provided by a dedicated amplifier. Both Sallen-Key (SK) VCVS and multiple-feedback (MFB) filter 0.0C11(cid:3)F 31R.61k(cid:8) 49R.93(cid:8) 1+0(cid:3)F A5N0D0H UzP architectures are useful in implementing active crossover HI networks (see Reference 4, page 14), and the circuit shown in VIN C0.201(cid:3)F +VSU1A 100k(cid:8) Figure 18 is a two-way active crossover that combines the advan- RIN 3 OP279 tages of both filter topologies. This active crossover exhibits less 100k(cid:8) 1 2 than 0.01% THD+N at output levels of 1 V rms using general R2 31.6k(cid:8) 4 purpose unity gain HP/LP stages. In this two-way example, the CIN LO signal is a dc-500 Hz LP woofer output, and the HI signal is 10(cid:3)F R5 R6 R4 DC – the HP (> 500 Hz) tweeter output. U1B forms an MFB LP 31.6k(cid:8) 31.6k(cid:8) 49.9(cid:8) 10(cid:3)F 500Hz + section at 500 Hz, while U1A provides an SK HP section, cov- LO ering frequencies ≥ 500 Hz. 15R.87k(cid:8) 0.0C13(cid:3)F 100k(cid:8) +VS This crossover network is a Linkwitz-Riley type (see Reference 5, page 14), with a damping factor or α of 2 (also referred to as 100k(cid:8) C0.402(cid:3)F 6 7 “Butterworth squared”). A hallmark of the Linkwitz-Riley type 5 U1B of filter is the fact that the summed magnitude response is flat 100k(cid:8) 10(cid:3)F OP279 across the pass band. A necessary condition for this to happen is the relative signal polarity of the HI output must be inverted with respect to the LOW outputs. If only SK filter sections were +VS +5V used, this requires that the connections to one speaker be reversed 0.1(cid:3)F 100(cid:3)F/25V on installation. Alternately, with one inverting stage used in the TO U1 COM LO channel, this accomplishes the same effect. In the circuit as shown, stage U1B is the MFB LP filter, which provides the necessary polarity inversion. Like the SK sections, it is config- Figure 19.A Single-Supply, Two-Way Active Crossover ured for unity gain and an α of 2. The cutoff frequency is 500 Hz, which complements the SK HP section of U4. REV. G –13–

OP179/OP279 The crossover example frequency of 500 Hz can be shifted lower References on Active Filters and Active Crossover Networks or higher by frequency scaling of either resistors or capacitors. In 1. Sallen, R.P.; Key, E.L., “A Practical Method of Designing configuring the circuit for other frequencies, complementary LP/ RC Active Filters,” IRE Transactions on Circuit Theory, Vol. HP action must be maintained between sections, and component CT-2, March 1955. values within the sections must be in the same ratio. Table II 2. Huelsman, L.P.; Allen, P.E., Introduction to the Theory and provides a design aid to adaptation, with suggested standard Design of Active Filters, McGraw-Hill, 1980. component values for other frequencies. 3. Zumbahlen, H., “Chapter 6: Passive and Active Analog Filtering,” within 1992 Analog Devices Amplifier Applications Table II. RC Component Selection for Various Crossover Guide. Frequencies 4. Zumbahlen, H., “Speaker Crossovers,” within Chapter 8 of R1/C1 (U1A)* 1993 Analog Devices System Applications Guide. Crossover Frequency (Hz) R5/C3 (U1B)** 5. Linkwitz, S., “Active Crossover Networks for Noncoincident 100 160 kΩ/0.01 µF Drivers,” JAES, Vol. 24, #1, Jan/Feb 1976. 200 80.6 kΩ/0.01 µF 319 49.9 kΩ/0.01 µF 500 31.6 kΩ/0.01 µF 1 k 16 kΩ/0.01 µF 2 k 8.06 kΩ/0.01 µF 5 k 3.16 kΩ/0.01 µF 10 k 1.6 kΩ/0.01 µF Table notes (applicable for α = 2). ** For SK stage U1A: R1 = R2, and C1 = C2, etc. ** For MFB stage U1B: R6 = R5, R7 = R5/2, and C4 = 2C3. –14– REV. G

OP179/OP279 OP179/OP279 Spice Macro Model R10 16 98 10 C3 15 16 15.915E-12 * OP179/OP279 SPICE Macro Model Rev. A, 5/94 * * ARG / ADI * ZERO AT 1.5 MHz * * E1 14 98 (9,39) 1E6 * Copyright 1994 by Analog Devices R5 14 18 1E6 * R6 18 98 1 * Refer to “README.DOC” file for License Statement. Use of C4 14 18 106.103E-15 * * this model indicates your acceptance of the terms and pro- * BIAS CURRENT-VS-COMMON-MODE VOLTAGE * visions in the License Statement. * EP 97 0 (99,0) 1 * EN 51 0 (50,0) 1 * Node assignments V3 20 21 1.6 * noninverting input V4 22 23 2.8 R12 97 20 530 * | inverting input R13 23 51 1E3 * | | positive supply D13 15 21 DX * | | | negative supply D14 22 15 DX FIB 98 24 POLY(2) V3 V4 0 –1 1 * | | | | output RIB 24 98 10E3 * | | | | | E3 97 25 POLY(1) (99,39) –1.63 1 .SUBCKT OP179/OP279 3 2 99 50 45 E4 26 51 POLY(1) (39,50) –2.73 1 D15 24 25 DX * D16 26 24 DX * INPUT STAGE AND POLE AT 6 MHz * * * POLE AT 6 MHz * I1 1 50 60.2E-6 G6 98 40 (18,39) 1E 6 Q1 5 2 7 QN R20 40 98 1E6 Q2 6 4 8 QN C10 40 98 26.526E-15 D1 4 2 DX * D2 2 4 DX * OUTPUT STAGE R1 1 7 1.628E3 * R2 1 8 1.628E3 RS1 99 39 6.0345E3 R3 5 99 2.487E3 RS2 39 50 6.0345E3 R4 6 99 2.487E3 RO1 99 45 40 C1 5 6 5.333E-12 RO2 45 50 40 EOS 4 3 POLY(1) (16,39) 0.25E-3 50.118 G7 45 99 (99,40) 25E-3 IOS 2 3 5E-9 G8 50 45 (40,50) 25E-3 GB1 2 98 (24,98) 100E-9 G9 98 60 (45,40) 25E-3 GB2 4 98 (24,98) 100E-9 D9 60 61 DX CIN 2 3 1E-12 D10 62 60 DX * V7 61 98 DC 0 * GAIN STAGE AND DOMINANT POLE AT 16 Hz V8 98 62 DC 0 * FSY 99 50 POLY(2) V7 V8 1.711E-3 1 1 EREF 98 0 (39,0) 1 D11 41 45 DZ G1 98 9 (5,6) 402.124E-6 D12 45 42 DZ R7 9 98 497.359E6 V5 40 41 1.54 C2 9 98 20E-12 V6 42 40 1.54 V1 99 10 0.58 .MODEL DX D() V2 11 50 0.47 .MODEL DZ D(IS=1E-6) D5 9 10 DX .MODEL QN NPN(BF=300) D6 11 9 DX .ENDS * * COMMON-MODE STAGE WITH ZERO AT 10 kHz * ECM 15 98 POLY(2) (3,39) (2,39) 0 0.5 0.5 R9 15 16 1E6 REV. G –15–

OP179/OP279 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead TSSOP 8-Lead Narrow-Body SO (RU-8) (SO-8) 0.122 (3.10) 0.1968 (5.00) 0.114 (2.90) 0.1890 (4.80) G) 2( 8 5 0 0.177 (4.50)0.169 (4.30) 81 5 0.256 (6.50)0.246 (6.25) 000...011054979847 (((043...P208I500N))) 11 00..40065830082.. 22((1142..48730455 ))((65..2800)) 00..00109969 ((00..5205))x 45° C00290–0–1/ 4 0.0040 (0.10) PIN 1 8° 00..000062 ((00..1055))0.02B56S C(0.65) 0.0433 SEPALTAINNGE 0(B.10.S52C070) 00..00119328 ((00..4395)) 00..00009785 ((00..2159)) 0° 00..00510600 ((10..2471)) (1.10) MAX 8(cid:4) 0.028 (0.70) SEPALTAINNGE 00..00101785 ((00..3109)) 0.0079 (0.20)0(cid:4) 0.020 (0.50) 0.0035 (0.090) 5-Lead SOT-23 (RT-5) 0.1220 (3.100) 0.1063 (2.700) PIN 1 3 2 1 0.0709 (1.800) 0.1181 (3.000) 0.0590 (1.500) 4 5 0.0984 (2.500) 0.0374 (0.950) REF 0.0748 (1.900) REF 0.0079 (0.200) 0.0512 (1.300) 0.0571 (1.450) 0.0035 (0.090) 0.0354 (0.900) 0.0354 (0.900) 0.0590 (0.150) 0.0197 (0.500) SPELAANTIENG 100(cid:4)(cid:4) 0.0236 (0.600) 0.0000 (0.000) 0.0118 (0.300) 0.0039 (0.100) NOTE: PACKAGE OUTLINE INCLUSIVE AS SOLDER PLATING. Revision History A. S. U. Location Page N D I Data Sheet changed from REV. F to REV. G. TE N Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 RI P Edits to PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to PACKAGE TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Edits to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 –16– REV. G