a Operational Amplifiers OP196/OP296/OP496 FEATURES PIN CONFIGURATIONS Rail-to-Rail Input and Output Swing Low Power: 60 (cid:1)A/Amplifier 8-Lead Narrow-Body SO 8-Lead Narrow-Body SO Gain Bandwidth Product: 450 kHz Single-Supply Operation: 3 V to 12 V NULL 1 8 NC OUT A 1 8 V+ Low Offset Voltage: 300 (cid:1)V max –IN A 2 7 V+ –IN A 2 7 OUT B OP196 OP296 High Open-Loop Gain: 500 V/mV +IN A 3 6 OUT A +IN A 3 6 –IN B Unity-Gain Stable V– 4 5 NULL V– 4 5 +IN B No Phase Reversal NC = NO CONNECT APPLICATIONS Battery Monitoring Sensor Conditioners Portable Power Supply Control 8-Lead TSSOP Portable Instrumentation 1 8 OUT A V+ –IN A OP296 OUT B +IN A –IN B V– +IN B GENERAL DESCRIPTION 4 5 The OP196 family of CBCMOS operational amplifiers features micropower operation and rail-to-rail input and output ranges. The extremely low power requirements and guaranteed opera- tion from 3 V to 12 V make these amplifiers perfectly suited to monitor battery usage and to control battery charging. Their dynamic performance, including 26 nV/√Hz voltage noise density, recommends them for battery-powered audio applica- 14-Lead Narrow-Body SO tions. Capacitive loads to 200 pF are handled without oscillation. The OP196/OP296/OP496 are specified over the OUT A 1 14 OUT D industrial (–40°C to +125°C) temperature range. 3 V operation –IN A 2 13 –IN D is specified over the 0°C to 125°C temperature range. +IN A 3 12 +IN D V+ 4 OP496 11 V– The single OP196 and the dual OP296 are available in 8-lead +IN B 5 10 +IN C –IN B 6 9 –IN C OUT B 7 8 OUT C 14-Lead TSSOP (RU Suffix) 1 14 OUT A OUT D –IN A –IN D +IN A +IN D V+ OP496 V– +IN B +IN C –IN B –IN C OUT B OUT C 7 8 REV. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Fax: 781/ 14 of 14

OP196/OP296/OP496–SPECIFICATIONS ELECTRICAL SPECIFICATIONS (@ V = 5.0 V, V = 2.5 V, T = 25(cid:2)C, unless otherwise noted.) S CM A Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V OP196G, OP296G, OP496G 35 300 µV OS –40°C ≤ T ≤ +125°C 650 µV A OP296H, OP496H 800 µV –40°C ≤ T ≤ +125°C 1.2 mV A Input Bias Current I –40°C ≤ T ≤ +125°C ±10 ±50 nA B A Input Offset Current I ±1.5 ±8 nA OS –40°C ≤ T ≤ +125°C ±20 nA A Input Voltage Range V 0 5.0 V CM Common-Mode Rejection Ratio CMRR 0 V ≤ V ≤ 5.0 V, CM –40°C ≤ T ≤ +125°C 65 dB A Large Signal Voltage Gain A R = 100 kΩ, VO L 0.30 V ≤ V ≤ 4.7 V, OUT –40°C ≤ T ≤ +125°C 150 200 V/mV A Long-Term Offset Voltage V G Grade, Note 1 550 µV OS H Grade, Note 1 1 mV Offset Voltage Drift ∆V /∆T G Grade, Note 2 1.5 µV/°C OS H Grade, Note 2 2 µV/°C OUTPUT CHARACTERISTICS Output Voltage Swing High V I = +100 µA 4.85 4.92 V OH L I = 1 mA 4.30 4.56 V L I = 2 mA 4.1 V L Output Voltage Swing Low V I = – 36 70 mV OL L I = –1 mA 350 550 mV L I = –2 mA 750 mV L Output Current I ±4 mA OUT POWER SUPPLY Power Supply Rejection Ratio PSRR ±2.5 V ≤ V ≤ ±6 V, S –40°C ≤ T ≤ +125°C 85 dB Supply Current per Amplifier I V = 2.5A V, R = ∞ 60 µA SY OUT L –40°C ≤ T ≤ +125°C 45 80 µA A DYNAMIC PERFORMANCE Slew Rate SR R = 100 kΩ 0.3 V/µs L Gain Bandwidth Product GBP 350 kHz Phase Margin ø 47 Degrees m NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 0.8 µV p-p n Voltage Noise Density e f = 1 kHz 26 nV/√Hz n Current Noise Density i f = 1 kHz 0.19 pA/√Hz n NOTES 1Long-term offset voltage is guaranteed by a 1,000 hour life test performed on three independent lots at 125°C, with an LTPD of 1.3. 2Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta. Specifications subject to change without notice. –2– REV.

OP196/OP296/OP496 ELECTRICAL SPECIFICATIONS (@ V = 3.0 V, V = 1.5 V, T = 25(cid:2)C, unless otherwise noted.) S CM A Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V OP196G, OP296G, OP496G 35 300 µV OS 0°C ≤ T ≤ 125°C 650 µV A OP296H, OP496H 800 µV 0°C ≤ T ≤ 125°C 1.2 mV A Input Bias Current I ±10 ±50 nA B Input Offset Current I ±1 ±8 nA OS Input Voltage Range V 0 3.0 V CM Common-Mode Rejection Ratio CMRR 0 V ≤ V ≤ 3.0 V, CM 0°C ≤ T ≤ 125°C 60 dB A Large Signal Voltage Gain A R = 100 kΩ 80 200 V/mV VO L Long-Term Offset Voltage V G Grade, Note 1 550 µV OS H Grade, Note 1 1 mV Offset Voltage Drift ∆V /∆T G Grade, Note 2 1.5 µV/°C OS H Grade, Note 2 2 µV/°C OUTPUT CHARACTERISTICS Output Voltage Swing High V I = 100 µA 2.85 V OH L Output Voltage Swing Low V I = –100 µA 70 mV OL L POWER SUPPLY Supply Current per Amplifier I V = 1.5 V, R = ∞ 40 60 µA SY OUT L 0°C ≤ T ≤ 125°C 80 µA A DYNAMIC PERFORMANCE Slew Rate SR R = 100 kΩ 0.25 V/µs L Gain Bandwidth Product GBP 350 kHz Phase Margin ø 45 Degrees m NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 0.8 µV p-p n Voltage Noise Density e f = 1 kHz 26 nV/√Hz n Current Noise Density i f = 1 kHz 0.19 pA/√Hz n NOTES 1Long-term offset voltage is guaranteed by a 1,000 hour life test performed on three independent lots at 125°C, with an LTPD of 1.3. 2Offset voltage drift is the average of the 0°C to 25°C delta and the 25°C to 125°C delta. Specifications subject to change without notice. REV. –3– f 1 4

OP196/OP296/OP496 ELECTRICAL SPECIFICATIONS (@ V = 12.0 V, V = 6 V, T = 25(cid:2)C, unless otherwise noted.) S CM A Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V OP196G, OP296G, OP496G 35 300 µV OS 0°C ≤ T ≤ 125°C 650 µV A OP296H, OP496H 800 µV 0°C ≤ T ≤ 125°C 1.2 mV A Input Bias Current I –40°C ≤ T ≤ +125°C ±10 ±50 nA B A Input Offset Current I ±1 ±8 nA OS –40°C ≤ T ≤ +125°C ±15 nA A Input Voltage Range V 0 12 V CM Common-Mode Rejection Ratio CMRR 0 V ≤ V ≤ 12 V, CM –40°C ≤ T ≤ +125°C 65 dB A Large Signal Voltage Gain A R = 100 kΩ 300 1000 V/mV VO L Long-Term Offset Voltage V G Grade, Note 1 550 µV OS H Grade, Note 1 1 mV Offset Voltage Drift ∆V /∆T G Grade, Note 2 1.5 µV/°C OS H Grade, Note 2 2 µV/°C OUTPUT CHARACTERISTICS Output Voltage Swing High V I = 100 µA 11.85 V OH L I = 1 mA 11.30 V L Output Voltage Swing Low V I = – 70 mV OL L I = –1 mA 550 mV L Output Current I ±4 mA OUT POWER SUPPLY Supply Current per Amplifier I V = 6 V, R = ∞ 60 µA SY OUT L –40°C ≤ T ≤ +125°C 80 µA A Supply Voltage Range V 3 12 V S DYNAMIC PERFORMANCE Slew Rate SR R = 100 kΩ 0.3 V/µs L Gain Bandwidth Product GBP 450 kHz Phase Margin ø 50 Degrees m NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 0.8 µV p-p n Voltage Noise Density e f = 1 kHz 26 nV/√Hz n Current Noise Density i f = 1 kHz 0.19 pA/√Hz n NOTES 1Long-term offset voltage is guaranteed by a 1,000 hour life test performed on three independent lots at 125°C, with an LTPD of 1.3. 2Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta. Specifications subject to change without notice. –4– REV.

OP196/OP296/OP496 ABSOLUTE MAXIMUM RATINGS1 SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 V DifferentialInputVoltage2 . . . . . . . . . . . . . . . . . . . . . . . .15V Output Short Circuit Duration . . . . . . . . . . . . . . . . .Indefinite Storage Temperature Range S, RU Package . . . . . . . . . . . . . . . . . . . .–65°C to +150°C Operating Temperature Range OP196G, OP296G, OP496G, H . . . . . . . –40°C to +125°C Junction Temperature Range S, RU Package . . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 60sec) . . . . . . . . 300°C Package Type (cid:3) 3 (cid:3) Unit JA JC 8-Lead SOIC 158 43 °C/W 8-Lead TSSOP 240 43 °C/W 14-Lead SOIC 120 36 °C/W 14-Lead TSSOP 180 35 °C/W NOTES 1Absolute maximum ratings apply to 2For supply voltages less than 15V, the absolute maximum input voltage is equal to the supply voltage. 3θ is specified for the worst case conditions JA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the OP196/OP296/OP496 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, ESD SENSITIVE DEVICE proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. –5–

OP196/OP296/OP496–Typical Performance Characteristics 250 25 VS = 5V 200 TVAS == 235V(cid:2)C 20 TVAC M= =– 420.5(cid:2)CV TO (cid:4)125(cid:2)C mplifiers150 COUNT = 400 mplifiers 15 A A Y – Y – T T TI100 TI 10 N N A A U U Q Q 50 5 0 0 –250 –200 –150 –100 –50 0 50 100 150 200 250 –4.0 –3.5 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 INPUT OFFSET VOLTAGE – (cid:1)V INPUT OFFSET DRIFT, TCVOS – (cid:1)V/(cid:2)C TPC 1.Input Offset Voltage Distribution TPC 4.Input Offset Voltage Distribution (TCV ) OS 250 25 VS = 12V VS = 5V VCM = 6V 200 TA = 25(cid:2)C 20 TA = –40(cid:2)C TO (cid:4)125(cid:2)C COUNT = 400 mplifiers150 mplifiers 15 A A Y – Y – T T TI100 TI 10 N N A A U U Q Q 50 5 0 0 –250 –200 –150 –100 –50 0 50 100 150 200 250 –4.0 –3.5 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 INPUT OFFSET VOLTAGE – (cid:1)V INPUT OFFSET DRIFT, TCVOS – (cid:1)V/(cid:2)C TPC 2.Input Offset Voltage Distribution TPC 5.Input Offset Voltage Distribution (TCV ) OS 250 600 mplifiers210500 TVCASO =U= N2152T(cid:2)V C= 400 (cid:1)AGE – V 240000 3VVC M = VVS2S 12V – A OLT Y V NTIT100 SET 0 QUA T OFF 50 PU–200 N I 0 –400 –250 –200 –150 –100 –50 0 50 100 150 200 250 –75 –50 –25 0 25 50 75 100 125 150 INPUT OFFSET VOLTAGE – (cid:1)V TEMPERATURE – (cid:2)C TPC 3. Input Offset Voltage Distribution TPC 6.Input Offset Voltage vs. Temperature –6– REV.

OP196/OP296/OP496 25 1000 VS = 5V VCM = 2.5V 20 VS = (cid:5)1.5V nA mV – – 100 T E SOURCE N15 G E A R T UR OL SINK C V S 10 T T BAI UTPU 10 U O P N 5 I 0 1 –75 –50 –25 0 25 50 75 100 125 150 0.001 0.01 0.1 1 10 TEMPERATURE – (cid:2)C LOAD CURRENT – mA TPC 7.Input Bias Current vs. Temperature TPC 10.Output Voltage to Supply Rail vs. Load Current 16 1000 VS = (cid:5)2.5V NT – nA12 E – mV100 SOURCE E G R A R T CU OL SINK AS T V T BI 8 TPU 10 U U P O N I 4 1 2 3 5 12 14 0.001 0.01 0.1 1 10 SUPPLY VOLTAGE – V LOAD CURRENT – mA TPC 8.Input Bias Current vs. Supply Voltage TPC 11.Output Voltage to Supply Rail vs. Load Current 40 1000 VS = (cid:5)2.5V 30 TA = 25(cid:2)C VS = (cid:5)6V NT – nA 2100 E – mV100 SOURCE E G R A R T CU 0 OL SINK AS T V T BI–10 TPU 10 U U NP–20 O I –30 –40 1 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 0.001 0.01 0.1 1 10 COMMON-MODE VOLTAGE – V LOAD CURRENT – mA TPC 9.Input Bias Current vs. Common-Mode Voltage TPC 12.Output Voltage to Supply Rail vs. Load Current REV. –7–

OP196/OP296/OP496 4.95 90 IL = 100(cid:1)A 80 VS = (cid:5)2.5V TA = –40(cid:2)C 4.70 70 V GE – IL = 1mA – dB60 GAIN A 4.45 N 50 LT AI O G T V OP 40 0 OUTPUH 4.2 VS = 5V IL = 2mA OPEN-LO3200 PHASE 4950 (cid:2)HIFT – C O S V 3.85 10 135E S A 0 180H P 3.7 –10 225 –75 –50 –25 0 25 50 75 100 125 150 10 100 1k 10k 100k 1M TEMPERATURE – (cid:2)C FREQUENCY – Hz TPC 13.Output Voltage Swing vs. Temperature TPC 16.Open-Loop Gain and Phase vs. Frequency (No Load) 0.80 90 VS = 5V 80 VS = (cid:5)2.5V TA = 125(cid:2)C 0.60 70 V E – IL = –1mA dB60 G – GAIN LTA 0.50 AIN 50 O G T V OP 40 0 V OUTPUOL00..3100 OPEN-LO321000 PHASE 4913505(cid:2)E SHIFT – C S A IL = –100(cid:1)A 0 180PH –10 225 –75 –50 –25 0 25 50 75 100 125 150 10 100 1k 10k 100k 1M TEMPERATURE – (cid:2)C FREQUENCY – Hz TPC 14.Output Voltage Swing vs. Temperature TPC 17.Open-Loop Gain and Phase vs. Frequency (No Load) 90 950 80 VS = (cid:5)2.5V VS = 5V TA = 25(cid:2)C 0.3V < VO < 4.7V 70 800 RL = 100k(cid:6) – dB60 GAIN mV N 50 V/ 650 AI – G N P 40 0 AI O G OPEN-LO3200 PHASE 4950 (cid:2)SHIFT – C EN-LOOP 500 10 135SE OP 350 A 0 180H P –10 225 200 10 100 1k 10k 100k 1M –75 –50 –25 0 25 50 75 100 125 150 FREQUENCY – Hz TEMPERATURE – (cid:2)C TPC 15.Open-Loop Gain and Phase vs. Frequency TPC 18.Open-Loop Gain vs. Temperature (No Load) –8– REV.

OP196/OP296/OP496 600 160 140 VS = (cid:5)2.5V 500 VS = 5V TA = 25(cid:2)C TA = 25(cid:2)C 120 ALL CHANNELS V m 100 V/ 400 N – B 80 GAI 300 – d 60 P R O R O M 40 L C EN- 200 20 P O 0 100 –20 0 –40 150 100 50 10 2 1 100 1k 10k 100k 1M 10M LOAD – k(cid:6) FREQUENCY – Hz TPC 19.Open-Loop Gain vs. Resistive Load TPC 22.CMRR vs. Frequency 70 160 60 VRSL == (cid:5)102k.5(cid:6)V 140 TVAS == 255V(cid:2)C 50 TA = 25(cid:2)C 120 B d40 100 – AIN 30 dB 80 OP G20 RR – 60 +PSRR O S ED-L10 P 40 –PSRR OS 0 20 L C–10 0 –20 –20 –30 –40 10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M 10M FREQUENCY – Hz FREQUENCY – Hz TPC 20.Closed-Loop Gain vs. Frequency TPC 23.PSRR vs. Frequency 1000 6 900 VS = (cid:5)2.5V (cid:6)NCE – 870000 TVAS == 2(cid:5)52(cid:2)C.5V WING – V 45 RVAILVN === 1150V0 kp(cid:6)-p A600 S ED ACL = 10 UT P500 P 3 M T TPUT I400 ACL = 1 UM OU 2 U300 M O XI A 200 M 1 100 0 0 100 1k 10k 100k 1M 1k 10k 100k 1M FREQUENCY – Hz FREQUENCY – Hz TPC 21.Output Impedance vs. Frequency TPC 24.Maximum Output Swing vs. Frequency REV. –9–

OP196/OP296/OP496 90 0.6 80 Hz0.5 TVVACS M== =2(cid:5) 502(cid:2)V.C5V (cid:1)R – A7600 VS = 12V TY – pA/0.4 MPLIFIE50 E DENSI0.3 A S I/SY40 VS = 5V T NOI0.2 N 30 VS = 3V RRE0.1 U C 20 0 –75 –50 –40 –25 0 25 50 75 85 100 125 150 1 10 100 1k TEMPERATURE – (cid:2)C FREQUENCY – Hz TPC 25.Supply Current/Amplifier vs. Temperature TPC 28.Input Bias Current Noise Density vs. Frequency 55 10 TA = 25(cid:2)C 8 VS = (cid:5)6V TA = 25(cid:2)C 6 50 TO 0.1% (cid:4)OUTPUT SWING 4 (cid:1)ER – A 45 TEP – V 20 MPLIFI NPUT S–2 A I–4 /SY40 – OUTPUT SWING I –6 –8 35 –10 1 3 5 7 9 11 12 13 0 5 10 15 20 25 30 SUPPLY VOLTAGE – V SETTLING TIME – (cid:1)s TPC 26.Supply Current/Amplifier vs. Supply Voltage TPC 29.Settling Time to 0.1% vs. Step Size 80 VS = (cid:5)2.5V Hz 70 TVAC M= =2 50(cid:2)VC 2mV 1s V/ 60 100 n 90 – TY 50 SI N DE 40 E S NOI 30 10 VS = (cid:5)2.5V E 0% AV = 10k AG 20 en = 0.8(cid:1)V p-p T L VO 10 0 1 10 100 1k FREQUENCY – Hz TPC 27.Voltage Noise Density vs. Frequency TPC 30.0.1 Hz to 10 Hz Noise –10– REV.

OP196/OP296/OP496 VS = (cid:5)2.5V 100mV 100 100 RL = 10k(cid:6) 90 90 VS = 2.5V AV = 1 10 RL = 10k(cid:6) 10 0V 0% CL = 100pF 0% 20mV TA = 25(cid:2)C 2(cid:1)s 1V 10(cid:1)s TPC 31.Small Signal Transient Response TPC 33.Large Signal Transient Response VS = (cid:5)2.5V 100mV100 100 RL = 100k(cid:6) 90 90 VS = (cid:5)2.5V AV = 1 0V 01%0 RCLL == 110000kp(cid:6)F 01%0 20mV TA = 25(cid:2)C 2(cid:1)s 1V 10(cid:1)s TPC 32.Small Signal Transient Response TPC 34.Large Signal Transient Response CH A: 40.0(cid:1)V FS 5.00(cid:1)V/DIV MKR: 36.8(cid:1)V/Hz 0Hz 10Hz MKR: 1.00Hz BW: 145mHz TPC 35.1/f Noise Corner, V = ±5 V, A = 1,000 S V VCC R1 I1 R2 R6 R7 I4 R8 I5 D3 Q11 QL1 D9 Q22 Q12 Q5 Q6 D4 Q17 2x 2x D8 Q21 QC1 Q3 Q4 CC2 1x 1x OUT 1x 1x Q13 CF1 CF2 Q14 Q7 Q8 2x 2x Q9 Q10 D5 Q18 D6 Q19 +IN Q1 Q2 QC2 2x 1x R5 Q23 –IN CC1 R9 R3A R4A I2 I3 Q16 Q20 Q15 D7 R3B R4B 1.5x D10 1x VEE 1* 5* *OP196 ONLY TPC 36.Simplified Schematic REV. –11–

OP196/OP296/OP496 APPLICATIONS INFORMATION the supply rails. In the circuit of Figure 2, the source ampli- Functional Description tude is ±15 V, while the supply voltage is only ±5 V. In this The OP196 family of operational amplifiers is comprised of single- case, a 2 kΩ source resistor limits the input current to 5 mA. supply, micropower, rail-to-rail input and output amplifiers. Input offset voltage (V ) is only 300 µV maximum, while the output OS will deliver ±5 mA to a load. Supply current is only 50 µA, while 5V VS = 5V bandwidth is over 450 kHz and slew rate is 0.3 V/µs. TPC 36 is 100 AV = 1 a simplified schematic of the OP196—it displays the novel cir- DIV 90 VIN V/ 0 cuit design techniques used to achieve this performance. – 5 E Input Overvoltage Protection G A The OPx96 family of op amps uses a composite PNP/NPN LT VOUT O input stage. Transistor Q1 in Figure 36 has a collector-base V 10 0 0% voltage of 0 V if +IN = V . If +IN then exceeds V , the junc- EE EE 5V 1ms tion will be forward biased and large diode currents will flow, which may damage the device. The same situation applies to TIME – 1ns/DIV +IN on the base of transistor Q5 being driven above V . There- CC fore, the inverting and noninverting inputs must not be driven Figure 2.Output Voltage Phase Reversal Behavior above or below either supply rail unless the input current is Input Offset Voltage Nulling limited. The OP196 provides two offset adjust terminals that can be Figure 1 shows the input characteristics for the OPx96 family. used to null the amplifier’s internal V . In general, operational OS This photograph was generated with the power supply pins amplifier terminals should never be used to adjust system offset connected to ground and a curve tracer’s collector output drive voltages. A 100 kΩ potentiometer, connected as shown in Fig- connected to the input. As shown in the figure, when the input ure 3, is recommended to null the OP196’s offset voltage. Offset voltage exceeds either supply by more than 0.6 V, internal nulling does not adversely affect TCV performance, providing OS pn-junctions energize and permit current flow from the inputs that the trimming potentiometer temperature coefficient does to the supplies. If the current is not limited, the amplifier may not exceed ±100 ppm/°C. be damaged. To prevent damage, the input current should be limited to no more than 5 mA. V+ 8 2 7 6 OP196 6 mA 419000 3 5 4 – 1 T 2 N E 100k(cid:6) R 0 R U C–2 V– T PU–4 10 Figure 3.Offset Nulling Circuit IN–6 0% Driving Capacitive Loads –8 OP196 family amplifiers are unconditionally stable with capaci- –1.5 –1 –0.5 0 0.5 1 1.5 tive loads less than 170 pF. When driving large capacitive loads INPUT VOLTAGE – V in unity-gain configurations, an in-the-loop compensation Figure 1.Input Overvoltage I-V Characteristics of the technique is recommended, as illustrated in Figure 4. OPx96 Family Output Phase Reversal RG RF Some other operational amplifiers designed for single-supply VIN CF operation exhibit an output voltage phase reversal when their inputs are driven beyond their useful common-mode range. Typically for single-supply bipolar op amps, the negative supply RX OP296 VOUT determines the lower limit of their common-mode range. With CL these common-mode limited devices, external clamping diodes are required to prevent input signal excursions from exceeding RO RG the device’s negative supply rail (i.e., GND) and triggering RX = R F WHERE RO = OPEN-LOOP OUTPUT RESISTANCE output phase reversal. The OPx96 family of op amps is free from output phase reversal CF = I + ( | A I C L | ) ( R F R + F R G ) CL RO effects due to its novel input structure. Figure 2 illustrates the performance of the OPx96 op amps when the input is driven Figure 4.In-the-Loop Compensation Technique for beyond the supply rails. As previously mentioned, amplifier Driving Capacitive Loads input current must be limited if the inputs are driven beyond –12– REV.

OP196/OP296/OP496 A Micropower False-Ground Generator same potential and no current flows in R1. Since there is no Some single supply circuits work best when inputs are biased current flow in R1, the same condition must exist in R2; thus, above ground, typically at 1/2 of the supply voltage. In these the output of the circuit tracks the input signal. When the input cases, a false-ground can be created by using a voltage divider signal is below 0 V, the output voltage of A1 is forced to 0 V. buffered by an amplifier. One such circuit is shown in Figure 5. This condition now forces A2 to operate as an inverting voltage follower because the noninverting terminal of A2 is also at 0 V. This circuit will generate a false-ground reference at 1/2 of the supply voltage, while drawing only about 55 µA from a 5 V The output voltage of VOUTA is then a full-wave rectified supply. The circuit includes compensation to allow for a 1 µF version of the input signal. A resistor in series with A1’s noninverting input protects the ESD diodes when the input bypass capacitor at the false-ground output. The benefit of a signal goes below ground. large capacitor is that not only does the false-ground present a very low dc resistance to the load, but its ac impedance is low as well. Square Wave Oscillator The oscillator circuit in Figure 7 demonstrates how a rail-to-rail 5V OR 12V output swing can reduce the effects of power supply variations 10k(cid:6) on the oscillator’s frequency. This feature is especially valuable 240k(cid:6) 0.022(cid:1)F in battery powered applications, where voltage regulation may not be available. The output frequency remains stable as the supply voltage changes because the RC charging current, which 2 7 100(cid:6) is derived from the rail-to-rail output, is proportional to the OP196 6 2.5V OR 6V supply voltage. Since the Schmitt trigger threshold level is also 3 4 1(cid:1)F proportional to supply voltage, the frequency remains relatively 240k(cid:6) 1(cid:1)F independent of supply voltage. For a supply voltage change from 9 V to 5 V, the output frequency only changes about 4 Hz. The slew rate of the amplifier limits the oscillation frequency to Figure 5.A Micropower False-Ground Generator a maximum of about 200 Hz at a supply voltage of 5 V. Single-Supply Half-Wave and Full-Wave Rectifiers An OP296, configured as a voltage follower operating from a V+ single supply, can be used as a simple half-wave rectifier in low frequency (<400 Hz) applications. A full-wave rectifier can be 100k(cid:6) 59k(cid:6) configured with a pair of OP296s as illustrated in Figure 6. 3 8 10R01k(cid:6) 10R02k(cid:6) 100k(cid:6) 1 FREQ OUT 2 4 1/2 2k(cid:6) 5V 6 VOUTA R OOPP249966/ fOSC = R 1 C < 200Hz @ V+ = 5V 2Vp-p 3 8 A2 7 FULL-WAVE <500Hz A1 1 5 1/2 RECTIFIED C 2 4 1/2 OP296 OUTPUT Figure 7.Square Wave Oscillator Has Stable Frequency OP296 VOUTB HALF-WAVE Regardless of Supply Voltage Changes RECTIFIED OUTPUT A 3 V Low Dropout, Linear Voltage Regulator Figure 8 shows a simple 3 V voltage regulator design. The regu- 1V 500mV 500µs lator can deliver 50 mA load current while allowing a 0.2 V dropout voltage. The OP296’s rail-to-rail output swing easily 100 INPUT 90 drives the MJE350 pass transistor without requiring special drive circuitry. With no load, its output can swing to less than VOUTB the pass transistor’s base-emitter voltage, turning the device (HALF-WAVE nearly off. At full load, and at low emitter-collector voltages, the OUTPUT) f = 500Hz transistor beta tends to decrease. The additional base current is 10 VOUTA 0% easily handled by the OP296 output. (FULL-WAVE OUTPUT) 500mV The AD589 provides a 1.235 V reference voltage for the regula- tor. The OP296, operating with a noninverting gain of 2.43, Figure 6.Single-Supply Half-Wave and Full-Wave drives the base of the MJE350 to produce an output voltage of Rectifiers Using an OP296 3.0 V. Since the MJE350 operates in an inverting (common- The circuit works as follows: When the input signal is above emitter) mode, the output feedback is applied to the OP296’s 0 V, the output of amplifier A1 follows the input signal. Since noninverting input. the noninverting input of amplifier A2 is connected to A1’s output, op amp loop control forces A2’s inverting input to the same potential. The result is that both terminals of R1 are at the REV. –13–

OP196/OP296/OP496 IL < 50mA The next two DACs, B and C, sum their outputs into the other MJE 350 OP296 amplifier. In this circuit DAC C provides the coarse VO 5V TO 3V.2IVN 44.2k(cid:6) 100(cid:1)F output voltage setting and DAC B is used for fine adjustment. 1% The insertion of R1 in series with DAC B attenuates its contri- 8 3 bution to the voltage sum node at the DAC C output. 1/2 30.9k(cid:6) 1 OP296 1% A High-Side Current Monitor 4 2 In the design of power supply control circuits, a great deal of 1000pF design effort is focused on ensuring a pass transistor’s long-term 43k(cid:6) 1.235V reliability over a wide range of load current conditions. As a result, monitoring and limiting device power dissipation is of prime AD589 importance in these designs. The circuit illustrated in Figure 11 is an example of a 5 V, single-supply high-side current monitor Figure 8.3 V Low Dropout Voltage Regulator that can be incorporated into the design of a voltage regulator Figure 9 shows the regulator’s recovery characteristics when its with fold-back current limiting or a high current power supply output underwent a 20 mA to 50 mA step current change. with crowbar protection. This design uses an OP296’s rail-to- rail input voltage range to sense the voltage drop across a 0.1 Ω current shunt. A p-channel MOSFET is used as the feedback 2V STEP 50mA element in the circuit to convert the op amp’s differential input CURRENT 100 voltage into a current. This current is then applied to R2 to gen- CONTROL 90 WAVEFORM 30mA erate a voltage that is a linear representation of the load current. The transfer equation for the current monitor is given by: R  OUTPUT 10 Monitor Output =R2× SREN1SE×IL 0% 10mV 50µs For the element values shown, the Monitor Output’s transfer characteristic is 2.5 V/A. Figure 9.Output Step Load Current Recovery Buffering a DAC Output R0S.E1N(cid:6)SE IL Multichannel TrimDACs® such as the AD8801/AD8803, are 5V 5V 5V widely used for digital nulling and similar applications. These R1 DACs have rail-to-rail output swings, with a nominal output 100(cid:6) 3 8 resistance of 5 kΩ. If a lower output impedance is required, an OP1/2296 1 OP296 amplifier can be added. Two examples are shown in 2 4 Figure 10. One amplifier of an OP296 is used as a simple buffer S to reduce the output resistance of DAC A. The OP296 provides M1 G 3N163 rail-to-rail output drive while operating down to a 3 V supply MONITOR D OUTPUT and requiring only 50 µA of supply current. R2 2.49k(cid:6) 5V Figure 11.A High-Side Load Current Monitor VREFH VDD OP296 A Single-Supply RTD Amplifier VH The circuit in Figure 12 uses three op amps on the OP496 to VL SIMPLE BUFFER produce a bridge driver for an RTD amplifier while operating 0V TO 5V +4.983V from a single 5 V supply. The circuit takes advantage of the VH +1.1mV OP496’s wide output swing to generate a bridge excitation VL R1 voltage of 3.9 V. An AD589 provides a 1.235 V reference for VH 100k(cid:6) the bridge current. Op amp A1 drives the bridge to maintain SUMMER CIRCUIT VL WITH FINE TRIM 1.235 V across the parallel combination of the 6.19 kΩ and AD8801/ ADJUSTMENT 2.55 MΩ resistors, which generates a 200 µA current source. AD8803 This current divides evenly and flows through both halves of VREFL GND the bridge. Thus, 100 µA flows through the RTD to generate DIGITAL INTERFACING an output voltage which is proportional to its resistance. For OMITTED FOR CLARITY improved accuracy, a 3-wire RTD is recommended to balance Figure 10.Buffering a TrimDAC OutputTPC the line resistance in both 100 Ω legs of the bridge. TrimDAC is a registered trademark of Analog Devices Inc. –14– REV.

OP196/OP296/OP496 Amplifiers A2 and A3 are configured in a two op amp instru- 200(cid:6) GAIN = 259 mentation amplifier configuration. For ease of measurement, 10-TURNS the IA resistors are chosen to produce a gain of 259, so that 5V 26.7k(cid:6) 26.7k(cid:6) 1/4 each 1°C increase in temperature results in a 10 mV increase in OP496 1R00T(cid:6)D 1O/P4496 A3 VOUT twhied tohu otpf utth ev oalmtapglei.f iTero i sr eldimuictee dm. eAa s0u.r1e mµFe ncta pnaocisiteo, rt,h ceo bnannedct-ed 2.55M(cid:6) 100(cid:6) A2 in parallel with the 100 kΩ resistor on amplifier A3, creates a 1/4 392(cid:6) 392(cid:6) 100k(cid:6) pole at 16 Hz. 6.17k(cid:6) OP496 20k(cid:6) 100k(cid:6) A1 0.1(cid:1)F AD589 37.4k(cid:6) NALOLT ER:ESISTORS 1% OR BETTER 5V Figure 12.A Single-Supply RTD Amplifier * OP496 SPICE Macro-model REV. C, 5/95 CIN 1 2 1P * ARG / ADSC * * * GAIN STAGE * Copyright 1995 by Analog Devices, Inc. * * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 * Refer to “README.DOC” file for License Statement. G1 98 15 POLY(2) (6,5) (13,12) 0 10U10U * Use of this model indicates your acceptance of the R10 15 98 251.641MEG * terms and provisions in the License Statement. CC 15 49 8P * D1 15 99 DX * Node assignments D2 50 15 DX * Noninverting input * * Inverting input * COMMON-MODE STAGE * Positive supply * * Negative supply ECM 16 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 * Output R11 16 17 1MEG * R12 17 98 10 * * .SUBCKT OP496 1 2 99 50 49 * OUTPUT STAGE * * ISY 99 50 20U * INPUT STAGE EIN 35 50 POLY(1) (15,98) 1.42735 1 * Q24 37 35 36 50 QN 1 IREF 21 50 1U QD4 37 37 38 99 QP 1 QB1 21 21 99 99 QP 1 Q27 40 37 38 99 QP 1 QB2 22 21 99 99 QP 1 R5 36 39 150K QB3 4 21 99 99 QP 1.5 R6 99 38 45K QB4 22 22 50 50 QN 2 Q26 39 42 50 50 QN 3 QB5 11 22 50 50 QN 3 QD5 40 40 39 50 QN 1 Q1 5 4 7 50 QN 2 Q28 41 40 44 50 QN 1 Q2 6 4 8 50 QN 2 QL1 37 41 99 99 QP 1 Q3 4 4 7 50 QN 1 R7 99 41 10.7K Q4 4 4 8 50 QN 1 I4 99 43 2U Q5 50 1 7 99 QP 2 QD7 42 42 50 50 QN 2 Q6 50 3 8 99 QP 2 QD6 43 43 42 50 QN 2 EOS 3 2 POLY(1) (17,98) 35U 1 Q29 47 43 44 50 QN 1 Q7 99 1 9 50 QN 2 Q30 44 45 50 50 QN 1.5 Q8 99 3 10 50 QN 2 QD10 45 46 50 50 QN 1 Q9 12 11 9 99 QP 2 R9 45 46 175 Q10 13 11 10 99 QP 2 Q31 46 47 48 99 QP 1 Q11 11 11 9 99 QP 1 QD8 47 47 48 99 QP 1 Q12 11 11 10 99 QP 1 QD9 48 48 51 99 QP 5 R1 99 5 50K R8 99 51 2.9K R2 99 6 50K I5 99 46 1U R3 12 50 50K Q32 49 48 99 99 QP 10 R4 13 50 50K Q33 49 44 50 50 QN 4 IOS 1 2 0.75N .MODEL DX D() C10 5 6 3.183P .MODEL QN NPN(BF=120VAF=100) C11 12 13 3.183P .MODEL QP PNP(BF=80 VAF=60) .ENDS REV. –15–

OP196/OP296/OP496 OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA C(RINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure13. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 14 8 6.20 (0.2441) 3.80 (0.1496) 1 7 5.80 (0.2283) 1.27 (0.0500) 0.50 (0.0197) BSC 1.75 (0.0689) 0.25 (0.0098) 45° 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) PLANE 0.25 (0.0098) 1.27 (0.0500) 0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157) COMPLIANTTO JEDEC STANDARDS MS-012-AB C(RINOEFNPETARRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 060606-A Figure 14. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) –18– REV. E

OP196/OP296/OP496 3.10 3.00 2.90 8 5 4.50 4.40 6.40 BSC 4.30 1 4 PIN 1 0.65 BSC 0.15 1.20 0.05 MAX 8° COPLANARITY 0.30 SEATING 0.20 0° 0.75 0.10 0.19 PLANE 0.09 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AA Figure 15. 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8) Dimensions shown in millimeters 5.10 5.00 4.90 14 8 4.50 4.40 6.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.00 1M.2A0X 0.20 0.80 0.09 0.75 0.15 8° 0.60 0.05 0.30 SPELAATNIENG 0° 0.45 COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 061908-A Figure 16. 14-Lead Thin Shrink Small Outline Package (RU-14) Dimensions shown in millimeters REV. E –17–

OP196/OP296/OP496 ORDERING GUIDE Model1, 2 Temperature Range Package Description Package Option OP196GSZ −40°C to +85°C (Ambient) 8-Lead SOIC_N R-8 OP196GSZ-REEL −40°C to +85°C (Ambient) 8-Lead SOIC_N R-8 OP196GSZ-REEL7 −40°C to +85°C (Ambient) 8-Lead SOIC_N R-8 OP296GSZ −40°C to +85°C (Ambient) 8-Lead SOIC_N R-8 OP296GSZ-REEL −40°C to +85°C (Ambient) 8-Lead SOIC_N R-8 OP296GSZ-REEL7 −40°C to +85°C (Ambient) 8-Lead SOIC_N R-8 OP296HRUZ-REEL −40°C to +85°C (Ambient) 8-Lead TSSOP RU-8 OP496GS −40°C to +85°C (Ambient) 14-Lead SOIC_N R-14 OP496GS-REEL −40°C to +85°C (Ambient) 14-Lead SOIC_N R-14 OP496GS-REEL7 −40°C to +85°C (Ambient) 14-Lead SOIC_N R-14 OP496GSZ −40°C to +85°C (Ambient) 14-Lead SOIC_N R-14 OP496GSZ-REEL −40°C to +85°C (Ambient) 14-Lead SOIC_N R-14 OP496GSZ-REEL7 −40°C to +85°C (Ambient) 14-Lead SOIC_N R-14 OP496HRUZ-REEL −40°C to +85°C (Ambient) 14-Lead TSSOP RU-14 1 Z = RoHS Compliant Part. 2 Note OP496GS, OP496GS-REEL, and OP496GS-REEL7 are not RoHS compliant parts. –18– REV. E

OP196/OP296/OP496 REVISION HISTORY 12/10—Rev. C to Rev. D 9/11—Rev. D to Rev. E Change to Data Sheet Title .............................................................. 1 Deleted DIP Pin Configuration Figures ......................................... 1 Changes to General Description Section ....................................... 1 Changes to Absolute Maximum Ratings Table and Package Changes to Electrical Specifications Table (@V = 5.0 V), S Type Table, Moved Ordering Guide ............................................... 5 Output Voltage Swing High and Output Swing Low Parameters, Updated Outline Dimensions ........................................................ 16 Conditions Column .......................................................................... 2 Changes to Ordering Guide ........................................................... 16 Change to Electrical Specifications Table (@V = 12.0 V), S Output Swing Low Parameter, Conditions Column .................... 4 Changes to Ordering Guide ........................................................... 18 1/02—Rev. B to Rev. C Edits to Typical Performance Characteristics ............................. 10 ©2002–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00312-0-9/11(E) REV. E –19–

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: OP296GSZ-REEL OP296HRUZ-REEL OP496GSZ-REEL OP496GSZ-REEL7 OP296GSZ-REEL7 OP496GSZ OP196GSZ-REEL OP196GSZ-REEL7 OP296GSZ OP496HRUZ-REEL OP196GSZ