NUP4114 Series ESD Protection Diode Low Clamping Voltage The NUP4114 ESD protection diode array is designed to protect high speed data lines from ESD. Ultra−low capacitance and high level of ESD protection make these devices well suited for use in USB 2.0 high speed applications. www.onsemi.com Features 5 • Low Clamping Voltage • Low Capacitance (<0.6 pF Typical, I/O to GND) • Low Leakage 1 6 3 4 • Response Time is Typically < 1.0 ns • IEC61000−4−2 Level 4 ESD Protection • SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and 2 PPAP Capable • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS MARKING DIAGRAMS Compliant 6 Typical Applications • SC−88 LVDS X2 M(cid:2) W1 SUFFIX • (cid:2) USB 2.0 High Speed Data Line and Power Line Protection 1 CASE 419B • Digital Video Interface (DVI) and HDMI 1 • Gigabit Ethernet 6 • Monitors and Flat Panel Displays • Notebook Computers SC−88 X4 M(cid:2) W1 SUFFIX (cid:2) 1 CASE 419B MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) 1 Rating Symbol Value Unit 6 Operating Junction Temperature Range TJ −40 to +125 °C CATSSOE P3−168G P4H(cid:2) M(cid:2) Storage Temperature Range Tstg −55 to +150 °C 1 STYLE 12 1 Lead Solder Temperature − TL 260 °C Maximum (10 Seconds) IEC 61000−4−2 Contact ESD ±8 kV 6 SOT−563 P4M(cid:2) IEC 61000−4−2 Air ±15 1 CASE 463A 1 (cid:2) ISO 10605 330 pF / 330 (cid:2) Contact ±10 ISO 10605 330 pF / 2 k(cid:2) Contact ±21 ISO 10605 150 pF / 2 k(cid:2) Contact ±30 XXX = Specific Device Code M = Date Code Stresses exceeding those listed in the Maximum Ratings table may damage the (cid:2) = Pb−Free Package device. If any of these limits are exceeded, device functionality should not be (Note: Microdot may be in either location) assumed, damage may occur and reliability may be affected. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: July, 2018 − Rev. 6 NUP4114/D

NUP4114 Series ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) I Symbol Parameter IF IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM Working Peak Reverse Voltage VC VBRVRWM IR Maximum Reverse Leakage Current @ VRWM IR VF V VBR Breakdown Voltage @ IT IT IT Test Current IF Forward Current VF Forward Voltage @ IF IPP Ppk Peak Power Dissipation C Capacitance @ VR = 0 and f = 1.0 MHz Uni−Directional *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Conditions Min Typ Max Unit Reverse Working Voltage VRWM 5.5 V Breakdown Voltage VBR IT = 1 mA, (Note 1) 5.5 6.5 V Reverse Leakage Current IR VRWM = 5.5 V 1.0 (cid:3)A Clamping Voltage VC IPP = 1 A (Note 2) 8.3 10 V IPP = 5 A (Note 3) 8.5 9.0 V IPP = 8 A (Note 3) 9.2 10 V ESD Clamping Voltage VC Per IEC61000−4−2 (Note 4) See Figures 1 & 2 Maximum Peak Pulse Current IPP 8/20 (cid:3)s Waveform (Note 3) 12 A Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins and GND 0.6 pF VR = 0 V, f = 1 MHz between I/O Pins 0.3 pF 1. VBR is measured at pulse test current IT. 2. Nonrepetitive current pulse (I/O to GND). 3. Nonrepetitive current pulse (Pin 5 to Pin 2) 4. For test procedure see Figures 3 and 4 and Application Note AND8307/D. Figure 1. ESD Clamping Voltage Screenshot Figure 2. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 Negative 8 kV Contact per IEC61000−4−2 www.onsemi.com 2

NUP4114 Series IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak First Peak Test Volt- Current Current at Current at 100% Level age (kV) (A) 30 ns (A) 60 ns (A) 90% 1 2 7.5 4 2 2 4 15 8 4 I @ 30 ns 3 6 22.5 12 6 4 8 30 16 8 I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec Device Under ESD Gun Oscilloscope Test 50 (cid:2) 50 (cid:2) Cable Figure 4. Diagram of ESD Test Setup The following is taken from Application Note systems such as cell phones or laptop computers it is not AND8308/D − Interpretation of Datasheet Parameters clearly defined in the spec how to specify a clamping voltage for ESD Devices. at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD ESD Voltage Clamping protection diode over the time domain of an ESD pulse in the For sensitive circuit elements it is important to limit the form of an oscilloscope screenshot, which can be found on voltage that an IC will be exposed to during an ESD event the datasheets for all ESD protection diodes. For more to as low a voltage as possible. The ESD clamping voltage information on how ON Semiconductor creates these is the voltage drop across the ESD protection diode during screenshots and how to interpret them please refer to an ESD event per the IEC61000−4−2 waveform. Since the AND8307/D. IEC61000−4−2 was written as a pass/fail spec for larger 100 tr PEAK VALUE IRSM @ 8 (cid:3)s 90 T N E 80 PULSE WIDTH (tP) IS DEFINED R AS THAT POINT WHERE THE R U 70 PEAK CURRENT DECAY = 8 (cid:3)s C E 60 ULS 50 HALF VALUE IRSM/2 @ 20 (cid:3)s P K 40 A E P 30 F tP O 20 % 10 0 0 20 40 60 80 t, TIME ((cid:3)s) Figure 5. 8/20 (cid:2)s Pulse Waveform www.onsemi.com 3

NUP4114 Series Figure 6. 500 MHz Data Pattern ORDERING INFORMATION Device Marking Package Shipping† NUP4114UCLW1T2G X2 SC−88 SZNUP4114UCLW1T2G X2 3000 / Tape & Reel (Pb−Free) NUP4114UCW1T2G X4 NUP4114UPXV6T1G SOT−563 P4 4000 / Tape & Reel NUP4114UPXV6T2G (Pb−Free) NUP4114HMR6T1G P4H TSOP−6 3000 / Tape & Reel SZNUP4114HMR6T1G P4H (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 4

NUP4114 Series APPLICATIONS INFORMATION The new NUP4114 is a low capacitance ESD diode array Option 2 designed to protect sensitive electronics such as Protection of four data lines with bias and power supply communications systems, computers, and computer isolation resistor. peripherals against damage due to ESD events or transient overvoltage conditions. Because of its low capacitance, it I/O 1 can be used in high speed I/O data lines. The integrated I/O 2 VCC design of the NUP4114 offers low capacitance steering diodes and an ESD diode integrated in a single package 1 6 10 k (TSOP−6). If a transient condition occurs, the steering diodes will drive the transient to the positive rail of the 2 5 power supply or to ground. This device protects the power line against overvoltage conditions to avoid damage to the 3 4 power supply and any downstream components. I/O 3 NUP4114 Configuration Options I/O 4 The NUP4114 is able to protect up to four data lines against transient overvoltage conditions by driving them to The NUP4114 can be isolated from the power supply by a fixed reference point for clamping purposes. The steering connecting a series resistor between pin 5 and VCC. A 10 k(cid:2) diodes will be forward biased whenever the voltage on the resistor is recommended for this application. This will protected line exceeds the reference voltage (V or maintain a bias on the internal ESD and steering diodes, f V + V). The diodes will force the transient current to reducing their capacitance. CC f bypass the sensitive circuit. Option 3 Data lines are connected at pins 1, 3, 4 and 6. The negative Protection of four data lines using the internal ESD diode reference is connected at pin 2. This pin must be connected as reference. directly to ground by using a ground plane to minimize the PCB’s ground inductance. It is very important to reduce the I/O 1 PCB trace lengths as much as possible to minimize parasitic I/O 2 inductances. 1 6 Option 1 Protection of four data lines and the power supply using V as reference. 2 5 NC CC I/O 1 3 4 I/O 2 I/O 3 1 6 I/O 4 2 5 VCC In applications lacking a positive supply reference or those cases in which a fully isolated power supply is 3 4 required, the internal ESD can be used as the reference. For these applications, pin 5 is not connected. In this I/O 3 configuration, the steering diodes will conduct whenever the I/O 4 voltage on the protected line exceeds the working voltage of the ESD plus one diode drop (VC = Vf + VESD). For this configuration, connect pin 5 directly to the ESD Protection of Power Supply Lines positive supply rail (V ), the data lines are referenced to When using diodes for data line protection, referencing to CC the supply voltage. The internal ESD diode prevents a supply rail provides advantages. Biasing the diodes overvoltage on the supply rail. Biasing of the steering diodes reduces their capacitance and minimizes signal distortion. reduces their capacitance. www.onsemi.com 5

NUP4114 Series Implementing this topology with discrete devices does have layout. Taking care to minimize the effects of parasitic disadvantages. This configuration is shown below: inductance will provide significant benefits in transient immunity. Even with good board layout, some disadvantages are still Power present when discrete diodes are used to suppress ESD Supply IESDpos VCC events across datalines and the supply rail. Discrete diodes with good transient power capability will have larger die and D1 IESDpos therefore higher capacitance. This capacitance becomes Protected Data Line IESDneg problematic as transmission frequencies increase. Reducing Device capacitance generally requires reducing die size. These small die will have higher forward voltage characteristics at D2 IESDneg VF + VCC typical ESD transient current levels. This voltage combined with the smaller die can result in device failure. The ON Semiconductor NUP4114 was developed to −VF overcome the disadvantages encountered when using Looking at the figure above, it can be seen that when a discrete diodes for ESD protection. This device integrates an positive ESD condition occurs, diode D1 will be forward ESD diode within a network of steering diodes. biased while diode D2 will be forward biased when a negative ESD condition occurs. For slower transient 5 conditions, this system may be approximated as follows: For positive pulse conditions: V = V + V c CC fD1 1 6 3 4 For negative pulse conditions: V = −V c fD2 ESD events can have rise times on the order of some number of nanoseconds. Under these conditions, the effect 2 of parasitic inductance must be considered. A pictorial representation of this is shown below. Figure 7. NUP4114 Equivalent Circuit During an ESD condition, the ESD current will be driven Power Supply IESDpos to ground through the ESD diode as shown below. VCC Power D1 IESDpos Supply Protected IESDneg Device Data Line VCC D2 VC = VCC + Vf + (L diESD/dt) D1 IESDpos IESDneg Protected Device Data Line D2 VC = −Vf − (L diESD/dt) An approximation of the clamping voltage for these fast transients would be: For positive pulse conditions: V = V + Vf + (L di /dt) c CC ESD For negative pulse conditions: The resulting clamping voltage on the protected IC will V = −V – (L di /dt) be: c f ESD As shown in the formulas, the clamping voltage (Vc) not Vc = VF + VESD. only depends on the Vf of the steering diodes but also on the The clamping voltage of the ESD diode depends on the L di /dt factor. A relatively small trace inductance can magnitude of the ESD current. The steering diodes are fast ESD result in hundreds of volts appearing on the supply rail. This switching devices with unique forward voltage and low endangers both the power supply and anything attached to capacitance characteristics. that rail. This highlights the importance of good board www.onsemi.com 6

NUP4114 Series PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE V D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. H 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. É6ÉÉ5 4 L2 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, GAUGE PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR E1 E PLANE GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D ÉÉÉ AND E1 ARE DETERMINED AT DATUM H. 1 2 3 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. L NOTE 5 b M C PSLEAANTIENG DIM MIN MILLNIMOEMTERSMAX DETAIL Z A 0.90 1.00 1.10 e A1 0.01 0.06 0.10 b 0.25 0.38 0.50 c 0.10 0.18 0.26 c D 2.90 3.00 3.10 A E 2.50 2.75 3.00 0.05 E1 1.30 1.50 1.70 e 00.8°5 0.95 11.00°5 A1 L 0.20 0.40 0.60 DETAIL Z L2 0.25 BSC M − RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 3.20 6X 0.95 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 7

NUP4114 Series PACKAGE DIMENSIONS SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE Y 2X aaa H D D H N1O.TDEISM:ENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. A 3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, D PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU- GAGE PLANE SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END. 4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF 6 5 4 THE PLASTIC BODY AND DATUM H. L2 L 5. DATUMS A AND B ARE DETERMINED AT DATUM H. E E1 6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE DETAIL A LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. 1 2 3 ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN aaa C EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI- 2X TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER bbb H D 2X 3 TIPS RADIUS OF THE FOOT. e MILLIMETERS INCHES B 6X b DIM MIN NOM MAX MIN NOM MAX A −−− −−− 1.10 −−− −−− 0.043 TOP VIEW ddd M C A-B D AA12 00..0700 0−.−9−0 10..0100 00..000207 0.−0−35− 00..000349 b 0.15 0.20 0.25 0.006 0.008 0.010 C 0.08 0.15 0.22 0.003 0.006 0.009 A2 DETAIL A D 1.80 2.00 2.20 0.070 0.078 0.086 A E 2.00 2.10 2.20 0.078 0.082 0.086 E1 1.15 1.25 1.35 0.045 0.049 0.053 e 0.65 BSC 0.026 BSC L 0.26 0.36 0.46 0.010 0.014 0.018 L2 0.15 BSC 0.006 BSC aaa 0.15 0.006 bbb 0.30 0.012 6X ccc C ccc 0.10 0.004 A1 ddd 0.10 0.004 C SEATING c PLANE SIDE VIEW END VIEW RECOMMENDED SOLDERING FOOTPRINT* 6X 6X 0.30 0.66 2.50 0.65 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 8

NUP4114 Series PACKAGE DIMENSIONS SOT−563, 6 LEAD CASE 463A ISSUE G NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. D 2. CONTROLLING DIMENSION: MILLIMETERS A −X− 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD L FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 6 5 4 MILLIMETERS INCHES −YE− HE DAIM 0M.5IN0 N0O.5M5 M0.A60X 0.M02IN0 0N.0O2M1 0M.0A23X 1 2 3 b 0.17 0.22 0.27 0.007 0.009 0.011 C 0.08 0.12 0.18 0.003 0.005 0.007 D 1.50 1.60 1.70 0.059 0.062 0.066 b 65 PL C E 1.10 1.20 1.30 0.043 0.047 0.051 e e 0.5 BSC 0.02 BSC 0.08 (0.003) M X Y L 0.10 0.20 0.30 0.004 0.008 0.012 HE 1.50 1.60 1.70 0.059 0.062 0.066 SOLDERING FOOTPRINT* 0.3 0.0118 0.45 0.0177 1.0 1.35 0.0394 0.0531 0.5 0.5 0.0197 0.0197 (cid:2) (cid:3) mm SCALE 20:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada For additional information, please contact your local Email: orderlit@onsemi.com Sales Representative ◊ www.onsemi.com NUP4114/D 9