NUC123 ® ® ARM Cortex -M0 32-bit Microcontroller ® NuMicro Family NUC123 Series Datasheet N U C 1 2 3 S The information described in this document is the exclusive intellectual property of E R Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. IE S D A Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based T A system design. Nuvoton assumes no responsibility for errors or omissions. S H All data and specifications are subject to change without notice. E E T For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com May 3, 2017 Page 1 of 99 Rev.2.04

NUC123 TABLE OF CONTENTS List of Figures .............................................................................................. 6 List of Tables ............................................................................................... 7 1 GENERAL DESCRIPTION ....................................................................... 8 2 FEATURES ......................................................................................... 9 2.1 NuMicro® NUC123 Series Features ................................................................ 9 3 Abbreviations ..................................................................................... 12 4 PARTS INFORMATION LIST AND PIN CONFIGURATION .............................. 14 4.1 NuMicro® NUC123 Series Naming Rule .......................................................... 14 4.2 NuMicro® NUC123 Series Selection Guide ....................................................... 15 4.2.1 NuMicro® NUC123xxxANx Selection Guide .............................................................. 15 4.2.2 NuMicro® NUC123xxxAEx Selection Guide .............................................................. 15 4.3 NuMicro® NUC123 Series Pin Configuration ..................................................... 16 4.3.1 NuMicro® NUC123xxxANx Pin Diagram .................................................................. 16 4.3.2 NuMicro® NUC123xxxAEx Pin Diagram .................................................................. 19 4.4 Pin Description ........................................................................................ 22 4.4.1 NuMicro® NUC123 Pin Description ........................................................................ 22 5 BLOCK DIAGRAM ............................................................................... 27 5.1 NuMicro® NUC123 Block Diagram ................................................................. 27 N U C 6 FUNCTIONAL DESCRIPTION ................................................................. 28 1 2 3 6.1 ARM® Cortex®-M0 Core .............................................................................. 28 S E R 6.2 System Manager ...................................................................................... 30 IE S 6.2.1 Overview ....................................................................................................... 30 D A 6.2.2 System Reset.................................................................................................. 30 T A S 6.2.3 Power modes and Wake-up sources ...................................................................... 36 H E E 6.2.4 System Power Distribution .................................................................................. 39 T 6.2.5 System Memory Map ......................................................................................... 40 6.2.6 System Timer (SysTick) ..................................................................................... 42 6.2.7 Nested Vectored Interrupt Controller (NVIC) ............................................................. 43 6.3 Clock Controller ....................................................................................... 47 6.3.1 Overview ....................................................................................................... 47 6.3.2 System Clock and SysTick Clock .......................................................................... 50 6.3.3 Peripherals Clock ............................................................................................. 50 May 3, 2017 Page 2 of 99 Rev.2.04

NUC123 6.3.4 Power-down Mode Clock .................................................................................... 50 6.3.5 Frequency Divider Output ................................................................................... 51 6.4 Flash Memory Controller (FMC) .................................................................... 52 6.4.1 Overview ....................................................................................................... 52 6.4.2 Features ........................................................................................................ 52 6.5 General Purpose I/O (GPIO) ........................................................................ 53 6.5.1 Overview ....................................................................................................... 53 6.5.2 Features ........................................................................................................ 53 6.6 PDMA Controller (PDMA) ........................................................................... 54 6.6.1 Overview ....................................................................................................... 54 6.6.2 Features ........................................................................................................ 54 6.7 Timer Controller (TMR) .............................................................................. 55 6.7.1 Overview ....................................................................................................... 55 6.7.2 Features ........................................................................................................ 55 6.8 PWM Generator and Capture Timer (PWM) ..................................................... 56 6.8.1 Overview ....................................................................................................... 56 6.8.2 Features ........................................................................................................ 56 6.9 Watchdog Timer (WDT).............................................................................. 57 6.9.1 Overview ....................................................................................................... 57 6.9.2 Features ........................................................................................................ 57 6.10 Window Watchdog Timer (WWDT) ................................................................ 58 N U 6.10.1 Overview ....................................................................................................... 58 C 1 2 6.10.2 Features ........................................................................................................ 58 3 S E 6.11 UART Interface Controller (UART) ................................................................. 59 R IE 6.11.1 Overview ....................................................................................................... 59 S D 6.11.2 Features ........................................................................................................ 59 A T A 6.12 PS/2 Device Controller (PS2D) ..................................................................... 60 S H E 6.12.1 Overview ....................................................................................................... 60 E T 6.12.2 Features ........................................................................................................ 60 6.13 I2C Serial Interface Controller (Master/Slave) (I2C) .............................................. 61 6.13.1 Overview ....................................................................................................... 61 6.13.2 Features ........................................................................................................ 61 6.14 Serial Peripheral Interface (SPI) .................................................................... 62 6.14.1 Overview ....................................................................................................... 62 6.14.2 Features ........................................................................................................ 62 May 3, 2017 Page 3 of 99 Rev.2.04

NUC123 6.15 I2S Controller (I2S) .................................................................................... 63 6.15.1 Overview ....................................................................................................... 63 6.15.2 Features ........................................................................................................ 63 6.16 USB Device Controller (USB) ....................................................................... 64 6.16.1 Overview ....................................................................................................... 64 6.16.2 Features ........................................................................................................ 64 6.17 Analog-to-Digital Converter (ADC) ................................................................. 65 6.17.1 Overview ....................................................................................................... 65 6.17.2 Features ........................................................................................................ 65 7 ELECTRICAL CHARACTERISTICS (NUC123xxxANx) ................................... 66 7.1 Absolute Maximum Ratings ......................................................................... 66 7.2 DC Electrical Characteristics ........................................................................ 67 7.3 AC Electrical Characteristics ........................................................................ 71 7.3.1 External 4~24 MHz High Speed Oscillator ............................................................... 71 7.3.2 External 4~24 MHz High Speed Crystal .................................................................. 71 7.3.3 Internal 22.1184 MHz High Speed Oscillator ............................................................. 72 7.3.4 Internal 10 kHz Low Speed Oscillator ..................................................................... 72 7.4 Analog Characteristics ............................................................................... 73 7.4.1 10-bit SARADC Specifications .............................................................................. 73 7.4.2 LDO and Power Management Specifications ............................................................ 74 N 7.4.3 Low Voltage Reset Specifications .......................................................................... 74 U C 1 7.4.4 Brown-out Detector Specifications ......................................................................... 75 2 3 S 7.4.5 Power-On Reset (5V) Specifications ...................................................................... 75 E R 7.4.6 USB PHY Specifications ..................................................................................... 76 IE S 7.5 Flash DC Electrical Characteristics ................................................................ 77 D A T 7.6 SPI Dynamic Characteristics ........................................................................ 78 A S H 8 ELECTRICAL CHARACTERISTICS (NUC123xxxAEx).................................... 80 E E T 8.1 Absolute Maximum Ratings ......................................................................... 80 8.2 DC Electrical Characteristics ........................................................................ 81 8.3 AC Electrical Characteristics ........................................................................ 85 8.3.1 External 4~24 MHz High Speed Oscillator ............................................................... 85 8.3.2 External 4~24 MHz High Speed Crystal .................................................................. 85 8.3.3 Internal 22.1184 MHz High Speed Oscillator ............................................................. 86 8.3.4 Internal 10 kHz Low Speed Oscillator ..................................................................... 86 8.4 Analog Characteristics ............................................................................... 87 May 3, 2017 Page 4 of 99 Rev.2.04

NUC123 8.4.1 10-bit SARADC Specifications .............................................................................. 87 8.4.2 LDO and Power Management Specifications ............................................................ 88 8.4.3 Low Voltage Reset Specifications .......................................................................... 88 8.4.4 Brown-out Detector Specifications ......................................................................... 89 8.4.5 Power-On Reset (5V) Specifications ...................................................................... 89 8.4.6 USB PHY Specifications ..................................................................................... 90 8.5 Flash DC Electrical Characteristics ................................................................ 92 8.6 SPI Dynamic Characteristics ........................................................................ 93 9 PACKAGE DIMENSIONS ...................................................................... 95 9.1 64L LQFP (7x7x1.4 mm footprint 2.0 mm) ........................................................ 95 9.2 48L LQFP (7x7x1.4 mm footprint 2.0 mm) ........................................................ 96 9.3 33L QFN (5x5x0.8 mm) .............................................................................. 97 10 REVISION HISTORY ............................................................................ 98 N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 5 of 99 Rev.2.04

NUC123 List of Figures Figure 4-1 NuMicro® NUC123 Series Selection Code ................................................................... 14 Figure 4-2 NuMicro® NUC123SxxANx LQFP 64-pin Diagram ....................................................... 16 Figure 4-3 NuMicro® NUC123LxxANx LQFP 48-pin Diagram ....................................................... 17 Figure 4-4 NuMicro® NUC123ZxxANx QFN 33-pin Diagram ......................................................... 18 Figure 4-5 NuMicro® NUC123SxxAEx LQFP 64-pin Diagram ....................................................... 19 Figure 4-6 NuMicro® NUC123LxxAEx LQFP 48-pin Diagram ....................................................... 20 Figure 4-7 NuMicro® NUC123ZxxAEx QFN 33-pin Diagram ......................................................... 21 Figure 5-1 NuMicro® NUC123 Block Diagram ............................................................................... 27 Figure 6-1 Functional Controller Diagram ...................................................................................... 28 Figure 6-2 System Reset Resources ............................................................................................. 31 Figure 6-3 nRESET Reset Waveform ............................................................................................ 33 Figure 6-4 Power-on Reset (POR) Waveform ............................................................................... 34 Figure 6-5 Low Voltage Reset Waveform ...................................................................................... 34 Figure 6-6 Brown-Out Detector Waveform .................................................................................... 35 Figure 6-7 Power Mode State Machine ......................................................................................... 36 Figure 6-8 NuMicro® NUC123 Power Distribution Diagram ........................................................... 39 Figure 6-9 Clock Generator Global View Diagram ......................................................................... 48 Figure 6-10 Clock Generator Global View Diagram ....................................................................... 49 Figure 6-11 System Clock Block Diagram ..................................................................................... 50 Figure 6-12 SysTick Clock Control Block Diagram ........................................................................ 50 N Figure 6-13 Clock Source of Frequency Divider ............................................................................ 51 U C 1 Figure 6-14 Block Diagram of Frequency Divider .......................................................................... 51 2 3 S Figure 7-1 Typical Crystal Application Circuit ................................................................................ 71 E R Figure 7-2 SPI Master Dynamic Characteristics Timing ................................................................ 78 IE S Figure 7-3 SPI Slave Dynamic Characteristics Timing .................................................................. 79 D A Figure 8-1 Typical Crystal Application Circuit ................................................................................ 85 T A S Figure 8-2 SPI Master Dynamic Characteristics timing ................................................................. 93 H E Figure 8-3 SPI Slave Dynamic Characteristics Timing .................................................................. 94 E T May 3, 2017 Page 6 of 99 Rev.2.04

NUC123 List of Tables Table 1-1 Key Features Support Table ............................................................................................ 8 Table 3-1 List of Abbreviations ....................................................................................................... 13 Table 6-1 Reset Value of Registers ............................................................................................... 32 Table 6-2 Power Mode Difference Table ....................................................................................... 36 Table 6-3 Clocks in Power Modes ................................................................................................. 37 Table 6-4 Condition of Entering Power-down Mode Again ............................................................ 38 Table 6-5 Address Space Assignments for On-Chip Controllers ................................................... 41 Table 6-6 Exception Model ............................................................................................................ 44 Table 6-7 System Interrupt Map ..................................................................................................... 45 Table 6-8 Vector Table Format ...................................................................................................... 46 Table 6-9 Clock Stable Count Value Table .................................................................................... 47 N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 7 of 99 Rev.2.04

NUC123 1 GENERAL DESCRIPTION The NuMicro® NUC123 series is a new 32-bit Cortex®-M0 microcontroller with USB 2.0 Full-speed devices and a 10-bit ADC. The NUC123 series provides the high 72 MHz operating speed, large 20 Kbytes SRAM, 8 USB endpoints and three sets of SPI controllers, which make it powerful in USB communication and data processing. The NUC123 series is ideal for industrial control, consumer electronics, and communication system applications such as printers, touch panel, gaming keyboard, gaming joystick, USB audio, PC peripherals, and alarm systems. The NUC123 series runs up to 72 MHz and supports 32-bit multiplier, structure NVIC (Nested Vector Interrupt Control), dual-channel APB and PDMA (Peripheral Direct Memory Access) with CRC function. Besides, the NUC123 series is equipped with 36/68 Kbytes Flash memory, 12/20 Kbytes SRAM, and 4 Kbytes loader ROM for the ISP. It operates at a wide voltage range of 2.5V ~ 5.5V and temperature range of -40℃ ~ +105℃ and -40℃ ~ +85℃. It is also equipped with plenty of peripheral devices, such as 8-channel 10-bit ADC, UART, SPI, I2C, I2S, USB 2.0 FS devices, and offers low-voltage reset and Brown-out detection, PWM (Pulse-width Modulation), capture and compare features, four sets of 32-bit timers, Watchdog Timer, and internal RC oscillator. All these peripherals have been incorporated into the NUC123 series to reduce component count, board space and system cost. Additionally, the NUC123 series is equipped with ISP (In-System Programming), IAP (In- Application-Programming) and ICP (In-Circuit Programming) functions, which allows the user to update the program under software control through the on-chip connectivity interface, such as SWD, UART and USB. Product Line UART SPI I2C USB PS/2 I2S PWM ADC NUC123 2 3 2 1 1 1 4 8 Table 1-1 Key Features Support Table N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 8 of 99 Rev.2.04

NUC123 2 FEATURES 2.1 NuMicro® NUC123 Series Features  Core – ARM® Cortex®-M0 core runs up to 72 MHz – One 24-bit system timer – Supports low power sleep mode – Single-cycle 32-bit hardware multiplier – NVIC for the 32 interrupt inputs, each with 4-levels of priority – Supports Serial Wire Debug with 2 watchpoints/4 breakpoints  Built-in LDO for wide operating voltage ranges from 2.5 V to 5.5 V  Flash Memory – 36/68 KB Flash for program code – 4 KB flash for ISP loader – Supports In-System Program (ISP) application code update – 512 byte page erase for flash – Configurable Data Flash address and size for both 36KB and 68KB system – Supports 2-wire ICP update through SWD/ICE interface – Supports fast parallel programming mode by external programmer  SRAM Memory – 12/20 KB embedded SRAM – Supports PDMA mode  PDMA (Peripheral DMA) – Supports 6 channels PDMA for automatic data transfer between SRAM and peripherals such as SPI, UART, I2S, USB 2.0 FS device, PWM and ADC – Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC- 16 and CRC-32  Clock Control N – Flexible selection for different applications U C – Built-in 22.1184 MHz high speed oscillator (Trimmed to 1%) for system operation, and 1 2 low power 10 kHz low speed oscillator for watchdog and wake-up operation 3 – Supports one PLL, up to 144 MHz, for high performance system operation S E – External 4~24 MHz high speed crystal input for precise timing operation R IE  GPIO S D – Four I/O modes: A T  Quasi bi-direction A  Push-Pull output S H  Open-Drain output E E  Input only with high impendence T – TTL/Schmitt trigger input selectable – I/O pin configured as interrupt source with edge/level setting – Supports High Driver and High Sink I/O mode  Timer – Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter – Independent clock source for each timer – Provides one-shot, periodic, toggle and continuous counting operation modes – Supports event counting function  Watchdog/Windowed-Watchdog Timer – Multiple clock sources May 3, 2017 Page 9 of 99 Rev.2.04

NUC123 – 8 selectable time-out period from 1.6ms ~ 26.0sec (depending on clock source) – Wake-up from Power-down or Idle mode – Interrupt or reset selectable on watchdog timer time-out – Interrupt on windowed-watchdog timer time-out – Reset on windowed-watchdog timer time-out or reload in an unexpected time window  PWM/Capture – Up to two built-in 16-bit PWM generators provided with four PWM outputs or two complementary paired PWM outputs – Each PWM generator equipped with one clock source selector, one clock divider, one 8-bit prescaler and one Dead-zone generator for complementary paired PWM – Up to four 16-bit digital Capture timers (shared with PWM timers) provided with four rising/falling capture inputs – Supports Capture interrupt  UART – Up to two UART controllers – UART ports with flow control (TXD, RXD, CTS and RTS) – UART0/1 with 16-byte FIFO for standard device – Support IrDA (SIR) function – Supports RS-485 9-bit mode and direction control. – Programmable baud-rate generator up to 1/16 system clock – Supports PDMA mode  SPI – Up to three sets of SPI controllers – Supports SPI master/Slave mode – Full duplex synchronous serial data transfer – Variable length of transfer data from 8 to 32 bits – MSB or LSB first data transfer – Up to two slave/device select lines in Master mode – Supports Byte Suspend mode in 16/24/32-bit transmission – Supports PDMA transfer NU  I2C C 1 – Up to two sets of I2C devices 2 3 – Master/Slave mode S E – Bidirectional data transfer between masters and slaves R – Multi-master bus (no central master) IE S – Arbitration between simultaneously transmitting masters without corruption of serial D data on the bus A T – Serial clock synchronization allows devices with different bit rates to communicate via A one serial bus S H – Serial clock synchronization used as a handshake mechanism to suspend and resume E E serial transfer T – Programmable clocks allowing versatile rate control – Supports multiple address recognition (four slave address with mask option) – Supports wake-up by address recognition (for 1st slave address only)  I2S – Interface with external audio CODEC – Operated as either master or Slave mode – Capable of handling 8-, 16-, 24- and 32-bit word sizes – Supports Mono and stereo audio data – Supports I2S and MSB justified data format – Two 8 word FIFO data buffers are provided, one for transmitting and the other for receiving May 3, 2017 Page 10 of 99 Rev.2.04

NUC123 – Generates interrupt requests when buffer levels cross a programmable boundary – Supports two DMA requests, one for transmitting and the other for receiving  PS/2 Device Controller – Host communication inhibit and request to send detection – Reception frame error detection – Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention – Double buffer for data reception – S/W override bus  USB 2.0 Full-Speed Device – One set of USB 2.0 FS Device 12 Mbps – On-chip USB transceiver – Provides 1 interrupt source with 4 interrupt events – Supports Control, Bulk In/Out, Interrupt and Isochronous transfers – Auto suspend function when no bus signaling for 3 ms – Provides 8 programmable endpoints – Includes 512 bytes internal SRAM as USB buffer – Provides remote wake-up capability  ADC – 10-bit SAR ADC with 150K SPS (for NUC123xxxANx) – 10-bit SAR ADC with 200K SPS (for NUC123xxxAEx) – Up to 8-ch single-end input – Single scan/single cycle scan/continuous scan – Each channel with individual result register – Scan on enabled channels – Threshold voltage detection – Conversion start by software programming or external input – Supports PDMA mode  Brown-out detector – With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V – Supports Brown-out Interrupt and Reset option N U  Low Voltage Reset C 1 2 – Threshold voltage levels: 2.0 V 3 S  One built-in LDO E R  Operating Temperature: -40℃~85℃ (for NUC123xxxANx) IE S  Operating Temperature: -40℃~105℃ (for NUC123xxxAEx) D A T  Packages: A S H – All Green package (RoHS) E – LQFP 64-pin E T – LQFP 48-pin – QFN 33-pin May 3, 2017 Page 11 of 99 Rev.2.04

NUC123 3 ABBREVIATIONS Acronym Description ACMP Analog Comparator Controller ADC Analog-to-Digital Converter AES Advanced Encryption Standard APB Advanced Peripheral Bus AHB Advanced High-Performance Bus BOD Brown-out Detection CAN Controller Area Network DAP Debug Access Port DES Data Encryption Standard EBI External Bus Interface EPWM Enhanced Pulse Width Modulation FIFO First In, First Out FMC Flash Memory Controller FPU Floating-point Unit GPIO General-Purpose Input/Output HCLK The Clock of Advanced High-Performance Bus HIRC 22.1184 MHz Internal High Speed RC Oscillator HXT 4~20 MHz External High Speed Crystal Oscillator N IAP In Application Programming U C ICP In Circuit Programming 1 2 3 S ISP In System Programming E R LDO Low Dropout Regulator IE S LIN Local Interconnect Network D A LIRC 10 kHz internal low speed RC oscillator (LIRC) T A S MPU Memory Protection Unit H E E NVIC Nested Vectored Interrupt Controller T PCLK The Clock of Advanced Peripheral Bus PDMA Peripheral Direct Memory Access PLL Phase-Locked Loop PWM Pulse Width Modulation QEI Quadrature Encoder Interface SD Secure Digital SPI Serial Peripheral Interface May 3, 2017 Page 12 of 99 Rev.2.04

NUC123 SPS Samples per Second TDES Triple Data Encryption Standard TK Touch Key TMR Timer Controller UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID USB Universal Serial Bus WDT Watchdog Timer WWDT Window Watchdog Timer Table 3-1 List of Abbreviations N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 13 of 99 Rev.2.04

NUC123 4 PARTS INFORMATION LIST AND PIN CONFIGURATION 4.1 NuMicro® NUC123 Series Naming Rule ARM–Based 32-bit Microcontroller NUC 1 2 3 - XXXXXX CPU Core Option 1: Cortex®-M0 0: SRAM 20 KB 5/7: ARM7 1: SRAM 12 KB 9: ARM9 Temperature Product Line Function N: -40oC ~ +85oC E: -40oC ~ +105oC 0: Advance Line 2: USB Line 3: Automotive Line Reserved 4: Connectivity Line 5: High Density SRAM Size Reserved 2: 12 KB 0~9: Sub Product Line 4: 20 KB N Package Type U Flash ROM C 1 Z: QFN 33 5x5mm 2 3 L: LQFP 48 7x7mm C: 36 KB S E S: LQFP 64 7x7mm D: 68 KB R IE S D Figure 4-1 NuMicro® NUC123 Series Selection Code A T A S H E E T May 3, 2017 Page 14 of 99 Rev.2.04

NUC123 4.2 NuMicro® NUC123 Series Selection Guide 4.2.1 NuMicro® NUC123xxxANx Selection Guide Part Number Flash (KB) SRAM (KB) ISP ROM (KB) I/O Timer UART SPI Con2IC necUSB tivityLIN PS/2 2IS Comp. PWM ADC RTC EBI ISP\ICP\IAP 1.8V Power Pin Package NUC123ZD4AN0 68 20 4 Up to 20 4x32-bit 1 3 1 1 - - 1 - 2 3x10-bit - - v - QFN33 NUC123ZC2AN1 36 12 4 up to 20 4x32-bit 1 3 1 1 - - 1 - 2 3x10-bit - - v - QFN33 NUC123LD4AN0 68 20 4 up to 36 4x32-bit 2 3 2 1 - 1 1 - 4 8x10-bit - - v - LQFP48 NUC123LC2AN1 36 12 4 up to 36 4x32-bit 2 3 2 1 - 1 1 - 4 8x10-bit - - v - LQFP48 NUC123SD4AN0 68 20 4 up to 47 4x32-bit 2 3 2 1 - 1 1 - 4 8x10-bit - - v - LQFP64 NUC123SC2AN1 36 12 4 up to 47 4x32-bit 2 3 2 1 - 1 1 - 4 8x10-bit - - v - LQFP64 4.2.2 NuMicro® NUC123xxxAEx Selection Guide Part Number Flash (KB) SRAM (KB) ISP ROM (KB) I/O Timer UART SPI Con2IC necUSB tivityLIN PS/2 2IS Comp. PWM ADC RTC EBI ISP\ICP\IAP 1.8V Power Pin Package NUC123ZD4AE0 68 20 4 Up to 20 4x32-bit 1 3 1 1 - - 1 - 3 3x10-bit - - v - QFN33 NUC123ZC2AE1 36 12 4 up to 20 4x32-bit 1 3 1 1 - - 1 - 3 3x10-bit - - v - QFN33 NUC123LD4AE0 68 20 4 up to 36 4x32-bit 2 3 2 1 - 1 1 - 4 8x10-bit - - v - LQFP48 N U NUC123LC2AE1 36 12 4 up to 36 4x32-bit 2 3 2 1 - 1 1 - 4 8x10-bit - - v - LQFP48 C 1 NUC123SD4AE0 68 20 4 up to 47 4x32-bit 2 3 2 1 - 1 1 - 4 8x10-bit - - v - LQFP64 2 3 S NUC123SC2AE1 36 12 4 up to 47 4x32-bit 2 3 2 1 - 1 1 - 4 8x10-bit - - v - LQFP64 E R IE S D A T A S H E E T May 3, 2017 Page 15 of 99 Rev.2.04

NUC123 4.3 NuMicro® NUC123 Series Pin Configuration 4.3.1 NuMicro® NUC123xxxANx Pin Diagram 4.3.1.1 NuMicro® NUC123SxxANx LQFP 64 pin K L C M O LK/CLKO WM2/I2S_ WM3/CLK C P P M 0 0 1/ 1/ M0 M1 M2 M3/I2S_ _SS0 _CLK 1_MISO 1_MOSI 1_MISO 1_MOSI AVDD ICE_CLK ICE_DAT PA.12/PW PA.13/PW PA.14/PW VSS PA.15/PW PC.8/SPI1 PC.9/SPI1 VDD PC.10/SPI PC.11/SPI PC.12/SPI PC.13/SPI VSS 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 SPI2_SS0/ADC0/PD.0 49 32 PB.9/SPI1_SS1/TM1 SPI0_SS1/SPI2_CLK/ADC1/PD.1 50 31 PB.10/SPI0_SS1/TM2 SPI0_MISO1/SPI2_MISO0/ADC2/PD.2 51 30 PC.0/SPI0_SS0/I2S_LRCLK SPI0_MOSI1/SPI2_MOSI0/ADC3/PD.3 52 29 PC.1/SPI0_CLK/I2S_BCLK SPI2_MISO1/ADC4/PD.4 53 28 PC.2/SPI0_MISO0/I2S_DI SPI2_MOSI1/ADC5/PD.5 54 27 PC.3/SPI0_MOSI0/I2S_DO TM0_EXT/INT1/PB.15 55 26 PC.4/SPI0_MISO1/UART0_RXD NUC123SxxANx XT1_OUT/PF.0 56 25 PC.5/SPI0_MOSI1/UART0_TXD XT1_IN/PF.1 57 LQFP 64-pin 24 PB.3/UART0_nCTS/TM3_EXT nRESET 58 23 PB.2/UART0_nRTS/TM2_EXT VSS 59 22 PB.1/UART0_TXD VDD 60 21 PB.0/UART0_RXD PS2_DAT/I2C0_SDA/ADC6/PF.2 61 20 USB_D+ PS2_CLK/I2C0_SCL/ADC7/PF.3 62 19 USB_D- PVSS 63 18 USB_VDD33_CAP TM0/PB.8 64 17 USB_VBUS 0 1 2 3 4 5 6 N 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 U C123 SERIES DATA INT0/PB.14 PB.13 CLKO/SPI1_SS0/PB.12 _SCL/SPI2_MOSI0/SPI1_CLK/PA.11 DA/SPI2_MISO0/SPI1_MISO0/PA.10 SPI1_MOSI0/PD.8 PD.9 CLKO/PD.10 INT1/PD.11 1_SS1/SPI2_SS0/UART1_RXD/PB.4 SPI2_CLK/UART1_TXD/PB.5 SPI2_MOSI0/UART1_nRTS/PB.6 SPI2_MISO0/UART1_nCTS/PB.7 LDO_CAP VDD VSS SH I2C1 C1_S SPI E I2 E T Figure 4-2 NuMicro® NUC123SxxANx LQFP 64-pin Diagram May 3, 2017 Page 16 of 99 Rev.2.04

NUC123 4.3.1.2 NuMicro® NUC123LxxANx LQFP 48 pin K L C M O CLKO 2/I2S_ 3/CLK LK/ WM WM C P P M 0 0 1/ 1/ M0 M1 M2 M3/I2S_ _SS0 _CLK 1_MISO 1_MOSI 1_MISO 1_MOSI _CLK _DAT 12/PW 13/PW 14/PW 15/PW 8/SPI1 9/SPI1 10/SPI 11/SPI 12/SPI 13/SPI ICE ICE PA. PA. PA. PA. PC. PC. PC. PC. PC. PC. 6 5 4 3 2 1 0 9 8 7 6 5 3 3 3 3 3 3 3 2 2 2 2 2 AVDD 37 24 PB.9/SPI1_SS1/TM1 SPI2_SS0/ADC0/PD.0 38 23 PB.10/SPI0_SS1/TM2 SPI0_SS1/SPI2_CLK/ADC1/PD.1 39 22 PC.0/SPI0_SS0/I2S_LRCLK SPI0_MISO1/SPI2_MISO0/ADC2/PD.2 40 21 PC.1/SPI0_CLK/I2S_BCLK SPI0_MOSI1/SPI2_MOSI0/ADC3/PD.3 41 20 PC.2/SPI0_MISO0/I2S_DI NUC123LxxANx SPI2_MISO1/ADC4/PD.4 42 19 PC.3/SPI0_MOSI0/I2S_DO SPI2_MOSI1/ADC5/PD.5 43 LQFP 48-pin 18 PC.4/SPI0_MISO1/UART0_RXD XT1_OUT/PF.0 44 17 PC.5/SPI0_MOSI1/UART0_TXD XT1_IN/PF.1 45 16 USB_D+ nRESET 46 15 USB_D- PS2_DAT/I2C0_SDA/ADC6/PF.2 47 14 USB_VDD33_CAP PS2_CLK/I2C0_SCL/ADC7/PF.3 48 13 USB_VBUS 0 1 2 1 2 3 4 5 6 7 8 9 1 1 1 PVSS PB.8 B.14 A.11 A.10 PB.4 PB.5 PB.6 PB.7 CAP VDD VSS TM0/ INT0/P I2C1_SCL/SPI2_MOSI0/SPI1_CLK/P C1_SDA/SPI2_MISO0/SPI1_MISO0/P SPI1_SS1/SPI2_SS0/UART1_RXD/ SPI2_CLK/UART1_TXD/ SPI2_MOSI0/UART1_nRTS/ SPI2_MISO0/UART1_nCTS/ LDO_ NUC123 SERIE I2 S D Figure 4-3 NuMicro® NUC123LxxANx LQFP 48-pin Diagram A T A S H E E T May 3, 2017 Page 17 of 99 Rev.2.04

NUC123 4.3.1.3 NuMicro® NUC123ZxxANx QFN 33 pin K L C M O _ K S L 2 C 2/I 3/ M M W W P P 0 0 1/ 1/ O SI O SI S0 LK MIS MO MIS MO S C _ _ _ _ _ _ 1 1 1 1 _CLK _DAT 8/SPI1 9/SPI1 10/SPI 11/SPI 12/SPI 13/SPI ICE ICE PC. PC. PC. PC. PC. PC. 4 3 2 1 0 9 8 7 2 2 2 2 2 1 1 1 AV 25 16 PC.0/SPI0_SS0/I2S_LRCLK DD SPI0_SS1/SPI2_CLK/ADC1/PD.1 26 15 PC.1/SPI0_CLK/I2S_BCLK SPI0_MISO1/SPI2_MISO0/ADC2/PD.2 27 14 PC.2/SPI0_MISO0/I2S_DI SPI0_MOSI1/SPI2_MOSI0/ADC3/PD.3 28 NUC123ZxxANx 13 PC.3/SPI0_MOSI0/I2S_DO XT1_OUT/PF.0 29 QFN 33-pin 12 USB_D+ XT1_IN/PF.1 30 11 USB_D- nRESET 31 33 VSS 10 USB_VDD33_CAP PV 32 9 USB_VBUS SS 1 2 3 4 5 6 7 8 4 1 0 4 5 P D S B.1 A.1 A.1 PB. PB. CA VD VS NU INT0/P MOSI0/SPI1_CLK/P SO0/SPI1_MISO0/P _SS0/UART1_RXD/ _CLK/UART1_TXD/ LDO_ C123 S SCL/SPI2_ A/SPI2_MI _SS1/SPI2 SPI2 E _ D 1 RIE I2C1 C1_S SPI S I2 D AT Figure 4-4 NuMicro® NUC123ZxxANx QFN 33-pin Diagram A S H E E T May 3, 2017 Page 18 of 99 Rev.2.04

NUC123 4.3.2 NuMicro® NUC123xxxAEx Pin Diagram 4.3.2.1 NuMicro® NUC123SxxAEx LQFP 64 pin K L C M O CLK/CLKO M0 PWM2/I2S_ PWM3/CLK M W 0 0 1/ 1/ M0 M1 M2 M3/I2S_ _SS0/P _CLK 1_MISO 1_MOSI 1_MISO 1_MOSI AVDD ICE_CLK ICE_DAT PA.12/PW PA.13/PW PA.14/PW VSS PA.15/PW PC.8/SPI1 PC.9/SPI1 VDD PC.10/SPI PC.11/SPI PC.12/SPI PC.13/SPI VSS 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 SPI2_SS0/ADC0/PD.0 49 32 PB.9/SPI1_SS1/TM1/PWM1 SPI0_SS1/SPI2_CLK/ADC1/PD.1 50 31 PB.10/SPI0_SS1/TM2 SPI0_MISO1/SPI2_MISO0/ADC2/PD.2 51 30 PC.0/SPI0_SS0/I2S_LRCLK SPI0_MOSI1/SPI2_MOSI0/ADC3/PD.3 52 29 PC.1/SPI0_CLK/I2S_BCLK SPI2_MISO1/ADC4/PD.4 53 28 PC.2/SPI0_MISO0/I2S_DI SPI2_MOSI1/ADC5/PD.5 54 27 PC.3/SPI0_MOSI0/I2S_DO TM0_EXT/INT1/PB.15 55 26 PC.4/SPI0_MISO1/UART0_RXD NUC123SxxAEx XT1_OUT/PF.0 56 25 PC.5/SPI0_MOSI1/UART0_TXD XT1_IN/PF.1 57 LQFP 64-pin 24 PB.3/UART0_nCTS/TM3_EXT nRESET 58 23 PB.2/UART0_nRTS/TM2_EXT VSS 59 22 PB.1/UART0_TXD VDD 60 21 PB.0/UART0_RXD PS2_DAT/I2C0_SDA/ADC6/PF.2 61 20 USB_D+ PS2_CLK/I2C0_SCL/ADC7/PF.3 62 19 USB_D- PVSS 63 18 USB_VDD33_CAP TM0/PB.8 64 17 USB_VBUS 0 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 INT0/PB.14 PB.13 CLKO/SPI1_SS0/PB.12 2C1_SCL/SPI2_MOSI0/SPI1_CLK/PA.11 1_SDA/SPI2_MISO0/SPI1_MISO0/PA.10 SPI1_MOSI0/PD.8 PD.9 CLKO/PD.10 INT1/PD.11 SPI1_SS1/SPI2_SS0/UART1_RXD/PB.4 SPI2_CLK/UART1_TXD/PB.5 SPI2_MOSI0/UART1_nRTS/PB.6 SPI2_MISO0/UART1_nCTS/PB.7 LDO_CAP VDD VSS NUC123 SERIES DA I C I2 TA S Figure 4-5 NuMicro® NUC123SxxAEx LQFP 64-pin Diagram H E E T May 3, 2017 Page 19 of 99 Rev.2.04

NUC123 4.3.2.2 NuMicro® NUC123LxxAEx LQFP 48 pin K L C M O CLKO 2/I2S_ 3/CLK LK/ 0 WM WM C M P P M W 0 0 1/ 1/ M0 M1 M2 M3/I2S_ _SS0/P _CLK 1_MISO 1_MOSI 1_MISO 1_MOSI _CLK _DAT 12/PW 13/PW 14/PW 15/PW 8/SPI1 9/SPI1 10/SPI 11/SPI 12/SPI 13/SPI ICE ICE PA. PA. PA. PA. PC. PC. PC. PC. PC. PC. 6 5 4 3 2 1 0 9 8 7 6 5 3 3 3 3 3 3 3 2 2 2 2 2 AVDD 37 24 PB.9/SPI1_SS1/TM1/PWM1 SPI2_SS0/ADC0/PD.0 38 23 PB.10/SPI0_SS1/TM2 SPI0_SS1/SPI2_CLK/ADC1/PD.1 39 22 PC.0/SPI0_SS0/I2S_LRCLK SPI0_MISO1/SPI2_MISO0/ADC2/PD.2 40 21 PC.1/SPI0_CLK/I2S_BCLK SPI0_MOSI1/SPI2_MOSI0/ADC3/PD.3 41 20 PC.2/SPI0_MISO0/I2S_DI NUC123LxxAEx SPI2_MISO1/ADC4/PD.4 42 19 PC.3/SPI0_MOSI0/I2S_DO SPI2_MOSI1/ADC5/PD.5 43 LQFP 48-pin 18 PC.4/SPI0_MISO1/UART0_RXD XT1_OUT/PF.0 44 17 PC.5/SPI0_MOSI1/UART0_TXD XT1_IN/PF.1 45 16 USB_D+ nRESET 46 15 USB_D- PS2_DAT/I2C0_SDA/ADC6/PF.2 47 14 USB_VDD33_CAP PS2_CLK/I2C0_SCL/ADC7/PF.3 48 13 USB_VBUS 0 1 2 1 2 3 4 5 6 7 8 9 1 1 1 PVSS PB.8 B.14 A.11 A.10 PB.4 PB.5 PB.6 PB.7 CAP VDD VSS NUC123 SERIE TM0/ INT0/P I2C1_SCL/SPI2_MOSI0/SPI1_CLK/P C1_SDA/SPI2_MISO0/SPI1_MISO0/P SPI1_SS1/SPI2_SS0/UART1_RXD/ SPI2_CLK/UART1_TXD/ SPI2_MOSI0/UART1_nRTS/ SPI2_MISO0/UART1_nCTS/ LDO_ S I2 D A Figure 4-6 NuMicro® NUC123LxxAEx LQFP 48-pin Diagram T A S H E E T May 3, 2017 Page 20 of 99 Rev.2.04

NUC123 4.3.2.3 NuMicro® NUC123ZxxAEx QFN 33 pin K L C M O _ K S L 2 C 2/I 3/ M M 0 W W M P P W 0 0 1/ 1/ P O SI O SI S0/ LK MIS MO MIS MO S C _ _ _ _ _ _ 1 1 1 1 _CLK _DAT 8/SPI1 9/SPI1 10/SPI 11/SPI 12/SPI 13/SPI ICE ICE PC. PC. PC. PC. PC. PC. 4 3 2 1 0 9 8 7 2 2 2 2 2 1 1 1 AV 25 16 PC.0/SPI0_SS0/I2S_LRCLK DD SPI0_SS1/SPI2_CLK/ADC1/PD.1 26 15 PC.1/SPI0_CLK/I2S_BCLK SPI0_MISO1/SPI2_MISO0/ADC2/PD.2 27 14 PC.2/SPI0_MISO0/I2S_DI SPI0_MOSI1/SPI2_MOSI0/ADC3/PD.3 28 NUC123ZxxAEx 13 PC.3/SPI0_MOSI0/I2S_DO XT1_OUT/PF.0 29 QFN 33-pin 12 USB_D+ XT1_IN/PF.1 30 11 USB_D- nRESET 31 33 VSS 10 USB_VDD33_CAP PV 32 9 USB_VBUS SS 1 2 3 4 5 6 7 8 4 1 0 4 5 P D S B.1 A.1 A.1 PB. PB. CA VD VS INT0/P MOSI0/SPI1_CLK/P SO0/SPI1_MISO0/P _SS0/UART1_RXD/ _CLK/UART1_TXD/ LDO_ NU SCL/SPI2_ A/SPI2_MI _SS1/SPI2 SPI2 C123 S _ D 1 E I2C1 C1_S SPI RIE I2 S D Figure 4-7 NuMicro® NUC123ZxxAEx QFN 33-pin Diagram AT A S H E E T May 3, 2017 Page 21 of 99 Rev.2.04

NUC123 4.4 Pin Description 4.4.1 NuMicro® NUC123 Pin Description Pin No Pin Name Type Description LQFP 64- LQFP 48- QFN 33- pin pin pin PB.14 I/O Digital GPIO pin 1 3 1 INT0 I External interrupt 0 input pin 2 PB.13 I/O Digital GPIO pin PB.12 I/O Digital GPIO pin 3 SPI1_SS0 I/O SPI1 1st slave select pin CLKO O Frequency Divider output pin PA.11 I/O Digital GPIO pin SPI1_CLK I/O SPI1 serial clock pin 4 4 2 SPI2_MOSI0 I/O SPI2 1st MOSI (Master Out, Slave In) pin I2C1_SCL I/O I2C1 clock pin PA.10 I/O Digital GPIO pin SPI1_MISO0 I/O SPI1 1st MISO (Master In, Slave Out) pin 5* 5* 3* SPI2_MISO0 I/O SPI2 1st MISO (Master In, Slave Out) pin I2C1_SDA I/O I2C1 data input/output pin PD.8 I/O Digital GPIO pin 6 N SPI1_MOSI0 I/O SPI1 1st MOSI (Master Out, Slave In) pin U C 7 PD.9 I/O Digital GPIO pin 1 2 3 S PD.10 I/O Digital GPIO pin 8 E R CLKO O Frequency Divider output pin IE S PD.11 I/O Digital GPIO pin D 9 A INT1 I External interrupt 1 input pin T A S PB.4 I/O Digital GPIO pin H E E UART1_RXD I UART1 data receiver input pin T 10 6 4 SPI2_SS0 I/O SPI2 1st slave select pin SPI1_SS1 I/O SPI1 2nd slave select pin PB.5 I/O Digital GPIO pin 11 7 5 UART1_TXD O UART1 data transmitter output pin SPI2_CLK I/O SPI2 serial clock pin PB.6 I/O Digital GPIO pin 12 8 UART1_nRTS O UART1 request to send output pin May 3, 2017 Page 22 of 99 Rev.2.04

NUC123 SPI2_MOSI0 I/O SPI2 1st MOSI (Master Out, Slave In) pin PB.7 I/O Digital GPIO pin 13 9 UART1_nCTS I UART1 clear to send input pin SPI2_MISO0 I/O SPI2 1st MISO (Master In, Slave Out) pin 14 10 6 LDO_CAP P LDO output pin V P Power supply for I/O ports and LDO source for internal PLL 15 11 7 DD and digital function. Voltage range is 2.5V ~ 5V. 16 12 8 V P Ground SS 17 13 9 USB_VBUS USB Power supply from USB host or hub 18 14 10 USB_VDD33_CAP USB Internal power regulator output 3.3V decoupling pin 19 15 11 USB_D- USB USB differential signal D- 20 16 12 USB_D+ USB USB differential signal D+ PB.0 I/O Digital GPIO pin 21 UART0_RXD I UART0 data receiver input pin PB.1 I/O Digital GPIO pin 22 UART0_TXD O UART0 data transmitter output pin PB.2 I/O Digital GPIO pin 23 UART0_nRTS O UART0 request to send output pin TM2_EXT I Timer2 external capture input pin PB.3 I/O Digital GPIO pin 24 UART0_nCTS I UART0 clear to send input pin N TM3_EXT I Timer3 external capture input pin U C PC.5 I/O Digital GPIO pin 1 2 3 25 17 SPI0_MOSI1 I/O SPI0 2nd MOSI (Master Out, Slave In) pin S E R UART0_TXD O UART0 data transmitter output pin IE S PC.4 I/O Digital GPIO pin D A 26 18 SPI0_MISO1 I/O SPI0 2nd MISO (Master In, Slave Out) pin T A S UART0_RXD I UART0 data receiver input pin H E E PC.3 I/O Digital GPIO pin T 27 19 13 SPI0_MOSI0 I/O SPI0 1st MOSI (Master Out, Slave In) pin I2S_DO O I2S data output pin PC.2 I/O Digital GPIO pin 28 20 14 SPI0_MISO0 I/O SPI0 1st MISO (Master In, Slave Out) pin I2S_DI I I2S data input pin PC.1 I/O Digital GPIO pin 29 21 15 SPI0_CLK I/O SPI0 serial clock pin May 3, 2017 Page 23 of 99 Rev.2.04

NUC123 I2S_BCLK I/O I2S bit clock pin PC.0 I/O Digital GPIO pin 30 22 16 SPI0_SS0 I/O SPI0 1st slave select pin I2S_LRCLK I/O I2S left/right channel clock pin PB.10 I/O Digital GPIO pin 31 23 SPI0_SS1 I/O SPI0 2nd slave select pin TM2 I/O Timer2 event counter input / toggle output pin PB.9 I/O Digital GPIO pin SPI1_SS1 I/O SPI1 2nd slave select pin 32 24 TM1 I/O Timer1 event counter input / toggle output pin PWM1 I/O PWM1 PWM output / capture input pin (NUC123xxxAEx Only) 33 V P Ground SS PC.13 I/O Digital GPIO pin SPI1_MOSI1 I/O SPI1 2nd MOSI (Master Out, Slave In) pin 34 25 17 PWM3 I/O PWM3 PWM output / capture input pin CLKO O Frequency Divider output pin PC.12 I/O Digital GPIO pin SPI1_MISO1 I/O SPI1 2nd MISO (Master In, Slave Out) pin 35 26 18 PWM2 I/O PWM2 PWM output / capture input pin I2S_MCLK O I2S master clock output pin N U PC.11 I/O Digital GPIO pin C 36 27 19 1 SPI1_MOSI0 I/O SPI1 1st MOSI (Master Out, Slave In) pin 2 3 S PC.10 I/O Digital GPIO pin E 37 28 20 RIE SPI1_MISO0 I/O SPI1 1st MISO (Master In, Slave Out) pin S D 38 V P Power supply for I/O ports and LDO source for internal PLL A DD and digital function. Voltage range is 2.5V ~ 5V. T A S PC.9 I/O Digital GPIO pin H 39 29 21 E SPI1_CLK I/O SPI1 serial clock pin E T PC.8 I/O Digital GPIO pin SPI1_SS0 I/O SPI1 1st slave select pin 40 30 22 PWM0 I/O PWM0 PWM output / capture input pin (NUC123xxxAEx Only) PA.15 I/O Digital GPIO pin PWM3 I/O PWM3 PWM output / capture input pin 41 31 I2S_MCLK O I2S master clock output pin CLKO O Frequency Divider output pin May 3, 2017 Page 24 of 99 Rev.2.04

NUC123 42 V P Ground SS PA.14 I/O Digital GPIO pin 43 32 PWM2 I/O PWM2 PWM output / capture input pin PA.13 I/O Digital GPIO pin 44 33 PWM1 I/O PWM1 PWM output / capture input pin PA.12 I/O Digital GPIO pin 45 34 PWM0 I/O PWM0 PWM output / capture input pin 46 35 23 ICE_DAT I/O Serial wired debugger data pin 47 36 24 ICE_CLK I Serial wired debugger clock input pin 48 37 25 AV AP Power supply for internal analog circuit DD PD.0 I/O Digital GPIO pin 49 38 ADC0 AI ADC channel 0 analog input pin SPI2_SS0 I/O SPI2 1st slave select pin PD.1 I/O Digital GPIO pin SPI2_CLK I/O SPI2 serial clock pin 50 39 26 SPI0_SS1 I/O SPI0 2nd slave select pin ADC1 AI ADC channel 1 analog input pin PD.2 I/O Digital GPIO pin SPI2_MISO0 I/O SPI2 1st MISO (Master In, Slave Out) pin 51 40 27 SPI0_MISO1 I/O SPI0 2nd MISO (Master In, Slave Out) pin ADC2 AI ADC channel 2 analog input pin N U PD.3 I/O Digital GPIO pin C 1 SPI2_MOSI0 I/O SPI2 1st MOSI (Master Out, Slave In) pin 23 52 41 28 S SPI0_MOSI1 I/O SPI0 2nd MOSI (Master Out, Slave In) pin E R IE ADC3 AI ADC channel 3 analog input pin S D PD.4 I/O Digital GPIO pin A T A 53 42 ADC4 AI ADC channel 4 analog input pin S H SPI2_MISO1 I/O SPI2 2nd MISO (Master In, Slave Out) pin E E T PD.5 I/O Digital GPIO pin 54 43 ADC5 AI ADC channel 5 analog input pin SPI2_MOSI1 I/O SPI2 2nd MOSI (Master Out, Slave In) pin PB.15 I/O Digital GPIO pin 55 INT1 I External interrupt 1 input pin TM0_EXT I Timer0 external capture input pin 56 44 29 PF.0 I/O Digital GPIO pin May 3, 2017 Page 25 of 99 Rev.2.04

NUC123 XT1_OUT O External 4~24 MHz high speed crystal output pin PF.1 I/O Digital GPIO pin 57 45 30 XT1_IN I External 4~24 MHz high speed crystal input pin nRESET I External reset input: Low active, set this pin low reset chip to 58 46 31 initial state. With internal pull-up. 59 V P Ground SS Power supply for I/O ports and LDO source for internal PLL 60 V P DD and digital circuit. Voltage range is 2.5 V ~ 5V. PF.2 I/O Digital GPIO pin ADC6 AI ADC channel 6 analog input pin 61 47 I2C0_SDA I/O I2C0 data input/output pin PS2_DAT I/O PS/2 data pin PF.3 I/O Digital GPIO pin ADC7 AI ADC channel 7 analog input pin 62 48 I2C0_SCL I/O I2C0 clock pin PS2_CLK I/O PS/2 clock pin 63 1 32 PV P PLL ground SS PB.8 I/O Digital GPIO pin 64 2 TM0 I/O Timer0 event counter input / toggle output pin Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 26 of 99 Rev.2.04

NUC123 5 BLOCK DIAGRAM 5.1 NuMicro® NUC123 Block Diagram Memory Timer/PWM Analog Interface 32-bit Timer x 4 APROM & DataFlash 10-bit ADC x 8 ARM 36/68 KB Watchdog Timer Cortex-M0 PDMA 72MHz Windowed Watchdog Timer LDROM SRAM 4 KB 12/20 KB PWM/Capture Timer x 4 AHB/APB Bus Clock Control Connectivity I/O Ports LDO UART x 2 General Purpose High Speed High Speed Power On Reset Oscillator Crystal SPI x 3 I/O 22.1184 MHz 4 ~ 24 MHz I2C x 2 Reset Pin LVR I2S Low Speed Oscillator PLL PS/2 Brownout 10 KHz External Interrupt Detection USB Figure 5-1 NuMicro® NUC123 Block Diagram N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 27 of 99 Rev.2.04

NUC123 6 FUNCTIONAL DESCRIPTION 6.1 ARM® Cortex®-M0 Core The Cortex®-M0 processor, a configurable, multistage, 32-bit RISC processor, has an AMBA AHB-Lite interface and includes an NVIC component. The processor has optional hardware debug functionality, can execute Thumb code, and is compatible with other Cortex®-M profile processors. The profile supports two modes -Thread mode and Handler mode. Handler mode is entered as a result of an exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of an exception return. Figure 6-1 shows the functional controller of processor. Cortex-M0 components Cortex-M0 processor Debug Interrupts Nested Breakpoint Vectored Cortex-M0 and Interrupt Processor Watchpoint Controller Core Unit (NVIC) Wakeup Debug Interrupt Access Debugger Controller Bus Matrix Port interface (WIC) (DAP) AHB-Lite Serial Wire or interface JTAG debug port Figure 6-1 Functional Controller Diagram N U C 12 The implemented device provides: 3 S  A low gate count processor: E R IE – ARMv6-M Thumb® instruction set S D – Thumb-2 technology A T – ARMv6-M compliant 24-bit SysTick timer A S H – A 32-bit hardware multiplier E E – System interface supporting little-endian data accesses T – Ability to have deterministic, fixed-latency, interrupt handling – Load/store-multiples and multicycle-multiplies abandoned and restarted to facilitate rapid interrupt handling – C Application Binary Interface compliant exception model, which is the ARMv6- M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers – Low power sleep mode entry using Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or the return from interrupt sleep-on-exit feature  NVIC : May 3, 2017 Page 28 of 99 Rev.2.04

NUC123 – 32 external interrupt inputs, each with four levels of priority – Dedicated Non-Maskable Interrupt (NMI) input – Supports both level-sensitive and pulse-sensitive interrupt lines – Supports Wake-up Interrupt Controller (WIC) with ultra-low power sleep mode  Debug support – Four hardware breakpoints – Two watchpoints – Program Counter Sampling Register (PCSR) for non-intrusive code profiling – Single step and vector catch capabilities  Bus interfaces: – Single 32-bit AMBA-3 AHB-Lite system interface providing simple integration to all system peripherals and memory – Single 32-bit slave port supporting the DAP (Debug Access Port) N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 29 of 99 Rev.2.04

NUC123 6.2 System Manager 6.2.1 Overview The system manager provides the functions of system control, power modes, wake-up sources, reset sources, system memory map, product ID and multi-function pin control. The following sections describe the functions for  System Reset  System Power Architecture  System Memory Map  System management registers for Part Number ID, chip reset and on-chip controllers reset, and multi-functional pin control  System Timer (SysTick)  Nested Vectored Interrupt Controller (NVIC)  System Control registers 6.2.2 System Reset The system reset can be issued by one of the events listed below. These reset event flags can be read from RSTSRC register to determine the reset source. Hardware reset can reset chip through peripheral reset signals. Software reset can trigger reset through control registers.  Hardware Reset Sources – Power-on Reset (POR) – Low level on the nRESET pin – Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset) – Low Voltage Reset (LVR) N U – Brown-out Detector Reset (BOD Reset) C 1 2  Software Reset Sources 3 S – CHIP Reset will reset whole chip by writing 1 to CHIPRST (IPRSTC1[0]) E R IE – MCU Reset to reboot but keeping the booting setting from APROM or LDROM S by writing 1 to SYSRESETREQ (AIRCR[2]) D A – CPU Reset for Cortex®-M0 core Only by writing 1 to CPURST (IPRSTC1[1]) T A S Power-on Reset or CHIP_RST (IPRST1[0]) resets the whole chip including all peripherals, H E external crystal circuit and BS (ISPCON[1]) bit. E T SYSRESETREQ (AIRCR[2]) resets the whole chip including all peripherals, but does not reset external crystal circuit and BS (ISPCON[1]) bit. May 3, 2017 Page 30 of 99 Rev.2.04

NUC123 Glitch Filter nRESET 36 us ~50k ohm @5v POR_DIS_CODE(PORCR[15:0]) Power-on V DD Reset LVR_EN(BODCR[7]) Low Voltage Reset Pulse Width AVDD Reset 3.2ms BOD_RSTEN(BODCR[3]) Brown-out Reset WDT/WWDT Reset Pulse Width System Reset Reset 64 WDT clocks CHIP Reset CHIP_RST(IPRSTC1[0]) MCU Reset Software Reset Reset Pulse Width SYSRESETREQ(AIRCR[2]) 2 system clocks CPU Reset CPU_RST(IPRSTC1[1]) Figure 6-2 System Reset Resources There are a total of 8 reset sources in the NuMicro® family. In general, CPU reset is used to reset Cortex®-M0 only; the other reset sources will reset Cortex®-M0 and all peripherals. However, there are small differences between each reset source and they are listed in Table 6-1. Reset Sources POR NRESET WDT LVR BOD CHIP MCU CPU N Register U C 1 RSTSRC Bit 0 = 1 Bit 1 = 1 Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Bit 0 = 1 Bit 5 = 1 Bit 7 = 1 2 3 S CHIP_RST 0x0 - - - - - - - E R (IPRSTC1[0]) IE S BOD_EN Reload from Reload Reload Reload - Reload from Reload - D (BODCR[0]) CONFIG0 from from from CONFIG0 from A CONFIG0 CONFIG0 CONFIG0 CONFIG0 T A BOD_VL S H (BODCR[2:1]) E E T BOD_RSTEN (BODCR[3]) XTL12M_EN Reload from Reload Reload Reload Reload Reload from Reload - CONFIG0 from from from from CONFIG0 from (PWRCON [0]) CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 WDT_EN 0x1 - 0x1 - - 0x1 - - (APBCLK[0]) HCLK_S Reload from Reload Reload Reload Reload Reload from Reload - CONFIG0 from from from from CONFIG0 from (CLKSEL0[2:0]) CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 May 3, 2017 Page 31 of 99 Rev.2.04

NUC123 WDT_S 0x3 0x3 - - - - - - (CLKSEL1[1:0]) XTL12M_STB 0x0 - - - - - - - (CLKSTATUS[0]) PLL_STB 0x0 - - - - - - - (CLKSTATUS[2]) OSC10K_STB 0x0 - - - - - - - (CLKSTATUS[3]) OSC22M_STB 0x0 - - - - - - - (CLKSTATUS[4]) CLK_SW_FAIL 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - (CLKSTATUS[7]) WTE Reload from Reload Reload Reload Reload Reload from CONFIG0 from from from from CONFIG0 (WTCR[7]) CONFIG0 CONFIG0 CONFIG0 CONFIG0 WTCR 0x0700 0x0700 0x0700 0x0700 0x0700 0x0700 - - WTCRALT 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - WWDTRLD 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - WWDTCR 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 - - WWDTSR 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - WWDTCVR 0x3F 0x3F 0x3F 0x3F 0x3F 0x3F - - BS Reload from Reload Reload Reload Reload Reload from - - CONFIG0 from from from from CONFIG0 (ISPCON[1]) CONFIG0 CONFIG0 CONFIG0 CONFIG0 N U DFBADR Reload from Reload Reload Reload Reload Reload from - - C 1 CONFIG1 from from from from CONFIG1 2 CONFIG1 CONFIG1 CONFIG1 CONFIG1 3 S E CBS Reload from Reload Reload Reload Reload Reload from - - R CONFIG0 from from from from CONFIG0 IE (ISPSTA[2:1)) CONFIG0 CONFIG0 CONFIG0 CONFIG0 S D VECMAP Reload Reload Reload Reload Reload Reload base - - A T (ISPSTA[20:9]) base on base on base on base on base on on A CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 S (NUC123xxxAEx Only) H E E Other Peripheral Reset Value - T Registers FMC Registers Reset Value Note: ‘-‘ means that the value of register keeps original setting. Table 6-1 Reset Value of Registers 6.2.2.1 nRESET Reset The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage is lower than 0.2 V and the state keeps longer than 36 us (glitch filter), chip will be DD May 3, 2017 Page 32 of 99 Rev.2.04

NUC123 reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 V and the state keeps longer than 36 us (glitch filter). The RSTS_RESET (RSTSRC[1]) will DD be set to 1 if the previous reset source is nRESET reset. nRESET 0.7 VDD 36 us 0.2 V DD SS 36 us nRESET Reset SS Figure 6-3 shows the nRESET reset waveform. nRESET 0.7 VDD 36 us 0.2 V DD SS 36 us nRESET Reset SS Figure 6-3 nRESET Reset Waveform N U C 6.2.2.2 Power-On Reset (POR) 1 2 3 The Power-on reset (POR) is used to generate a stable system reset signal and forces the S E system to be reset when power-on to avoid unexpected behavior of MCU. When applying the R power to MCU, the POR module will detect the rising voltage and generate reset signal to system IE S until the voltage is ready for MCU operation. At POR reset, the RSTS_POR (RSTSRC[0]) will be D set to 1 to indicate there is a POR reset event. The RSTS_POR (RSTSRC[0]) bit can be cleared A by writing 1 to it. Figure 6-4 shows the waveform of Power-On reset. T A S H E E T V POR 0.1V V DD Power On Reset May 3, 2017 Page 33 of 99 Rev.2.04

NUC123 Figure 6-4 Power-on Reset (POR) Waveform 6.2.2.3 Low Voltage Reset (LVR) If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVR_EN (BODCR[7]) to 1, after 100us delay, LVR detection circuit will be stable and the LVR function will be active. Then LVR function will detect AV during system operation. When the DD AV voltage is lower than V and the state keeps longer than De-glitch time (16*HCLK cycles), DD LVR chip will be reset. The LVR reset will control the chip in reset state until the AV voltage rises DD above V and the state keeps longer than De-glitch time. The RSTS_RESET (RSTSRC[1]) will LVR be set to 1 if the previous reset source is nRESET reset. Figure 6-5 shows the Low Voltage Reset waveform. AV DD V LVR T T 1 2 (<De-glitch time) (=De-glitch time) T 3 (=De-glitch time) Low Voltage Reset 100 us Delay for LVR stable N U LVR_EN C 1 2 3 S E Figure 6-5 Low Voltage Reset Waveform R IE S D A 6.2.2.4 Brown-out Detector Reset (BOD Reset) T A If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit S H BOD_EN (BODCR[0]), Brown-Out Detector function will detect AV during system operation. E DD E When the AV voltage is lower than V which is decided by BOD_EN (BODCR[0]) and DD BOD T BOD_VL (BODCR[2:1]) and the state keeps longer than De-glitch time (Max(20*HCLK cycles, 1*LIRC cycle)), chip will be reset. The BOD reset will control the chip in reset state until the AV DD voltage rises above V and the state keeps longer than De-glitch time. The default value of BOD BOD_EN, BOD_VL and BOD_RSTEN is set by flash controller user configuration register CBODEN (CONFIG0[23]), CBOV1-0 (CONFIG0[22:21]) and CBORST (CONFIG0[20]) respectively. User can determine the initial BOD setting by setting the CONFIG0 register. Figure 6-6 shows the Brown-Out Detector waveform. May 3, 2017 Page 34 of 99 Rev.2.04

NUC123 AV DD V BODH Hysteresis V BODL T T 1 2 (< de-glitch time) (= de-glitch time) BODOUT T 3 (= de-glitch time) BODRSTEN Brown-out Reset Figure 6-6 Brown-Out Detector Waveform 6.2.2.5 Watch Dog Timer Reset In most industrial applications, system reliability is very important. To automatically recover the N U MCU from failure status is one way to improve system reliability. The watch dog timer (WDT) is C widely used to check if the system works fine. If the MCU is crashed or out of control, it may 1 2 cause the watch dog time-out. User may decide to enable system reset during watch dog time-out 3 S to recover the system and take action for the system crash/out-of-control after reset. E R Software can check if the reset is caused by watch dog time-out to indicate the previous reset is a IE watch dog reset and handle the failure of MCU after watch dog time-out reset by checking S D RSTS_WDT (RSTSRC[2]). A T A S H 6.2.2.6 CPU Reset, CHIP Reset and MCU Reset E E The CPU Reset means only Cortex®-M0 core is reset and all other peripherals remain the same T status after CPU reset. User can set the CPU Reset CPU_RST (IPRSTC1[1]) to 1 to assert the CPU Reset signal. The CHIP Reset is same with Power-On Reset. The CPU and all peripherals are reset and BS (ISPCON[1]) bit is automatically reloaded from CONFIG0 setting. User can set the CHIP Reset CHIP_RST (IPRSTC1[0]) to 1 to assert the CHIP Reset signal. The MCU Reset is similar with CHIP Reset. The difference is that BS (ISPCON[1]) will not be reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or LDROM. User can set the MCU Reset SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset. May 3, 2017 Page 35 of 99 Rev.2.04

NUC123 6.2.3 Power modes and Wake-up sources There are several wake-up sources in Idle mode and Power-down mode. Table 6-2 lists the available clocks for each power mode. Power Mode Normal Mode Idle Mode Power-Down Mode Definition CPU is in active state CPU is in sleep state CPU is in sleep state and all clocks stop except LIRC. SRAM content retended. Entry Condition Chip is in normal mode after CPU executes WFI instruction. CPU sets sleep mode enable system reset released and power down enable and executes WFI instruction. Wake-up Sources N/A All interrupts WDT, I²C, Timer, UART, BOD and GPIO Available Clocks All All except CPU clock LIRC After Wake-up N/A CPU back to normal mode CPU back to normal mode Table 6-2 Power Mode Difference Table System reset released Normal Mode CPU Clock ON HXT, HIRC, LIRC, HCLK, PCLK ON Flash ON CPU executes WFI Interrupts occur 1. SLEEPDEEP(SCR[2]) = 1 Wake-up events N 2. PWR_DOWN_EN (PWRCON[7]) = 1 occur U PD_WAIT_CPU (PWRCON[8]) = 1 C 3. CPU executes WFI 1 Idle Mode 2 Power-down Mode 3 S CPU Clock OFF CPU Clock OFF HXT, HIRC, LIRC, HCLK, PCLK ON E HXT, HIRC, HCLK, PCLK OFF R Flash Halt LIRC ON IE Flash Halt S D A Figure 6-7 Power Mode State Machine T A S H E E T May 3, 2017 Page 36 of 99 Rev.2.04

NUC123 1. LIRC (10 kHz OSC) ON or OFF depends on Software setting in run mode. 2. If TIMER clock source is selected as LIRC and LIRC is on. 3. If WDT clock source is selected as LIRC and LIRC is on. Normal Mode Idle Mode Power-Down Mode HXT (4~20 MHz XTL) ON ON Halt HIRC (12/16 MHz OSC) ON ON Halt LIRC (10 kHz OSC) ON ON ON/OFF1 PLL ON ON Halt LDO ON ON ON CPU ON Halt Halt HCLK/PCLK ON ON Halt SRAM retention ON ON ON FLASH ON ON Halt GPIO ON ON Halt PDMA ON ON Halt TIMER ON ON ON/OFF2 PWM ON ON Halt WDT ON ON ON/OFF3 WWDT ON ON Halt UART ON ON Halt PS/2 ON ON Halt I2C ON ON Halt NU C SPI ON ON Halt 1 2 3 I2S ON ON Halt S E R USB ON ON Halt IE S ADC ON ON Halt D A T Table 6-3 Clocks in Power Modes A S H E Wake-up sources in Power-down mode: E T WDT, I²C, Timer, UART, BOD, GPIO and USB After chip enters power down, the following wake-up sources can wake chip up to normal mode. Wake-Up Wake-Up Condition System Can Enter Power-Down Mode Again Condition* Source BOD Brown-Out Detector Interrupt After software writes 1 to clear BOD_INTF (BODCR[4]). GPIO GPIO Interrupt After software write 1 to clear the ISRC[n] bit. TIMER Timer Interrupt After software writes 1 to clear TWF (TISRx[1]) and TIF (TISRx[0]). May 3, 2017 Page 37 of 99 Rev.2.04

NUC123 WDT WDT Interrupt After software writes 1 to clear WTWKF (WTCR[5]) (Write Protect). UART nCTS wake-up After software writes 1 to clear DCTSF (UA_MSR[0]). I2C Addressing I2C device After software writes 1 to clear WKUPIF (I2CWKUPSTS[0]). USB Remote Wake-up After software writes 1 to clear BUS_STS (USBD_INTSTS[0]). Table 6-4Table 6-4 lists the condition about how to enter Power-down mode again for each peripheral. *User needs to wait this condition before setting PWR_DOWN_EN (PWRCON[7]) and execute WFI to enter Power-down mode. Wake-Up Wake-Up Condition System Can Enter Power-Down Mode Again Condition* Source BOD Brown-Out Detector Interrupt After software writes 1 to clear BOD_INTF (BODCR[4]). GPIO GPIO Interrupt After software write 1 to clear the ISRC[n] bit. TIMER Timer Interrupt After software writes 1 to clear TWF (TISRx[1]) and TIF (TISRx[0]). WDT WDT Interrupt After software writes 1 to clear WTWKF (WTCR[5]) (Write Protect). UART nCTS wake-up After software writes 1 to clear DCTSF (UA_MSR[0]). I2C Addressing I2C device After software writes 1 to clear WKUPIF (I2CWKUPSTS[0]). USB Remote Wake-up After software writes 1 to clear BUS_STS (USBD_INTSTS[0]). Table 6-4 Condition of Entering Power-down Mode Again N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 38 of 99 Rev.2.04

NUC123 6.2.4 System Power Distribution In this chip, power distribution is divided into three segments:  Analog power from AV and AV provides the power for analog components DD SS operation.  Digital power from V and V supplies the power to the internal regulator which DD SS provides a fixed 1.8 V power for digital operation and I/O pins.  USB transceiver power from VBUS offers the power for operating the USB transceiver. The outputs of internal voltage regulators, LDO and USB_VDD33_CAP, require an external capacitor which should be located close to the corresponding pin. Analog power (AV ) should be DD the same voltage level of the digital power (V ). Figure 6-8 shows the power distribution of the DD NuMicro® NUC123 series. USB USB_D+ 10-bit Transceiver USB_D- AV DD ADC NUC123 Power USB_VDD33_CAP 3.3V Distribution 1uF Low Brown- Voltage out 5V to 3.3V LDO Reset Detector USB_VBUS 22.1184 MHz 10 kHz Digital SRAM FLASH HIRC LIRC Logic Oscillator Oscillator LDO_CAP N U 1.8V 1uF C 1 2 3 PLL POR18 POR50 VDDL tDo O1.8V IO cell GPIO SE R IE S D A T A SS DD SS S V V V H P E E T Figure 6-8 NuMicro® NUC123 Power Distribution Diagram May 3, 2017 Page 39 of 99 Rev.2.04

NUC123 6.2.5 System Memory Map The NuMicro® NUC123 series provides 4G-byte addressing space. The memory locations assigned to each on-chip controllers are shown in the Table 6-5. The detailed register definition, memory space, and programming detailed will be described in the following sections for each on- chip peripherals. The NuMicro® NUC123 Series only supports little-endian data format. Address Space Token Controllers Flash and SRAM Memory Space 0x0000_0000 – 0x0000_FFFF FLASH_BA FLASH Memory Space (64KB) 0x2000_0000 – 0x2000_4FFF SRAM_BA SRAM Memory Space (20KB) AHB Controllers Space (0x5000_0000 – 0x501F_FFFF) 0x5000_0000 – 0x5000_01FF GCR_BA System Global Control Registers 0x5000_0200 – 0x5000_02FF CLK_BA Clock Control Registers 0x5000_0300 – 0x5000_03FF INT_BA Interrupt Multiplexer Control Registers 0x5000_4000 – 0x5000_7FFF GPIO_BA GPIO Control Registers 0x5000_8000 – 0x5000_BFFF PDMA_BA Peripheral DMA Control Registers 0x5000_C000 – 0x5000_FFFF FMC_BA Flash Memory Control Registers APB1 Controllers Space (0x4000_0000 ~ 0x400F_FFFF) 0x4000_4000 – 0x4000_7FFF WDT_BA Watchdog/Window Watchdog Timer Control Registers 0x4001_0000 – 0x4001_3FFF TMR01_BA Timer0/Timer1 Control Registers 0x4002_0000 – 0x4002_3FFF I2C0_BA I2C0 Interface Control Registers N 0x4003_0000 – 0x4003_3FFF SPI0_BA SPI0 with master/slave function Control Registers U C 0x4003_4000 – 0x4003_7FFF SPI1_BA SPI1 with master/slave function Control Registers 1 2 3 0x4004_0000 – 0x4004_3FFF PWMA_BA PWM0/1/2/3 Control Registers S E R 0x4005_0000 – 0x4005_3FFF UART0_BA UART0 Control Registers IE S 0x4006_0000 – 0x4006_3FFF USBD_BA USB 2.0 FS device Controller Registers D A 0x400E_0000 – 0x400E_FFFF ADC_BA Analog-Digital-Converter (ADC) Control Registers T A S APB2 Controllers Space (0x4010_0000 ~ 0x401F_FFFF) H E E 0x4010_0000 – 0x4010_3FFF PS2_BA PS/2 Interface Control Registers T 0x4011_0000 – 0x4011_3FFF TMR23_BA Timer2/Timer3 Control Registers 0x4012_0000 – 0x4012_3FFF I2C1_BA I2C1 Interface Control Registers 0x4013_0000 – 0x4013_3FFF SPI2_BA SPI2 with master/slave function Control Registers 0x4015_0000 – 0x4015_3FFF UART1_BA UART1 Control Registers 0x401A_0000 – 0x401A_3FFF I2S_BA I2S Interface Control Registers System Controllers Space (0xE000_E000 ~ 0xE000_EFFF) 0xE000_E010 – 0xE000_E0FF SCS_BA System Timer Control Registers May 3, 2017 Page 40 of 99 Rev.2.04

NUC123 0xE000_E100 – 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers 0xE000_ED00 – 0xE000_ED8F SCS_BA System Control Registers Table 6-5 Address Space Assignments for On-Chip Controllers N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 41 of 99 Rev.2.04

NUC123 6.2.6 System Timer (SysTick) The Cortex®-M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter. When system timer is enabled, it will count down from the value in the SysTick Current Value Register (SYST_CVR) to zero, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_RVR) on the next clock cycle, and then decrement on subsequent clocks. When the counter transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads. The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to zero before enabling the feature. This ensures the timer will count from the SYST_RVR value rather than an arbitrary value when it is enabled. If the SYST_RVR is zero, the timer will be maintained with a current value of zero after it is reloaded with this value. This mechanism can be used to disable the feature independently from the timer enable bit. For more detailed information, please refer to the “ARM® Cortex®-M0 Technical Reference Manual” and “ARM® v6-M Architecture Reference Manual”. N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 42 of 99 Rev.2.04

NUC123 6.2.7 Nested Vectored Interrupt Controller (NVIC) Cortex®-M0 provides an interrupt controller as an integral part of the exception mode, named as “Nested Vectored Interrupt Controller (NVIC)”. It is closely coupled to the processor kernel and provides following features:  Nested and Vectored interrupt support  Automatic processor state saving and restoration  Dynamic priority changing  Reduced and deterministic interrupt latency The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in Handler mode. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of the interrupts and most of the system exceptions can be configured to different priority levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. When any interrupts is accepted, the starting address of the interrupt service routine (ISR) is fetched from a vector table in memory. There is no need to determine which interrupt is accepted and branch to the starting address of the correlated ISR by software. While the starting address is fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the normal execution. Thus it will take less and deterministic time to process the interrupt request. The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will give priority to the higher one without delay penalty. Thus it advances the real-time capability. For more detailed information, please refer to the “ARM® Cortex®-M0 Technical Reference N Manual” and “ARM® v6-M Architecture Reference Manual”. U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 43 of 99 Rev.2.04

NUC123 6.2.7.1 Exception Model and System Interrupt Map Table 6-6 lists the exception model supported by the NuMicro® NUC123 Series. Software can set four levels of priority on some of these exceptions as well as on all interrupts. The highest user- configurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority of all the user-configurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”. Exception Name Vector Number Priority Reset 1 -3 NMI 2 -2 Hard Fault 3 -1 Reserved 4 ~ 10 Reserved SVCall 11 Configurable Reserved 12 ~ 13 Reserved PendSV 14 Configurable SysTick 15 Configurable Interrupt (IRQ0 ~ IRQ31) 16 ~ 47 Configurable Table 6-6 Exception Model Interrupt Number Vector Number (Bit In Interrupt Interrupt Name Source IP Interrupt Description Registers) 0 ~ 15 - - - System exceptions N U 16 0 BOD_OUT Brown-out Brown-out low voltage detected interrupt C 1 2 17 1 WDT_INT WDT Watchdog/Window Watchdog Timer interrupt 3 S E 18 2 EINT0 GPIO External signal interrupt from PB.14 pin R IE 19 3 EINT1 GPIO External signal interrupt from PB.15 or PD.11 pin S D 20 4 GPAB_INT GPIO External signal interrupt from PA[15:0]/PB[13:0] A T A 21 5 GPCDF_INT GPIO External interrupt from PC[15:0]/PD[15:0]/PF[3:0] S H E 22 6 PWMA_INT PWM0~3 PWM0, PWM1, PWM2 and PWM3 interrupt E T 23 7 Reserved Reserved Reserved 24 8 TMR0_INT TMR0 Timer 0 interrupt 25 9 TMR1_INT TMR1 Timer 1 interrupt 26 10 TMR2_INT TMR2 Timer 2 interrupt 27 11 TMR3_INT TMR3 Timer 3 interrupt 28 12 UART0_INT UART0 UART0 interrupt 29 13 UART1_INT UART1 UART1 interrupt 30 14 SPI0_INT SPI0 SPI0 interrupt May 3, 2017 Page 44 of 99 Rev.2.04

NUC123 31 15 SPI1_INT SPI1 SPI1 interrupt 32 16 SPI2_INT SPI2 SPI2 interrupt 33 17 Reserved Reserved Reserved 34 18 I2C0_INT I2C0 I2C0 interrupt 35 19 I2C1_INT I2C1 I2C1 interrupt 36 20 Reserved Reserved Reserved 37 21 Reserved Reserved Reserved 38 22 Reserved Reserved Reserved 39 23 USB_INT USBD USB 2.0 FS Device interrupt 40 24 PS2_INT PS/2 PS/2 interrupt 41 25 Reserved Reserved Reserved 42 26 PDMA_INT PDMA PDMA interrupt 43 27 I2S_INT I2S I2S interrupt Clock controller interrupt for chip wake-up from Power- 44 28 PWRWU_INT CLKC down state 45 29 ADC_INT ADC ADC interrupt 46 30 Reserved Reserved Reserved 47 31 Reserved Reserved Reserved Table 6-7 System Interrupt Map N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 45 of 99 Rev.2.04

NUC123 6.2.7.2 Vector Table When any interrupts is accepted, the processor will automatically fetch the starting address of the interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base address is fixed at 0x00000000. The vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. The vector number on previous page defines the order of entries in the vector table associated with exception handler entry as illustrated in previous section. Vector Table Word Offset Description 0 SP_main – The Main stack pointer Vector Number Exception Entry Pointer using that Vector Number Table 6-8 Vector Table Format 6.2.7.3 Operation Description NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set- Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write- 1-to-clear policy, both registers reading back the current enabled state of the corresponding interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become Pending; however, the interrupt will not activate. If an interrupt is Active when it is disabled, it remains in its Active state until cleared by reset or an exception return. Clearing the enable bit prevents new activations of the associated interrupt. NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current pended state of the corresponding interrupts. The Clear-Pending Register has no effect on the execution status of an Active interrupt. N NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register U C supporting four interrupts). 1 23 The general registers associated with the NVIC are all accessible from a block of memory in the S System Control Space and will be described in next section. E R IE S D A T A S H E E T May 3, 2017 Page 46 of 99 Rev.2.04

NUC123 6.3 Clock Controller 6.3.1 Overview The clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and clock divider. The chip enters Power-down mode when Cortex®-M0 core executes the WFI instruction only if the PWR_DOWN_EN (PWRCON[7]) bit and PD_WAIT_CPU (PWRCON[8]) bit are both set to 1. After that, chip enters Power-down mode and wait for wake-up interrupt source triggered to leave Power-down mode. In the Power-down mode, the clock controller turns off the 4~24 MHz external high speed crystal oscillator and 22.1184 MHz internal high speed RC oscillator to reduce the overall system power consumption. The Figure 6-9 and Figure 6-10 show the clock generator and the overview of the clock source control. The clock generator consists of 4 clock sources as listed below:  4~24 MHz external high speed crystal oscillator (HXT)  Programmable PLL output clock frequency(PLL FOUT), PLL source can be from 4~24 MHz external high speed crystal oscillator (HXT) or 22.1184 MHz internal high speed RC oscillator (HIRC))  22.1184 MHz internal high speed RC oscillator (HIRC)  10 kHz internal low speed RC oscillator (LIRC) Each of these clock sources has certain stable time to wait for clock operating at stable frequency. When clock source is enabled, a stable counter start counting and correlated clock stable index (OSC22M_STB(CLKSTATUS[4]), OSC10K_STB(CLKSTATUS[3]), PLL_STB(CLKSTATUS[2]) and XTL12M_STB(CLKSTATUS[0])) are set to 1 after stable counter value reach a define value asshown in Table 6-9. System and peripheral can use the clock as its operating clock only when correlate clock stable index is set to 1. The clock stable index will auto N U clear when user disables the clock source (OSC10K_EN(PWRCON[3]), C OSC22M_EN(PWRCON[2]), XTL12M_EN(PWRCON[0]) and PD(PLLCON[16])). Besides, the 1 2 clock stable index of HXT, HIRC and PLL will auto clear when chip enter power-down and clock 3 S stable counter will re-counting after chip wake-up if correlate clock is enabled. E R IE Clock Source Clock Stable Count Value S D HXT 4096 HXT clock A T A PLL 6144 PLL source S H (PLL source is HXT if PLL_SRC(PLLCON[19]) = 0, or HIRC if PLL_SRC(PLLCON[19]) = 1) E E HIRC 256 HIRC clock T LIRC 1 LIRC Table 6-9 Clock Stable Count Value Table May 3, 2017 Page 47 of 99 Rev.2.04

NUC123 XTL12M_EN (PWRCON[0]) HXT XT1_OUT 4~24 MHz PLL_SRC (PLLCON[19]) HXT XT1_IN 0 PLL FOUT PLL OSC22M_EN (PWRCON[2]) 1 22.1184 MHz HIRC HIRC OSC10K_EN (PWRCON[3]) 10 kHz LIRC LIRC Legend: HXT = 4~24 MHz external high speed crystal oscillator HIRC = 22.1184 MHz internal high speed RC oscillator LIRC = 10 kHz internal low speed RC oscillator Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6-9 Clock Generator Global View Diagram N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 48 of 99 Rev.2.04

NUC123 LIRC (10 kHz) HIRC 111 LIRC CPUCLK CPU 011 HIRC PLLFOUT 010 1/(HCLK_N+1) HCLK AHB (22.1184 MHz) 1/2 001 PDMA HXT 000 HXT 1/(APBDIV+1) PCLK APB (4~12 MHz) I2C 0-1 CLKSEL0[2:0] HIRC 111 HIRC LIRC 1 PLLFOUT 100 TMR 0 HXT PLL TMx, x = 0, 1, 2 0 011 TMR 1 HCLK 010 TMR 2 PLLCON[19] HXT 000 TMR 3 HIRC CLKSEL1[22:20] LIRC BOD 1/2 111 CLKSEL1[18:16] CLKSEL1[14:12] HCLK 1/2 011 CLKSEL1[10: 8] SysTick 1/2 010 HXT LIRC 000 111 HIRC 011 HCLK PWM 2-3 CLKSEL0[5:3] 010 HXT PWM 0-1 000 PS2 {CLKSEL2[9], CLKSEL1[31:30]} HIRC HIRC FMC 11 {CLKSEL2[8], CLKSEL1[29:28]} HCLK 10 FDIV HXT 00 HIRC 11 HCLK CLKSEL2[3:2] 10 PLLFOUT I2S 01 HXT 1/(ADC_N+1) ADC 00 N CLKSEL2[1:0] U C CLKSEL1[3:2] 1 2 3 PLLFOUT 1/(USB_N+1) USB S LIRC 11 E R WDT IE HCLK 1/2048 10 S D LIRC CLKSEL1[1:0] 11 A T WWDT A HCLK S 1/2048 10 H HIRC E 11 CLKSEL2[17:16] E T PLLFOUT 01 1/(UART_N+1) UART0/1 HXT 00 HCLK 1 PLLFOUT SPI0 CLKSEL1[25:24] 0 SPI1 CLKSEL1[4] SPI2 CLKSEL1[5] CLKSEL1[6] Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6-10 Clock Generator Global View Diagram May 3, 2017 Page 49 of 99 Rev.2.04

NUC123 6.3.2 System Clock and SysTick Clock The system clock has 5 clock sources which were generated from clock generator block. The clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is shown in Figure 6-11. HIRC (22.1184 MHz) 111 LIRC (10 KHz) 011 CPUCLK CPU PLLFOUT 010 1/(HCLK_N+1) HCLK AHB 1/2 001 HXT (4~24 MHz) 000 CPU in Power Down Mode 1/(APBDIV+1) PCLK APB HCLK_S (CLKSEL0[2:0]) Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6-11 System Clock Block Diagram The clock source of SysTick in Cortex®-M0 core can use CPU clock or external clock (SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources. The clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block diagram is shown in Figure 6-12. HIRC (22.1184 MHz) 1/2 111 HCLK 1/2 011 STCLK 1/2 010 HXT (4~24 MHz) 000 N U C STCLK_S (CLKSEL0[5:3]) 1 2 3 Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on S and stable. E R IE Figure 6-12 SysTick Clock Control Block Diagram S D A T A 6.3.3 Peripherals Clock S H E E The peripherals clock had different clock source switch setting depending on different peripherals. T Please refer to the CLKSEL1 and CLKSEL2 register description in TRM. 6.3.4 Power-down Mode Clock When chip enters into Power-down mode, system clocks, some clock sources, and some peripheral clocks will be disabled. Some clock sources and peripherals clock are still active in Power-down mode. The clocks kept active are listed below:  Clock Generator – Internal 10 kHz low speed oscillator clock May 3, 2017 Page 50 of 99 Rev.2.04

NUC123  WDT/Timer/PWM Peripherals Clock (when 10 kHz intertnal low speed RC oscillator (LIRC) is adopted as clock source) 6.3.5 Frequency Divider Output This device is equipped with a power-of-2 frequency divider which is composed by16 chained divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided clocks with the frequency from F /21 to F /216 where Fin is input clock frequency to the clock in in divider. The output formula is F = F /2(N+1), where F is the input clock frequency, F is the clock out in in out divider output frequency and N is the 4-bit value in FSEL (FRQDIV[3:0]). When writing 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When writing 0 to DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low state and stay in low state. HIRC (22.1184 MHz) 11 HCLK 10 HXT (4~24 MHz) FRQDIV_CLK 00 FDIV_EN (APBCLK[6]) FRQDIV_S (CLKSEL2[3:2]) Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6-13 Clock Source of Frequency Divider N U C DIVIDER_EN 1 (FRQDIV[4]) 2 3 Enable S 16 chained E divide-by-2 counter R divide-by-2 counter IE FRQDIV_CLK S 1/2 1/22 1/23 …... 1/215 1/216 D A T 0000 A 0001 S : 16 to 1 CLKO H : MUX E E 1110 T 1111 FSEL (FRQDIV[3:0]) Figure 6-14 Block Diagram of Frequency Divider May 3, 2017 Page 51 of 99 Rev.2.04

NUC123 6.4 Flash Memory Controller (FMC) 6.4.1 Overview The NuMicro® NUC123 series is equipped with 68/36 Kbytes on-chip embedded flash for application program memory (APROM) and Data Flash, and 4 Kbytes for ISP loader program memory (LDROM) that could be programmed boot loader to update APROM and Data Flash through In-System-Programming (ISP) procedure. The ISP function enables user to update embedded flash when chip is soldered on PCB. After chip is powered on, Cortex®-M0 CPU fetches code from APROM or LDROM decided by boot select (CBS (Config0[7:6]). User can also select to enable or disable In-Application-Programming (IAP) function through boot select (CBS (Config0[7:6]). Also, the NUC123 provides Data Flash for user, to store some application dependent data before chip is powered off. 6.4.2 Features  Runs up to 72 MHz and optional up to 50MHz with zero wait state for continuous address read access  Supports 68/36 KB application program ROM (APROM)  Supports 4KB loader ROM (LDROM)  Supports Data Flash with configurable memory size  Supports 8 bytes User Configuration block to control system initiation  Supports 512 bytes page erase for all embedded flash  Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update embedded flash memory N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 52 of 99 Rev.2.04

NUC123 6.5 General Purpose I/O (GPIO) 6.5.1 Overview The NuMicro® NUC123 series has up to 47 General Purpose I/O pins shared with other function pins depending on the chip configuration. These 47 pins are arranged in 5 ports named GPIOA, GPIOB, GPIOC, GPIOD and GPIOF. GPIOA has 6 pins on PA[15:10]. GPIOB has 15 pins on PB[15:12] and PB[10:0]. GPIOC has 12 pins on PC[13:8] and PC[5:0]. GPIOD has 10 pins on PD[11:8] and PD[5:0]. GPIOF has 4 pins on PF[3:0]. Each one of the 47 pins is independent and has the corresponding register bits to control the pin mode function and data. The I/O type of each of I/O pins can be configured by software individually as input, output, open- drain or quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins are depending on CIOINI (Config0[10]) (NUC123xxxAEx Only). Each I/O pin has a very weakly individual pull-up resistor which is about 110 K~300 K for V is from 5.0 V to 2.5 V. DD 6.5.2 Features  Four I/O modes: – Quasi bi-direction – Push-Pull output – Open-Drain output – Input only with high impendence  TTL/Schmitt trigger input selectable by GPx_TYPE[15:0] in GPx_MFP[31:16]  I/O pin can be configured as interrupt source with edge/level setting  Supports High Driver and High Sink I/O mode  Configurable default I/O mode of all pins after reset by CIOINI (Config0[10]) setting (NUC123xxxAEx Only) – If CIOINI (Config[10]) is 0, all GPIO pins in input tri-state mode after chip reset N U C – If CIOINI (Config[10]) is 1, all GPIO pins in Quasi-bidirectional mode after chip reset 1 2 3  I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode S E  Enabling the pin interrupt function will also enable the wake-up function R IE S D A T A S H E E T May 3, 2017 Page 53 of 99 Rev.2.04

NUC123 6.6 PDMA Controller (PDMA) 6.6.1 Overview The NuMicro® NUC123 contains a six-channel peripheral direct memory access (PDMA) controller and a cyclic redundancy check (CRC) generator. The PDMA can transfer data to and from memory or transfer data to and from APB devices. For PDMA channel (PDMA CH0~CH5), there is one-word buffer as transfer buffer between the Peripherals APB devices and Memory. The CPU can recognize the completion of a PDMA operation by software polling or when it receives an internal PDMA interrupt. The PDMA controller can increase source or destination address or fixed them as well. The PDMA controller contains a cyclic redundancy check (CRC) generator that can perform CRC calculation with programmable polynomial settings. The CRC engine supports CPU PIO mode and PDMA transfer mode. 6.6.2 Features  Supports six PDMA channels and one CRC channel; each PDMA channel can support a unidirectional transfer  AMBA AHB master/slave interface compatible, for data transfer and register read/write  Hardware round robin priority scheme. PDMA channel 0 has the highest priority  PDMA – Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer – Supports word/half-word/byte transfer data width from/to peripheral – Supports address direction: increment, fixed – Supports software, SPI, UART, ADC, PWM and I2S request  Cyclic Redundancy Check (CRC) N U – Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 C 12  CRC-CCITT: X16 + X12 + X5 + 1 3 S  CRC-8: X8 + X2 + X + 1 E  CRC-16: X16 + X15 + X2 + 1 R IE  CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 S D – Programmable seed value A T – Supports programmable order reverse setting for input data and CRC checksum A S H – Supports programmable 1’s complement setting for input data and CRC checksum. E E T – Supports CPU PIO mode or PDMA transfer mode – Supports 8/16/32-bit of data width in CPU PIO mode  8-bit write mode: 1-AHB clock cycle operation  16-bit write mode: 2-AHB clock cycle operation  32-bit write mode: 4-AHB clock cycle operation – Supports byte alignment transfer length in CRC PDMA mode May 3, 2017 Page 54 of 99 Rev.2.04

NUC123 6.7 Timer Controller (TMR) 6.7.1 Overview The Timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily implement a timer control for applications. The timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins. 6.7.2 Features  Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter  Independent clock source for each timer  Provides one-shot, periodic, toggle-output and continuous counting operation modes  24-bit up counter value is readable through TDR (TDR[23:0])  Supports event counting function  24-bit capture value is readable through TCAP (TCAP[23:0])  Supports external capture pin event for interval measurement  Supports external capture pin event to reset 24-bit up counter  Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 55 of 99 Rev.2.04

NUC123 6.8 PWM Generator and Capture Timer (PWM) 6.8.1 Overview The NuMicro® NUC123 series has 1 set of PWM group supporting 1 set of PWM generators which can be configured as 4 independent PWM outputs, PWM0~PWM3, or as 2 complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3) with two programmable dead-zone generators. PWM output function can be alternated to capture function. Each PWM generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM down-counters for PWM period control, two 16-bit comparators for PWM duty control and one dead-zone generator. The PWM generators provide four independent PWM interrupt flags which are set by hardware when the corresponding PWM period down counter reaches zero. Each PWM interrupt source with its corresponding enable bit can cause CPU to request PWM interrupt. The PWM generators can be configured as one-shot mode to produce only one PWM cycle signal or auto-reload mode to output PWM waveform continuously. PWM can be used to trigger ADC when operation in center-aligned mode. 6.8.2 Features PWM function:  Up to 1 PWM group (PWMA) to support 4 PWM channels or 2 PWM paired channels  Supports 8-bit prescaler from 1 to 255  Up to 16-bit resolution PWM timer  PWM timer supports down and up-down operation type  One-shot or Auto-reload mode PWM  PWM Interrupt request synchronized with PWM period or duty N U C  Supports dead-zone generator with 8-bit resolution for 2 PWM paired channels 1 2 3  Supports trigger ADC on center point in center-aligned mode S E R IE Capture function: S D  Supports 4 Capture input channels shared with 4 PWM output channels A T A  Supports rising or falling capture condition S H  Supports rising or falling capture interrupt E E T  Supports PDMA transfer function for each channel May 3, 2017 Page 56 of 99 Rev.2.04

NUC123 6.9 Watchdog Timer (WDT) 6.9.1 Overview The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer supports the function to wake-up system from Idle/Power-down mode. 6.9.2 Features  18-bit free running up counter for WDT time-out interval  Selectable time-out interval (24 ~ 218) and the time-out interval is 1.6 ms ~ 26.214 s if WDT_CLK = 10 kHz.  System kept in reset state for a period of (1 / WDT_CLK) * 63  Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK reset delay period  Supports to force WDT enabled after chip powered on or reset by setting CWDTEN in Config0 register  Supports WDT time-out wake-up function only if WDT clock source is selected as 10 kHz. N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 57 of 99 Rev.2.04

NUC123 6.10 Window Watchdog Timer (WWDT) 6.10.1 Overview The Window Watchdog Timer is used to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. The 6-bit down counter value will stop to update when chip is in Idle or Power-down mode. 6.10.2 Features  6-bit down counter value WWDTCVAL (WWDTCVR[5:0]) and 6-bit compare value WINCMP (WWDTCR[21:16]) to make the WWDT time-out window period flexible  Supports 4-bit value PERIODSEL (WWDTCR[11:8]) to programmable maximum 11-bit prescale counter period of WWDT counter N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 58 of 99 Rev.2.04

NUC123 6.11 UART Interface Controller (UART) 6.11.1 Overview The NuMicro® NUC123 series provides two channels of Universal Asynchronous Receiver/ Transmitters (UART). UART Controller performs Normal Speed UART and supports flow control function. The UART Controller performs a serial-to-parallel conversion on data received from the peripheral and a parallel-to-serial conversion on data transmitted from the CPU. Each UART Controller channel supports six types of interrupts. The UART controller also supports IrDA SIR and RS-485. 6.11.2 Features  Full duplex, asynchronous communications  Separates receive / transmit 16/16 bytes entry FIFO for data payloads  Supports hardware auto flow control/flow control  Programmable receiver buffer trigger level  Supports programmable baud-rate generator for each channel individually  Supports nCTS wake-up function  Supports 8-bit receiver buffer time-out detection function  UART0/UART1 served by the DMA controller  Programmable transmitting data delay time between the last stop and the next start bit by setting DLY (UA_TOR [15:8])  Supports break error, frame error, parity error and receive/transmit buffer overflow detect function  Fully programmable serial-interface characteristics N U – Programmable number of data bit, 5-, 6-, 7-, 8-bit character C 1 2 – Programmable parity bit, even, odd, no parity or stick parity bit generation and 3 detection S E R – Programmable stop bit, 1, 1.5, or 2 stop bit generation IE S  Supports IrDA SIR function mode D A – Supports for 3/16-bit duration for normal mode T A S  Supports RS-485 function mode. H E E – Supports RS-485 9-bit mode T – Supports hardware or software direct enable to program nRTS pin to control RS-485 transmission direction May 3, 2017 Page 59 of 99 Rev.2.04

NUC123 6.12 PS/2 Device Controller (PS2D) 6.12.1 Overview PS/2 device controller provides basic timing control for PS/2 communication. All communication between the device and the host is managed through the CLK and DATA pins. Unlike PS/2 keyboard or mouse device controller, the received/transmit code needs to be translated as meaningful code by firmware. The device controller generates the CLK signal after receiving a request to send, but host has ultimate control over communication. DATA sent from the host to the device is read on the rising edge and DATA sent from device to the host is change after rising edge. A 16 bytes FIFO is used to reduce CPU intervention. Software can select 1 to 16 bytes for a continuous transmission. 6.12.2 Features  Host communication inhibit and request to send detection  Reception frame error detection  Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention  Double buffer for data reception  S/W override bus N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 60 of 99 Rev.2.04

NUC123 6.13 I2C Serial Interface Controller (Master/Slave) (I2C) 6.13.1 Overview I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. There are two sets of I2C controllers which support Power-down wake-up function. 6.13.2 Features  Supports up to two I2C ports  Master/Slave mode  Bidirectional data transfer between masters and slaves  Multi-master bus (no central master)  Arbitration between simultaneously transmitting masters without corruption of serial data on the bus  Serial clock synchronization allow devices with different bit rates to communicate via one serial bus  Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and timer- out counter overflows.  Programmable clocks allow for versatile rate control  Supports 7-bit addressing mode  Supports multiple address recognition ( four slave address with mask option)  Supports Power-down wake-up function N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 61 of 99 Rev.2.04

NUC123 6.14 Serial Peripheral Interface (SPI) 6.14.1 Overview The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full duplex transfer. Devices communicate in Master/Slave mode with 4-wire bi-direction interface. This NuMicro® NUC123 series contains up to three sets of SPI controllers performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. Each set of SPI controller can be configured as a Master or a Slave device. This controller supports variable serial clock function for special application and it also supports 2- bit Transfer mode. The controller also supports PDMA function to access the data buffer and also supports Dual I/O transfer mode. 6.14.2 Features  Up to three sets of SPI controllers  Supports Master or Slave mode operation  Supports 2-bit Transfer mode  Supports Dual I/O transfer mode  Configurable bit length of a transfer word from 8 to 32-bit  Provide separate 8-layer depth transmit and receive FIFO buffers  Supports MSB first or LSB first transfer sequence  Up to two slave select lines in Master mode  Supports Byte Reorder function  Supports configurable suspend interval in Master mode  Variable output serial clock frequency in Master mode N U C  Supports PDMA transfer 1 2 3  Supports 3-Wire, no slave select signal, bi-direction interface S E R IE S D A T A S H E E T May 3, 2017 Page 62 of 99 Rev.2.04

NUC123 6.15 I2S Controller (I2S) 6.15.1 Overview The I2S controller consists of IIS protocol to interface with external audio CODEC. Two 8 word depth FIFO buffers for read path and write path respectively and is capable of handling 8/16/24/32 bits word sizes. PDMA controller handles the data movement between FIFO and memory. 6.15.2 Features  Operated as either Master or Slave  Capable of handling 8, 16, 24 and 32 bits word  Supports monaural and stereo audio data  Supports four data format: – I2S data format – MSB justified data format – PCM mode A – PCM mode B  Provides two 8 word depth FIFO buffers, one for transmitting and the other for receiving  Generates interrupt requests when buffer levels cross a programmable boundary  Supports PDMA transfer N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 63 of 99 Rev.2.04

NUC123 6.16 USB Device Controller (USB) 6.16.1 Overview There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant with USB 2.0 full-speed device specification and supports Control/Bulk/Interrupt/ Isochronous transfer types. In this device controller, there are two main interfaces: APB bus and USB bus which comes from the USB PHY transceiver. For the APB bus, the CPU can program control registers through it. There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User needs to set the effective starting address of SRAM for each endpoint buffer through buffer segmentation register (BUFSEGx). There are 8 endpoints in this controller. Each of the endpoint can be configured as IN or OUT endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are implemented in this block. The block of ENDPOINT CONTROL is also used to manage the data sequential synchronization, endpoint state control, current start address, transaction status, and data buffer status for each endpoint. There are four different interrupt events in this controller. They are the wake-up event, device plug-in or plug-out event, USB events, such as IN ACK, OUT ACK, and BUS events, such as suspend and resume, etc. Any event will cause an interrupt, and user just needs to check the related event flags in interrupt event status register (USB_INTSTS) to acknowledge what kind of interrupt occurring, and then check the related USB Endpoint Status Register (USB_EPSTS) to acknowledge what kind of event occurring in this endpoint. A software-disable function is also supported for this USB controller. It is used to simulate the disconnection of this device from the host. If user enables DRVSE0 bit (USB_DRVSE0), the USB controller will force the output of USB_D+ and USB_D- to level low and its function is disabled. After disable the DRVSE0 bit, host will enumerate this USB device again. For more information on the Universal Serial Bus, please refer to Universal Serial Bus Specification Revision 1.1. N U C 1 2 3 6.16.2 Features S E R  Compliant with USB 2.0 Full-Speed specification IE S D  Provides 1 interrupt vector with 4 different interrupt events (WAKEUP, FLDET, USB and A BUS) T A S  Supports Control/Bulk/Interrupt/Isochronous transfer types H E  Supports suspend function when no bus activity existing for 3 ms E T  Provides 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types and maximum 512 bytes buffer size  Provides remote wake-up capability May 3, 2017 Page 64 of 99 Rev.2.04

NUC123 6.17 Analog-to-Digital Converter (ADC) 6.17.1 Overview NuMicro® NUC123 Series contains one 10-bit successive approximation analog-to-digital converters (SAR A/D converter) with 8 input channels. The A/D converter supports three operation modes: single, single-cycle scan and continuous scan mode. The A/D converters can be started by software, PWM center-aligned trigger and external STADC pin. 6.17.2 Features  Conversion range : 0 to AV DD  10-bit resolution and 8-bit accuracy is guaranteed  Up to 8 single-end analog input channels  Maximum ADC clock frequency as 6 MHz (NUC123xxxANx Only)  Maximum ADC clock frequency as 3 MHz (NUC123xxxAEx Only)  Up to 166 kSPS (Samples Per Second) conversion rate (NUC123xxxANx Only)  Up to 200 kSPS (Samples Per Second) conversion rate (NUC123xxxAEx Only)  Three operating modes – Single mode: A/D conversion is performed one time on a specified channel – Single-cycle Scan mode: A/D conversion is performed one cycle on all specified channels with the sequence from the lowest numbered channel to the highest numbered channel – Continuous Scan mode: A/D converter continuously performs Single-cycle scan mode until software stops A/D conversion  A/D conversion started by: – Software writes 1 to ADST bit N U C – External pin STADC (PB.8) 1 2 3 – PWM center-aligned trigger S E  Supports 8 data registers to stored conversion result with valid and overrun indicators R IE  Supports 2 sets of digital comparators to monitor conversion result of specified channel and S D to generate an interrupt when conversion result matches comparison condition A T  Channel 7 supports 2 input sources: external analog voltage and internal band-gap voltage A S H  Supports PDMA transfer E E T May 3, 2017 Page 65 of 99 Rev.2.04

NUC123 7 ELECTRICAL CHARACTERISTICS (NUC123XXXANX) 7.1 Absolute Maximum Ratings Symbol Parameter Min Max Unit V  V DC Power Supply -0.3 +7.0 V DD SS V Input Voltage V - 0.3 V + 0.3 V IN SS DD 1/t Oscillator Frequency 4 24 MHz CLCL T Operating Temperature -40 +85 A T Storage Temperature -55 +150 ℃ ST I Maximum Current into V - 120 mA DD DD I Maximum Current out of V 120 mA SS SS Maximum Current sunk by a I/O pin 35 mA Maximum Current sourced by a I/O pin 35 mA I IO Maximum Current sunk by total I/O pins 100 mA Maximum Current sourced by total I/O pins 100 mA Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the lift and reliability of the device. N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 66 of 99 Rev.2.04

NUC123 7.2 DC Electrical Characteristics (VDD -VSS = 5.5 V, TA = 25C) SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT Operation voltage V 2.5 5.5 V V = 2.5V ~ 5.5V up to 72 MHz DD DD V rise rate to ensure internal DD V 0.05 V/ms operation correctly RISE V SS Power ground -0.3 V AV SS LDO output voltage V 1.62 1.8 1.98 V V > 2.5V LDO DD When system uses analog function, Analog operating voltage AV 0 V V please refer to chapter 7.4 for DD DD corresponding analog operating voltage V = 5.5V at 72 MHz, DD IDD1 36 mA All IP and PLL Enabled, XTAL = 12 MHz V = 5.5V at 72 MHz, DD IDD2 21 mA All IP Disabled and PLL Enabled, XTAL = Operating current 12 MHz Normal Run mode V = 3V at 72 MHz, at 72 MHz DD IDD3 35 mA All IP and PLL enabled, XTAL = 12 MHz V = 3V at 72 MHz, N DD U IDD4 20 mA All IP Disabled and PLL Enabled, XTAL = C 12 MHz 1 2 3 V = 5.5V at 12 MHz, S DD E IDD5 7 mA All IP Enabled and PLL Disabled, XTAL = R 12 MHz IE S V = 5.5V at 12 MHz, D DD A IDD6 4 mA All IP and PLL Disabled, T Operating current XTAL = 12 MHz A S Normal Run mode H V = 3V at 12 MHz, E at 12 MHz DD E IDD7 6 mA All IP Enabled and PLL Disabled, XTAL = T 12 MHz V = 3V at 12 MHz, DD I 3 mA All IP and PLL Disabled, DD8 XTAL = 12 MHz V = 5V at 4 MHz, Operating current DD IDD9 4 mA All IP Enabled and PLL Disabled, XTAL = Normal Run mode 4 MHz May 3, 2017 Page 67 of 99 Rev.2.04

NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT at 4 MHz V = 5V at 4 MHz, DD IDD10 3 mA All IP and PLL Disabled, XTAL = 4 MHz V = 3V at 4 MHz, DD IDD11 4 mA All IP Enabled and PLL Disabled, XTAL = 4 MHz V = 3V at 4 MHz, DD IDD12 2 mA All IP and PLL Disabled, XTAL = 4 MHz V = 5.5V at 72 MHz, DD IIDLE1 29 mA All IP and PLL Enabled, XTAL = 12 MHz V = 5.5V at 72 MHz, DD IIDLE2 14 mA All IP Disabled and PLL Enabled, XTAL = Operating current 12 MHz Idle mode V = 3V at 72 MHz, at 72 MHz DD IIDLE3 28 mA All IP and PLL Enabled, XTAL = 12 MHz V = 3V at 72 MHz, DD IIDLE4 13 mA All IP Disabled and PLL Enabled, XTAL=12 MHz V = 5.5V at 12 MHz, DD IIDLE5 6 mA All IP Enabled and PLL Disabled, XTAL = 12 MHz V = 5.5V at 12 MHz, DD N U IIDLE6 3 mA All IP and PLL Disabled, Operating current C XTAL = 12 MHz 1 Idle mode 2 3 V = 3V at 12 MHz, S at 12 MHz DD E IIDLE7 5 mA All IP Enabled and PLL Disabled, XTAL = R 12 MHz IE S V = 3 V at 12 MHz, D DD A IIDLE8 2 mA All IP and PLL Disabled, T XTAL = 12 MHz A S H V = 5V at 4 MHz, DD E E IIDLE9 3 mA All IP Enabled and PLL Disabled, XTAL = T 4 MHz V = 5V at 4 MHz, DD IIDLE10 2 mA All IP and PLL Disabled, Operating current XTAL = 4 MHz Idle mode V = 3V at 4 MHz, at 4 MHz DD IIDLE11 2 mA All IP Enabled and PLL Disabled, XTAL = 4 MHz V = 3V at 4 MHz, DD IIDLE12 1 mA All IP and PLL Disabled, XTAL = 4 MHz May 3, 2017 Page 68 of 99 Rev.2.04

NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT V = 5.5V at 10 kHz, DD IIDLE5 131 uA All IP Enabled and PLL Disabled, LIRC 10 kHz Enabled V = 5.5V at 10 kHz, DD IIDLE6 129 uA All IP and PLL Disabled, Operating current LIRC 10 kHz Enabled Idle mode V = 3V at 10 kHz, at 10 kHz DD IIDLE7 125 uA All IP Enabled and PLL Disabled, LIRC 10 kHz Enabled V = 3 V at 10 kHz, DD IIDLE8 124 uA All IP and PLL Disabled, LIRC 10 kHz Enabled V = 5.5V, No load DD I 12 A PWD1 Standby current when BOV function Disabled Power-down mode V = 3.3V, No load DD I 9 A PWD2 when BOV function Disabled Input Current PA, PB, PC, PD, PE, I -64 A V = 5.5V, V = 0V or V = V PF (Quasi-bidirectional mode) IN1 DD IN IN DD Input Current at /RESET[1] IIN2 -55 -45 -30 A VDD = 3.3V, VIN = 0.45V Input Leakage Current PA, PB, PC, I -2 - +2 A V = 5.5V, 0 < V < V PD, PE, PF LK DD IN DD Logic 1 to 0 Transition Current I [3] -650 - -200 A V = 5.5V, V < 2.0V PA~PF (Quasi-bidirectional mode) TL DD IN -0.3 - 0.8 V = 4.5V Input Low Voltage PA, PB, PC, PD, V V DD N PE, PF (TTL input) IL1 U -0.3 - 0.6 VDD = 2.5V C 1 2 Input High Voltage PA, PB, PC, 2.0 - VDD +0.2 VDD = 5.5V 3 PD, PE, PF (TTL input) VIH1 V S 1.5 - V +0.2 V = 3.0V E DD DD R Input Low Voltage PA, PB, PC, PD, IE V -0.5 - 0.35 V V S PE, PF (Schmitt input) IL2 DD D A Input High Voltage PA, PB, PC, T PD, PE, PF (Schmitt input) VIH2 0.65 VDD - VDD+0.5 V A S H Hysteresis voltage of PA~PE E (Schmitt input) VHY 0.2 VDD V E T 0 - 0.8 V = 4.5V DD Input Low Voltage XT1[*2] V V IL3 0 - 0.4 V = 3.0V DD 3.5 - V +0.2 V V = 5.5V DD DD Input High Voltage XT1[*2] V IH3 2.4 - V +0.2 V = 3.0V DD DD Negative going threshold V -0.5 - 0.2 V V ILS DD (Schmitt input), /RESET Positive going threshold V 0.6 V - V +0.5 V IHS DD DD (Schmitt input), /RESET May 3, 2017 Page 69 of 99 Rev.2.04

NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT ISR11 -300 -370 -450 A VDD = 4.5V, VS = 2.4V Source Current PA, PB, PC, PD, PE, PF (Quasi-bidirectional Mode) ISR12 -50 -70 -90 A VDD = 2.7V, VS = 2.2V I -40 -60 -80 A V = 2.5V, V = 2.0V SR12 DD S I -20 -24 -28 mA V = 4.5V, V = 2.4V SR21 DD S Source Current PA, PB, PC, PD, I -4 -6 -8 mA V = 2.7V, V = 2.2V PE, PF (Push-pull Mode) SR22 DD S I -3 -5 -7 mA V = 2.5V, V = 2.0V SR22 DD S I 10 16 20 mA V = 4.5V, V = 0.45V SK1 DD S Sink Current PA, PB, PC, PD, PE, PF (Quasi-bidirectional and Push- I 7 10 13 mA V = 2.7V, V = 0.45V SK1 DD S pull Mode) I 6 9 12 mA V = 2.5V, V = 0.45V SK1 DD S Brown-out voltage with V 2.1 2.2 2.3 V BOV_VL [1:0] =00b BO2.2 Brown-out voltage with V 2.6 2.7 2.8 V BOV_VL [1:0] =01b BO2.7 Brown-out voltage with V 3.7 3.8 3.9 V BOV_VL [1:0] =10b BO3.8 Brown-out voltage with V 4.4 4.5 4.6 V BOV_VL [1:0] =11b BO4.5 Hysteresis range of BOD voltage V 30 - 150 mV V = 2.5V - 5.5V BH DD Notes: 1. nRESET pin is a Schmitt trigger input. 2. Crystal Input is a CMOS input. N U 3. Pins of PA, PB, PC, PD and PE can source a transition current when they are being externally driven from 1 to 0. In the C 1 condition of VDD=5.5 V, 5he transition current reaches its maximum value when VIN approximates to 2V. 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 70 of 99 Rev.2.04

NUC123 7.3 AC Electrical Characteristics 7.3.1 External 4~24 MHz High Speed Oscillator t CLCL t CLCH 0.7 V 90% DD t CLCX 10% 0.3 V DD t t CHCL CHCX Note: Duty cycle is 50%. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT t Clock High Time 10 - - nS CHCX t Clock Low Time 10 - - nS CLCX t Clock Rise Time 2 - 15 nS CLCH t Clock Fall Time 2 - 15 nS CHCL 7.3.2 External 4~24 MHz High Speed Crystal PARAMETER CONDITIONS MIN TYP MAX UNIT Input clock frequency External crystal 4 12 24 MHz Temperature - -40 - 85 ℃ V - 2.5 5 5.5 V DD N U 7.3.2.1 Typical Crystal Application Circuits C 1 2 CRYSTAL C1 C2 R 3 S E 4 MHz ~ 24 MHz 10~20pF 10~20pF without R IE S D A T A S H XT1_OUT XT1_IN E E T R C2 C1 Figure 7-1 Typical Crystal Application Circuit May 3, 2017 Page 71 of 99 Rev.2.04

NUC123 7.3.3 Internal 22.1184 MHz High Speed Oscillator PARAMETER CONDITIONS MIN TYP MAX UNIT Supply voltage[1] - 2.5 - 5.5 V Center Frequency - - 22.1184 - MHz +25℃; VDD =5 V -1 - +1 % Calibrated Internal Oscillator Frequency -40℃~+85℃; -3 - +3 % V =2.5 V~5.5 V DD Operation Current V =5 V - 500 - uA DD 7.3.4 Internal 10 kHz Low Speed Oscillator PARAMETER CONDITIONS MIN TYP MAX UNIT Supply voltage[1] - 2.5 - 5.5 V Center Frequency - - 10 - kHz +25℃; V =5 V -30 - +30 % DD Calibrated Internal Oscillator Frequency -40℃~+85℃; -50 - +50 % V =2.5 V~5.5 V DD Note: Internal operation voltage comes from LDO. N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 72 of 99 Rev.2.04

NUC123 7.4 Analog Characteristics 7.4.1 10-bit SARADC Specifications SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT Operating Voltage AV 2.7 5.5 V AV = V DD DD DD Operating Current I 1.5 mA AV = V = 5V, F = 150K ADC DD DD SPS Resolution R 10 bit ADC Reference Voltage V AV V V Connected to AV in Chip REF DD REF DD ADC input Voltage V 0 AV V IN DD V = 5V, ADC Clock = 6MHz DD Sampling Rate F 150K Hz SPS Free Running Conversion Integral Non-linearity Error (INL) INL ±1 LSB Differential Non-linearity Error DNL ±1 LSB (DNL) Gain Error E ±2 LSB G Offset Error E 3 LSB OFFSET Absolute Error E 4 LSB ABS ADC Clock Frequency F 100K 6M Hz V = 5V ADC DD Clock Cycle AD 36 Cycle CYC N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 73 of 99 Rev.2.04

NUC123 7.4.2 LDO and Power Management Specifications PARAMETER MIN TYP MAX UNIT NOTE Input Voltage 2.5 5 5.5 V V input voltage DD Output Voltage 1.62 1.8 1.98 V V > 2.5V DD Temperature -40 25 85 ℃ Cbp - 1 - uF Resr = 1Ω Notes: 1. It is recommended that a 10uF or higher capacitor and a 100nF bypass capacitor are connected between V and the DD closest V pin of the device. SS 2. To ensure power stability, a 1uF (Cbp) or higher capacitor must be connected between LDO pin and the closest VSS pin of the device. 7.4.3 Low Voltage Reset Specifications PARAMETER CONDITIONS MIN TYP MAX UNIT Operation voltage - 1.7 - 5.5 V Quiescent current V = 5.5 V - - 5 uA DD Temperature - -40 25 85 ℃ Temperature = 25℃ 1.7 2.0 2.3 V Threshold voltage Temperature = -40℃ - 2.4 - V N U Temperature = 85℃ - 1.6 - V C 1 2 3 Hysteresis - 0 0 0 V S E R IE S D A T A S H E E T May 3, 2017 Page 74 of 99 Rev.2.04

NUC123 7.4.4 Brown-out Detector Specifications PARAMETER CONDITIONS MIN TYP MAX UNIT Operation voltage - 2.5 - 5.5 V Quiescent current AV = 5.5 V - - 125 μA DD Temperature - -40 25 85 ℃ BOV_VL[1:0] = 11 4.4 4.5 4.6 V BOV_VL [1:0] = 10 3.7 3.8 3.9 V Brown-out voltage BOV_VL [1:0] = 01 2.6 2.7 2.8 V BOV_VL [1:0] = 00 2.1 2.2 2.3 V Hysteresis - 30 - 150 mV 7.4.5 Power-On Reset (5V) Specifications PARAMETER CONDITIONS MIN TYP MAX UNIT Temperature - -40 25 85 ℃ Reset voltage V+ - 2 - V Quiescent current Vin>reset voltage - 1 - nA N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 75 of 99 Rev.2.04

NUC123 7.4.6 USB PHY Specifications 7.4.6.1 USB DC Electrical Characteristics SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT V Input high (driven) 2.0 V IH V Input low 0.8 V IL V Differential input sensitivity |PADP-PADM| 0.2 V DI Differential V Includes V range 0.8 2.5 V CM DI common-mode range V Single-ended receiver threshold 0.8 2.0 V SE Receiver hysteresis 200 mV V Output low (driven) 0 0.3 V OL V Output high (driven) 2.8 3.6 V OH V Output signal cross voltage 1.3 2.0 V CRS R Pull-up resistor 1.425 1.575 kΩ PU R Pull-down resistor 14.25 15.75 kΩ PD Termination Voltage for upstream port V 3.0 3.6 V TRM pull up (RPU) Z Driver output resistance Steady state drive* 10 Ω DRV C Transceiver capacitance Pin to GND 20 pF IN Note: Driver output resistance doesn’t include series resistor resistance. N 7.4.6.2 USB Full-Speed Driver Electrical Characteristics U C 1 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT 2 3 S T Rising time C = 50p 4 20 ns E FR L R IE TFF Falling time CL = 50p 4 20 ns S D TFRFF Rising and falling time matching TFRFF = TFR/TFF 90 111.11 % A T A S H 7.4.6.3 USB Power Dissipation E E T SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT VBUS current I Standby 50 uA VBUS (steady state) 7.4.6.4 USB LDO Specification SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V VBUS Pin Input Voltage 4.0 5.0 5.5 V BUS V LDO Output Voltage 3.0 3.3 3.6 V DD33 May 3, 2017 Page 76 of 99 Rev.2.04

NUC123 C External Bypass Capacitor 1.0 - uF bp 7.5 Flash DC Electrical Characteristics SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V Supply voltage 1.62 1.8 1.98 V[1] DD T Data Retention Temp=85 ℃ 10 year RET T Page Erase Time 20 ms ERASE T Mass Erase Time 40 ms MER T Program Time 40 us PROG I Read Current 0.25 mA DD1 I Program/Erase Current 7 mA DD2 I Power Down Current 1 20 uA PD Note: V is source from chip LDO output voltage. DD N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 77 of 99 Rev.2.04

NUC123 7.6 SPI Dynamic Characteristics SYMBOL PARAMETER MIN TYP MAX UNIT SPI Master mode (V = 4.5V ~ 5.5V, 30pF loading Capacitor) DD t Data setup time TBD TBD - ns DS t Data hold time TBD - - ns DH t Data output valid time - TBD TBD ns V SPI Master mode (V = 3.0V ~ 3.6V, 30pF loading Capacitor) DD t Data setup time TBD TBD - ns DS t Data hold time TBD - - ns DH t Data output valid time - TBD TBD ns V SPI Slave mode (V = 4.5V ~ 5.5V, 30pF loading Capacitor) DD t Data setup time TBD - - ns DS t Data hold time TBD - - ns DH t Data output valid time - TBD TBD ns V SPI Slave mode (V = 3.0V ~ 3.6V, 30pF loading Capacitor) DD t Data setup time TBD - - ns DS t Data hold time TBD - - ns DH t Data output valid time - TBD TBD ns V N U TBD: To be defined. C 1 2 3 S E CLKP=0 R IE SPICLK S CLKP=1 D A tV T A S MOSI Data Valid Data Valid H CLKP=0, TX_NEG=1, RX_NEG=0 E E tDS tDH or T CLKP=1, TX_NEG=0, RX_NEG=1 MISO Data Valid Data Valid t V MOSI Data Valid Data Valid CLKP=0, TX_NEG=0, RX_NEG=1 t t or DS DH CLKP=1, TX_NEG=1, RX_NEG=0 MISO Data Valid Data Valid Figure 7-2 SPI Master Dynamic Characteristics Timing May 3, 2017 Page 78 of 99 Rev.2.04

NUC123 CLKP=0 SPICLK CLKP=1 t t DS DH MOSI Data Valid Data Valid CLKP=0, TX_NEG=1, RX_NEG=0 tv or CLKP=1, TX_NEG=0, RX_NEG=1 MISO Data Valid Data Valid t t DS DH MOSI Data Valid Data Valid CLKP=0, TX_NEG=0, RX_NEG=1 tv or CLKP=1, TX_NEG=1, RX_NEG=0 MISO Data Valid Data Valid Figure 7-3 SPI Slave Dynamic Characteristics Timing N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 79 of 99 Rev.2.04

NUC123 8 ELECTRICAL CHARACTERISTICS (NUC123XXXAEX) 8.1 Absolute Maximum Ratings Symbol Parameter Min Max Unit V  V DC Power Supply -0.3 +7.0 V DD SS V Input Voltage V - 0.3 V + 0.3 V IN SS DD 1/t Oscillator Frequency 4 24 MHz CLCL T Operating Temperature -40 +105 A T Storage Temperature -55 +150 ℃ ST I Maximum Current into V - 120 mA DD DD I Maximum Current out of V 120 mA SS SS Maximum Current sunk by a I/O pin 35 mA Maximum Current sourced by a I/O pin 35 mA I IO Maximum Current sunk by total I/O pins 100 mA Maximum Current sourced by total I/O pins 100 mA Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the lift and reliability of the device. N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 80 of 99 Rev.2.04

NUC123 8.2 DC Electrical Characteristics (V -V =2.5 ~ 5.5 V, T = 25C) DD SS A SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT Operation voltage V 2.5 5.5 V V = 2.5V ~ 5.5V up to 72 MHz DD DD V rise rate to ensure internal DD V 0.05 V/ms operation correctly RISE V SS Power ground -0.3 V AV SS LDO output voltage V 1.62 1.8 1.98 V V > 2.5V LDO DD Analog operating voltage AV 0 V V DD DD V = 5.5V at 72 MHz, DD IDD1 39 mA All IP and PLL Enabled, XTAL = 12 MHz V = 5.5V at 72 MHz, DD IDD2 24 mA All IP Disabled and PLL Enabled, XTAL = Operating current 12 MHz Normal Run mode V = 3V at 72 MHz, at 72 MHz DD IDD3 37 mA All IP and PLL enabled, XTAL = 12 MHz V = 3V at 72 MHz, N DD U IDD4 23 mA All IP Disabled and PLL Enabled, XTAL = C 12 MHz 1 2 3 VDD = 5.5V at 12 MHz, S E IDD5 10 mA All IP Enabled and PLL Disabled, XTAL = R 12 MHz IE S V = 5.5V at 12 MHz, D DD A IDD6 7 mA All IP and PLL Disabled, T Operating current XTAL = 12 MHz A S Normal Run mode H V = 3V at 12 MHz, E at 12 MHz DD E IDD7 8 mA All IP Enabled and PLL Disabled, XTAL = T 12 MHz V = 3V at 12 MHz, DD I 6 mA All IP and PLL Disabled, DD8 XTAL = 12 MHz V = 5V at 4 MHz, Operating current DD IDD9 6 mA All IP Enabled and PLL Disabled, XTAL = Normal Run mode 4 MHz May 3, 2017 Page 81 of 99 Rev.2.04

NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT at 4 MHz V = 5V at 4 MHz, DD IDD10 5 mA All IP and PLL Disabled, XTAL = 4 MHz V = 3V at 4 MHz, DD IDD11 4 mA All IP Enabled and PLL Disabled, XTAL = 4 MHz V = 3V at 4 MHz, DD IDD12 3 mA All IP and PLL Disabled, XTAL = 4 MHz V = 5.5V at 72 MHz, DD IIDLE1 28 mA All IP and PLL Enabled, XTAL = 12 MHz V = 5.5V at 72 MHz, DD IIDLE2 12 mA All IP Disabled and PLL Enabled, XTAL = Operating current 12 MHz Idle mode V = 3V at 72 MHz, at 72 MHz DD IIDLE3 25 mA All IP and PLL Enabled, XTAL = 12 MHz V = 3V at 72 MHz, DD IIDLE4 10 mA All IP Disabled and PLL Enabled, XTAL=12 MHz V = 5.5V at 12 MHz, DD IIDLE5 6 mA All IP Enabled and PLL Disabled, XTAL = 12 MHz V = 5.5V at 12 MHz, DD N U IIDLE6 3 mA All IP and PLL Disabled, Operating current C XTAL = 12 MHz 1 Idle mode 2 3 V = 3V at 12 MHz, S at 12 MHz DD E IIDLE7 5 mA All IP Enabled and PLL Disabled, XTAL = R 12 MHz IE S V = 3 V at 12 MHz, D DD A IIDLE8 2 mA All IP and PLL Disabled, T XTAL = 12 MHz A S H V = 5V at 4 MHz, DD E E IIDLE9 5 mA All IP Enabled and PLL Disabled, XTAL = T 4 MHz V = 5V at 4 MHz, DD IIDLE10 4 mA All IP and PLL Disabled, Operating current XTAL = 4 MHz Idle mode V = 3V at 4 MHz, at 4 MHz DD IIDLE11 3 mA All IP Enabled and PLL Disabled, XTAL = 4 MHz V = 3V at 4 MHz, DD IIDLE12 2 mA All IP and PLL Disabled, XTAL = 4 MHz May 3, 2017 Page 82 of 99 Rev.2.04

NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT V = 5.5V at 10 kHz, DD IIDLE5 110 uA All IP Enabled and PLL Disabled, LIRC 10 kHz Enabled V = 5.5V at 10 kHz, DD IIDLE6 110 uA All IP and PLL Disabled, Operating current LIRC 10 kHz Enabled Idle mode V = 3V at 10 kHz, at 10 kHz DD IIDLE7 100 uA All IP Enabled and PLL Disabled, LIRC 10 kHz Enabled V = 3 V at 10 kHz, DD IIDLE8 100 uA All IP and PLL Disabled, LIRC 10 kHz Enabled V = 5.5V, No load DD I 15 A PWD1 Standby current when BOV function Disabled Power-down mode V = 3.3V, No load DD I 13 A PWD2 when BOV function Disabled Input Current PA, PB, PC, PD, PE, I -64 A V = 5.5V, V = 0V PF (Quasi-bidirectional mode) IN1 DD IN Input Current at /RESET[1] IIN2 -55 -45 -30 A VDD = 3.3V, VIN = 0.45V Input Leakage Current PA, PB, PC, I -2 - +2 A V = 5.5V, 0 < V < V PD, PE, PF LK DD IN DD Logic 1 to 0 Transition Current I [3] -650 - -200 A V = 5.5V, V < 2.0V PA~PF (Quasi-bidirectional mode) TL DD IN -0.3 - 0.8 V = 4.5V Input Low Voltage PA, PB, PC, PD, V V DD N PE, PF (TTL input) IL1 U -0.3 - 0.6 VDD = 2.5V C 1 2 Input High Voltage PA, PB, PC, 2.0 - VDD +0.2 VDD = 5.5V 3 PD, PE, PF (TTL input) VIH1 V S 1.5 - V +0.2 V = 3.0V E DD DD R Input Low Voltage PA, PB, PC, PD, IE V -0.5 - 0.35 V V S PE, PF (Schmitt input) IL2 DD D A Input High Voltage PA, PB, PC, T PD, PE, PF (Schmitt input) VIH2 0.65 VDD - VDD+0.5 V A S H Hysteresis voltage of PA~PE E (Schmitt input) VHY 0.2 VDD V E T 0 - 0.8 V = 4.5V DD Input Low Voltage XT1[*2] V V IL3 0 - 0.4 V = 3.0V DD 3.9 - V +0.2 V V = 5.5V DD DD Input High Voltage XT1[*2] V IH3 2.4 - V +0.2 V = 3.0V DD DD Negative going threshold V -0.5 - 0.2 V V ILS DD (Schmitt input), /RESET Positive going threshold V 0.6 V - V +0.5 V IHS DD DD (Schmitt input), /RESET May 3, 2017 Page 83 of 99 Rev.2.04

NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT ISR11 -300 -370 -450 A VDD = 4.5V, VS = 2.4V Source Current PA, PB, PC, PD, PE, PF (Quasi-bidirectional Mode) ISR12 -50 -70 -90 A VDD = 2.7V, VS = 2.2V I -40 -60 -80 A V = 2.5V, V = 2.0V SR12 DD S I -24 -28 -32 mA V = 4.5V, V = 2.4V SR21 DD S Source Current PA, PB, PC, PD, I -4 -6 -8 mA V = 2.7V, V = 2.2V PE, PF (Push-pull Mode) SR22 DD S I -3 -5 -7 mA V = 2.5V, V = 2.0V SR22 DD S I 10 16 20 mA V = 4.5V, V = 0.45V SK1 DD S Sink Current PA, PB, PC, PD, PE, PF (Quasi-bidirectional and Push- I 7 10 13 mA V = 2.7V, V = 0.45V SK1 DD S pull Mode) I 6 9 12 mA V = 2.5V, V = 0.45V SK1 DD S Brown-out voltage with V 2.1 2.2 2.3 V BOV_VL [1:0] =00b BO2.2 Brown-out voltage with V 2.6 2.7 2.8 V BOV_VL [1:0] =01b BO2.7 Brown-out voltage with V 3.5 3.7 3.9 V BOV_VL [1:0] =10b BO3.8 Brown-out voltage with V 4.2 4.4 4.6 V BOV_VL [1:0] =11b BO4.5 Hysteresis range of BOD voltage V 30 - 150 mV V = 2.5V - 5.5V BH DD Notes: 1. nRESET pin is a Schmitt trigger input. 2. Crystal Input is a CMOS input. N U 3. Pins of PA, PB, PC, PD and PE can source a transition current when they are being externally driven from 1 to 0. In the C 1 condition of VDD=5.5 V, 5he transition current reaches its maximum value when VIN approximates to 2V. 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 84 of 99 Rev.2.04

NUC123 8.3 AC Electrical Characteristics 8.3.1 External 4~24 MHz High Speed Oscillator t CLCL t CLCH 0.7 V 90% DD t CLCX 10% 0.3 V DD t t CHCL CHCX Note: Duty cycle is 50%. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT t Clock High Time 10 - - nS CHCX t Clock Low Time 10 - - nS CLCX t Clock Rise Time 2 - 15 nS CLCH t Clock Fall Time 2 - 15 nS CHCL 8.3.2 External 4~24 MHz High Speed Crystal PARAMETER CONDITIONS MIN TYP MAX UNIT Input clock frequency External crystal 4 - 24 MHz Temperature - -40 - 105 ℃ V - 2.5 - 5.5 V DD N U C 1 8.3.2.1 Typical Crystal Application Circuits 2 3 S CRYSTAL C1 C2 R E R IE 4 MHz ~ 24 MHz 10~20pF 10~20pF without S D A T A S H E E XT1_OUT XT1_IN T R C2 C1 Figure 8-1 Typical Crystal Application Circuit May 3, 2017 Page 85 of 99 Rev.2.04

NUC123 8.3.3 Internal 22.1184 MHz High Speed Oscillator PARAMETER CONDITIONS MIN TYP MAX UNIT Supply voltage[1] - 2.5 - 5.5 V Center Frequency - - 22.1184 - MHz +25℃; V =5 V -1 - +1 % DD Calibrated Internal Oscillator Frequency -40℃~+105℃; -3 - +3 % V =2.5 V~5.5 V DD Operation Current V =5 V - 500 - uA DD 8.3.4 Internal 10 kHz Low Speed Oscillator PARAMETER CONDITIONS MIN TYP MAX UNIT Supply voltage[1] - 2.5 - 5.5 V Center Frequency - - 10 - kHz +25℃; V =5 V -30 - +30 % DD Calibrated Internal Oscillator Frequency -40℃~+105℃; -50 - +50 % V =2.5 V~5.5 V DD Note: Internal operation voltage comes from LDO. N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 86 of 99 Rev.2.04

NUC123 8.4 Analog Characteristics 8.4.1 10-bit SARADC Specifications Specification PARAMETER Sym. TEST CONDITIONS Min. TYP. Max. Unit Operating voltage AV 2.7 5.5 V AV = V DD DD DD Operating current I 1.5 mA AV = V = 5V, F = 200K ADC DD DD SPS Resolution R 10 bit ADC Reference voltage V AV V V connected to AV in chip REF DD REF DD ADC input voltage V 0 AV V IN DD V = 5V, ADC clock = 3MHz DD Sampling rate F 200K Hz SPS Free running conversion Integral non-linearity error INL ±1 LSB (INL) Differential non-linearity DNL ±1 LSB (DNL) Gain error E ±2 LSB G Offset error E 3 LSB OFFSET Absolute error E 4 LSB ABS ADC clock frequency F 100K 3M Hz V = 5V ADC DD Clock cycle AD 16 Cycle CYC N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 87 of 99 Rev.2.04

NUC123 8.4.2 LDO and Power Management Specifications PARAMETER MIN TYP MAX UNIT NOTE Input Voltage 2.5 5 5.5 V V input voltage DD Output Voltage 1.62 1.8 1.98 V V > 2.5V DD Temperature -40 25 105 ℃ Cbp - 1 - uF Resr = 1Ω Notes: 1. It is recommended that a 10uF or higher capacitor and a 100nF bypass capacitor are connected between V and the DD closest V pin of the device. SS 2. To ensure power stability, a 1uF (Cbp) or higher capacitor must be connected between LDO pin and the closest V pin SS of the device. 8.4.3 Low Voltage Reset Specifications PARAMETER CONDITIONS MIN TYP MAX UNIT Operation voltage - 1.7 - 5.5 V Quiescent current V = 5.5 V - - 5 uA DD Temperature - -40 25 105 ℃ Temperature = 25℃ 1.7 2.0 2.3 V Threshold voltage Temperature = -40℃ - 1.8 - V N U Temperature = 85℃ - 2.2 - V C 1 2 3 Hysteresis - 0 0 0 V S E R IE S D A T A S H E E T May 3, 2017 Page 88 of 99 Rev.2.04

NUC123 8.4.4 Brown-out Detector Specifications PARAMETER CONDITIONS MIN TYP MAX UNIT Operation voltage - 2.5 - 5.5 V Quiescent current AV = 5.5 V - - 125 μA DD Temperature - -40 25 105 ℃ BOV_VL[1:0] = 11 4.2 4.4 4.6 V BOV_VL [1:0] = 10 3.5 3.7 3.9 V Brown-out voltage BOV_VL [1:0] = 01 2.6 2.7 2.8 V BOV_VL [1:0] = 00 2.1 2.2 2.3 V Hysteresis - 30 - 150 mV 8.4.5 Power-On Reset (5V) Specifications PARAMETER CONDITIONS MIN TYP MAX UNIT Temperature - -40 25 105 ℃ Reset voltage V+ - 2 - V Quiescent current Vin>reset voltage - 1 - nA N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 89 of 99 Rev.2.04

NUC123 8.4.6 USB PHY Specifications 8.4.6.1 USB DC Electrical Characteristics SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT V Input high (driven) 2.0 V IH V Input low 0.8 V IL V Differential input sensitivity |PADP-PADM| 0.2 V DI Differential V Includes V range 0.8 2.5 V CM DI common-mode range V Single-ended receiver threshold 0.8 2.0 V SE Receiver hysteresis 200 mV V Output low (driven) 0 0.3 V OL V Output high (driven) 2.8 3.6 V OH V Output signal cross voltage 1.3 2.0 V CRS R Pull-up resistor 1.425 1.575 kΩ PU R Pull-down resistor 14.25 15.75 kΩ PD Termination Voltage for upstream port V 3.0 3.6 V TRM pull up (RPU) Z Driver output resistance Steady state drive* 10 Ω DRV C Transceiver capacitance Pin to GND 20 pF IN Note: Driver output resistance doesn’t include series resistor resistance. N 8.4.6.2 USB Full-Speed Driver Electrical Characteristics U C 1 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT 2 3 S T Rising time C = 50p 4 20 ns E FR L R IE TFF Falling time CL = 50p 4 20 ns S D TFRFF Rising and falling time matching TFRFF = TFR/TFF 90 111.11 % A T A S H 8.4.6.3 USB Power Dissipation E E T SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT VBUS current I Standby 50 uA VBUS (steady state) 8.4.6.4 USB LDO Specification SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V VBUS Pin Input Voltage 4.0 5.0 5.5 V BUS V LDO Output Voltage 3.0 3.3 3.6 V DD33 May 3, 2017 Page 90 of 99 Rev.2.04

NUC123 C External Bypass Capacitor 1.0 - uF bp N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 91 of 99 Rev.2.04

NUC123 8.5 Flash DC Electrical Characteristics SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V Supply Voltage 1.62 1.8 1.98 V[1] DD N Endurance 20000 cycles[2] ENDUR T Data Retention At 25℃ 100 year RET T Page Erase Time 20 ms ERASE T Mass Erase Time 40 ms MER T Program Time 35 μs PROG I Read Current - TBD mA/MHz DD1 I Program/Erase Current 7 mA DD2 I Power Down Current - 1 20 μA PD Note1: V is source from chip LDO output voltage. DD Note2: Number of program/erase cycles. Note3: This table is guaranteed by design, not test in production. N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 92 of 99 Rev.2.04

NUC123 8.6 SPI Dynamic Characteristics SYMBOL PARAMETER MIN TYP MAX UNIT SPI Master mode (V = 4.5V ~ 5.5V, 30pF loading Capacitor) DD t Data setup time 4 2 - ns DS t Data hold time 0 - - ns DH t Data output valid time - 7 11 ns V SPI Master mode (V = 3.0V ~ 3.6V, 30pF loading Capacitor) DD t Data setup time 5 3 - ns DS t Data hold time 0 - - ns DH t Data output valid time - 13 18 ns V SPI Slave mode (V = 4.5V ~ 5.5V, 30pF loading Capacitor) DD t Data setup time 0 - - ns DS t Data hold time 2*PCLK+4 - - ns DH t Data output valid time - 2*PCLK+11 2*PCLK+19 ns V SPI Slave mode (V = 3.0V ~ 3.6V, 30pF loading Capacitor) DD t Data setup time 0 - - ns DS t Data hold time 2*PCLK+6 - - ns DH t Data output valid time - 2*PCLK+19 2*PCLK+25 ns V N U C 1 2 3 S E CLKP=0 R IE SPICLK S CLKP=1 D A t T V A S MOSI Data Valid Data Valid H E CLKP=0, TX_NEG=1, RX_NEG=0 E tDS tDH or T CLKP=1, TX_NEG=0, RX_NEG=1 MISO Data Valid Data Valid t V MOSI Data Valid Data Valid CLKP=0, TX_NEG=0, RX_NEG=1 t t or DS DH CLKP=1, TX_NEG=1, RX_NEG=0 MISO Data Valid Data Valid Figure 8-2 SPI Master Dynamic Characteristics timing May 3, 2017 Page 93 of 99 Rev.2.04

NUC123 CLKP=0 SPICLK CLKP=1 t t DS DH MOSI Data Valid Data Valid CLKP=0, TX_NEG=1, RX_NEG=0 tv or CLKP=1, TX_NEG=0, RX_NEG=1 MISO Data Valid Data Valid t t DS DH MOSI Data Valid Data Valid CLKP=0, TX_NEG=0, RX_NEG=1 tv or CLKP=1, TX_NEG=1, RX_NEG=0 MISO Data Valid Data Valid Figure 8-3 SPI Slave Dynamic Characteristics Timing N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 94 of 99 Rev.2.04

NUC123 9 PACKAGE DIMENSIONS 9.1 64L LQFP (7x7x1.4 mm footprint 2.0 mm) N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 95 of 99 Rev.2.04

NUC123 9.2 48L LQFP (7x7x1.4 mm footprint 2.0 mm) N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 96 of 99 Rev.2.04

NUC123 9.3 33L QFN (5x5x0.8 mm) 32 25 1 24 8 17 9 16 25 32 24 1 17 8 16 9 N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 97 of 99 Rev.2.04

NUC123 10 REVISION HISTORY Date Revision Description 2012.04.01 1.00 Preliminary version. 2015.05.29 2.00 1. Merged NUC123xxxANx & NUC123xxxAEx into this document. 1. Removed ADC function pins of NUC123 QFN33 package type in section 4.3.1.3, 2015.11.04 2.01 4.3.2.3 and 4.4.1. 2016.01.12 2.02 1. Revised section 8.2 Source Current PA, PB, PC, PD, PE, PF (Push-pull Mode). 1. Updated ADC function pins of NUC123 QFN33 package type in section 4.3.1.3, 2016.07.06 2.03 4.3.2.3 and 4.4.1. 1. Updated Typical Crystal Application Circuit for External 4~24 MHz High Speed 2017.05.03 2.04 Crystal in section 7.3.2.1. N U C 1 2 3 S E R IE S D A T A S H E E T May 3, 2017 Page 98 of 99 Rev.2.04

NUC123 N U C 1 2 3 S E R Important Notice IE S Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any D malfunction or failure of which may cause loss of human life, bodily injury or severe property A T damage. Such applications are deemed, “Insecure Usage”. A S H Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic E E energy control instruments, airplane or spaceship instruments, the control or operation of T dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. May 3, 2017 Page 99 of 99 Rev.2.04