NUC100/120xxxDN ® ® ARM Cortex -M 32-bit Microcontroller ® NuMicro NUC100 Series NUC100/120xxxDN Datasheet N U C The information described in this document is the exclusive intellectual property of 1 0 Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. 0 /1 20 X Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based X X system design. Nuvoton assumes no responsibility for errors or omissions. D N All data and specifications are subject to change without notice. D A T A S For additional information or questions, please contact: Nuvoton Technology Corporation. H E E www.nuvoton.com T Mar. 02, 2017 Page 1 of 107 Rev 1.02

NUC100/120xxxDN Table of Contents 1 GENERAL DESCRIPTION .............................................................. 8 2 FEATURES ................................................................................ 9 2.1 NuMicro® NUC100 Features – Advanced Line ........................................... 9 2.2 NuMicro® NUC120 Features – USB Line ................................................ 13 3 ABBREVIATIONS ....................................................................... 17 4 PARTS INFORMATION LIST AND PIN CONFIGURATION ..................... 19 4.1 NuMicro® NUC100/120xxxDN Selection Guide ......................................... 19 4.1.1 NuMicro® NUC100 Advanced Line Selection Guide .......................................... 19 4.1.2 NuMicro® NUC120 USB Line Selection Guide ................................................. 19 4.2 Pin Configuration ............................................................................. 21 4.2.1 NuMicro® NUC100 Pin Diagram .................................................................. 21 4.2.2 NuMicro® NUC120 Pin Diagram .................................................................. 24 4.3 Pin Description ............................................................................... 27 4.3.1 NuMicro® NUC100 Pin Description .............................................................. 27 4.3.2 NuMicro® NUC120 Pin Description .............................................................. 34 5 BLOCK DIAGRAM ...................................................................... 41 5.1 NuMicro® NUC100 Block Diagram ........................................................ 41 5.2 NuMicro® NUC120 Block Diagram ........................................................ 42 N 6 FUNCTIONAL DESCRIPTION ........................................................ 43 U C 1 6.1 ARM® Cortex®-M0 Core ..................................................................... 43 0 0 /1 6.2 System Manager ............................................................................. 45 2 0 XX 6.2.1 Overview ............................................................................................. 45 X D 6.2.2 System Reset........................................................................................ 45 N D 6.2.3 Power Modes and Wake-up Sources ............................................................ 51 A T A 6.2.4 System Power Distribution ........................................................................ 53 S H E 6.2.5 System Memory Map ............................................................................... 56 E T 6.2.6 System Timer (SysTick) ........................................................................... 58 6.2.7 Nested Vectored Interrupt Controller (NVIC) ................................................... 59 6.3 Clock Controller .............................................................................. 60 6.3.1 Overview ............................................................................................. 60 6.3.2 Clock Generator ..................................................................................... 62 6.3.3 System Clock and SysTick Clock ................................................................ 63 6.3.4 Peripherals Clock ................................................................................... 64 Mar. 02, 2017 Page 2 of 107 Rev 1.02

NUC100/120xxxDN 6.3.5 Power-down Mode Clock .......................................................................... 64 6.3.6 Frequency Divider Output ......................................................................... 64 6.4 FLASH MEMORY CONTROLLER (FMC) ............................................... 66 6.4.1 Overview ............................................................................................. 66 6.4.2 Features .............................................................................................. 66 6.5 External Bus Interface (EBI) ............................................................... 67 6.5.1 Overview ............................................................................................. 67 6.5.2 Features .............................................................................................. 67 6.6 General Purpose I/O (GPIO) ............................................................... 68 6.6.1 Overview ............................................................................................. 68 6.6.2 Features .............................................................................................. 68 6.7 PDMA Controller (PDMA) .................................................................. 69 6.7.1 Overview ............................................................................................. 69 6.7.2 Features .............................................................................................. 69 6.8 Timer Controller (TMR) ..................................................................... 70 6.8.1 Overview ............................................................................................. 70 6.8.2 Features .............................................................................................. 70 6.9 PWM Generator and Capture Timer (PWM) ............................................ 71 6.9.1 Overview ............................................................................................. 71 6.9.2 Features .............................................................................................. 72 N 6.10 Watchdog Timer (WDT)..................................................................... 73 U C 6.10.1 Overview .......................................................................................... 73 10 0 6.10.2 Features ........................................................................................... 73 /1 2 0 6.11 Window Watchdog Timer (WWDT) ....................................................... 74 X X X 6.11.1 Overview .......................................................................................... 74 D N 6.11.2 Features ........................................................................................... 74 D A T 6.13 Real Time Clock (RTC) ..................................................................... 75 A S H 6.13.1 Overview .......................................................................................... 75 E E T 6.13.2 Features ........................................................................................... 75 6.14 UART Interface Controller (UART) ........................................................ 76 6.14.1 Overview .......................................................................................... 76 6.14.2 Features ........................................................................................... 78 6.15 Smart Card Host Interface (SC) ........................................................... 80 6.15.1 Overview .......................................................................................... 80 6.15.2 Features ........................................................................................... 80 Mar. 02, 2017 Page 3 of 107 Rev 1.02

NUC100/120xxxDN 6.16 PS/2 Device Controller (PS2D) ............................................................ 81 6.16.1 Overview .......................................................................................... 81 6.16.2 Features ........................................................................................... 81 6.17 I2C Serial Interface Controller (I2C) ....................................................... 82 6.17.1 Overview .......................................................................................... 82 6.17.2 Features ........................................................................................... 83 6.18 Serial Peripheral Interface (SPI) ........................................................... 84 6.18.1 Overview .......................................................................................... 84 6.18.2 Features ........................................................................................... 84 6.19 I2S Controller (I2S) ........................................................................... 85 6.19.1 Overview .......................................................................................... 85 6.19.2 Features ........................................................................................... 85 6.20 USB Device Controller (USB) .............................................................. 86 6.20.1 Overview .......................................................................................... 86 6.20.2 Features ........................................................................................... 86 6.21 Analog-to-Digital Converter (ADC) ........................................................ 87 6.21.1 Overview .......................................................................................... 87 6.21.2 Features ........................................................................................... 87 6.22 Analog Comparator (ACMP) ............................................................... 88 6.22.1 Overview .......................................................................................... 88 N U 6.22.2 Features ........................................................................................... 88 C 10 7 APPLICATION CIRCUIT ............................................................... 89 0 /1 2 8 ELECTRICAL CHARACTERISTICS ................................................. 90 0 X X 8.1 Absolute Maximum Ratings ................................................................ 90 X D N 8.2 DC Electrical Characteristics ............................................................... 91 D A 8.3 AC Electrical Characteristics ............................................................... 95 T A S 8.3.1 External 4~24 MHz High Speed Oscillator ..................................................... 95 H E E 8.3.2 External 4~24 MHz High Speed Crystal ........................................................ 95 T 8.3.3 External 32.768 kHz Low Speed Crystal Oscillator ........................................... 96 8.3.4 Internal 22.1184 MHz High Speed Oscillator ................................................... 96 8.3.5 Internal 10 kHz Low Speed Oscillator ........................................................... 96 8.4 Analog Characteristics ...................................................................... 97 8.4.1 12-bit SARADC Specification ..................................................................... 97 8.4.2 LDO and Power Management Specification.................................................... 97 8.4.3 Low Voltage Reset Specification ................................................................. 98 Mar. 02, 2017 Page 4 of 107 Rev 1.02

NUC100/120xxxDN 8.4.4 Brown-out Detector Specification ................................................................ 98 8.4.5 Power-on Reset Specification .................................................................... 98 8.4.6 Temperature Sensor Specification ............................................................... 99 8.4.7 Comparator Specification .......................................................................... 99 8.4.8 USB PHY Specification .......................................................................... 100 8.5 Flash DC Electrical Characteristics ..................................................... 102 9 PACKAGE DIMENSIONS ............................................................ 103 9.1 100-pin LQFP (14x14x1.4 mm footprint 2.0 mm) ..................................... 103 9.2 64-pin LQFP (10x10x1.4 mm footprint 2.0 mm) ...................................... 104 9.3 48-pin LQFP (7x7x1.4 mm footprint 2.0 mm) ......................................... 105 10 REVISION HISTORY .................................................................. 106 N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 5 of 107 Rev 1.02

NUC100/120xxxDN List of Figures Figure 4-1 NuMicro® NUC100 Series Selection Code ................................................................... 20 Figure 4-2 NuMicro® NUC100VxxDN LQFP 100-pin Diagram ...................................................... 21 Figure 4-3 NuMicro® NUC100RxxDN LQFP 64-pin Diagram ........................................................ 22 Figure 4-4 NuMicro® NUC100LxxDN LQFP 48-pin Diagram ......................................................... 23 Figure 4-5 NuMicro® NUC120VxxDN LQFP 100-pin Diagram ...................................................... 24 Figure 4-6 NuMicro® NUC120RxxDN LQFP 64-pin Diagram ........................................................ 25 Figure 4-7 NuMicro® NUC120LxxDN LQFP 48-pin Diagram ......................................................... 26 Figure 5-1 NuMicro® NUC100 Block Diagram ............................................................................... 41 Figure 5-2 NuMicro® NUC120 Block Diagram ............................................................................... 42 Figure 6-1 Functional Controller Diagram ...................................................................................... 43 Figure 6-2 System Reset Resources ............................................................................................. 46 Figure 6-3 nRESET Reset Waveform ............................................................................................ 48 Figure 6-4 Power-on Reset (POR) Waveform ............................................................................... 48 Figure 6-5 Low Voltage Reset (LVR) Waveform ............................................................................ 49 Figure 6-6 Brown-Out Detector (BOD) Waveform ......................................................................... 50 Figure 6-7 Power Mode State Machine ......................................................................................... 51 Figure 6-8 NuMicro® NUC100 Power Distribution Diagram ........................................................... 54 Figure 6-9 NuMicro® NUC120 Power Distribution Diagram ........................................................... 55 Figure 6-10 Clock Generator Global View Diagram ....................................................................... 61 Figure 6-11 Clock Generator Block Diagram ................................................................................. 62 N Figure 6-12 System Clock Block Diagram ..................................................................................... 63 U C 1 Figure 6-13 SysTick Clock Control Block Diagram ........................................................................ 63 0 0 /1 Figure 6-14 Clock Source of Frequency Divider ............................................................................ 64 2 0X Figure 6-15 Frequency Divider Block Diagram .............................................................................. 65 X X Figure 6-16 UART nRTS Auto-Flow Control Trigger Level ............................................................ 77 D N D Figure 6-17 I2C Bus Timing ............................................................................................................ 82 A T Figure 8-1 Typical Crystal Application Circuit ................................................................................ 96 A S H E E T Mar. 02, 2017 Page 6 of 107 Rev 1.02

NUC100/120xxxDN List of Tables Table 1-1 NuMicro® NUC100 Series Connectivity Support Table ................................................... 8 Table 3-1 List of Abbreviations ....................................................................................................... 18 Table 6-1 Reset Value of Registers ............................................................................................... 47 Table 6-2 Power Mode Difference Table ....................................................................................... 51 Table 6-3 Clocks in Power Modes ................................................................................................. 52 Table 6-4 Condition of Entering Power-down Mode Again ............................................................ 53 Table 6-5 Address Space Assignments for On-Chip Controllers ................................................... 57 Table 6-6 UART Baud Rate Equation ............................................................................................ 76 Table 6-7 UART Baud Rate Setting Table ..................................................................................... 77 N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 7 of 107 Rev 1.02

NUC100/120xxxDN 1 GENERAL DESCRIPTION The NuMicro® NUC100 series 32-bit microcontroller (MCU) is embedded with the ARM® Cortex®- M0 core with the cost equivalent to traditional 8-bit MCU. The NUC100 series can be used in consumer electronics, industrial control and applications which requiring rich communication interfaces such as industrial automation, alarm system, energy system and power system. The NuMicro® NUC100 Advanced Line and NUC120 USB Line are embedded with the Cortex®- M0 core running up to 50 MHz and features 32/64/128 Kbytes Flash, 4/8/16 Kbytes embedded SRAM and 4 Kbytes loader ROM for the ISP. It operates at a wide voltage range of 2.5V ~ 5.5V and temperature range of -40℃ ~ +85℃. The NUC100 series is also provided with plenty of peripheral devices, such as Timers, Watchdog Timer, Window Watchdog Timer, RTC, PDMA with CRC calculation unit, UART, SPI, I2C, I2S, PWM Timer, GPIO, PS/2, EBI, Smart Card Host, 12-bit ADC, Analog Comparator, Low Voltage Reset Controller and Brown-out Detector. Additionally, the NUC120 USB Line is equipped with a USB 2.0 Full-speed Device. These peripherals have been incorporated into the NUC100 series to reduce component count, board space and system cost. The NUC100 series is equipped with ISP (In-System Programming), IAP (In-Application- Programming) and ICP (In-Circuit Programming) functions, which allows the user to update the program under software control through the on-chip connectivity interface, such as SWD, UART and USB. Product Line UART SPI I2C USB PS/2 I2S SC NUC100xxxDN 3 4 2 - 1 1 3 NUC120xxxDN 3 4 2 1 1 1 3 Table 1-1 NuMicro® NUC100 Series Connectivity Support Table N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 8 of 107 Rev 1.02

NUC100/120xxxDN 2 FEATURES The equipped features are dependent on the product line and their sub products. 2.1 NuMicro® NUC100 Features – Advanced Line  ARM® Cortex®-M0 core – Runs up to 50 MHz – One 24-bit system timer – Supports low power sleep mode – Single-cycle 32-bit hardware multiplier – NVIC for the 32 interrupt inputs, each with 4-levels of priority – Serial Wire Debug supports with 2 watchpoints/4 breakpoints  Built-in LDO for wide operating voltage ranged from 2.5 V to 5.5 V  Flash Memory – 32/64/128 Kbytes Flash for program code – 4 KB flash for ISP loader – Supports In-System-Program (ISP) and In-Application-Program (IAP) application code update – 512 byte page erase for flash – Configurable Data Flash address and size for 128 KB system, fixed 4 KB Data Flash for the 32 KB and 64 KB system – Supports 2-wired ICP update through SWD/ICE interface – Supports fast parallel programming mode by external programmer  SRAM Memory – 4/8/16 Kbytes embedded SRAM – Supports PDMA mode  PDMA (Peripheral DMA) – Supports 9 channels PDMA for automatic data transfer between SRAM and peripherals N U – Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC- C 16 and CRC-32 1 0 0  Clock Control /1 2 – Flexible selection for different applications 0X – Built-in 22.1184 MHz high speed oscillator for system operation X X  Trimmed to ±1 % at +25 ℃ and V = 5 V D DD N  Trimmed to ±3 % at -40 ℃ ~ +85 ℃ and VDD = 2.5 V ~ 5.5 V D – Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation A T – Supports one PLL, up to 50 MHz, for high performance system operation A S – External 4~24 MHz high speed crystal input for precise timing operation H E – External 32.768 kHz low speed crystal input for RTC function and low power system E operation T  GPIO – Four I/O modes:  Quasi-bidirectional  Push-pull output  Open-drain output  Input only with high impendence – TTL/Schmitt trigger input selectable – I/O pin configured as interrupt source with edge/level setting  Timer Mar. 02, 2017 Page 9 of 107 Rev 1.02

NUC100/120xxxDN – Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter – Independent clock source for each timer – Provides one-shot, periodic, toggle and continuous counting operation modes – Supports event counting function – Supports input capture function  Watchdog Timer – Multiple clock sources – 8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source) – Wake-up from Power-down or Idle mode – Interrupt or reset selectable on watchdog time-out  Window Watchdog Timer – 6-bit down counter with 11-bit prescale for wide range window selected  RTC – Supports software compensation by setting frequency compensate register (FCR) – Supports RTC counter (second, minute, hour) and calendar counter (day, month, year) – Supports Alarm registers (second, minute, hour, day, month, year) – Selectable 12-hour or 24-hour mode – Automatic leap year recognition – Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second – Supports wake-up function  PWM/Capture – Up to four built-in 16-bit PWM generators providing eight PWM outputs or four complementary paired PWM outputs – Each PWM generator equipped with one clock source selector, one clock divider, one 8-bit prescaler and one Dead-Zone generator for complementary paired PWM – Up to eight 16-bit digital capture timers (shared with PWM timers) providing eight rising/falling capture inputs – Supports Capture interrupt N U  UART C 1 0 – Up to three UART controllers 0 /1 – UART ports with flow control (TXD, RXD, CTS and RTS) 2 0 – UART0 with 64-byte FIFO is for high speed X X – UART1/2(optional) with 16-byte FIFO for standard device X – Supports IrDA (SIR) and LIN function D N – Supports RS-485 9-bit mode and direction control D – Programmable baud-rate generator up to 1/16 system clock A T – Supports PDMA mode A S  SPI H E E – Up to four sets of SPI controllers T – SPI clock rate of Master can be up to 36 MHz (chip working at 5V); SPI clock rate of Slave can be up to 18 MHz (chip working at 5V) – Supports SPI Master/Slave mode – Full duplex synchronous serial data transfer – Variable length of transfer data from 8 to 32 bits – MSB or LSB first data transfer – Rx and Tx on both rising or falling edge of serial clock independently – Two slave/device select lines in Master mode, and one slave/device select line in Slave mode – Supports Byte Suspend mode in 32-bit transmission – Supports PDMA mode Mar. 02, 2017 Page 10 of 107 Rev 1.02

NUC100/120xxxDN – Supports three wire, no slave select signal, bi-direction interface  I2C – Up to two sets of I2C device – Master/Slave mode – Bidirectional data transfer between masters and slaves – Multi-master bus (no central master) – Arbitration between simultaneously transmitting masters without corruption of serial data on the bus – Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus – Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer – Programmable clocks allowing for versatile rate control – Supports multiple address recognition (four slave address with mask option) – Supports wake-up function  I2S – Interface with external audio CODEC – Operate as either Master or Slave mode – Capable of handling 8-, 16-, 24- and 32-bit word sizes – Supports mono and stereo audio data – Supports I2S and MSB justified data format – Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving – Generates interrupt requests when buffer levels cross a programmable boundary – Supports two DMA requests, one for transmitting and the other for receiving  PS/2 Device – Host communication inhibit and request to send detection – Reception frame error detection – Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention – Double buffer for data reception – Software override bus N U  EBI (External bus interface) C 1 – Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode 0 0 – Supports 8-/16-bit data width /1 2 – Supports byte write in 16-bit data width mode 0 X  ADC X X D – 12-bit SAR ADC with 760 kSPS N – Up to 8-ch single-end input or 4-ch differential input D A – Single scan/single cycle scan/continuous scan T A – Each channel with individual result register S – Scan on enabled channels H E – Threshold voltage detection E T – Conversion started by software programming or external input – Supports PDMA mode  Analog Comparator – Up to two analog comparators – External input or internal Band-gap voltage selectable at negative node – Interrupt when compare results change – Supports Power-down wake-up  Smart Card Host (SC) – Compliant to ISO-7816-3 T=0, T=1 – Supports up to three ISO-7816-3 ports Mar. 02, 2017 Page 11 of 107 Rev 1.02

NUC100/120xxxDN – Separate receive / transmit 4 bytes entry FIFO for data payloads – Programmable transmission clock frequency – Programmable receiver buffer trigger level – Programmable guard time selection (11 ETU ~ 266 ETU) – One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting times processing – Supports auto inverse convention function – Supports transmitter and receiver error retry and error limit function – Supports hardware activation sequence process – Supports hardware warm reset sequence process – Supports hardware deactivation sequence process – Supports hardware auto deactivation sequence when detecting the card is removal  96-bit unique ID (UID)  One built-in temperature sensor with 1℃ resolution  Brown-out Detector – With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V – Supports Brown-out Interrupt and Reset option  Low Voltage Reset – Threshold voltage level: 2.0 V  Operating Temperature: -40℃ ~ 85℃  Packages: – All Green package (RoHS) – LQFP 100-pin – LQFP 64-pin – LQFP 48-pin N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 12 of 107 Rev 1.02

NUC100/120xxxDN 2.2 NuMicro® NUC120 Features – USB Line  ARM® Cortex®-M0 core – Runs up to 50 MHz – One 24-bit system timer – Supports low power sleep mode – Single-cycle 32-bit hardware multiplier – NVIC for the 32 interrupt inputs, each with 4-levels of priority – Serial Wire Debug supports with 2 watchpoints/4 breakpoints  Built-in LDO for wide operating voltage ranges from 2.5 V to 5.5 V  Flash Memory – 32/64/128 Kbytes Flash for program code – 4 KB flash for ISP loader – Supports In-System-Program (ISP) and In-Application-Program (IAP) application code update – 512 byte page erase for flash – Configurable Data Flash address and size for 128 KB system, fixed 4 KB Data Flash for the 32 KB and 64 KB system – Supports 2-wired ICP update through SWD/ICE interface – Supports fast parallel programming mode by external programmer  SRAM Memory – 4/8/16 Kbytes embedded SRAM – Supports PDMA mode  PDMA (Peripheral DMA) – Supports 9 channels PDMA for automatic data transfer between SRAM and peripherals – Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC- 16 and CRC-32  Clock Control N U – Flexible selection for different applications C 1 – Built-in 22.1184 MHz high speed oscillator for system operation 0 0  Trimmed to ±1 % at +25 ℃ and VDD = 5 V /1 2  Trimmed to ±3 % at -40 ℃ ~ +85 ℃ and V = 2.5 V ~ 5.5 V 0 DD X – Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation X X – Supports one PLL, up to 50 MHz, for high performance system operation D – External 4~24 MHz high speed crystal input for USB and precise timing operation N D – External 32.768 kHz low speed crystal input for RTC function and low power system A operation T A S  GPIO H E – Four I/O modes: E T  Quasi-bidirectional  Push-pull output  Open-drain output  Input only with high impendence – TTL/Schmitt trigger input selectable – I/O pin configured as interrupt source with edge/level setting  Timer – Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter – Independent clock source for each timer – Provides one-shot, periodic, toggle and continuous counting operation modes Mar. 02, 2017 Page 13 of 107 Rev 1.02

NUC100/120xxxDN – Supports event counting function – Supports input capture function  Watchdog Timer – Multiple clock sources – 8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source) – Wake-up from Power-down or Idle mode – Interrupt or reset selectable on watchdog time-out  Window Watchdog Timer – 6-bit down counter with 11-bit prescale for wide range window selected  RTC – Supports software compensation by setting frequency compensate register (FCR) – Supports RTC counter (second, minute, hour) and calendar counter (day, month, year) – Supports Alarm registers (second, minute, hour, day, month, year) – Selectable 12-hour or 24-hour mode – Automatic leap year recognition – Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second – Supports wake-up function  PWM/Capture – Up to four built-in 16-bit PWM generators providing eight PWM outputs or four complementary paired PWM outputs – Each PWM generator equipped with one clock source selector, one clock divider, one 8-bit prescaler and one Dead-Zone generator for complementary paired PWM – Up to eight 16-bit digital capture timers (shared with PWM timers) providing eight rising/falling capture inputs – Supports Capture interrupt  UART – Up to three UART controllers N – UART ports with flow control (TXD, RXD, CTS and RTS) U C – UART0 with 64-byte FIFO is for high speed 1 0 – UART1/2(optional) with 16-byte FIFO for standard device 0 /1 – Supports IrDA (SIR) and LIN function 2 0 – Supports RS-485 9-bit mode and direction control X X – Programmable baud-rate generator up to 1/16 system clock X – Supports PDMA mode D N  SPI D A – Up to four sets of SPI controllers T A – The maximum SPI clock rate of Master can up to 36 MHz (chip working at 5V) S H – The maximum SPI clock rate of Slave can up to 18 MHz (chip working at 5V) E E – Supports SPI Master/Slave mode T – Full duplex synchronous serial data transfer – Variable length of transfer data from 8 to 32 bits – MSB or LSB first data transfer – Rx and Tx on both rising or falling edge of serial clock independently – Two slave/device select lines in Master mode, and one slave/device select line in Slave mode – Supports Byte Suspend mode in 32-bit transmission – Supports PDMA mode – Supports three wire, no slave select signal, bi-direction interface  I2C Mar. 02, 2017 Page 14 of 107 Rev 1.02

NUC100/120xxxDN – Up to two sets of I2C device – Master/Slave mode – Bidirectional data transfer between masters and slaves – Multi-master bus (no central master) – Arbitration between simultaneously transmitting masters without corruption of serial data on the bus – Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus – Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer – Programmable clocks allowing for versatile rate control – Supports multiple address recognition (four slave address with mask option) – Supports wake-up function  I2S – Interface with external audio CODEC – Operate as either Master or Slave mode – Capable of handling 8-, 16-, 24- and 32-bit word sizes – Supports mono and stereo audio data – Supports I2S and MSB justified data format – Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving – Generates interrupt requests when buffer levels cross a programmable boundary – Supports two DMA requests, one for transmitting and the other for receiving  PS/2 Device – Host communication inhibit and request to send detection – Reception frame error detection – Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention – Double buffer for data reception – Software override bus  EBI (External bus interface) – Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode N – Supports 8-/16-bit data width U C – Supports byte write in 16-bit data width mode 1 0  USB 2.0 Full-Speed Device 0 /1 2 – One set of USB 2.0 FS Device 12 Mbps 0 X – On-chip USB Transceiver X X – Provides 1 interrupt source with 4 interrupt events D – Supports Control, Bulk In/Out, Interrupt and Isochronous transfers N D – Auto suspend function when no bus signaling for 3 ms A – Provides 6 programmable endpoints T A – Includes 512 Bytes internal SRAM as USB buffer S H – Provides remote wake-up capability E E  ADC T – 12-bit SAR ADC with 760 kSPS – Up to 8-ch single-end input or 4-ch differential input – Single scan/single cycle scan/continuous scan – Each channel with individual result register – Scan on enabled channels – Threshold voltage detection – Conversion started by software programming or external input – Supports PDMA mode  Analog Comparator Mar. 02, 2017 Page 15 of 107 Rev 1.02

NUC100/120xxxDN – Up to two analog comparators – External input or internal Band-gap voltage selectable at negative node – Interrupt when compare results change – Supports Power-down wake-up  Smart Card Host (SC) – Compliant to ISO-7816-3 T=0, T=1 – Supports up to three ISO-7816-3 ports – Separate receive / transmit 4 bytes entry FIFO for data payloads – Programmable transmission clock frequency – Programmable receiver buffer trigger level – Programmable guard time selection (11 ETU ~ 266 ETU) – One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting times processing – Supports auto inverse convention function – Supports transmitter and receiver error retry and error limit function – Supports hardware activation sequence process – Supports hardware warm reset sequence process – Supports hardware deactivation sequence process – Supports hardware auto deactivation sequence when detecting the card removal  96-bit unique ID (UID)  One built-in temperature sensor with 1℃ resolution  Brown-out Detector – With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V – Supports Brown-out Interrupt and Reset option  Low Voltage Reset – Threshold voltage level: 2.0 V  Operating Temperature: -40℃ ~ 85℃ N  Packages: U C – All Green package (RoHS) 1 0 – LQFP 100-pin 0 /1 – LQFP 64-pin 2 0 – LQFP48-pin X X X D N D A T A S H E E T Mar. 02, 2017 Page 16 of 107 Rev 1.02

NUC100/120xxxDN 3 ABBREVIATIONS Acronym Description ACMP Analog Comparator Controller ADC Analog-to-Digital Converter AES Advanced Encryption Standard APB Advanced Peripheral Bus AHB Advanced High-Performance Bus BOD Brown-out Detection CAN Controller Area Network DAP Debug Access Port DES Data Encryption Standard EBI External Bus Interface EPWM Enhanced Pulse Width Modulation FIFO First In, First Out FMC Flash Memory Controller FPU Floating-point Unit GPIO General-Purpose Input/Output HCLK The Clock of Advanced High-Performance Bus HIRC 22.1184 MHz Internal High Speed RC Oscillator HXT 4~24 MHz External High Speed Crystal Oscillator IAP In Application Programming N U C ICP In Circuit Programming 1 0 0 ISP In System Programming /1 2 0 LDO Low Dropout Regulator X X LIN Local Interconnect Network X D N LIRC 10 kHz internal low speed RC oscillator (LIRC) D A MPU Memory Protection Unit T A S NVIC Nested Vectored Interrupt Controller H E E PCLK The Clock of Advanced Peripheral Bus T PDMA Peripheral Direct Memory Access PLL Phase-Locked Loop PWM Pulse Width Modulation QEI Quadrature Encoder Interface SDIO Secure Digital Input/Output SPI Serial Peripheral Interface Mar. 02, 2017 Page 17 of 107 Rev 1.02

NUC100/120xxxDN SPS Samples per Second TDES Triple Data Encryption Standard TMR Timer Controller UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID USB Universal Serial Bus WDT Watchdog Timer WWDT Window Watchdog Timer Table 3-1 List of Abbreviations N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 18 of 107 Rev 1.02

NUC100/120xxxDN 4 PARTS INFORMATION LIST AND PIN CONFIGURATION 4.1 NuMicro® NUC100/120xxxDN Selection Guide 4.1.1 NuMicro® NUC100 Advanced Line Selection Guide ISP Connectivity Part Number APROM RAM Data Loader I/O Timer I2S SC Co PWM ADC RTC EBI ISP Package Flash mp. ICP ROM UART SPI I2C USB LIN CAN up to 4x32- 8x12- NUC100LC1DN 32 KB 4 KB 4 KB 4 KB 2 1 2 - - - 1 3 1 6 v - v LQFP48 37 bit bit up to 4x32- 8x12- NUC100LD2DN 64 KB 8 KB 4 KB 4 KB 2 1 2 - - - 1 3 1 6 v - v LQFP48 37 bit bit Defin up to 4x32- 8x12- NUC100LE3DN 128 KB 16 KB 4 KB 2 1 2 - - - 1 3 1 6 v - v LQFP48 able 37 bit bit up to 4x32- 8x12- NUC100RC1DN 32 KB 4 KB 4 KB 4 KB 3 2 2 - - - 1 3 2 6 v v v LQFP64 51 bit bit up to 4x32- 8x12- NUC100RD1DN 64 KB 4 KB 4 KB 4 KB 3 2 2 - - - 1 3 2 6 v v v LQFP64 51 bit bit up to 4x32- 8x12- NUC100RD2DN 64 KB 8 KB 4 KB 4 KB 3 2 2 - - - 1 3 2 6 v v v LQFP64 51 bit bit Defin up to 4x32- 8x12- NUC100RE3DN 128 KB 16 KB 4 KB 3 2 2 - - - 1 3 2 6 v v v LQFP64 able 51 bit bit Defin up to 4x32- 8x12- NUC100VE3DN 128 KB 16 KB 4 KB 3 4 2 - - - 1 3 2 8 v v v LQFP100 able 84 bit bit 4.1.2 NuMicro® NUC120 USB Line Selection Guide ISP Connectivity Part Number APROM RAM FDlaastah Loader I/O Timer I2S SC mCpo. PWM ADC RTC EBI IICSPP Package N ROM UART SPI I2C USB LIN CAN U C NUC120LC1DN 32 KB 4 KB 4 KB 4 KB up to 4x32- 2 1 2 1 - - 1 3 1 4 8x12- v - v LQFP48 10 33 bit bit 0 /1 NUC120LD2DN 64 KB 8 KB 4 KB 4 KB up to 4x32- 2 1 2 1 - - 1 3 1 4 8x12- v - v LQFP48 20 33 bit bit X X X Defin up to 4x32- 8x12- NUC120LE3DN 128 KB 16 KB 4 KB 2 1 2 1 - - 1 3 1 4 v - v LQFP48 D able 33 bit bit N D NUC120RC1DN 32 KB 4 KB 4 KB 4 KB up to 4x32- 2 2 2 1 - - 1 3 2 6 8x12- v v v LQFP64 A 47 bit bit T A up to 4x32- 8x12- S NUC120RD1DN 64 KB 4 KB 4 KB 4 KB 2 2 2 1 - - 1 3 2 6 v v v LQFP64 H 47 bit bit E E up to 4x32- 8x12- T NUC120RD2DN 64 KB 8 KB 4 KB 4 KB 47 bit 2 2 2 1 - - 1 3 2 6 bit v v v LQFP64 Defin up to 4x32- 8x12- NUC120RE3DN 128 KB 16 KB 4 KB 2 2 2 1 - - 1 3 2 6 v v v LQFP64 able 47 bit bit Defin up to 4x32- 8x12- NUC120VE3DN 128 KB 16 KB 4 KB 3 4 2 1 - - 1 3 2 8 v v v LQFP100 able 80 bit bit Mar. 02, 2017 Page 19 of 107 Rev 1.02

NUC100/120xxxDN NUC 1 0 0 - X X X X X ARM-Based 32-bit Microcontroller Temperature N: -40℃ ~ +85℃ E: -40℃ ~ +105℃ CPU core C: -40℃ ~ +125℃ 1/2: Cortex-M0 5/7: ARM7 Reserve 9: ARM9 Function RAM Size 1: 4 KB 0: Advanced Line 2: 8 KB 2: USB Line 3: 16 KB 3: Automotive Line 4: Connectivity Line APROM Size Package Type A: 8 KB B: 16 KB Y: QFN 36 C: 32 KB L: LQFP 48 D: 64 KB R: LQFP 64 E: 128 KB V: LQFP 100 Figure 4-1 NuMicro® NUC100 Series Selection Code N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 20 of 107 Rev 1.02

NUC100/120xxxDN 4.2 Pin Configuration 4.2.1 NuMicro® NUC100 Pin Diagram 4.2.1.1 NuMicro® NUC100VxxDN LQFP 100 pin R W PA.4/ADC4/AD9/SC1PWR PA.3/ADC3/AD10/SC0DAT PA.2/ADC2/AD11/SC0CLK PA.1/ADC1/AD12/SC0RST PA.0/ADC0/SC0PWR AVSS VSS VDD ICE_CK ICE_DAT PA.12/PWM0/AD13/SC2DAT PA.13/PWM1/AD14/SC2CLK PA.14/PWM2/AD15/SC2RST PA.15/PWM3/I2SMCLK/SC2P PC.8/SPISS10/MCLK PC.9/SPICLK1 PC.10/MISO10 PC.11/MOSI10 PC.12/MISO11 PC.13/MOSI11 PE.0/PWM6 PE.1/PWM7 PE.2 PE.3 PE.4 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SC1RST/AD8/ADC5/PA.5 76 50 PB.9/TM0/SPISS11 SC1CLK/AD7/ADC6/PA.6 77 49 PB.10/TM1/SPISS01 SC1DAT/AD6/ADC7/SPISS21/PA.7 78 48 PB.11/TM2/PWM4 VREF 79 47 PE.5/T1EX/PWM5 AVDD 80 46 PE.6 SPISS20/PD.0 81 45 PC.0/SPISS00/I2SLRCLK SPICLK2/PD.1 82 44 PC.1/SPICLK0/I2SBCLK MISO20/PD.2 83 43 PC.2/MISO00/I2SDI MOSI20/PD.3 84 42 PC.3/MOSI00/I2SDO MISO21/PD.4 85 41 PC.4/MISO01 MOSI21/PD.5 86 40 PC.5/MOSI01 SC1CD/AD5/CPN0/PC.7 87 NUC100VxxDN 39 PD.15/TXD2 SC0CD/AD4/CPP0/PC.6 88 38 PD.14/RXD2 LQFP 100-pin AD3/CPN1/PC.15 89 37 PD.7 AD2/CPP1/PC.14 90 36 PD.6 T0EX/INT1/PB.15 91 35 PB.3/CTS0/T3EX/nWRH/SC2CD XT1_OUT/PF.0 92 34 PB.2/RTS0/T2EX/nWRL XT1_IN/PF.1 93 33 PB.1/TXD0 /RESET 94 32 PB.0/RXD0 VSS 95 31 PE.7 VDD 96 30 PE.8 PS2DAT/PF.2 97 29 PE.9 PS2CLK/PF.3 98 28 PE.10 N PVSS 99 27 PE.11 U TM0/STADC/PB.8 100 26 PE.12 C 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 00 PE.15 PE.14 PE.13 SPISS31/INT0/PB.14 AD1/CPO1/PB.13 AD0/CLKO/CPO0/PB.12 X32O X32I nRD/I2C1SCL/PA.11 nWR/I2C1SDA/PA.10 I2C0SCL/PA.9 I2C0SDA/PA.8 SPISS30/PD.8 SPICLK3/PD.9 MISO30/PD.10 MOSI30/PD.11 MISO31/PD.12 MOSI31/PD.13 RXD1/PB.4 TXD1/PB.5 ALE/RTS1/PB.6 nCS/CTS1/PB.7 LDO VDD VSS /120XXXDN D A T Figure 4-2 NuMicro® NUC100VxxDN LQFP 100-pin Diagram A S H E E T Mar. 02, 2017 Page 21 of 107 Rev 1.02

NUC100/120xxxDN 4.2.1.2 NuMicro® NUC100RxxDN LQFP 64 pin R W P DC4/AD9/SC1PWR DC3/AD10/SC0DAT DC2/AD11/SC0CLK DC1/AD12/SC0RST DC0/SC0PWR K AT PWM0/AD13/SC2DAT PWM1/AD14/SC2CLK PWM2/AD15/SC2RST PWM3/I2SMCLK/SC2 PISS10/MCLK PICLK1 MISO10 MOSI10 PA.4/A PA.3/A PA.2/A PA.1/A PA.0/A AVSS ICE_C ICE_D PA.12/ PA.13/ PA.14/ PA.15/ PC.8/S PC.9/S PC.10/ PC.11/ 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 SC1RST/AD8/ADC5/PA.5 49 32 PB.9/TM1 SC1CLK/AD7/ADC6/PA.6 50 31 PB.10/TM2 SC1DAT/AD6/ADC7/PA.7 51 30 PB.11/TM3/PWM4 AVDD 52 29 PE.5/T1EX/PWM5 SC1CD/AD5/CPN0/PC.7 53 28 PC.0/SPISS00/I2SLRCLK SC0CD/AD4/CPP0/PC.6 54 27 PC.1/SPICLK0/I2SBCLK AD3/CPN1/PC.15 55 26 PC.2/MISO00/I2SDI NUC100RxxDN AD2/CPP1/PC.14 56 25 PC.3/MOSI00/I2SDO T0EX/INT1/PB.15 57 LQFP 64-pin 24 PD.15/TXD2 XT1_OUT/PF.0 58 23 PD.14/RXD2 XT1_IN/PF.1 59 22 PD.7 /RESET 60 21 PD.6 VSS 61 20 PB.3/CTS0/T3EX/nWRH/SC2CD VDD 62 19 PB.2/RTS0/T2EX/nWRL PVSS 63 18 PB.1/TXD0 TM0/STADC/PB.8 64 17 PB.0/RXD0 0 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 NUC100/120 INT0/PB.14 AD1/CPO1/PB.13 LKO/CPO0/PB.12 X32O X32I D/I2C1SCL/PA.11 R/I2C1SDA/PA.10 I2C0SCL/PA.9 I2C0SDA/PA.8 RXD1/PB.4 TXD1/PB.5 ALE/RTS1/PB.6 nCS/CTS1/PB.7 LDO VDD VSS X C R W X 0/ n n X AD D N D A T AS Figure 4-3 NuMicro® NUC100RxxDN LQFP 64-pin Diagram H E E T Mar. 02, 2017 Page 22 of 107 Rev 1.02

NUC100/120xxxDN 4.2.1.3 NuMicro® NUC100LxxDN LQFP 48 pin R W P 2 C S WR AT LK ST WR DAT CLK RST MCLK/ SC1P SC0D SC0C SC0R SC0P 0/SC2 1/SC2 2/SC2 3/I2S 4/ 3/ 2/ 1/ 0/ M M M M C C C C C T W W W W D D D D D K A P P P P 4/A 3/A 2/A 1/A 0/A S _C _D 12/ 13/ 14/ 15/ PA. PA. PA. PA. PA. AVS CE CE PA. PA. PA. PA. I I 6 5 4 3 2 1 0 9 8 7 6 5 3 3 3 3 3 3 3 2 2 2 2 2 SC1RST/ADC5/PA.5 37 24 PB.9/TM1 SC1CLK/ADC6/PA.6 38 23 PB.10/TM2 SC1DAT/ADC7/PA.7 39 22 PB.11/TM3/PWM4 AV 40 21 PE.5/T1EX/PWM5 DD SC1CD/CPN0/PC.7 41 20 PC.0/SPISS00/I2SLRCLK NUC100LxxDN SC0CD/CPP0/PC.6 42 19 PC.1/SPICLK0/I2SBCLK T0EX/INT1/PB.15 43 LQFP 48-pin 18 PC.2/MISO00/I2SDI XT1_OUT/PF.0 44 17 PC.3/MOSI00/I2SDO XT1_IN/PF.1 45 16 PB.3/CTS0/T3EX/SC2CD /RESET 46 15 PB.2/RTS0/T2EX PV 47 14 PB.1/TXD0 SS TM0/STADC/PB.8 48 13 PB.0/RXD0 0 1 2 1 2 3 4 5 6 7 8 9 1 1 1 N U O/CPO0/PB.12 X32O X32I 2C1SCL/PA.11 2C1SDA/PA.10 I2C0SCL/PA.9 I2C0SDA/PA.8 RXD1/PB.4 TXD1/PB.5 LDO VDD VSS C100/120XX K I I X CL D N D A T A S Figure 4-4 NuMicro® NUC100LxxDN LQFP 48-pin Diagram H E E T Mar. 02, 2017 Page 23 of 107 Rev 1.02

NUC100/120xxxDN 4.2.2 NuMicro® NUC120 Pin Diagram 4.2.2.1 NuMicro® NUC120VxxDN LQFP 100 pin R W PA.4/ADC4/AD9/SC1PWR PA.3/ADC3/AD10/SC0DAT PA.2/ADC2/AD11/SC0CLK PA.1/ADC1/AD12/SC0RST PA.0/ADC0/SC0PWR AVSS VSS VDD ICE_CK ICE_DAT PA.12/PWM0/AD13/SC2DAT PA.13/PWM1/AD14/SC2CLK PA.14/PWM2/AD15/SC2RST PA.15/PWM3/I2SMCLK/SC2P PC.8/SPISS10/MCLK PC.9/SPICLK1 PC.10/MISO10 PC.11/MOSI10 PC.12/MISO11 PC.13/MOSI11 PE.0/PWM6 PE.1/PWM7 PE.2 PE.3 PE.4 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SC1RST/AD8/ADC5/PA.5 76 50 PB.9/TM1/SPISS11 SC1CLK/AD7/ADC6/PA.6 77 49 PB.10/TM2/SPISS01 SC1DAT/AD6/ADC7/SPISS21/PA.7 78 48 PB.11/TM3/PWM4 VREF 79 47 PE.5/T1EX/PWM5 AVDD 80 46 PE.6 SPISS20/PD.0 81 45 PC.0/SPISS00/I2SLRCLK SPICLK2/PD.1 82 44 PC.1/SPICLK0/I2SBCLK MISO20/PD.2 83 43 PC.2/MISO00/I2SDI MOSI20/PD.3 84 42 PC.3/MOSI00/I2SDO MISO21/PD.4 85 41 PC.4/MISO01 MOSI21/PD.5 86 40 PC.5/MOSI01 SC1CD/AD5/CPN0/PC.7 87 NUC120VxxDN 39 PD.15/TXD2 SC0CD/AD4/CPP0/PC.6 88 38 PD.14/RXD2 LQFP 100-pin AD3/CPN1/PC.15 89 37 PD.7 AD2/CPP1/PC.14 90 36 PD.6 T0EX/INT1/PB.15 91 35 PB.3/CTS0/T3EX/nWRH/SC2CD XT1_OUT/PF.0 92 34 PB.2/RTS0/T2EX/nWRL XT1_IN/PF.1 93 33 PB.1/TXD0 /RESET 94 32 PB.0/RXD0 VSS 95 31 D+ VDD 96 30 D- PS2DAT/PF.2 97 29 VDD33 PS2CLK/PF.3 98 28 VBUS PVSS 99 27 PE.7 TM0/STADC/PB.8 100 26 PE.8 N U 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 C 100/120XXX PE.15 PE.14 PE.13 SPISS31/INT0/PB.14 AD1/CPO1/PB.13 AD0/CLKO/CPO0/PB.12 X32O X32I nRD/I2C1SCL/PA.11 nWR/I2C1SDA/PA.10 I2C0SCL/PA.9 I2C0SDA/PA.8 SPISS30/PD.8 SPICLK3/PD.9 MISO30/PD.10 MOSI30/PD.11 MISO31/PD.12 MOSI31/PD.13 RXD1/PB.4 TXD1/PB.5 ALE/RTS1/PB.6 nCS/CTS1/PB.7 LDO VDD VSS D N D Figure 4-5 NuMicro® NUC120VxxDN LQFP 100-pin Diagram A T A S H E E T Mar. 02, 2017 Page 24 of 107 Rev 1.02

NUC100/120xxxDN 4.2.2.2 NuMicro® NUC120RxxDN LQFP 64 pin R W P DC4/AD9/SC1PWR DC3/AD10/SC0DAT DC2/AD11/SC0CLK DC1/AD12/SC0RST DC0/SC0PWR K AT PWM0/AD13/SC2DAT PWM1/AD14/SC2CLK PWM2/AD15/SC2RST PWM3/I2SMCLK/SC2 PISS10/MCLK PICLK1 MISO10 MOSI10 PA.4/A PA.3/A PA.2/A PA.1/A PA.0/A AVSS ICE_C ICE_D PA.12/ PA.13/ PA.14/ PA.15/ PC.8/S PC.9/S PC.10/ PC.11/ 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 SC1RST/AD8/ADC5/PA.5 49 32 PB.9/TM1 SC1CLK/AD7/ADC6/PA.6 50 31 PB.10/TM2 SC1DAT/AD6/ADC7/PA.7 51 30 PB.11/TM3/PWM4 AVDD 52 29 PE.5/T1EX/PWM5 SC1CD/AD5/CPN0/PC.7 53 28 PC.0/SPISS00/I2SLRCLK SC0CD/AD4/CPP0/PC.6 54 27 PC.1/SPICLK0/I2SBCLK AD3/CPN1/PC.15 55 26 PC.2/MISO00/I2SDI NUC120RxxDN AD2/CPP1/PC.14 56 25 PC.3/MOSI00/I2SDO T0EX/INT1/PB.15 57 LQFP 64-pin 24 PB.3/CTS0/T3EX/nWRH/SC2CD XT1_OUT/PF.0 58 23 PB.2/RTS0/T2EX/nWRL XT1_IN/PF.1 59 22 PB.1/TXD0 /RESET 60 21 PB.0/RXD0 VSS 61 20 D+ VDD 62 19 D- PVSS 63 18 VDD33 TM0/STADC/PB.8 64 17 VBUS 0 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 N INT0/PB.14 AD1/CPO1/PB.13 CLKO/CPO0/PB.12 X32O X32I RD/I2C1SCL/PA.11 WR/I2C1SDA/PA.10 I2C0SCL/PA.9 I2C0SDA/PA.8 RXD1/PB.4 TXD1/PB.5 ALE/RTS1/PB.6 nCS/CTS1/PB.7 LDO VDD VSS UC100/120X 0/ n n X D X A D N D A T A Figure 4-6 NuMicro® NUC120RxxDN LQFP 64-pin Diagram S H E E T Mar. 02, 2017 Page 25 of 107 Rev 1.02

NUC100/120xxxDN 4.2.2.3 NuMicro® NUC120LxxDN LQFP 48 pin R W P 2 C S WR AT LK ST WR DAT CLK RST MCLK/ SC1P SC0D SC0C SC0R SC0P 0/SC2 1/SC2 2/SC2 3/I2S 4/ 3/ 2/ 1/ 0/ M M M M C C C C C T W W W W D D D D D K A P P P P 4/A 3/A 2/A 1/A 0/A S _C _D 12/ 13/ 14/ 15/ PA. PA. PA. PA. PA. AVS CE CE PA. PA. PA. PA. I I 6 5 4 3 2 1 0 9 8 7 6 5 3 3 3 3 3 3 3 2 2 2 2 2 SC1RST/ADC5/PA.5 37 24 PC.0/SPISS00/I2SLRCLK SC1CLK/ADC6/PA.6 38 23 PC.1/SPICLK0/I2SBCLK SC1DAT/ADC7/PA.7 39 22 PC.2/MISO00/I2SDI AV 40 21 PC.3/MOSI00/I2SDO DD SC1CD/CPN0/PC.7 41 20 PB.3/CTS0/T3EX/SC2CD NUC120LxxDN SC0CD/CPP0/PC.6 42 19 PB.2/RTS0/T2EX T0EX/INT1/PB.15 43 LQFP 48-pin 18 PB.1/TXD0 XT1_OUT/PF.0 44 17 PB.0/RXD0 XT1_IN/PF.1 45 16 D+ /RESET 46 15 D- PV 47 14 V SS DD33 TM0/STADC/PB.8 48 13 V BUS 0 1 2 1 2 3 4 5 6 7 8 9 1 1 1 N U C100/120XX O/CPO0/PB.12 X32O X32I 2C1SCL/PA.11 2C1SDA/PA.10 I2C0SCL/PA.9 I2C0SDA/PA.8 RXD1/PB.4 TXD1/PB.5 LDO VDD VSS X K I I D CL N D A T A S H Figure 4-7 NuMicro® NUC120LxxDN LQFP 48-pin Diagram E E T Mar. 02, 2017 Page 26 of 107 Rev 1.02

NUC100/120xxxDN 4.3 Pin Description 4.3.1 NuMicro® NUC100 Pin Description Pin No. Pin Name Pin Type Description LQFP LQFP LQFP 100-pin 64-pin 48-pin 1 PE.15 I/O General purpose digital I/O pin. 2 PE.14 I/O General purpose digital I/O pin. 3 PE.13 I/O General purpose digital I/O pin. PB.14 I/O General purpose digital I/O pin. 1 4 /INT0 I External interrupt0 input pin. SPISS31 I/O 2nd SPI3 slave select pin. PB.13 I/O General purpose digital I/O pin. 5 2 CPO1 O Comparator1 output pin. AD1 I/O EBI Address/Data bus bit1 PB.12 I/O General purpose digital I/O pin. 1 CPO0 O Comparator0 output pin 6 3 CLKO O Frequency Divider output pin AD0 I/O EBI Address/Data bus bit0 7 4 2 X32O O External 32.768 kHz low speed crystal output pin 8 5 3 X32I I External 32.768 kHz low speed crystal input pin N PA.11 I/O General purpose digital I/O pin. U 4 C 9 6 I2C1SCL I/O I2C1 clock pin. 1 0 0 nRD O EBI read enable output pin /1 2 0 PA.10 I/O General purpose digital I/O pin. X X 5 X 10 7 I2C1SDA I/O I2C1 data input/output pin. D N nWR O EBI write enable output pin D A T PA.9 I/O General purpose digital I/O pin. A 11 8 6 S H I2C0SCL I/O I2C0 clock pin. E E PA.8 I/O General purpose digital I/O pin. T 12 9 7 I2C0SDA I/O I2C0 data input/output pin. PD.8 I/O General purpose digital I/O pin. 13 SPISS30 I/O 1st SPI3 slave select pin. PD.9 I/O General purpose digital I/O pin. 14 SPICLK3 I/O SPI3 serial clock pin. 15 PD.10 I/O General purpose digital I/O pin. Mar. 02, 2017 Page 27 of 107 Rev 1.02

NUC100/120xxxDN Pin No. Pin Name Pin Type Description LQFP LQFP LQFP 100-pin 64-pin 48-pin MISO30 I/O 1st SPI3 MISO (Master In, Slave Out) pin. PD.11 I/O General purpose digital I/O pin. 16 MOSI30 I/O 1st SPI3 MOSI (Master Out, Slave In) pin. PD.12 I/O General purpose digital I/O pin. 17 MISO31 I/O 2nd SPI3 MISO (Master In, Slave Out) pin. PD.13 I/O General purpose digital I/O pin. 18 MOSI31 I/O 2nd SPI3 MOSI (Master Out, Slave In) pin. PB.4 I/O General purpose digital I/O pin. 19 10 8 RXD1 I Data receiver input pin for UART1. PB.5 I/O General purpose digital I/O pin. 20 11 9 TXD1 O Data transmitter output pin for UART1. PB.6 I/O General purpose digital I/O pin. 21 12 RTS1 O Request to Send output pin for UART1. ALE O EBI address latch enable output pin PB.7 I/O General purpose digital I/O pin. 22 13 CTS1 I Clear to Send input pin for UART1. nCS O EBI chip select enable output pin N 23 14 10 LDO P LDO output pin U C Power supply for I/O ports and LDO source for internal PLL and 1 24 15 11 V P 0 DD digital circuit. 0 /1 2 25 16 12 VSS P Ground pin for digital circuit. 0 X X 26 PE.12 I/O General purpose digital I/O pin. X D 27 PE.11 I/O General purpose digital I/O pin. N D 28 PE.10 I/O General purpose digital I/O pin. A T A 29 PE.9 I/O General purpose digital I/O pin. S H E 30 PE.8 I/O General purpose digital I/O pin. E T 31 PE.7 I/O General purpose digital I/O pin. PB.0 I/O General purpose digital I/O pin. 32 17 13 RXD0 I Data receiver input pin for UART0. PB.1 I/O General purpose digital I/O pin. 33 18 14 TXD0 O Data transmitter output pin for UART0. PB.2 I/O General purpose digital I/O pin. 34 19 15 RTS0 O Request to Send output pin for UART0. Mar. 02, 2017 Page 28 of 107 Rev 1.02

NUC100/120xxxDN Pin No. Pin Name Pin Type Description LQFP LQFP LQFP 100-pin 64-pin 48-pin T2EX I Timer2 external capture input pin. nWRL O EBI low byte write enable output pin PB.3 I/O General purpose digital I/O pin. CTS0 I Clear to Send input pin for UART0. 16 35 20 T3EX I Timer3 external capture input pin. SC2CD I SmartCard2 card detect pin. nWRH O EBI high byte write enable output pin 36 21 PD.6 I/O General purpose digital I/O pin. 37 22 PD.7 I/O General purpose digital I/O pin. PD.14 I/O General purpose digital I/O pin. 38 23 RXD2 I Data receiver input pin for UART2. PD.15 I/O General purpose digital I/O pin. 39 24 TXD2 O Data transmitter output pin for UART2. PC.5 I/O General purpose digital I/O pin. 40 MOSI01 I/O 2nd SPI0 MOSI (Master Out, Slave In) pin. PC.4 I/O General purpose digital I/O pin. 41 MISO01 I/O 2nd SPI0 MISO (Master In, Slave Out) pin. N U PC.3 I/O General purpose digital I/O pin. C 1 42 25 17 MOSI00 I/O 1st SPI0 MOSI (Master Out, Slave In) pin. 00 /1 I2SDO O I2S data output. 2 0 X PC.2 I/O General purpose digital I/O pin. X X D 43 26 18 MISO00 I/O 1st SPI0 MISO (Master In, Slave Out) pin. N D I2SDI I I2S data input. A T A PC.1 I/O General purpose digital I/O pin. S H E 44 27 19 SPICLK0 I/O SPI0 serial clock pin. E T I2SBCLK I/O I2S bit clock pin. PC.0 I/O General purpose digital I/O pin. 45 28 20 SPISS00 I/O 1st SPI0 slave select pin. I2SLRCLK I/O I2S left right channel clock. 46 PE.6 I/O General purpose digital I/O pin. PE.5 I/O General purpose digital I/O pin. 47 29 21 PWM5 I/O PWM5 output/Capture input. Mar. 02, 2017 Page 29 of 107 Rev 1.02

NUC100/120xxxDN Pin No. Pin Name Pin Type Description LQFP LQFP LQFP 100-pin 64-pin 48-pin T1EX I Timer1 external capture input pin. PB.11 I/O General purpose digital I/O pin. 48 30 22 TM3 I/O Timer3 event counter input / toggle output. PWM4 I/O PWM4 output/Capture input. PB.10 I/O General purpose digital I/O pin. 31 23 49 TM2 I/O Timer2 event counter input / toggle output. SPISS01 I/O 2nd SPI0 slave select pin. PB.9 I/O General purpose digital I/O pin. 32 24 50 TM1 I/O Timer1 event counter input / toggle output. SPISS11 I/O 2nd SPI1 slave select pin. 51 PE.4 I/O General purpose digital I/O pin. 52 PE.3 I/O General purpose digital I/O pin. 53 PE.2 I/O General purpose digital I/O pin. PE.1 I/O General purpose digital I/O pin. 54 PWM7 I/O PWM7 output/Capture input. PE.0 I/O General purpose digital I/O pin. 55 PWM6 I/O PWM6 output/Capture input. N PC.13 I/O General purpose digital I/O pin. U C 56 1 MOSI11 I/O 2nd SPI1 MOSI (Master Out, Slave In) pin. 0 0 /1 PC.12 I/O General purpose digital I/O pin. 2 57 0 X MISO11 I/O 2nd SPI1 MISO (Master In, Slave Out) pin. X X D PC.11 I/O General purpose digital I/O pin. N 58 33 D MOSI10 I/O 1st SPI1 MOSI (Master Out, Slave In) pin. A T A PC.10 I/O General purpose digital I/O pin. S 59 34 H MISO10 I/O 1st SPI1 MISO (Master In, Slave Out) pin. E E T PC.9 I/O General purpose digital I/O pin. 60 35 SPICLK1 I/O SPI1 serial clock pin. PC.8 I/O General purpose digital I/O pin. 61 36 SPISS10 I/O 1st SPI1 slave select pin. MCLK O EBI external clock output pin PA.15 I/O General purpose digital I/O pin. 62 37 25 PWM3 I/O PWM output/Capture input. Mar. 02, 2017 Page 30 of 107 Rev 1.02

NUC100/120xxxDN Pin No. Pin Name Pin Type Description LQFP LQFP LQFP 100-pin 64-pin 48-pin I2SMCLK O I2S master clock output pin. SC2PWR O SmartCard2 power pin. PA.14 I/O General purpose digital I/O pin. 26 PWM2 I/O PWM2 output/Capture input. 63 38 SC2RST O SmartCard2 reset pin. AD15 I/O EBI Address/Data bus bit15 PA.13 I/O General purpose digital I/O pin. 27 PWM1 I/O PWM1 output/Capture input. 64 39 SC2CLK O SmartCard2 clock pin. AD14 I/O EBI Address/Data bus bit14 PA.12 I/O General purpose digital I/O pin. 28 PWM0 I/O PWM0 output/Capture input. 65 40 SC2DAT O SmartCard2 data pin. AD13 I/O EBI Address/Data bus bit13 66 41 29 ICE_DAT I/O Serial Wire Debugger Data pin 67 42 30 ICE_CLK I Serial Wire Debugger Clock pin Power supply for I/O ports and LDO source for internal PLL and 68 V P DD digital circuit. N 69 V P Ground pin for digital circuit. U SS C 1 70 43 31 AV AP Ground pin for analog circuit. 0 SS 0 /1 PA.0 I/O General purpose digital I/O pin. 2 0 X 71 44 32 ADC0 AI ADC0 analog input. X X D SC0PWR O SmartCard0 power pin. N D PA.1 I/O General purpose digital I/O pin. A T A 33 ADC1 AI ADC1 analog input. S 72 45 H SC0RST O SmartCard0 reset pin. E E T AD12 I/O EBI Address/Data bus bit12 PA.2 I/O General purpose digital I/O pin. 34 ADC2 AI ADC2 analog input. 73 46 SC0CLK O SmartCard0 clock pin. AD11 I/O EBI Address/Data bus bit11 PA.3 I/O General purpose digital I/O pin. 74 47 35 ADC3 AI ADC3 analog input. Mar. 02, 2017 Page 31 of 107 Rev 1.02

NUC100/120xxxDN Pin No. Pin Name Pin Type Description LQFP LQFP LQFP 100-pin 64-pin 48-pin SC0DAT O SmartCard0 data pin. AD10 I/O EBI Address/Data bus bit10 PA.4 I/O General purpose digital I/O pin. 36 ADC4 AI ADC4 analog input. 75 48 SC1PWR O SmartCard1 power pin. AD9 I/O EBI Address/Data bus bit9 PA.5 I/O General purpose digital I/O pin. 37 ADC5 AI ADC5 analog input. 76 49 SC1RST O SmartCard1 reset pin. AD8 I/O EBI Address/Data bus bit8 PA.6 I/O General purpose digital I/O pin. 38 ADC6 AI ADC6 analog input. 77 50 SC1CLK I/O SmartCard1 clock pin. AD7 I/O EBI Address/Data bus bit7 PA.7 I/O General purpose digital I/O pin. ADC7 AI ADC7 analog input. 39 78 51 SC1DAT O SmartCard1 data pin. N SPISS21 I/O 2nd SPI2 slave select pin. U C AD6 I/O EBI Address/Data bus bit6 1 0 0 79 V AP Voltage reference input for ADC. /1 REF 2 0 80 52 40 AV AP Power supply for internal analog circuit. X DD X X PD.0 I/O General purpose digital I/O pin. D 81 N D SPISS20 I/O 1st SPI2 slave select pin. A T PD.1 I/O General purpose digital I/O pin. A 82 S H SPICLK2 I/O SPI2 serial clock pin. E E PD.2 I/O General purpose digital I/O pin. T 83 MISO20 I/O 1st SPI2 MISO (Master In, Slave Out) pin. PD.3 I/O General purpose digital I/O pin. 84 MOSI20 I/O 1st SPI2 MOSI (Master Out, Slave In) pin. PD.4 I/O General purpose digital I/O pin. 85 MISO21 I/O 2nd SPI2 MISO (Master In, Slave Out) pin. PD.5 I/O General purpose digital I/O pin. 86 MOSI21 I/O 2nd SPI2 MOSI (Master Out, Slave In) pin. Mar. 02, 2017 Page 32 of 107 Rev 1.02

NUC100/120xxxDN Pin No. Pin Name Pin Type Description LQFP LQFP LQFP 100-pin 64-pin 48-pin PC.7 I/O General purpose digital I/O pin. 41 CPN0 AI Comparator0 negative input pin. 87 53 SC1CD I SmartCard1 card detect pin. AD5 I/O EBI Address/Data bus bit5 PC.6 I/O General purpose digital I/O pin. 42 CPP0 AI Comparator0 positive input pin. 88 54 SC0CD I SmartCard0 card detect pin. AD4 I/O EBI Address/Data bus bit4 PC.15 I/O General purpose digital I/O pin. 89 55 CPN1 AI Comparator1 negative input pin. AD3 I/O EBI Address/Data bus bit3 PC.14 I/O General purpose digital I/O pin. 90 56 CPP1 AI Comparator1 positive input pin. AD2 I/O EBI Address/Data bus bit2 PB.15 I/O General purpose digital I/O pin. 91 57 43 /INT1 I External interrupt1 input pin. T0EX I Timer0 external capture input pin. PF.0 I/O General purpose digital I/O pin. N U 92 58 44 C XT1_OUT O External 4~24 MHz (high speed) crystal output pin. 1 0 0 PF.1 I/O General purpose digital I/O pin. /1 93 59 45 2 0 XT1_IN I External 4~24 MHz (high speed) crystal input pin. X X X 94 60 46 /RESET I External reset input: active LOW, with an internal pull-up. Set this D pin low reset chip to initial state. N 95 61 V P Ground pin for digital circuit. D SS A T 96 62 VDD P Power supply for I/O ports and LDO source for internal PLL and A digital circuit. S H PF.2 I/O General purpose digital I/O pin. E 97 E PS2DAT I/O PS/2 data pin. T PF.3 I/O General purpose digital I/O pin. 98 PS2CLK I/O PS/2 clock pin. 99 63 47 PV P PLL ground. SS PB.8 I/O General purpose digital I/O pin. 100 64 48 STADC I ADC external trigger input. TM0 I/O Timer0 event counter input / toggle output. Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power Mar. 02, 2017 Page 33 of 107 Rev 1.02

NUC100/120xxxDN 4.3.2 NuMicro® NUC120 Pin Description Pin No. Pin Name Pin Type Description LQFP LQFP LQFP 100-pin 64-pin 48-pin 1 PE.15 I/O General purpose digital I/O pin. 2 PE.14 I/O General purpose digital I/O pin. 3 PE.13 I/O General purpose digital I/O pin. PB.14 I/O General purpose digital I/O pin. 1 4 /INT0 I External interrupt0 input pin. SPISS31 I/O 2nd SPI3 slave select pin. PB.13 I/O General purpose digital I/O pin. 5 2 CPO1 O Comparator1 output pin. AD1 I/O EBI Address/Data bus bit1 PB.12 I/O General purpose digital I/O pin. 1 CPO0 O Comparator0 output pin 6 3 CLKO O Frequency Divider output pin AD0 I/O EBI Address/Data bus bit0 7 4 2 X32O O External 32.768 kHz low speed crystal output pin 8 5 3 X32I I External 32.768 kHz low speed crystal input pin PA.11 I/O General purpose digital I/O pin. 4 N 9 6 I2C1SCL I/O I2C1 clock pin. U C nRD O EBI read enable output pin 1 0 0 PA.10 I/O General purpose digital I/O pin. /12 5 0 10 7 I2C1SDA I/O I2C1 data input/output pin. X X X nWR O EBI write enable output pin D N D PA.9 I/O General purpose digital I/O pin. 11 8 6 A T I2C0SCL I/O I2C0 clock pin. A S H PA.8 I/O General purpose digital I/O pin. E 12 9 7 E I2C0SDA I/O I2C0 data input/output pin. T PD.8 I/O General purpose digital I/O pin. 13 SPISS30 I/O 1st SPI3 slave select pin. PD.9 I/O General purpose digital I/O pin. 14 SPICLK3 I/O SPI3 serial clock pin. PD.10 I/O General purpose digital I/O pin. 15 MISO30 I/O 1st SPI3 MISO (Master In, Slave Out) pin. 16 PD.11 I/O General purpose digital I/O pin. Mar. 02, 2017 Page 34 of 107 Rev 1.02

NUC100/120xxxDN Pin No. Pin Name Pin Type Description LQFP LQFP LQFP 100-pin 64-pin 48-pin MOSI30 I/O 1st SPI3 MOSI (Master Out, Slave In) pin. PD.12 I/O General purpose digital I/O pin. 17 MISO31 I/O 2nd SPI3 MISO (Master In, Slave Out) pin. PD.13 I/O General purpose digital I/O pin. 18 MOSI31 I/O 2nd SPI3 MOSI (Master Out, Slave In) pin. PB.4 I/O General purpose digital I/O pin. 19 10 8 RXD1 I Data receiver input pin for UART1. PB.5 I/O General purpose digital I/O pin. 20 11 9 TXD1 O Data transmitter output pin for UART1. PB.6 I/O General purpose digital I/O pin. 21 12 RTS1 O Request to Send output pin for UART1. ALE O EBI address latch enable output pin PB.7 I/O General purpose digital I/O pin. 22 13 CTS1 I Clear to Send input pin for UART1. nCS O EBI chip select enable output pin 23 14 10 LDO P LDO output pin Power supply for I/O ports and LDO source for internal PLL and 24 15 11 V P DD digital circuit. N 25 16 12 V P Ground pin for digital circuit. U SS C 1 26 PE.8 I/O General purpose digital I/O pin. 0 0 /1 27 PE.7 I/O General purpose digital I/O pin. 2 0 X 28 17 13 VBUS USB Power supply from USB host or HUB. X X 29 18 14 V USB Internal power regulator output 3.3V decoupling pin. D DD33 N D 30 19 15 D- USB USB differential signal D-. A T 31 20 16 D+ USB USB differential signal D+. A S H PB.0 I/O General purpose digital I/O pin. E 32 21 17 E T RXD0 I Data receiver input pin for UART0. PB.1 I/O General purpose digital I/O pin. 33 22 18 TXD0 O Data transmitter output pin for UART0. PB.2 I/O General purpose digital I/O pin. 29 RTS0 O Request to Send output pin for UART0. 34 23 T2EX I Timer2 external capture input pin. nWRL O EBI low byte write enable output pin Mar. 02, 2017 Page 35 of 107 Rev 1.02

NUC100/120xxxDN Pin No. Pin Name Pin Type Description LQFP LQFP LQFP 100-pin 64-pin 48-pin PB.3 I/O General purpose digital I/O pin. CTS0 I Clear to Send input pin for UART0. 20 35 24 T3EX I Timer3 external capture input pin. SC2CD I SmartCard2 card detect pin. nWRH O EBI high byte write enable output pin 36 PD.6 I/O General purpose digital I/O pin. 37 PD.7 I/O General purpose digital I/O pin. PD.14 I/O General purpose digital I/O pin. 38 RXD2 I Data receiver input pin for UART2. PD.15 I/O General purpose digital I/O pin. 39 TXD2 O Data transmitter output pin for UART2. PC.5 I/O General purpose digital I/O pin. 40 MOSI01 I/O 2nd SPI0 MOSI (Master Out, Slave In) pin. PC.4 I/O General purpose digital I/O pin. 41 MISO01 I/O 2nd SPI0 MISO (Master In, Slave Out) pin. PC.3 I/O General purpose digital I/O pin. 42 25 21 MOSI00 I/O 1st SPI0 MOSI (Master Out, Slave In) pin. N UC I2SDO O I2S data output. 1 00 PC.2 I/O General purpose digital I/O pin. /1 2 43 26 22 MISO00 I/O 1st SPI0 MISO (Master In, Slave Out) pin. 0 X X I2SDI I I2S data input. X D N PC.1 I/O General purpose digital I/O pin. D A 44 27 23 SPICLK0 I/O SPI0 serial clock pin. T A S I2SBCLK I/O I2S bit clock pin. H E E PC.0 I/O General purpose digital I/O pin. T 45 28 24 SPISS00 I/O 1st SPI0 slave select pin. I2SLRCLK I/O I2S left right channel clock. 46 PE.6 I/O General purpose digital I/O pin. PE.5 I/O General purpose digital I/O pin. 47 29 PWM5 I/O PWM5 output/Capture input. T1EX I Timer1 external capture input pin. 48 30 PB.11 I/O General purpose digital I/O pin. Mar. 02, 2017 Page 36 of 107 Rev 1.02

NUC100/120xxxDN Pin No. Pin Name Pin Type Description LQFP LQFP LQFP 100-pin 64-pin 48-pin TM3 I/O Timer3 event counter input / toggle output. PWM4 I/O PWM4 output/Capture input. PB.10 I/O General purpose digital I/O pin. 31 49 TM2 I/O Timer2 event counter input / toggle output. SPISS01 I/O 2nd SPI0 slave select pin. PB.9 I/O General purpose digital I/O pin. 32 50 TM1 I/O Timer1 event counter input / toggle output. SPISS11 I/O 2nd SPI1 slave select pin. 51 PE.4 I/O General purpose digital I/O pin. 52 PE.3 I/O General purpose digital I/O pin. 53 PE.2 I/O General purpose digital I/O pin. PE.1 I/O General purpose digital I/O pin. 54 PWM7 I/O PWM7 output/Capture input. PE.0 I/O General purpose digital I/O pin. 55 PWM6 I/O PWM6 output/Capture input. PC.13 I/O General purpose digital I/O pin. 56 MOSI11 I/O 2nd SPI1 MOSI (Master Out, Slave In) pin. PC.12 I/O General purpose digital I/O pin. N U 57 C MISO11 I/O 2nd SPI1 MISO (Master In, Slave Out) pin. 1 0 0 PC.11 I/O General purpose digital I/O pin. /1 58 33 2 0 MOSI10 I/O 1st SPI1 MOSI (Master Out, Slave In) pin. X X X PC.10 I/O General purpose digital I/O pin. D 59 34 N MISO10 I/O 1st SPI1 MISO (Master In, Slave Out) pin. D A PC.9 I/O General purpose digital I/O pin. T A 60 35 S H SPICLK1 I/O SPI1 serial clock pin. E E T PC.8 I/O General purpose digital I/O pin. 61 36 SPISS10 I/O 1st SPI1 slave select pin. MCLK O EBI external clock output pin PA.15 I/O General purpose digital I/O pin. PWM3 I/O PWM output/Capture input. 62 37 25 I2SMCLK O I2S master clock output pin. SC2PWR O SmartCard2 power pin. Mar. 02, 2017 Page 37 of 107 Rev 1.02

NUC100/120xxxDN Pin No. Pin Name Pin Type Description LQFP LQFP LQFP 100-pin 64-pin 48-pin PA.14 I/O General purpose digital I/O pin. 26 PWM2 I/O PWM2 output/Capture input. 63 38 SC2RST O SmartCard2 reset pin. AD15 I/O EBI Address/Data bus bit15 PA.13 I/O General purpose digital I/O pin. 27 PWM1 I/O PWM1 output/Capture input. 64 39 SC2CLK O SmartCard2 clock pin. AD14 I/O EBI Address/Data bus bit14 PA.12 I/O General purpose digital I/O pin. 28 PWM0 I/O PWM0 output/Capture input. 65 40 SC2DAT O SmartCard2 data pin. AD13 I/O EBI Address/Data bus bit13 66 41 29 ICE_DAT I/O Serial Wire Debugger Data pin 67 42 30 ICE_CLK I Serial Wire Debugger Clock pin Power supply for I/O ports and LDO source for internal PLL and 68 V P DD digital circuit. 69 V P Ground pin for digital circuit. SS 70 43 31 AV AP Ground pin for analog circuit. SS N U PA.0 I/O General purpose digital I/O pin. C 1 0 71 44 32 ADC0 AI ADC0 analog input. 0 /1 2 SC0PWR O SmartCard0 power pin. 0 X X PA.1 I/O General purpose digital I/O pin. X D 33 ADC1 AI ADC1 analog input. N D 72 45 SC0RST O SmartCard0 reset pin. A T A AD12 I/O EBI Address/Data bus bit12 S H E PA.2 I/O General purpose digital I/O pin. E T 34 ADC2 AI ADC2 analog input. 73 46 SC0CLK O SmartCard0 clock pin. AD11 I/O EBI Address/Data bus bit11 PA.3 I/O General purpose digital I/O pin. 35 ADC3 AI ADC3 analog input. 74 47 SC0DAT O SmartCard0 data pin. AD10 I/O EBI Address/Data bus bit10 Mar. 02, 2017 Page 38 of 107 Rev 1.02

NUC100/120xxxDN Pin No. Pin Name Pin Type Description LQFP LQFP LQFP 100-pin 64-pin 48-pin PA.4 I/O General purpose digital I/O pin. 36 ADC4 AI ADC4 analog input. 75 48 SC1PWR O SmartCard1 power pin. AD9 I/O EBI Address/Data bus bit9 PA.5 I/O General purpose digital I/O pin. 37 ADC5 AI ADC5 analog input. 76 49 SC1RST O SmartCard1 reset pin. AD8 I/O EBI Address/Data bus bit8 PA.6 I/O General purpose digital I/O pin. 38 ADC6 AI ADC6 analog input. 77 50 SC1CLK I/O SmartCard1 clock pin. AD7 I/O EBI Address/Data bus bit7 PA.7 I/O General purpose digital I/O pin. ADC7 AI ADC7 analog input. 39 78 51 SC1DAT O SmartCard1 data pin. SPISS21 I/O 2nd SPI2 slave select pin. AD6 I/O EBI Address/Data bus bit6 79 VREF AP Voltage reference input for ADC. N U 80 52 40 AV AP Power supply for internal analog circuit. C DD 1 0 PD.0 I/O General purpose digital I/O pin. 0 /1 81 2 SPISS20 I/O 1st SPI2 slave select pin. 0 X X PD.1 I/O General purpose digital I/O pin. X 82 D N SPICLK2 I/O SPI2 serial clock pin. D A PD.2 I/O General purpose digital I/O pin. T 83 A MISO20 I/O 1st SPI2 MISO (Master In, Slave Out) pin. SH E PD.3 I/O General purpose digital I/O pin. E T 84 MOSI20 I/O 1st SPI2 MOSI (Master Out, Slave In) pin. PD.4 I/O General purpose digital I/O pin. 85 MISO21 I/O 2nd SPI2 MISO (Master In, Slave Out) pin. PD.5 I/O General purpose digital I/O pin. 86 MOSI21 I/O 2nd SPI2 MOSI (Master Out, Slave In) pin. PC.7 I/O General purpose digital I/O pin. 87 53 41 CPN0 AI Comparator0 negative input pin. Mar. 02, 2017 Page 39 of 107 Rev 1.02

NUC100/120xxxDN Pin No. Pin Name Pin Type Description LQFP LQFP LQFP 100-pin 64-pin 48-pin SC1CD I SmartCard1 card detect pin. AD5 I/O EBI Address/Data bus bit5 PC.6 I/O General purpose digital I/O pin. 42 CPP0 AI Comparator0 positive input pin. 88 54 SC0CD I SmartCard0 card detect pin. AD4 I/O EBI Address/Data bus bit4 PC.15 I/O General purpose digital I/O pin. 89 55 CPN1 AI Comparator1 negative input pin. AD3 I/O EBI Address/Data bus bit3 PC.14 I/O General purpose digital I/O pin. 90 56 CPP1 AI Comparator1 positive input pin. AD2 I/O EBI Address/Data bus bit2 PB.15 I/O General purpose digital I/O pin. 91 57 43 /INT1 I External interrupt1 input pin. T0EX I Timer0 external capture input pin. PF.0 I/O General purpose digital I/O pin. 92 58 44 XT1_OUT O External 4~24 MHz (high speed) crystal output pin. N PF.1 I/O General purpose digital I/O pin. U 93 59 45 C XT1_IN I External 4~24 MHz (high speed) crystal input pin. 1 0 0 External reset input: active LOW, with an internal pull-up. Set this /1 94 60 46 /RESET I 2 pin low reset chip to initial state. 0 X X 95 61 VSS P Ground pin for digital circuit. X D Power supply for I/O ports and LDO source for internal PLL and N 96 62 V P D DD digital circuit. A T PF.2 I/O General purpose digital I/O pin. A 97 S H PS2DAT I/O PS/2 data pin. E E PF.3 I/O General purpose digital I/O pin. T 98 PS2CLK I/O PS/2 clock pin. 99 63 47 PV P PLL ground. SS PB.8 I/O General purpose digital I/O pin. 100 64 48 STADC I ADC external trigger input. TM0 I/O Timer0 event counter input / toggle output. Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power Mar. 02, 2017 Page 40 of 107 Rev 1.02

NUC100/120xxxDN 5 BLOCK DIAGRAM 5.1 NuMicro® NUC100 Block Diagram Memory Timer/PWM Analog Interface 32-bit Timer x 4 12-bit ADC x 8 APROM LDROM ARM 128/64/32 KB 4 KB RTC PDM Cortex-M0 EBI Analog A 50MHz Watchdog Timer Comparator x2 DataFlash SRAM 4 KB 16/8/4 KB PWM/Capture Timer x 8 AHB Bus Bridge APB Bus Power Control Clock Control Connectivity I/O Ports UART x 3 General Purpose LDO PLL I/O SPI x 4 External Power On Reset High Speed High Speed Oscillator Crystal Osc. I2C x 2 Interrupt 22.1184 MHz 4 ~ 24 MHz LVR I2S Reset Pin Low Speed Low Speed PS/2 Brownout Oscillator Crystal Osc. Detection 10 kHz 32.768 KHz SC x3 N U Figure 5-1 NuMicro® NUC100 Block Diagram C 1 00 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 41 of 107 Rev 1.02

NUC100/120xxxDN 5.2 NuMicro® NUC120 Block Diagram Memory Timer/PWM Analog Interface 32-bit Timer x 4 12-bit ADC x 8 APROM LDROM CoArtRexM-M0 128/64/32 KB 4 KB PDAM EBI RTC USB PHY 50MHz Watchdog Timer Analog DataFlash SRAM Comparator x2 4 KB 16/8/4 KB PWM/Capture Timer x 8 AHB Bus Bridge APB Bus Power Control Clock Control Connectivity I/O Ports UART x 3 General Purpose LDO PLL I/O SPI x 4 Power On Reset I2C x 2 External Interrupt High Speed High Speed Oscillator Crystal Osc. I2S 22.1184 MHz 4 ~ 24 MHz LVR PS/2 Reset Pin Low Speed Low Speed SC x3 Brownout Oscillator Crystal Osc. Detection 10 kHz 32.768 KHz USB Figure 5-2 NuMicro® NUC120 Block Diagram N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 42 of 107 Rev 1.02

NUC100/120xxxDN 6 FUNCTIONAL DESCRIPTION 6.1 ARM® Cortex®-M0 Core The Cortex®-M0 processor is a configurable, multistage, 32-bit RISC processor, which has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug functionality. The processor can execute Thumb code and is compatible with other Cortex®-M profile processor. The profile supports two modes -Thread mode and Handler mode. Handler mode is entered as a result of an exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of an exception return. Figure 6-1 shows the functional controller of processor. Cortex®-M0 Components Cortex®-M0 processor Debug Interrupts Nested Vectored Cortex®-M0 Breakpoint and Interrupt Processor Watchpoint Controller Core Unit (NVIC) Debug Wakeup Access Interrupt Debugger Port Controller Bus Matrix Interface (DAP) (WIC) AHB-Lite Serial Wire or Interface JTAG Debug Port Figure 6-1 Functional Controller Diagram N U C The implemented device provides the following components and features: 1 0 0  A low gate count processor: /1 2 – ARMv6-M Thumb® instruction set 0X X X – Thumb-2 technology D N – ARMv6-M compliant 24-bit SysTick timer D A – A 32-bit hardware multiplier T A S – System interface supported with little-endian data accesses H E E – Ability to have deterministic, fixed-latency, interrupt handling T – Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to facilitate rapid interrupt handling – C Application Binary Interface compliant exception model. This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers – Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or the return from interrupt sleep-on-exit feature  NVIC: Mar. 02, 2017 Page 43 of 107 Rev 1.02

NUC100/120xxxDN – 32 external interrupt inputs, each with four levels of priority – Dedicated Non-maskable Interrupt (NMI) input – Supports for both level-sensitive and pulse-sensitive interrupt lines – Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep mode  Debug support – Four hardware breakpoints – Two watchpoints – Program Counter Sampling Register (PCSR) for non-intrusive code profiling – Single step and vector catch capabilities  Bus interfaces: – Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all system peripherals and memory – Single 32-bit slave port that supports the DAP (Debug Access Port) N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 44 of 107 Rev 1.02

NUC100/120xxxDN 6.2 System Manager 6.2.1 Overview The system manager provides the functions of system control, power modes, wake-up sources, reset sources, system memory map, product ID and multi-function pin control. The following sections describe the functions for  System Reset  System Power Architecture  System Memory Map  System management registers for Part Number ID, chip reset and on-chip controllers reset, and multi-functional pin control  System Timer (SysTick)  Nested Vectored Interrupt Controller (NVIC)  System Control registers 6.2.2 System Reset The system reset can be issued by one of the events listed below. These reset event flags can be read from RSTSRC register to determine the reset source. Hardware reset can reset chip through peripheral reset signals. Software reset can trigger reset through control registers.  Hardware Reset Sources – Power-on Reset (POR) – Low level on the nRESET pin – Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset) – Low Voltage Reset (LVR) N – Brown-out Detector Reset (BOD Reset) U C  Software Reset Sources 1 0 0 – CHIP Reset will reset whole chip by writing 1 to CHIP_RST (IPRSTC1[0]) /1 2 0 – MCU Reset to reboot but keeping the booting setting from APROM or LDROM X X by writing 1 to SYSRESETREQ (AIRCR[2]) X D – CPU Reset for Cortex®-M0 core Only by writing 1 to CPU_RST (IPRSTC1[1]) N D Power-on Reset or CHIP_RST (IPRSTC1[0]) reset the whole chip including all peripherals, A T external crystal circuit and BS (ISPCON[1]) bit. A S H SYSRESETREQ (AIRCR[2]) reset the whole chip including all peripherals, but does not reset E external crystal circuit and BS (ISPCON[1]) bit. E T Mar. 02, 2017 Page 45 of 107 Rev 1.02

NUC100/120xxxDN Glitch Filter nRESET 36 us ~50k ohm @5v POR_DIS_CODE(PORCR[15:0]) Power-on V DD Reset LVR_EN(BODCR[7]) Low Voltage Reset Pulse Width AVDD Reset 3.2ms BOD_RSTEN(BODCR[3]) Brown-out Reset WDT/WWDT Reset Pulse Width System Reset Reset 64 WDT clocks CHIP Reset CHIP_RST(IPRSTC1[0]) MCU Reset Software Reset Reset Pulse Width SYSRESETREQ(AIRCR[2]) 2 system clocks CPU Reset CPU_RST(IPRSTC1[1]) Figure 6-2 System Reset Resources There are a total of 8 reset sources in the NuMicro® family. In general, CPU reset is used to reset Cortex®-M0 only; the other reset sources will reset Cortex®-M0 and all peripherals. However, there are small differences between each reset source and they are listed in Table 6-1. N Reset Sources U POR nRESET WDT LVR BOD CHIP MCU CPU C Register 1 0 0 RSTSRC Bit 0 = 1 Bit 1 = 1 Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Bit 0 = 1 Bit 5 = 1 Bit 7 = 1 /1 2 CHIP_RST 0x0 - - - - - - - 0 X X (IPRSTC1[0]) X D BOD_EN Reload Reload Reload Reload - Reload Reload - N from from from from from from D (BODCR[0]) CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 A T BOD_VL A S (BODCR[2:1]) H E E BOD_RSTEN T (BODCR[3]) XTL12M_EN Reload Reload Reload Reload Reload Reload Reload - from from from from from from from (PWRCON[0]) CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 WDT_EN 0x1 - 0x1 - - 0x1 - - (APBCLK[0]) HCLK_S Reload Reload Reload Reload Reload Reload Reload - from from from from from from from (CLKSEL0[2:0]) CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 WDT_S 0x3 0x3 - - - - - - Mar. 02, 2017 Page 46 of 107 Rev 1.02

NUC100/120xxxDN (CLKSEL1[1:0]) XTL12M_STB 0x0 - - - - - - - (CLKSTATUS[0]) XTL32K_STB 0x0 - - - - - - - (CLKSTATUS[1]) PLL_STB 0x0 - - - - - - - (CLKSTATUS[2]) OSC10K_STB 0x0 - - - - - - - (CLKSTATUS[3]) OSC22M_STB 0x0 - - - - - - - (CLKSTATUS[4]) CLK_SW_FAIL 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - (CLKSTATUS[7]) WTE Reload Reload Reload Reload Reload Reload - - from from from from from from (WTCR[7]) CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 WTCR 0x0700 0x0700 0x0700 0x0700 0x0700 0x0700 - - WTCRALT 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - WWDTRLD 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - WWDTCR 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 - - WWDTSR 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - WWDTCVR 0x3F 0x3F 0x3F 0x3F 0x3F 0x3F - - BS Reload Reload Reload Reload Reload Reload - - from from from from from from (ISPCON[1]) CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 N U DFBADR Reload Reload Reload Reload Reload Reload - - C from from from from from from 1 0 CONFIG1 CONFIG1 CONFIG1 CONFIG1 CONFIG1 CONFIG1 0 /1 CBS Reload Reload Reload Reload Reload Reload - - 2 0 (ISPSTA[2:1)) from from from from from from X CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 X X D VECMAP Reload Reload Reload Reload Reload Reload - - N (ISPSTA[20:9]) bCaOsNe FoInG 0 bCaOsNe FoInG 0 bCaOsNe FoInG 0 bCaOsNe FoInG 0 bCaOsNe FoInG 0 bCaOsNe FoInG 0 D A T Other Peripheral Reset Value - A Registers S H FMC Registers Reset Value E E T Note: ‘-‘ means that the value of register keeps original setting. Table 6-1 Reset Value of Registers Mar. 02, 2017 Page 47 of 107 Rev 1.02

NUC100/120xxxDN 6.2.2.1 nRESET Reset The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage is lower than 0.2 V and the state keeps longer than 36 us (glitch filter), chip will be DD reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 V and the state keeps longer than 36 us (glitch filter). The RSTS_RESET (RSTSRC[1]) will DD be set to 1 if the previous reset source is nRESET reset. Figure 6-3 shows the nRESET reset waveform. nRESET 0.7 VDD 36 us 0.2 V DD SS 36 us nRESET Reset SS Figure 6-3 nRESET Reset Waveform 6.2.2.2 Power-On Reset (POR) The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to be reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the POR module will detect the rising voltage and generate reset signal to system until the voltage is ready for MCU operation. At POR reset, the RSTS_POR (RSTSRC[0]) will be set to 1 to indicate there is a POR reset event. The RSTS_POR (RSTSRC[0]) bit can be cleared N by writing 1 to it. Figure 6-4 shows the waveform of Power-On reset. U C 1 0 0 /1 2 0 X X X V D POR N D A T A S H 0.1V E V E DD T Power On Reset Figure 6-4 Power-on Reset (POR) Waveform 6.2.2.3 Low Voltage Reset (LVR) If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVR_EN (BODCR[7]) to 1, after 100us delay, LVR detection circuit will be stable and the LVR function will be active. Then LVR function will detect AV during system operation. When the DD Mar. 02, 2017 Page 48 of 107 Rev 1.02

NUC100/120xxxDN AV voltage is lower than V and the state keeps longer than De-glitch time (16*HCLK cycles), DD LVR chip will be reset. The LVR reset will control the chip in reset state until the AV voltage rises DD above V and the state keeps longer than De-glitch time. The RSTS_RESET (RSTSRC[1]) will LVR be set to 1 if the previous reset source is nRESET reset. Figure 6-5 shows the Low Voltage Reset waveform. AV DD V LVR T T 1 2 (<De-glitch time) (=De-glitch time) T 3 (=De-glitch time) Low Voltage Reset 100 us Delay for LVR stable LVR_EN Figure 6-5 Low Voltage Reset (LVR) Waveform N 6.2.2.4 Brown-out Detector Reset (BOD Reset) U C If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit 1 0 BOD_EN (BODCR[0]), Brown-Out Detector function will detect AV during system operation. 0 DD /1 When the AV voltage is lower than V which is decided by BOD_EN (BODCR[0]) and 2 DD BOD 0 BOD_VL (BODCR[2:1]) and the state keeps longer than De-glitch time (Max(20*HCLK cycles, X X 1*LIRC cycle)), chip will be reset. The BOD reset will control the chip in reset state until the AVDD X D voltage rises above V and the state keeps longer than De-glitch time. The default value of BOD N BOD_EN, BOD_VL and BOD_RSTEN is set by flash controller user configuration register D CBODEN (CONFIG0[23]), CBOV1-0 (CONFIG0[22:21]) and CBORST (CONFIG0[20]) A T respectively. User can determine the initial BOD setting by setting the CONFIG0 register. Figure A S 6-6 shows the Brown-Out Detector waveform. H E E T Mar. 02, 2017 Page 49 of 107 Rev 1.02

NUC100/120xxxDN AV DD V BODH Hysteresis V BODL T T 1 2 (< de-glitch time) (= de-glitch time) BODOUT T 3 (= de-glitch time) BODRSTEN Brown-out Reset Figure 6-6 Brown-Out Detector (BOD) Waveform 6.2.2.5 Watchdog Timer Reset N U In most industrial applications, system reliability is very important. To automatically recover the C 1 MCU from failure status is one way to improve system reliability. The watchdog timer (WDT) is 0 0 widely used to check if the system works fine. If the MCU is crashed or out of control, it may /1 cause the watchdog time-out. User may decide to enable system reset during watchdog time-out 2 0 to recover the system and take action for the system crash/out-of-control after reset. X X X Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a D N watchdog reset and handle the failure of MCU after watchdog time-out reset by checking D RSTS_WDT (RSTSRC[2]). A T A S H 6.2.2.6 CPU Reset, CHIP Reset and MCU Reset E ET The CPU Reset means only Cortex®-M0 core is reset and all other peripherals remain the same status after CPU reset. User can set the CPU Reset CPU_RST (IPRSTC1[1]) to 1 to assert the CPU Reset signal. The CHIP Reset is same with Power-On Reset. The CPU and all peripherals are reset and BS (ISPCON[1]) bit is automatically reloaded from CONFIG0 setting. User can set the CHIP Reset CHIP_RST (IPRSTC1[0]) to 1 to assert the CHIP Reset signal. The MCU Reset is similar with CHIP Reset. The difference is that BS (ISPCON[1]) will not be reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or LDROM. User can set the MCU Reset SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset. Mar. 02, 2017 Page 50 of 107 Rev 1.02

NUC100/120xxxDN 6.2.3 Power Modes and Wake-up Sources There are several wake-up sources in Idle mode and Power-down mode. Table 6-2 lists the available clocks for each power mode. Power Mode Normal Mode Idle Mode Power-down Mode Definition CPU is in active state CPU is in sleep state CPU is in sleep state and all clocks stop except LXT and LIRC. SRAM content retended. Entry Condition Chip is in normal CPU executes WFI CPU sets sleep mode mode after system instruction. enable and power reset released down enable and executes WFI instruction. Wake-up Sources N/A All interrupts RTC, WDT, I²C, Timer, UART, BOD, USB and GPIO Available Clocks All All except CPU clock LXT and LIRC After Wake-up N/A CPU back to normal CPU back to normal mode mode Table 6-2 Power Mode Difference Table N System reset released U C 1 0 0 Normal Mode /1 CPU Clock ON 2 0 HXT, LXT, HIRC, LIRC, HCLK, PCLK ON X Flash ON X X D N D CPU executes WFI Interrupts occur A T 1. SLEEPDEEP(SCR[2]) = 1 Wake-up events A 2. PWR_DOWN_EN (PWRCON[7]) = 1 occur S PD_WAIT_CPU (PWRCON[8]) = 1 H 3. CPU executes WFI E E Idle Mode T Power-down Mode CPU Clock OFF CPU Clock OFF HXT, LXT, HIRC, LIRC, HCLK, PCLK ON Flash Halt HXT,HIRC, HCLK, PCLK OFF LXT, LIRC ON Flash Halt Figure 6-7 Power Mode State Machine 1. LXT (32 kHz XTL) ON or OFF depends on S/W setting in run mode. 2. LIRC (10 kHz OSC) ON or OFF depends on S/W setting in run mode. Mar. 02, 2017 Page 51 of 107 Rev 1.02

NUC100/120xxxDN 3. If TIMER clock source is selected as LXT/LIRC and LXT/LIRC is on. 4. If PWM clock source is selected as LXT and LXT is on. 5. If WDT clock source is selected as LXT/LIRC and LXT/LIRC is on. 6. If RTC clock source LXT is on. Normal Mode Idle Mode Power-down Mode HXT (4~20 MHz XTL) ON ON Halt HIRC (12/16 MHz OSC) ON ON Halt LXT (32 kHz XTL) ON ON ON/OFF1 LIRC (10 kHz OSC) ON ON ON/OFF2 PLL ON ON Halt LDO ON ON ON CPU ON Halt Halt HCLK/PCLK ON ON Halt SRAM retention ON ON ON FLASH ON ON Halt EBI ON ON Halt GPIO ON ON Halt PDMA ON ON Halt TIMER ON ON ON/OFF3 PWM ON ON ON/OFF4 WDT ON ON ON/OFF5 N U WWDT ON ON Halt C 1 0 RTC ON ON ON/OFF6 0 /1 2 UART ON ON Halt 0 X X SC ON ON Halt X D PS/2 ON ON Halt N D A I2C ON ON Halt T A SPI ON ON Halt S H E I2S ON ON Halt E T USB ON ON Halt ADC ON ON Halt ACMP ON ON Halt Table 6-3 Clocks in Power Modes Wake-up sources in Power-down mode: WDT, I²C, Timer, RTC, UART, BOD, GPIO and USB Mar. 02, 2017 Page 52 of 107 Rev 1.02

NUC100/120xxxDN After chip enters power down, the following wake-up sources can wake chip up to normal mode. Wake-Up Wake-Up Condition System Can Enter Power-Down Mode Again Condition* Source BOD Brown-Out Detector Interrupt After software writes 1 to clear BOD_INTF (BODCR[4]). GPIO GPIO Interrupt After software write 1 to clear the ISRC[n] bit. TIMER Timer Interrupt After software writes 1 to clear TWF (TISRx[1]) and TIF (TISRx[0]). WDT WDT Interrupt After software writes 1 to clear WTWKF (WTCR[5]) (Write Protect). RTC Alarm Interrupt After software writes 1 to clear AIF (RIIR[0]). Time Tick Interrupt After software writes 1 to clear TIF (RIIR[1]). UART nCTS wake-up After software writes 1 to clear DCTSF (UA_MSR[0]). I2C Addressing I2C device After software writes 1 to clear WKUPIF (I2CWKUPSTS[0]). USB Remote Wake-up After software writes 1 to clear BUS_STS (USBD_INTSTS[0]). *User needs to wait this condition before setting PWR_DOWN_EN (PWRCON[7]) and execute WFI to enter Power-down mode. Table 6-4*User needs to wait this condition before setting PWR_DOWN_EN (PWRCON[7]) and execute WFI to enter Power- down mode. Table 6-4 lists the condition about how to enter Power-down mode again for each peripheral. Wake-Up Wake-Up Condition System Can Enter Power-Down Mode Again Condition* Source BOD Brown-Out Detector Interrupt After software writes 1 to clear BOD_INTF (BODCR[4]). GPIO GPIO Interrupt After software write 1 to clear the ISRC[n] bit. N TIMER Timer Interrupt After software writes 1 to clear TWF (TISRx[1]) and TIF (TISRx[0]). U C WDT WDT Interrupt After software writes 1 to clear WTWKF (WTCR[5]) (Write Protect). 1 0 0 RTC Alarm Interrupt After software writes 1 to clear AIF (RIIR[0]). /1 2 0 Time Tick Interrupt After software writes 1 to clear TIF (RIIR[1]). X X X UART nCTS wake-up After software writes 1 to clear DCTSF (UA_MSR[0]). D N I2C Addressing I2C device After software writes 1 to clear WKUPIF (I2CWKUPSTS[0]). D A T USB Remote Wake-up After software writes 1 to clear BUS_STS (USBD_INTSTS[0]). A S H *User needs to wait this condition before setting PWR_DOWN_EN (PWRCON[7]) and execute WFI to enter Power-down mode. E E Table 6-4 Condition of Entering Power-down Mode Again T 6.2.4 System Power Distribution In this chip, the power distribution is divided into three segments.  Analog power from AV and AV provides the power for analog components DD SS operation.  Digital power from V and V supplies the power to the internal regulator which DD SS provides a fixed 1.8 V power for digital operation and I/O pins. Mar. 02, 2017 Page 53 of 107 Rev 1.02

NUC100/120xxxDN  USB transceiver power from V offers the power for operating the USB transceiver. BUS The outputs of internal voltage regulators, LDO and V , require an external capacitor which DD33 should be located close to the corresponding pin. Analog power (AV ) should be the same DD voltage level of the digital power (V ). Figure 6-8 shows the power distribution of NuMicro® DD NUC100. Figure 6-9 shows the power distribution of NuMicro® NUC120. NUC100 Power Distribution AV Brown Low DD 12-bit Analog Out Voltage SAR-ADC Comparator AVSS Detector Reset Internal Temperature FLASH Digital Logic 22.1184 MHz & 10 kHz Seneor Oscillator LDO 1.8V 1uF External POR18 PLL 32.768 kHz LDO IO cell GPIO Crystal POR50 VSS 2O 32I VDD VSS P X3 X N U C1 Figure 6-8 NuMicro® NUC100 Power Distribution Diagram 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 54 of 107 Rev 1.02

NUC100/120xxxDN AV D+ DD 12-bit USB 1.1 SAR-ADC Tranceiver AV D- SS NUC120 Analog Comparator Power V DD33 Distribution 3.3V 1uF Low Brown Voltage Out 5V to 3.3V LDO V BUS Reset Detector Internal Temperature FLASH Digital Logic 22.1184 MHz & 10 kHz Seneor Oscillator LDO 1.8V 1uF External POR18 PLL 32.768 kHz LDO IO cell GPIO Crystal POR50 VSS 2O 32I VDD VSS P X3 X N U Figure 6-9 NuMicro® NUC120 Power Distribution Diagram C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 55 of 107 Rev 1.02

NUC100/120xxxDN 6.2.5 System Memory Map The NuMicro® NUC100 series provides 4G-byte addressing space. The memory locations assigned to each on-chip controllers are shown in the following table. The detailed register definition, memory space, and programming detailed will be described in the following sections for each on-chip peripheral. The NuMicro® NUC100 series only supports little-endian data format. Address Space Token Controllers Flash and SRAM Memory Space 0x0000_0000 – 0x0001_FFFF FLASH_BA FLASH Memory Space (128 KB) 0x2000_0000 – 0x2000_3FFF SRAM_BA SRAM Memory Space (16 KB) AHB Controllers Space (0x5000_0000 – 0x501F_FFFF) 0x5000_0000 – 0x5000_01FF GCR_BA System Global Control Registers 0x5000_0200 – 0x5000_02FF CLK_BA Clock Control Registers 0x5000_0300 – 0x5000_03FF INT_BA Interrupt Multiplexer Control Registers 0x5000_4000 – 0x5000_7FFF GPIO_BA GPIO Control Registers 0x5000_8000 – 0x5000_BFFF PDMA_BA Peripheral DMA Control Registers 0x5000_C000 – 0x5000_FFFF FMC_BA Flash Memory Control Registers APB1 Controllers Space (0x4000_0000 ~ 0x400F_FFFF) 0x4000_4000 – 0x4000_7FFF WDT_BA Watchdog Timer Control Registers 0x4000_8000 – 0x4000_BFFF RTC_BA Real Time Clock (RTC) Control Register 0x4001_0000 – 0x4001_3FFF TMR01_BA Timer0/Timer1 Control Registers N 0x4002_0000 – 0x4002_3FFF I2C0_BA I2C0 Interface Control Registers U C 0x4003_0000 – 0x4003_3FFF SPI0_BA SPI0 with master/slave function Control Registers 1 0 0/1 0x4003_4000 – 0x4003_7FFF SPI1_BA SPI1 with master/slave function Control Registers 2 0 0x4004_0000 – 0x4004_3FFF PWMA_BA PWM0/1/2/3 Control Registers X X X 0x4005_0000 – 0x4005_3FFF UART0_BA UART0 Control Registers D N D 0x4006_0000 – 0x4006_3FFF USBD_BA USB 2.0 FS device Controller Registers A T 0x400D_0000 – 0x400D_3FFF ACMP_BA Analog Comparator Control Registers A S H 0x400E_0000 – 0x400E_FFFF ADC_BA Analog-Digital-Converter (ADC) Control Registers E E APB2 Controllers Space (0x4010_0000 ~ 0x401F_FFFF) T 0x4010_0000 – 0x4010_3FFF PS2_BA PS/2 Interface Control Registers 0x4011_0000 – 0x4011_3FFF TMR23_BA Timer2/Timer3 Control Registers 0x4012_0000 – 0x4012_3FFF I2C1_BA I2C1 Interface Control Registers 0x4013_0000 – 0x4013_3FFF SPI2_BA SPI2 with master/slave function Control Registers 0x4013_4000 – 0x4013_7FFF SPI3_BA SPI3 with master/slave function Control Registers 0x4014_0000 – 0x4014_3FFF PWMB_BA PWM4/5/6/7 Control Registers 0x4015_0000 – 0x4015_3FFF UART1_BA UART1 Control Registers Mar. 02, 2017 Page 56 of 107 Rev 1.02

NUC100/120xxxDN 0x4015_4000 – 0x4015_7FFF UART2_BA UART2 Control Registers 0x4019_0000 – 0x4019_3FFF SC0_BA SC0 Control Registers 0x4019_4000 – 0x4019_7FFF SC1_BA SC1 Control Registers 0x4019_8000 – 0x4019_BFFF SC2_BA SC2 Control Registers 0x401A_0000 – 0x401A_3FFF I2S_BA I2S Interface Control Registers System Controllers Space (0xE000_E000 ~ 0xE000_EFFF) 0xE000_E010 – 0xE000_E0FF SCS_BA System Timer Control Registers 0xE000_E100 – 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers 0xE000_ED00 – 0xE000_ED8F SCS_BA System Control Registers Table 6-5 Address Space Assignments for On-Chip Controllers N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 57 of 107 Rev 1.02

NUC100/120xxxDN 6.2.6 System Timer (SysTick) The Cortex®-M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter. When system timer is enabled, it will count down from the value in the SysTick Current Value Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_RVR) on the next clock cycle, then decrement on subsequent clocks. When the counter transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads. The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to 0 before enabling the feature. This ensures the timer will count from the SYST_RVR value rather than an arbitrary value when it is enabled. If the SYST_RVR is 0, the timer will be maintained with a current value of 0 after it is reloaded with this value. This mechanism can be used to disable the feature independently from the timer enable bit. For more detailed information, please refer to the “ARM® Cortex®-M0 Technical Reference Manual” and “ARM® v6-M Architecture Reference Manual”. N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 58 of 107 Rev 1.02

NUC100/120xxxDN 6.2.7 Nested Vectored Interrupt Controller (NVIC) The Cortex®-M0 provides an interrupt controller as an integral part of the exception mode, named as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor core and provides following features:  Nested and Vectored interrupt support  Automatic processor state saving and restoration  Reduced and deterministic interrupt latency The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of the interrupts and most of the system exceptions can be configured to different priority levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched from a vector table in memory. There is no need to determine which interrupt is accepted and branch to the starting address of the correlated ISR by software. While the starting address is fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the normal execution. Thus it will take less and deterministic time to process the interrupt request. The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will give priority to the higher one without delay penalty. Thus it advances the real-time capability. For more detailed information, please refer to the “ARM® Cortex®-M0 Technical Reference Manual” and “ARM® v6-M Architecture Reference Manual”. N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 59 of 107 Rev 1.02

NUC100/120xxxDN 6.3 Clock Controller 6.3.1 Overview The clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and clock divider. The chip enters Power-down mode when Cortex®-M0 core executes the WFI instruction only if the PWR_DOWN_EN (PWRCON[7]) bit and PD_WAIT_CPU (PWRCON[8]) bit are both set to 1. After that, chip enters Power-down mode and waits for wake-up interrupt source triggered to leave Power-down mode. In the Power-down mode, the clock controller turns off the external 4~24 MHz high speed crystal and internal 22.1184 MHz high speed oscillator to reduce the overall system power consumption. N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 60 of 107 Rev 1.02

NUC100/120xxxDN 22.1184 22.1184 MHz MHz 111 CPUCLK CPU 10 kHz 4~24 011 EBI MHz PLLFOUT 010 1/(HCLK_N+1) HCLK PDMA 32.768 32.768 kHz 001 ACMP kHz 4~24 MHz PCLK I2C 0~1 000 22.1184 MHz 111 10 kHz CLKSEL0[2:0] 10 kHz 101 External trigger TMR 3 011 TMR 2 22.1184 MHz 1 HCLK 010 TMR 1 4~24 MHz 0 PLLFOUT 32.768 kHz 001 TMR 0 4~24 MHz PLLCON[19] 000 22.1184 MHz CLKSEL1[22:20] FMC CLKSEL1[18:16] CLKSEL1[14:12] CPUCLK 22.1184 MHz 1/2 111 CLKSEL1[10:8] 1 SysTick HCLK 0 1/2 011 4~24 MHz 10 kHz SYST_CSR[2] 1/2 010 111 32.768 kHz 22.1184 MHz 001 011 PWM 6-7 4~24 MHz HCLK PWM 4-5 000 010 PWM 2-3 32.768 kHz CLKSEL0[5:3] 001 PWM 0-1 4~24 MHz 000 CLKSEL2[17:16] 22.1184 MHz 11 10 kHz 11 HCLK 10 CLKSEL2[11:4] 10 WWDT PLLFOUT CLKSEL1[31:28] 01 10 kHz 11 4~24 MHz 00 HCLK 1/2048 10 WDT CLKSEL2[1:0] 32.768 kHz 01 22.1184 MHz PS2 22.1184 MHz CLKSEL1[1:0] 11 I2S PLLFOUT 01 CPUCLK 1 4~24 MHz 00 0 SPI0-3 NU C CLKSEL1[25:24] SYST_CSR[2] 1 0 1/(UART_N+1) UART 0-2 0 22.1184 MHz 11 /1 2 HCLK 10 1/(ADC_N+1) ADC 0 X PLLFOUT 01 22.1184 MHz 10 kHz X 11 BOD X 4~24 MHz 00 HCLK D 10 N CLKSEL1[3:2] 32.768 kHz 01 FDIV D A 22.1184 MHz 11 4~24 MHz 00 32.768 kHz RTC TA S HCLK CLKSEL2[3:2] 10 H PLLFOUT 1/(SC2_N+1) SC 2 E 01 E 4~24 MHz 00 1/(SC1_N+1) SC 1 T CLKSEL3[5:4] 1/(SC0_N+1) SC 0 CLKSEL3[3:2] CLKSEL3[1:0] PLLFOUT 1/(USB_N+1) USB Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6-10 Clock Generator Global View Diagram Mar. 02, 2017 Page 61 of 107 Rev 1.02

NUC100/120xxxDN 6.3.2 Clock Generator The clock generator consists of 5 clock sources as listed below:  One external 32.768 kHz low speed crystal  One external 4~24 MHz high speed crystal  One programmable PLL FOUT (PLL source consists of external 4~24 MHz high speed crystal and internal 22.1184 MHz high speed oscillator)  One internal 22.1184 MHz high speed oscillator  One internal 10 kHz low speed oscillator XTL32K_EN (PWRCON[1]) X32I External 32.768 kHz 32.768 kHz Crystal X32O XTL12M_EN (PWRCON[0]) 4~24 MHz XT_IN External 4~24 MHz PLL_SRC (PLLCON[19]) Crystal XT_OUT 0 PLL FOUT PLL OSC22M_EN (PWRCON[2]) 1 Internal 22.1184 MHz Oscillator N 22.1184 MHz U C OSC10K_EN(PWRCON[3]) 1 0 0 /12 Internal 10 kHz 0 10 kHz X X Oscillator X D N D Figure 6-11 Clock Generator Block Diagram A T A S H E E T Mar. 02, 2017 Page 62 of 107 Rev 1.02

NUC100/120xxxDN 6.3.3 System Clock and SysTick Clock The system clock has 5 clock sources which were generated from clock generator block. The clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is shown in Figure 6-12. HCLK_S (CLKSEL0[2:0]) 22.1184 MHz 111 10 kHz 011 CPUCLK CPU PLLFOUT 010 HCLK 1/(HCLK_N+1) AHB 32.768 kHz 001 HCLK_N (CLKDIV[3:0]) PCLK APB 4~24 MHz 000 CPU in Power Down Mode Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6-12 System Clock Block Diagram The clock source of SysTick in Cortex®-M0 core can use CPU clock or external clock (SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block diagram is shown in Figure 6-13. N U STCLK_S (CLKSEL0[5:3]) C 1 0 0 /1 2 22.1184 MHz 0 1/2 111 X X HCLK X 1/2 011 D 4~24 MHz 1/2 010 STCLK N D A 32.768 kHz T 001 A S 4~24 MHz H 000 E E T Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6-13 SysTick Clock Control Block Diagram Mar. 02, 2017 Page 63 of 107 Rev 1.02

NUC100/120xxxDN 6.3.4 Peripherals Clock The peripherals clock can be selected as different clock source depends on the clock source select control registers (CLKSEL1, CLKSEL2 and CLKSEL3). 6.3.5 Power-down Mode Clock When chip enters Power-down mode, system clocks, some clock sources, and some peripheral clocks will be disabled. Some clock sources and peripherals clocks are still active in Power-down mode. The clocks still kept active are listed below:  Clock Generator  Internal 10 kHz low speed oscillator clock  External 32.768 kHz low speed crystal clock  Peripherals Clock (when IP adopt external 32.768 kHz low speed crystal oscillator or 10 kHz low speed oscillator as clock source) 6.3.6 Frequency Divider Output This device is equipped with a power-of-2 frequency divider which is composed by16 chained divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided clocks with the frequency from F /21 to F /216 where Fin is input clock frequency to the clock in in divider. The output formula is F = F /2(N+1), where F is the input clock frequency, F is the clock out in in out divider output frequency and N is the 4-bit value in FSEL (FRQDIV[3:0]). When writing 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When writing 0 to DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low N state and stay in low state. U C 1 0 0 /1 2 0 X FRQDIV_S (CLKSEL2[3:2]) X X D N FDIV_EN(APBCLK[6]) D 22.1184 MHz A 11 T A HCLK FRQDIV_CLK S 10 H E 32.768 kHz E 01 T 4~24 MHz 00 Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6-14 Clock Source of Frequency Divider Mar. 02, 2017 Page 64 of 107 Rev 1.02

NUC100/120xxxDN DIVIDER_EN (FRQDIV[4]) Enable 16 chained divide-by-2 counter divide-by-2 counter FRQDIV_CLK 1/2 1/22 1/23 …... 1/215 1/216 0000 0001 16 to 1 CLKO : : MUX 1110 1111 FSEL (FRQDIV[3:0]) Figure 6-15 Frequency Divider Block Diagram N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 65 of 107 Rev 1.02

NUC100/120xxxDN 6.4 FLASH MEMORY CONTROLLER (FMC) 6.4.1 Overview The NuMicro® NUC100 series has 128/64/32 Kbytes on-chip embedded Flash for application program memory (APROM) that can be updated through ISP procedure. The In-System- Programming (ISP) function enables user to update program memory when chip is soldered on PCB. After chip is powered on, Cortex®-M0 CPU fetches code from APROM or LDROM decided by boot select (CBS) in Config0. By the way, the NuMicro® NUC100 series also provides additional DATA Flash for user to store some application dependent data. For 128 Kbytes APROM device, the Data Flash is shared with original 128K program memory and its start address is configurable in Config1. For 64/32 Kbytes APROM device, the Data Flash is fixed at 4K. 6.4.2 Features  Runs up to 50 MHz with zero wait state for continuous address read access  All embedded flash memory supports 512 bytes page erase  128/64/32 KB application program memory (APROM)  4 KB In-System-Programming (ISP) loader program memory (LDROM)  4KB Data Flash for 64/32 KB APROM device  Configurable Data Flash size for 128KB APROM device  Configurable or fixed 4 KB Data Flash with 512 bytes page erase unit  Supports In-Application-Programming (IAP) to switch code between APROM and LDROM without reset  In-System-Programming (ISP) to update on-chip Flash N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 66 of 107 Rev 1.02

NUC100/120xxxDN 6.5 External Bus Interface (EBI) 6.5.1 Overview The NuMicro® NUC100 series LQFP-64 and LQFP-100 package is equipped with an external bus interface (EBI) for accessing an external device. To save the connections between external device and this chip, EBI supports address bus and data bus multiplex mode. And, address latch enable (ALE) signal is used to differentiate the address and data cycle. 6.5.2 Features External Bus Interface has the following functions:  Supports external devices with max. 64 KB size (8-bit data width)/128 KB (16-bit data width)  Supports variable external bus base clock (MCLK) which based on HCLK  Supports 8-bit or 16-bit data width  Supports variable data access time (tACC), address latch enable time (tALE) and address hold time (tAHD)  Supports address bus and data bus multiplex mode to save the address pins  Supports configurable idle cycle for different access condition: Write command finish (W2X), Read-to-Read (R2R) N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 67 of 107 Rev 1.02

NUC100/120xxxDN 6.6 General Purpose I/O (GPIO) 6.6.1 Overview The NuMicro® NUC100 series has up to 84 General Purpose I/O pins to be shared with other function pins depending on the chip configuration. These 84 pins are arranged in 6 ports named as GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and GPIOF. The GPIOA/B/C/D/E port has the maximum of 16 pins and GPIOF port has the maximum of 4 pins. Each of the 84 pins is independent and has the corresponding register bits to control the pin mode function and data. The I/O type of each of I/O pins can be configured by software individually as input, output, open- drain or Quasi-bidirectional mode. After reset, the I/O mode of all pins are depending on Config0[10] setting. In Quasi-bidirectional mode, I/O pin has a very weak individual pull-up resistor which is about 110~300 K for V is from 5.0 V to 2.5 V. DD 6.6.2 Features  Four I/O modes: – Quasi-bidirectional – Push-Pull output – Open-Drain output – Input only with high impendence  TTL/Schmitt trigger input selectable by GPx_TYPE[15:0] in GPx_MFP[31:16]  I/O pin configured as interrupt source with edge/level setting  Configurable default I/O mode of all pins after reset by Config0[10] setting – If Config[10] is 0, all GPIO pins in input tri-state mode after chip reset – If Config[10] is 1, all GPIO pins in Quasi-bidirectional mode after chip reset N U  I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode C 1 0  Enabling the pin interrupt function will also enable the pin wake-up function. 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 68 of 107 Rev 1.02

NUC100/120xxxDN 6.7 PDMA Controller (PDMA) 6.7.1 Overview The NuMicro® NUC100 series DMA contains nine-channel peripheral direct memory access (PDMA) controller and a cyclic redundancy check (CRC) generator. The PDMA that transfers data to and from memory or transfer data to and from APB devices. For PDMA channel (PDMA CH0~CH8), there is one-word buffer as transfer buffer between the Peripherals APB devices and Memory. Software can stop the PDMA operation by disable PDMA PDMA_CSRx[PDMACEN]. The CPU can recognize the completion of a PDMA operation by software polling or when it receives an internal PDMA interrupt. The PDMA controller can increase source or destination address or fixed them as well. The DMA controller contains a cyclic redundancy check (CRC) generator that can perform CRC calculation with programmable polynomial settings. The CRC engine supports CPU PIO mode and DMA transfer mode. 6.7.2 Features  Supports nine PDMA channels and one CRC channel. Each PDMA channel can support a unidirectional transfer  AMBA AHB master/slave interface compatible, for data transfer and register read/write  Hardware round robin priority scheme. DMA channel 0 has the highest priority and channel 8 has the lowest priority  PDMA operation – Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer – Supports word/half-word/byte transfer data width from/to peripheral – Supports address direction: increment, fixed.  Cyclic Redundancy Check (CRC) N – Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 U C  CRC-CCITT: X16 + X12 + X5 + 1 1  CRC-8: X8 + X2 + X + 1 00  CRC-16: X16 + X15 + X2 + 1 /1 2  CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 0X X – Supports programmable CRC seed value. X D – Supports programmable order reverse setting for input data and CRC checksum. N D – Supports programmable 1’s complement setting for input data and CRC checksum. A T A – Supports CPU PIO mode or DMA transfer mode. S H – Supports the follows write data length in CPU PIO mode E E  8-bit write mode (byte): 1-AHB clock cycle operation. T  16-bit write mode (half-word): 2-AHB clock cycle operation.  32-bit write mode (word): 4-AHB clock cycle operation. – Supports byte alignment transfer data length and word alignment transfer source address in CRC DMA mode. Mar. 02, 2017 Page 69 of 107 Rev 1.02

NUC100/120xxxDN 6.8 Timer Controller (TMR) 6.8.1 Overview The timer controller includes four 32-bit timers, TIMER0~TIMER3, allowing user to easily implement a timer control for applications. The timer can perform functions, such as frequency measurement, event counting, interval measurement, clock generation, and delay timing. The timer can generate an interrupt signal upon time-out, or provide the current value during operation. 6.8.2 Features  Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter  Independent clock source for each timer  Provides one-shot, periodic, toggle and continuous counting operation modes  Time-out period = (Period of timer clock input) * (8-bit prescale counter + 1) * (24-bit TCMP)  Maximum counting cycle time = (1 / T MHz) * (28) * (224), T is the period of timer clock  24-bit up counter value is readable through TDR (Timer Data Register)  Supports event counting function to count the event from external pin  Supports external pin capture function for interval measurement  Supports external pin capture function for reset timer counter  Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated (TIF set to 1) N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 70 of 107 Rev 1.02

NUC100/120xxxDN 6.9 PWM Generator and Capture Timer (PWM) 6.9.1 Overview The NuMicro® NUC100 series has 2 sets of PWM groups supporting a total of 4 sets of PWM generators that can be configured as 8 independent PWM outputs, PWM0~PWM7, or as 4 complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3), (PWM4, PWM5) and (PWM6, PWM7) with 4 programmable Dead-zone generators. Each PWM generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM counters for PWM period control, two 16-bit comparators for PWM duty control and one Dead-zone generator. The 4 sets of PWM generators provide eight independent PWM interrupt flags set by hardware when the corresponding PWM period down counter reaches 0. Each PWM interrupt source with its corresponding enable bit can cause CPU to request PWM interrupt. The PWM generators can be configured as one-shot mode to produce only one PWM cycle signal or auto-reload mode to output PWM waveform continuously. When PCR.DZEN01 is set, PWM0 and PWM1 perform complementary PWM paired function; the paired PWM period, duty and Dead-time are determined by PWM0 timer and Dead-zone generator 0. Similarly, the complementary PWM pairs of (PWM2, PWM3), (PWM4, PWM5) and (PWM6, PWM7) are controlled by PWM2, PWM4 and PWM6 timers and Dead-zone generator 2, 4 and 6, respectively. To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and 16-bit comparator are implemented with double buffer. When user writes data to counter/comparator buffer registers the updated value will be load into the 16-bit down counter/ comparator at the time down counter reaching 0. The double buffering feature avoids glitch at PWM outputs. When the 16-bit period down counter reaches 0, the interrupt request is generated. If PWM-timer is set as auto-reload mode, when the down counter reaches 0, it is reloaded with PWM Counter Register (CNRx) automatically then start decreasing, repeatedly. If the PWM-timer is set as one- shot mode, the down counter will stop and generate one interrupt request when it reaches 0. N The value of PWM counter comparator is used for pulse high width modulation. The counter U control logic changes the output to high level when down-counter value matches the value of C 1 compare register. 0 0 /1 The alternate feature of the PWM-timer is digital input Capture function. If Capture function is 2 0 enabled the PWM output pin is switched as capture input mode. The Capture0 and PWM0 share X X one timer which is included in PWM0 and the Capture1 and PWM1 share PWM1 timer, and etc. X Therefore user must setup the PWM-timer before enable Capture feature. After capture feature is D N enabled, the capture always latched PWM-counter to Capture Rising Latch Register (CRLR) D when input channel has a rising transition and latched PWM-counter to Capture Falling Latch A T Register (CFLR) when input channel has a falling transition. Capture channel 0 interrupt is A S programmable by setting CCR0.CRL_IE0[1] (Rising latch Interrupt enable) and H CCR0.CFL_IE0[2]] (Falling latch Interrupt enable) to decide the condition of interrupt occur. E E Capture channel 1 has the same feature by setting CCR0.CRL_IE1[17] and CCR0.CFL_IE1[18]. T And capture channel 2 to channel 3 on each group have the same feature by setting the corresponding control bits in CCR2. For each group, whenever Capture issues Interrupt 0/1/2/3, the PWM counter 0/1/2/3 will be reload at this moment. The maximum captured frequency that PWM can capture is confined by the capture interrupt latency. When capture interrupt occurred, software will do at least three steps, including: Read PIIR to get interrupt source and Read CRLRx/CFLRx(x=0~3) to get capture value and finally write 1 to clear PIIR to 0. If interrupt latency will take time T0 to finish, the capture signal mustn’t transition during this interval (T0). In this case, the maximum capture frequency will be 1/T0. For example: HCLK = 50 MHz, PWM_CLK = 25 MHz, Interrupt latency is 900 ns Mar. 02, 2017 Page 71 of 107 Rev 1.02

NUC100/120xxxDN So the maximum capture frequency will be 1/900ns = 1000 kHz 6.9.2 Features 6.9.2.1 PWM Function:  Up to 2 PWM groups (PWMA/PWMB) to support 8 PWM channels or 4 complementary PWM paired channels  Each PWM group has two PWM generators with each PWM generator supporting one 8-bit prescaler, two clock divider, two PWM-timers, one Dead-zone generator and two PWM outputs.  Up to 16-bit resolution  PWM Interrupt request synchronized with PWM period  One-shot or Auto-reload mode PWM  Edge-aligned type or Center-aligned type option 6.9.2.2 Capture Function:  Timing control logic shared with PWM Generators  Supports 8 Capture input channels shared with 8 PWM output channels  Each channel supports one rising latch register (CRLR), one falling latch register (CFLR) and Capture interrupt flag (CAPIFx) N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 72 of 107 Rev 1.02

NUC100/120xxxDN 6.10 Watchdog Timer (WDT) 6.10.1 Overview The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer supports the function to wake-up system from Idle/Power-down mode. 6.10.2 Features  18-bit free running up counter for Watchdog Timer time-out interval.  Selectable time-out interval (24 ~ 218) and the time-out interval is 104 ms ~ 26.3168 s if WDT_CLK = 10 kHz.  System kept in reset state for a period of (1 / WDT_CLK) * 63  Supports selectable Watchdog Timer reset delay period, it includes (1024+2)、(128+2) 、 (16+2) or (1+2) WDT_CLK reset delay period.  Supports force Watchdog Timer enabled after chip powered on or reset while CWDTEN (Config0[31] watchdog enable) bit is set to 0.  Supports Watchdog Timer time-out wake-up function when WDT clock source is selected to 10 kHz low speed oscillator. N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 73 of 107 Rev 1.02

NUC100/120xxxDN 6.11 Window Watchdog Timer (WWDT) 6.11.1 Overview The purpose of Window Watchdog Timer is to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. 6.11.2 Features  6-bit down counter (WWDTVAL[5:0]) and 6-bit compare value (WWDTCR[21:16] – WINCMP value) to make the window period flexible  Selectable maximum 11-bit WWDT clock prescale (WWDTCR[11:8] – PERIODSEL value) to make WWDT time-out interval variable N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 74 of 107 Rev 1.02

NUC100/120xxxDN 6.13 Real Time Clock (RTC) 6.13.1 Overview The Real Time Clock (RTC) controller provides user with the real time and calendar message. The clock source of RTC controller is from an external 32.768 kHz low speed crystal which connected at pins X32I and X32O (refer to pin Description) or from an external 32.768 kHz low speed oscillator output fed at pin X32I. The RTC controller provides the real time message (hour, minute, second) in TLR (RTC Time Loading Register) as well as calendar message (year, month, day) in CLR (RTC Calendar Loading Register). It also offers RTC alarm function that user can preset the alarm time in TAR (RTC Time Alarm Register) and alarm calendar in CAR (RTC Calendar Alarm Register). The data format of RTC time and calendar message are all expressed in BCD format. The RTC controller supports periodic RTC Time Tick and Alarm Match interrupts. The periodic RTC Time Tick interrupt has 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by TTR (TTR[2:0] Time Tick Register). When real time and calendar message in TLR and CLR are equal to alarm time and calendar settings in TAR and CAR, the AIF (RIIR [0] RTC Alarm Interrupt Flag) is set to 1 and the RTC alarm interrupt signal is generated if the AIER (RIER [0] Alarm Interrupt Enable) is enabled. Both RTC Time Tick and Alarm Match interrupt signal can cause chip to wake-up from Idle or Power-down mode if the correlate interrupt enable bit (AIER or TIER) is set to 1 before chip enters Idle or Power-down mode. 6.13.2 Features  Supports real time counter in TLR (hour, minute, second) and calendar counter in CLR (year, month, day) for RTC time and calendar check  Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in TAR and CAR  Selectable 12-hour or 24-hour time scale in TSSR register  Supports Leap Year indication in LIR register N U C  Supports Day of the Week counter in DWR register 1 0 0  Frequency of RTC clock source compensate by FCR register /1 2  All time and calendar message expressed in BCD format 0 X X  Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32, X D 1/16, 1/8, 1/4, 1/2 and 1 second N D  Supports RTC Time Tick and Alarm Match interrupt A T  Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is A S generated H E E T Mar. 02, 2017 Page 75 of 107 Rev 1.02

NUC100/120xxxDN 6.14 UART Interface Controller (UART) The NuMicro® NUC100 series provides up to three channels of Universal Asynchronous Receiver/Transmitters (UART). UART0 supports High Speed UART and UART1~2 perform Normal Speed UART. Besides, only UART0 and UART1 support the flow control function. 6.14.1 Overview The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the CPU. The UART controller also supports IrDA SIR, LIN master/slave mode and RS-485 mode functions. Each UART channel supports seven types of interrupts including:  Transmitter FIFO empty interrupt (INT_THRE)  Receiver threshold level reached interrupt (INT_RDA),  Line status interrupt (parity error or frame error or break interrupt) (INT_RLS),  Receiver buffer time-out interrupt (INT_TOUT),  MODEM/Wake-up status interrupt (INT_MODEM),  Buffer error interrupt (INT_BUF_ERR)  LIN interrupt (INT_LIN) Interrupts of UART0 and UART2 share the interrupt number 12 (vector number is 28); Interrupt number 13 (vector number is 29) only supports UART1 interrupt. Refer to the Nested Vectored Interrupt Controller chapter for System Interrupt Map. The UART0 is built-in with a 64-byte transmitter FIFO (TX_FIFO) and a 64-byte receiver FIFO (RX_FIFO) that reduces the number of interrupts presented to the CPU. The UART1~2 are equipped with 16-byte transmitter FIFO (TX_FIFO) and 16-byte receiver FIFO (RX_FIFO). The CPU can read the status of the UART at any time during the operation. The reported status information includes the type and condition of the transfer operations being performed by the UART, as well as 4 error conditions (parity error, frame error, break interrupt and buffer error) N probably occur while receiving data. The UART includes a programmable baud rate generator U C that is capable of dividing clock input by divisors to produce the serial clock that transmitter and 1 receiver need. The baud rate equation is Baud Rate = UART_CLK / M * [BRD + 2], where M and 0 0/1 BRD are defined in Baud Rate Divider Register (UA_BAUD). Table 6-6 lists the equations in the 2 various conditions and Table 6-7 lists the UART baud rate setting table. 0 X X X D N Mode DIV_X_EN DIV_X_ONE Divider X BRD Baud Rate Equation D A 0 0 0 Don’t care A UART_CLK / [16 * (A+2)] T A S 1 1 0 B A UART_CLK / [(B+1) * (A+2)] , B must >= 8 H E E 2 1 1 Don’t care A UART_CLK / (A+2), A must >=3 T Table 6-6 UART Baud Rate Equation System Clock = Internal 22.1184 MHz High Speed Oscillator Mode 0 Mode 1 Mode 2 Baud Rate Parameter Register Parameter Register Parameter Register 921600 x x A=0,B=11 0x2B00_0000 A=22 0x3000_0016 Mar. 02, 2017 Page 76 of 107 Rev 1.02

NUC100/120xxxDN A=1,B=15 0x2F00_0001 460800 A=1 0x0000_0001 A=46 0x3000_002E A=2,B=11 0x2B00_0002 A=4,B=15 0x2F00_0004 230400 A=4 0x0000_0004 A=94 0x3000_005E A=6,B=11 0x2B00_0006 A=10,B=15 0x2F00_000A 115200 A=10 0x0000_000A A=190 0x3000_00BE A=14,B=11 0x2B00_000E A=22,B=15 0x2F00_0016 57600 A=22 0x0000_0016 A=382 0x3000_017E A=30,B=11 0x2B00_001E A=62,B=8 0x2800_003E 38400 A=34 0x0000_0022 A=46,B=11 0x2B00_002E A=574 0x3000_023E A=34,B=15 0x2F00_0022 A=126,B=8 0x2800_007E 19200 A=70 0x0000_0046 A=94,B=11 0x2B00_005E A=1150 0x3000_047E A=70,B=15 0x2F00_0046 0x2800_00FE A=254,B=8 9600 A=142 0x0000_008E A=190,B=11 0x2B00_00BE A=2302 0x3000_08FE A=142,B=15 0x2F00_008E 0x2800_01FE A=510,B=8 4800 A=286 0x0000_011E A=382,B=11 0x2B00_017E A=4606 0x3000_11FE A=286,B=15 0x2F00_011E Table 6-7 UART Baud Rate Setting Table The UART0 and UART1 controllers support the auto-flow control function that uses two low-level signals, /CTS (clear-to-send) and /RTS (request-to-send), to control the flow of data transfer between the chip and external devices (e.g. Modem). When auto-flow is enabled, the UART is not allowed to receive data until the UART asserts /RTS to external device. When the number of N U bytes in the RX FIFO equals the value of RTS_TRI_LEV (UA_FCR [19:16]), the /RTS is de- C 1 asserted. The UART sends data out when UART controller detects /CTS is asserted from external 0 0 device. If a valid asserted /CTS is not detected the UART controller will not send data out. /1 2 0 UART Mode : MCR[LEV_RTS] = 1 X X X MCR [RTS] D N D MCR [RTS_ST] A T A S H UART Mode : MCR[LEV_RTS] = 0 E E T MCR [RTS] MCR [RTS_ST] Figure 6-16 UART nRTS Auto-Flow Control Trigger Level The UART controllers also provides Serial IrDA (SIR, Serial Infrared) function (User must set IrDA_EN (UA_FUN_SEL [1]) to enable IrDA function). The SIR specification defines a short-range infrared asynchronous serial transmission mode with 1 start bit, 8 data bits, and 1 stop bit. The maximum data rate supports up to 115.2 Kbps (half duplex). The IrDA SIR block contains an IrDA Mar. 02, 2017 Page 77 of 107 Rev 1.02

NUC100/120xxxDN SIR Protocol encoder/decoder. The IrDA SIR Protocol encoder/decoder is half-duplex only. So it cannot transmit and receive data at the same time. The IrDA SIR physical layer specifies a minimum 10ms transfer delay between transmission and reception, and this delay feature must be implemented by software. The alternate function of UART controllers is LIN (Local Interconnect Network) function. The LIN mode is selected by setting the UA_FUN_SEL[1:0] to ’01’. In LIN mode, 1 start bit and 8 data bits format with 1 stop bit are required in accordance with the LIN standard. For NuMicro® NUC100 series, another alternate function of UART controllers is RS-485 9-bit mode, and direction control provided by /RTS pin or can program GPIO (PB.2 for UART0_nRTS and PB.6 for UART1_nRTS) to implement the function by software. The RS-485 mode is selected by setting the UA_FUN_SEL register to select RS-485 function. The RS-485 transceiver control is implemented using the /RTS control signal from an asynchronous serial port to enable the RS- 485 transceiver. In RS-485 mode, many characteristics of the receiving and transmitting are same as UART. 6.14.2 Features  Full duplex, asynchronous communications  Separates receive / transmit 64/16/16 bytes (UART0/UART1/UART2) entry FIFO for data payloads  Supports hardware auto flow control/flow control function (CTS, RTS) and programmable RTS flow control trigger level (UART0 and UART1 support)  Programmable receiver buffer trigger level  Supports programmable baud-rate generator for each channel individually  Supports CTS wake-up function (UART0 and UART1 support)  Supports 7-bit receiver buffer time-out detection function N  UART0/UART1 can through DMA channels to receive/transmit data U C  Programmable transmitting data delay time between the last stop and the next start bit by 1 0 setting UA_TOR [DLY] register 0 /1 2  Supports break error, frame error, parity error and receive / transmit buffer overflow detect 0 X function X X D  Fully programmable serial-interface characteristics N D – Programmable data bit length, 5-, 6-, 7-, 8-bit character A T – Programmable parity bit, even, odd, no parity or stick parity bit generation and A S detection H E E – Programmable stop bit length, 1, 1.5, or 2 stop bit generation T  IrDA SIR function mode – Supports 3-/16-bit duration for normal mode  LIN function mode – Supports LIN master/slave mode – Supports programmable break generation function for transmitter – Supports break detect function for receiver  RS-485 function mode. Mar. 02, 2017 Page 78 of 107 Rev 1.02

NUC100/120xxxDN – Supports RS-485 9-bit mode – Supports hardware or software direct enable control provided by RTS pin N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 79 of 107 Rev 1.02

NUC100/120xxxDN 6.15 Smart Card Host Interface (SC) 6.15.1 Overview The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully compliant with PC/SC Specifications. It also provides status of card insertion/removal. 6.15.2 Features  ISO7816-3 T=0, T=1 compliant  EMV2000 compliant  Supports up to three ISO7816-3 ports  Separates receive/ transmit 4 byte entry buffer for data payloads  Programmable transmission clock frequency  Programmable receiver buffer trigger level  Programmable guard time selection (11 ETU ~ 266 ETU)  One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting times processing  Supports auto inverse convention function  Supports transmitter and receiver error retry and error retry number limitation function  Supports hardware activation sequence process  Supports hardware warm reset sequence process  Supports hardware deactivation sequence process  Supports hardware auto deactivation sequence when detecting the card removal N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 80 of 107 Rev 1.02

NUC100/120xxxDN 6.16 PS/2 Device Controller (PS2D) 6.16.1 Overview The PS/2 device controller provides a basic timing control for PS/2 communication. All communication between the device and the host is managed through the CLK and DATA pins. Unlike PS/2 keyboard or mouse device controller, the receive/transmit code needs to be translated as meaningful code by firmware. The device controller generates the CLK signal after receiving a “Request to Send” state, but host has ultimate control over communication. Data of DATA line sent from the host to the device is read on the rising edge and sent from the device to the host is change after rising edge. A 16 bytes FIFO is used to reduce CPU intervention. Software can select 1 to 16 bytes for a continuous transmission. 6.16.2 Features  Host communication inhibit and Request to Send state detection  Reception frame error detection  Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention  Double buffer for data reception  Software override bus N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 81 of 107 Rev 1.02

NUC100/120xxxDN 6.17 I2C Serial Interface Controller (I2C) 6.17.1 Overview I2C is a two-wire, bidirectional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. Data is transferred between a Master and a Slave. Data bits transfer on the SCL and SDA lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit long. There is one SCL clock pulse for each data bit with the MSB being transmitted first, and an acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to Figure 6-17 for more detailed I2C BUS Timing. Repeated STOP START START STOP SDA t BUF t LOW SCL t t r f t HIGH t t t t t HD;STA HD;DAT SU;DAT SU;STA SU;STO Figure 6-17 I2C Bus Timing N The device’s on-chip I2C logic provides a serial interface that meets the I2C bus standard mode U specification. The I2C port handles byte transfers autonomously. To enable this port, the bit ENS1 C 1 in I2CON should be set to '1'. The I2C hardware interfaces to the I2C bus via two pins: SDA and 00 SCL. Pull-up resistor is needed for I2C operation as the SDA and SCL are open drain pins. When /1 I/O pins are used as I2C ports, user must set the pins function to I2C in advance. 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 82 of 107 Rev 1.02

NUC100/120xxxDN 6.17.2 Features The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the bus include:  Master/Slave mode  Bidirectional data transfer between masters and slaves  Multi-master bus (no central master)  Arbitration between simultaneously transmitting masters without corruption of serial data on the bus  Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus  Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer  A built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and timer-out counter overflows  External pull-up resistors needed for high output  Programmable clocks allowing for versatile rate control  Supports 7-bit addressing mode  Supports multiple address recognition (four slave addresses with mask option) N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 83 of 107 Rev 1.02

NUC100/120xxxDN 6.18 Serial Peripheral Interface (SPI) 6.18.1 Overview The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bi- direction interface. The NuMicro® NUC100 series contains up to four sets of SPI controllers performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. Each set of SPI controller can be configured as a master or a slave device. The SPI controller supports the variable serial clock function for special applications and 2-bit Transfer mode to connect 2 off-chip slave devices at the same time. This controller also supports the PDMA function to access the data buffer and also supports Dual I/O Transfer mode. 6.18.2 Features  Up to four sets of SPI controllers  Supports Master or Slave mode operation  Supports 2-bit Transfer mode  Supports Dual I/O Transfer mode  Configurable bit length of a transfer word from 8 to 32-bit  Provides separate 8-layer depth transmit and receive FIFO buffers  Supports MSB first or LSB first transfer sequence  Two slave select lines in Master mode  Supports the byte reorder function  Supports Byte or Word Suspend mode  Variable output serial clock frequency in Master mode N U  Supports PDMA transfer C 1 0  Supports 3-wire, no slave select signal, bi-direction interface 0 /12 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 84 of 107 Rev 1.02

NUC100/120xxxDN 6.19 I2S Controller (I2S) 6.19.1 Overview The I2S controller consists of I2S protocol to interface with external audio CODEC. Two 8-word deep FIFO for read path and write path respectively and is capable of handling 8-, 16-, 24- and 32-bit word sizes. PDMA controller handles the data movement between FIFO and memory. 6.19.2 Features  Operated as either Master or Slave  Capable of handling 8-, 16-, 24- and 32-bit word sizes  Supports Mono and stereo audio data  Supports I2S and MSB justified data format  Provides two 8-word FIFO data buffers, one for transmitting and the other for receiving  Generates interrupt requests when buffer levels cross a programmable boundary  Two PDMA requests, one for transmitting and the other for receiving N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 85 of 107 Rev 1.02

NUC100/120xxxDN 6.20 USB Device Controller (USB) 6.20.1 Overview There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant with USB 2.0 full-speed device specification and supports control/bulk/interrupt/ isochronous transfer types. In this device controller, there are two main interfaces: the APB bus and USB bus which comes from the USB PHY transceiver. For the APB bus, the CPU can program control registers through it. There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User needs to set the effective starting address of SRAM for each endpoint buffer through “buffer segmentation register (USB_BUFSEGx)”. There are 6 endpoints in this controller. Each of the endpoint can be configured as IN or OUT endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are implemented in this block. The block of ENDPOINT CONTROL is also used to manage the data sequential synchronization, endpoint states, current start address, transaction status, and data buffer status for each endpoint. There are four different interrupt events in this controller. They are the wake-up function, device plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend and resume, etc. Any event will cause an interrupt, and users just need to check the related event flags in interrupt event status register (USB_INTSTS) to acknowledge what kind of interrupt occurring, and then check the related USB Endpoint Status Register (USB_EPSTS) to acknowledge what kind of event occurring in this endpoint. A software-disable function is also supported for this USB controller. It is used to simulate the disconnection of this device from the host. If user enables DRVSE0 bit (USB_DRVSE0), the USB controller will force the output of USB_DP and USB_DM to level low and its function is disabled. After disable the DRVSE0 bit, host will enumerate the USB device again. Please refer to Universal Serial Bus Specification Revision 1.1 N U C 1 6.20.2 Features 0 0 /1 This Universal Serial Bus (USB) performs a serial interface with a single connector type for 2 0 attaching all USB peripherals to the host system. Following is the feature list of this USB. X X X  Compliant with USB 2.0 Full-Speed specification D N  Provides 1 interrupt vector with 4 different interrupt events (WAKEUP, FLDET, USB D A and BUS) T A  Supports Control/Bulk/Interrupt/Isochronous transfer type S H E  Supports suspend function when no bus activity existing for 3 ms E T  Provides 6 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types and maximum 512 bytes buffer size  Provides remote wake-up capability Mar. 02, 2017 Page 86 of 107 Rev 1.02

NUC100/120xxxDN 6.21 Analog-to-Digital Converter (ADC) 6.21.1 Overview The NuMicro® NUC100 series contains one 12-bit successive approximation analog-to-digital converters (SAR A/D converter) with 8 input channels. The A/D converter supports three operation modes: single, single-cycle scan and continuous scan mode. The A/D converter can be started by software, PWM Center-aligned trigger and external STADC pin. 6.21.2 Features  Analog input voltage range: 0~V REF  12-bit resolution and 10-bit accuracy is guaranteed  Up to 8 single-end analog input channels or 4 differential analog input channels  Up to 760 kSPS conversion rate as ADC clock frequency is 16 MHz (chip working at 5V)  Three operating modes –Single mode: A/D conversion is performed one time on a specified channel –Single-cycle scan mode: A/D conversion is performed one cycle on all specified channels with the sequence from the smallest numbered channel to the largest numbered channel –Continuous scan mode: A/D converter continuously performs Single-cycle scan mode until software stops A/D conversion  An A/D conversion can be started by: –Writing 1 to ADST bit through software –PWM Center-aligned trigger –External pin STADC  Conversion results are held in data registers for each channel with valid and overrun N indicators U C 1  Conversion result can be compared with specify value and user can select whether to 0 0 generate an interrupt when conversion result matches the compare register setting /1 2 0  Channel 7 supports 3 input sources: external analog voltage, internal Band-gap voltage, X X and internal temperature sensor output X D N D A T A S H E E T Mar. 02, 2017 Page 87 of 107 Rev 1.02

NUC100/120xxxDN 6.22 Analog Comparator (ACMP) 6.22.1 Overview The NuMicro® NUC100 series contains two comparators which can be used in a number of different configurations. The comparator output is logic 1 when positive input voltage is greater than negative input voltage; otherwise the output is logic 0. Each comparator can be configured to cause an interrupt when the comparator output value changes. 6.22.2 Features  Analog input voltage range: 0~ V DDA  Supports Hysteresis function  Supports optional internal reference voltage input at negative end for each comparator N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 88 of 107 Rev 1.02

NUC100/120xxxDN 7 APPLICATION CIRCUIT DVCC [1] AVCC AVDD SSPPIICSLSK000 CCSLK VDD SPI Device DVCC FB MISO00 MISO Power VDD MOSI00 MOSI VSS 0.1uF 0.1uF VSS DVCC DVCC FB AVSS 4.7K 4.7K CLK I2C0SCL VDD I2C Device VDD I2C0SDA DIO SWD ICE_CLK VSS Interface ICE_DAT /RESET VSS Smart Card VCC 20p XT1_IN NUC1xx USB PORT Series VBUS 33 Crystal D+ 20p 4~24 MHz 33 crystal D- XT1_OUT VSS DVCC Reset 10K Circuit /RESET 10uF/25V PC COM Port RS232 Transceiver N RXD ROUT RIN U UART C LDO TXD TIN TOUT 1 0 0 1uF /1 LDO 2 0 Note: For the SPI device, the chip supply voltage X must be equal to SPI device working voltage. For X example, when the SPI Flash working voltage is X 3.3 V, the NUC1xx chip supply voltage must also D be 3.3V. N D A T A S H E E T Mar. 02, 2017 Page 89 of 107 Rev 1.02

NUC100/120xxxDN 8 ELECTRICAL CHARACTERISTICS 8.1 Absolute Maximum Ratings SYMBOL PARAMETER MIN. MAX UNIT DC Power Supply V V -0.3 +7.0 V DD SS Input Voltage V V -0.3 V +0.3 V IN SS DD Oscillator Frequency 1/t 4 24 MHz CLCL Operating Temperature TA -40 +85 C Storage Temperature TST -55 +150 C Maximum Current into V - 120 mA DD Maximum Current out of V 120 mA SS Maximum Current sunk by a I/O pin 35 mA Maximum Current sourced by a I/O pin 35 mA Maximum Current sunk by total I/O pins 100 mA Maximum Current sourced by total I/O pins 100 mA Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device. N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 90 of 107 Rev 1.02

NUC100/120xxxDN 8.2 DC Electrical Characteristics (V -V =5.5 V, T = 25C, F = 50 MHz unless otherwise specified.) DD SS A OSC SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT Operation Voltage V 2.5 5.5 V V = 2.5V ~ 5.5V up to 50 MHz DD DD V SS Power Ground -0.3 V AV SS LDO Output Voltage V 1.62 1.8 1.98 V V > 2.5V LDO DD When system used analog function, please refer to chapter 8.4 Analog Operating Voltage AV V V DD DD for corresponding analog operating voltage V XTAL PLL All IP DD I 34 mA DD1 5.5V 12 MHz V V Operating Current Normal Run Mode I 15 mA 5.5V 12 MHz V X DD2 at 50 MHz I 32 mA 3.3V 12 MHz V V DD3 I 14 mA 3.3V 12 MHz V X DD4 V XTAL PLL All IP DD I 8.5 mA DD5 5.5V 12 MHz X V Operating Current Normal Run Mode I 3.6 mA 5.5V 12 MHz X X N DD6 U C at 12 MHz I 7.5 mA 3.3V 12 MHz X V 1 DD7 0 0 I 2.6 mA 3.3V 12 MHz X X /1 DD8 2 0 X VDD XTAL PLL All IP X I 3.6 mA X DD9 D 5.5V 4 MHz X V Operating Current N D Normal Run Mode IDD10 2 mA 5.5V 4 MHz X X A T at 4 MHz A IDD11 2.8 mA 3.3V 4 MHz X V S H E IDD12 1.2 mA 3.3V 4 MHz X X E T V XTAL PLL All IP DD IDD13 141 A 32.768 5.5V X V Operating Current kHz Normal Run Mode 32.768 at 32.768 kHz IDD14 129 A 5.5V kHz X X 32.768 IDD15 138 A 3.3V kHz X V Mar. 02, 2017 Page 91 of 107 Rev 1.02

NUC100/120xxxDN SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT 32.768 IDD16 125 A 3.3V kHz X X V LIRC PLL All IP DD IDD17 125 A 5.5V 10 kHz X V Operating Current Normal Run Mode IDD18 120 A 5.5V 10 kHz X X at 10 kHz IDD19 125 A 3.3V 10 kHz X V IDD20 120 A 3.3V 10 kHz X X V XTAL PLL All IP DD I 28 mA IDLE1 5.5V 12 MHz V V Operating Current Idle Mode I 10 mA 5.5V 12 MHz V X IDLE2 at 50 MHz I 27 mA 3.3V 12 MHz V V IDLE3 I 9 mA 3.3V 12 MHz V X IDLE4 V XTAL PLL All IP DD I 7.5 mA IDLE5 5.5V 12 MHz X V Operating Current Idle Mode IIDLE6 2.4 mA 5.5V 12 MHz X X at 12 MHz I 6.5 mA 3.3V 12 MHz X V IDLE7 I 1.5 mA 3.3V 12 MHz X X IDLE8 N U V XTAL PLL All IP C DD I 3.3 mA 1 IDLE9 0 5.5V 4 MHz X V 0 Operating Current /1 20 Idle Mode IIDLE10 1.7 mA 5.5V 4 MHz X X X XX at 4 MHz IIDLE11 2.4 mA 3.3V 4 MHz X V D N D IIDLE12 0.8 mA 3.3V 4 MHz X X A T A VDD XTAL PLL All IP S H IIDLE13 133 A 32.768 E 5.5V X V E kHz T Operating Current 32.768 Idle Mode IIDLE14 120 A 5.5V kHz X X at 32.768 kHz 32.768 IIDLE15 133 A 3.3V kHz X V 32.768 IIDLE16 120 A 3.3V kHz X X Operating Current IIDLE13 122 A VDD LIRC PLL All IP Mar. 02, 2017 Page 92 of 107 Rev 1.02

NUC100/120xxxDN SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT Idle Mode 5.5V 10 kHz X V at 10 kHz IIDLE14 118 A 5.5V 10 kHz X X IIDLE15 122 A 3.3V 10 kHz X V IIDLE16 118 A 3.3V 10 kHz X X VDD RTC BOD function IPWD1 15 A Standby Current 5.5V X X Power-down Mode I 15 A 5.5V X X PWD2 (Deep Sleep Mode) I 17 A 3.3V X X PWD3 IPWD4 17 A 3.3V X X Input Current PA, PB, PC, PD, PE, PF (Quasi- IIN1 -50 -60 A VDD = 5.5V, VIN = 0V or VIN=VDD bidirectional mode) Input Current at /RESET[1] IIN2 -55 -45 -30 A VDD = 3.3V, VIN = 0.45V Input Leakage Current PA, PB, PC, PD, PE, PF ILK -2 - +2 A VDD = 5.5V, 0<VIN<VDD Logic 1 to 0 Transition Current PA~PF (Quasi-bidirectional ITL [3] -650 - -200 A VDD = 5.5V, VIN<2.0V mode) Input Low Voltage PA, PB, -0.3 - 0.8 VDD = 4.5V V V N PC, PD, PE, PF (TTL input) IL1 -0.3 - 0.6 VDD = 2.5V UC 1 V 0 2.0 - DD VDD = 5.5V 0 Input High Voltage PA, PB, +0.2 /1 PC, PD, PE, PF (TTL input) VIH1 V 2 V 0 1.5 - DD VDD =3.0V X +0.2 X X Input Low Voltage PA, PB, D N PC, PD, PE, PF (Schmitt VIL2 -0.3 - 0.3VDD V D input) A T Input High Voltage PA, PB, A V S PC, PD, PE, PF (Schmitt VIH2 0.7VDD - +0D.D2 V HE input) E T Hysteresis voltage of PA, PB, PC, PD,PE, PF (Schmitt VHY 0.2VDD V input) 0 - 0.8 VDD = 4.5V Input Low Voltage XT1_IN[*2] V V IL3 0 - 0.4 VDD = 3.0V V 3.5 - DD V VDD = 5.5V +0.2 Input High Voltage XT1_IN[*2] V IH3 V 2.4 - DD VDD = 3.0V +0.2 Mar. 02, 2017 Page 93 of 107 Rev 1.02

NUC100/120xxxDN SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT Input Low Voltage X32I[*2] V 0 - 0.4 v IL4 Input High Voltage X32I[*2] V 1.2 1.8 V IH4 Negative going threshold 0.2V V -0.5 - DD V (Schmitt input), /RESET ILS -0.2 Positive going threshold V V 0.7V - DD V (Schmitt input), /RESET IHS DD +0.5 ISR11 -300 -370 -450 A VDD = 4.5V, VS = 2.4V Source Current PA, PB, PC, PD, PE, PF (Quasi- ISR12 -50 -70 -90 A VDD = 2.7V, VS = 2.2V bidirectional Mode) ISR12 -40 -60 -80 A VDD = 2.5V, VS = 2.0V ISR21 -24 -28 -32 mA VDD = 4.5V, VS = 2.4V Source Current PA, PB, PC, PD, PE, PF (Push-pull Mode) ISR22 -4 -6 -8 mA VDD = 2.7V, VS = 2.2V ISR22 -3 -5 -7 mA VDD = 2.5V, VS = 2.0V ISK1 10 16 20 mA VDD = 4.5V, VS = 0.45V Sink Current PA, PB, PC, PD, PE, PF (Quasi-bidirectional ISK1 7 10 13 mA VDD = 2.7V, VS = 0.45V and Push-pull Mode) ISK1 6 9 12 mA VDD = 2.5V, VS = 0.45V Brown-out Voltage with V 2.1 2.2 2.3 V BOD_VL [1:0] = 00b BO2.2 Brown-out Voltage with V 2.6 2.7 2.8 V N BOD_VL [1:0] = 01b BO2.7 U C 1 Brown-out voltage with 0 BOD_VL [1:0] = 10b VBO3.7 3.5 3.7 3.9 V 0 /1 2 Brown-out Voltage with 0 X BOD_VL [1:0] = 11b VBO4.4 4.2 4.4 4.6 V X X D Hysteresis range of BOD N voltage VBH 30 - 150 mV VDD = 2.5V~5.5V D A TA Band-gap voltage VBG 1.175 1.20 1.225 V VDD = 2.5V - 5.5V S H Note: E E 1. /RESET pin is a Schmitt trigger input. T 2. Crystal Input is a CMOS input. 3. Pins of PA, PB, PC, PD, PE and PF can source a transition current when they are being externally driven from 1 to 0. In the condition of V = 5.5 V, the transition current reaches its maximum value when V approximates to 2 V. DD IN Mar. 02, 2017 Page 94 of 107 Rev 1.02

NUC100/120xxxDN 8.3 AC Electrical Characteristics 8.3.1 External 4~24 MHz High Speed Oscillator t CLCL t CLCH 0.7 V 90% DD t CLCX 10% 0.3 V DD t t CHCL CHCX Note: Duty cycle is 50%. SYMBOL PARAMETER CONDITION MIN. TYP. MAX. UNIT t Clock High Time 10 - - nS CHCX t Clock Low Time 10 - - nS CLCX t Clock Rise Time 2 - 15 nS CLCH t Clock Fall Time 2 - 15 nS CHCL 8.3.2 External 4~24 MHz High Speed Crystal PARAMETER CONDITION MIN. TYP.. MAX. UNIT Operation Voltage V - 2.5 - 5.5 V DD Temperature - -40 - 85 ℃ N U Operating Current 12 MHz at VDD = 5V - 1 - mA C 1 0 Clock Frequency External crystal 4 24 MHz 0 /1 2 0 X X 8.3.2.1 Typical Crystal Application Circuits X D N CRYSTAL C1 C2 R D A 4 MHz ~ 24 MHz 10~20pF 10~20pF without T A S H E E T Mar. 02, 2017 Page 95 of 107 Rev 1.02

NUC100/120xxxDN XT1_OUT XT1_IN R C2 C1 Figure 8-1 Typical Crystal Application Circuit 8.3.3 External 32.768 kHz Low Speed Crystal Oscillator PARAMETER CONDITION MIN. TYP. MAX. UNIT Operation Voltage V - 2.5 - 5.5 V DD Operation Temperature - -40 - 85 ℃ Operation Current 32.768KHz at VDD=5V 1.5 A Clock Frequency External crystal - 32.768 - kHz 8.3.4 Internal 22.1184 MHz High Speed Oscillator N U PARAMETER CONDITION MIN. TYP. MAX. UNIT C 1 0 Operation Voltage VDD - 2.5 - 5.5 V 0 /1 2 Center Frequency - - 22.1184 - MHz 0 X X +25℃; VDD =5 V -1 - +1 % X D N Calibrated Internal Oscillator Frequency -40℃~+85℃; D -3 - +3 % A V =2.5 V~5.5 V T DD A S Operation Current V =5 V - 500 - uA DD H E E T 8.3.5 Internal 10 kHz Low Speed Oscillator PARAMETER CONDITION MIN. TYP. MAX. UNIT Operation Voltage V - 2.5 - 5.5 V DD Center Frequency - - 10 - kHz Calibrated Internal Oscillator Frequency +25℃; VDD =5 V -30 - +30 % Mar. 02, 2017 Page 96 of 107 Rev 1.02

NUC100/120xxxDN -40℃~+85℃; -50 - +50 % V =2.5 V~5.5 V DD 8.4 Analog Characteristics 8.4.1 12-bit SARADC Specification SYMBOL PARAMETER MIN. TYP. MAX. UNIT - Resolution - - 12 Bit DNL Differential nonlinearity error - -1~2 -1~4 LSB INL Integral nonlinearity error - ±2 ±4 LSB EO Offset error - ±1 10 LSB EG Gain error (Transfer gain) - 1 1.005 - - Monotonic Guaranteed F ADC clock frequency (AV = 5V/3V) - - 16/8 MHz ADC DD F Sample rate - - 760 kSPS S V Supply voltage 3 - 5.5 V DDA I - 0.5 - mA DD Supply current (Avg.) I - 1.5 - mA DDA V Reference voltage 3 V V REF DDA I Reference current (Avg.) - 1 - mA N REF U C VIN Input voltage 0 - VREF V 1 0 0 /1 2 0 X 8.4.2 LDO and Power Management Specification X X D N PARAMETER MIN. TYP. MAX. UNIT NOTE D A T Input Voltage V 2.5 5.5 V V input voltage A DD DD S H E Output Voltage 1.62 1.8 1.98 V V > 2.5 V DD E T Operating Temperature -40 25 85 ℃ C - 1 - F R = 1 Ω bp ESR Note: 1. It is recommended that a 10 uF or higher capacitor and a 100 nF bypass capacitor are connected between V and the DD closest VSS pin of the device. 2. To ensure power stability, a 1 F or higher capacitor must be connected between LDO_CAP pin and the closest VSS pin of the device. Mar. 02, 2017 Page 97 of 107 Rev 1.02

NUC100/120xxxDN 8.4.3 Low Voltage Reset Specification PARAMETER CONDITION MIN. TYP. MAX. UNIT Operation Voltage - 0 - 5.5 V Quiescent Current V =5.5 V - 1 5 A DD Operation Temperature - -40 25 85 ℃ Threshold Voltage Temperature=-40~85℃ 1.7 2.0 2.3 V Hysteresis - 0 0 0 V 8.4.4 Brown-out Detector Specification PARAMETER CONDITION MIN. TYP. MAX. UNIT Operation Voltage - 0 - 5.5 V Temperature - -40 25 85 ℃ Quiescent Current AV =5.5 V - - 125 μA DD BOD_VL[1:0]=11 4.2 4.4 4.6 V BOD_VL [1:0]=10 3.5 3.7 3.9 V Brown-out Voltage BOD_VL [1:0]=01 2.6 2.7 2.8 V BOD_VL [1:0]=00 2.1 2.2 2.3 V N Hysteresis - 30 - 150 mV U C 1 0 0 /12 8.4.5 Power-on Reset Specification 0 X X X PARAMETER CONDITION MIN. TYP. MAX. UNIT D N D Operation Temperature - -40 25 85 ℃ A T A Reset Voltage V+ - 2 - V S H Quiescent Current Vin > reset voltage - 1 - nA E E T Mar. 02, 2017 Page 98 of 107 Rev 1.02

NUC100/120xxxDN 8.4.6 Temperature Sensor Specification PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Operation Voltage[1] 2.5 - 5.5 V Operation Temperature -40 - 85 ℃ Current Consumption 6.4 - 10.5 μA Gain -1.76 mV/℃ Offset Voltage Temp=0 ℃ 720 mV Note: Internal operation voltage comes from internal LDO. 8.4.7 Comparator Specification PARAMETER CONDITION MIN. TYP. MAX. UNIT Operation Voltage AV - 2.5 5.5 V DD Operation Temperature - -40 25 85 ℃ Operation Current V =3.0 V - 20 40 μA DD Input Offset Voltage - - 5 15 mV Output Swing - 0.1 - V -0.1 V DD Input Common Mode Range - 0.1 - V -0.1 V DD N DC Gain - - 70 - dB U C 1 VCM=1.2 V and 0 Propagation Delay - 200 - ns 0 VDIFF=0.1 V /1 2 0 20 mV at VCM=1 V X X 50 mV at VCM=0.1 V X D Comparison Voltage 10 20 - mV N 50 mV at VCM=VDD-1.2 D A 10 mV for non-hysteresis T A S H Hysteresis VCM=0.4 V ~ V -1.2 V - ±10 - mV DD E E T CINP=1.3 V Stable Time - - 2 μs CINN=1.2 V Mar. 02, 2017 Page 99 of 107 Rev 1.02

NUC100/120xxxDN 8.4.8 USB PHY Specification 8.4.8.1 USB DC Electrical Characteristics SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V Input High (driven) 2.0 V IH V Input Low 0.8 V IL V Differential Input Sensitivity |PADP-PADM| 0.2 V DI Differential V Includes V range 0.8 2.5 V CM DI Common-mode Range V Single-ended Receiver Threshold 0.8 2.0 V SE Receiver Hysteresis 200 mV V Output Low (driven) 0 0.3 V OL V Output High (driven) 2.8 3.6 V OH V Output Signal Cross Voltage 1.3 2.0 V CRS R Pull-up Resistor 1.425 1.575 kΩ PU Termination Voltage for Upstream V 3.0 3.6 V TRM Port Pull-up (RPU) Z Driver Output Resistance Steady state drive* 10 Ω DRV C Transceiver Capacitance Pin to GND 20 pF IN *Driver output resistance doesn’t include series resistor resistance. N U 8.4.8.2 USB Full-Speed Driver Electrical Characteristics C 1 0 0 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT /1 2 0X TFR Rise Time CL=50p 4 20 ns X X TFF Fall Time CL=50p 4 20 ns D N D TFRFF Rise and Fall Time Matching TFRFF=TFR/TFF 90 111.11 % A T A S H 8.4.8.3 USB Power Dissipation E E T SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VBUS Current I Standby 50 μA VBUS (Steady State) Mar. 02, 2017 Page 100 of 107 Rev 1.02

NUC100/120xxxDN 8.4.8.4 USB LDO Specification SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V VBUS Pin Input Voltage 4.0 5.0 5.5 V BUS V LDO Output Voltage 3.0 3.3 3.6 V DD33 C External Bypass Capacitor 1.0 - uF bp N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 101 of 107 Rev 1.02

NUC100/120xxxDN 8.5 Flash DC Electrical Characteristics SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V Supply Voltage 1.62 1.8 1.98 V[1] DD T Data Retention At 85℃ 10 year RET T Page Erase Time 2 ms ERASE T Mass Erase Time 10 ms MER T Program Time 20 μs PROG mA/MH I Read Current - 0.15 0.5 DD1 z I Program/Erase Current 7 mA DD2 I Power Down Current - 1 20 μA PD 1. V is source from chip LDO output voltage. DD 2. This table is guaranteed by design, not test in production. N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 102 of 107 Rev 1.02

NUC100/120xxxDN 9 PACKAGE DIMENSIONS 9.1 100-pin LQFP (14x14x1.4 mm footprint 2.0 mm) H D D A A2 7 51 A1 5 7 50 6 H E E 100 26 L1 L 1 25 e b c  Y Controlling Dimension : Millimeters Dimension in inch Dimension in mm Symbol Min Nom Max Min Nom Max A 0.063 1.60 N U A1 0.002 0.05 C 1 A 0.053 0.055 0.057 1.35 1.40 1.45 0 2 0 b 0.007 0.009 0.011 0.17 0.22 0.27 /1 c 0.004 0.006 0.008 0.10 0.15 0.20 20 D 0.547 0.551 0.556 13.90 14.00 14.10 XX E 0.547 0.551 0.556 13.90 14.00 14.10 XD e 0.020 0.50 N HD 0.622 0.630 0.638 15.80 16.00 16.20 D A HE 0.622 0.630 0.638 15.80 16.00 16.20 TA L 0.018 0.024 0.030 0.45 0.60 0.75 S H L1 0.039 1.00 E y E 0.004 0.10 T  0 7 0 7 Mar. 02, 2017 Page 103 of 107 Rev 1.02

NUC100/120xxxDN 9.2 64-pin LQFP (10x10x1.4 mm footprint 2.0 mm) N U C Dimension in inch Dimension in mm Symbol 1 0 Min Nom Max Min Nom Max 0 /1 A 0.063 1.60 2 0 A1 0.002 0.006 0.05 0.15 X X A2 0.053 0.055 0.057 1.35 1.40 1.45 X D b 0.007 0.008 0.011 0.17 0.20 0.27 N D c 0.004 0.008 0.09 0.20 A T D 0.393 10.00 A S E 0.393 10.00 H E e 0.020 0.50 E T HD 0.472 12.00 HE 0.472 12.00 L 0.018 0.024 0.030 0.45 0.60 0.75 L1 0.039 1.00 y 0.004 0.10 0 0 3.5 7 0 3.5 7 Mar. 02, 2017 Page 104 of 107 Rev 1.02

NUC100/120xxxDN 9.3 48-pin LQFP (7x7x1.4 mm footprint 2.0 mm) H 36 25 37 24 H 48 13 12 1  N U C Controlling dimension : Millimeters 10 0 Symbol Dimension in inch Dimension in mm /12 Min Nom Max Min Nom Max 0 X A X X A1 0.002 0.004 0.006 0.05 0.10 0.15 D A2 0.053 0.055 0.057 1.35 1.40 1.45 N b 0.006 0.008 0.010 0.15 0.20 0.25 D A c 0.004 0.006 0.008 0.10 0.15 0.20 T A D 0.272 0.276 0.280 6.90 7.00 7.10 S H E 0.272 0.276 0.280 6.90 7.00 7.10 E e 0.014 0.020 0.026 0.35 0.50 0.65 E T HD 0.350 0.354 0.358 8.90 9.00 9.10 HE 0.350 0.354 0.358 8.90 9.00 9.10 L 0.018 0.024 0.030 0.45 0.60 0.75 L1 0.039 1.00 Y 0.004 0.10 0 0 7 0 7 Mar. 02, 2017 Page 105 of 107 Rev 1.02

NUC100/120xxxDN 10 REVISION HISTORY Date Revision Description 2014.05.13 1.00 1. Preliminary version. 1. Reorganized the chapter sequence. 2. Added a note in all clock source block diagrams of all peripheral sections that “Before clock switching, both the pre-selected and newly selected 2015.08.31 1.01 clock sources must be turned on and stable.” 3. Revised package size of 64-pin LQFP (10x10x1.4 mm footprint 2.0 mm) in section 9.2. 1. Updated section 4.1 NuMicro® NUC100/120xxxDN Selection Guide. 2017.03.02 1.02 2. Updated Low Voltage Reset Specification in section 8.4.3. 3. Updated Comparator Specification in section 8.4.7. N U C 1 0 0 /1 2 0 X X X D N D A T A S H E E T Mar. 02, 2017 Page 106 of 107 Rev 1.02

NUC100/120xxxDN N U C 1 0 0 /1 2 0 X Important Notice X X D Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any N malfunction or failure of which may cause loss of human life, bodily injury or severe property D A damage. Such applications are deemed, “Insecure Usage”. T A S Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic H energy control instruments, airplane or spaceship instruments, the control or operation of E E dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all T types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. Mar. 02, 2017 Page 107 of 107 Rev 1.02