NTMD5836NL Power MOSFET 40 V, Dual N−Channel, SOIC−8 Features • Asymmetrical N Channels http://onsemi.com • Low R DS(on) • Low Capacitance N−Channel 1 N−Channel 2 • Optimized Gate Charge D1 D2 • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant G1 G2 ID Max V(BR)DSS RDS(on) Max (Notes 1 and 2) Channel 1 40 V 12 m(cid:2) @ 10 V 11 A S1 S2 16 m(cid:2) @ 4.5 V Channel 2 40 V 20 m(cid:2) @ 10 V 6.5 A MARKING DIAGRAM* 36.5 m(cid:2) @ 4.5 V AND PIN ASSIGNMENT 1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in D1 D1 D2D2 sq [2 oz] including traces) 8 8 2. Only selected channel is been powered 1W applied on channel 1: TJ = 1 W * 85°C/W + 25°C = 110°C 1 5836NL SOIC−8 AYWW(cid:2) (cid:2) CASE 751 1 S1 G1 S2G2 A = Assembly Location Y = Year WW = Work Week (cid:2) = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping† NTMD5836NLR2G SOIC−8 2500 / (Pb−Free) Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D © Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: February, 2012 − Rev. 1 NTMD5836NL/D

NTMD5836NL MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter Symbol Ch 1 Ch 2 Unit Drain−to−Source Voltage VDSS 40 40 V Gate−to−Source Voltage VGS (cid:2)20 (cid:2)20 V Continuous Drain Current RθJA (Notes 3 and 4) Steady TA = 25°C ID 9.0 5.7 A State TA = 70°C 7.2 4.6 Power Dissipation RθJA (Notes 3 and 4) TA = 25°C PD 1.5 1.5 W TA = 70°C 0.9 0.9 Continuous Drain Current RθJA (Notes 3 and 4) t (cid:3) 10s TA = 25°C ID 11 6.5 A TA = 70°C 8.6 4.6 Power Dissipation RθJA (Notes 3 and 4) TA = 25°C PD 2.1 1.9 W TA = 70°C 1.3 1.2 Pulsed Drain Current tp = 10 (cid:3)s IDM 43 26 A Operating Junction and Storage Temperature TJ, TSTG −55 to +150 °C Source Current (Body Diode) IS 10 7.0 A Single Pulse Drain−to−Source Avalanche Energy (VDD = 40 V, VGS = 10 V, L = 0.1 mH(cid:4) EAS 76 22 mJ IAS 39 21 A Lead Temperature for Soldering Purposes (1/8” from case for 10s) TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces) 4. Only selected channel is been powered 1W applied on channel 1: TJ = 1 W * 85°C/W + 25°C = 110°C THERMAL RESISTANCE RATINGS Parameter Symbol Ch 1 Ch 2 Unit Junction−to−Ambient Steady State (Notes 5 and 7) RθJA 85 86 °C/W Junction−to−Ambient – t (cid:3) 10 s (Notes 5 and 7) RθJA 60 65 Junction−to−Ambient Steady State (Notes 5 and 8) RθJA 59 Junction−to−Ambient Steady State (Notes 6 and 7) RθJA 136 136 5. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces) 6. Surface−mounted on FR4 board using 0.155 in sq (100 mm2) pad size 7. Only selected channel is been powered 1W applied on channel 1: TJ = 1 W * 85°C/W + 25°C = 110°C 8. Both channels receive equivalent power dissipation 1 W applied on each channel: TJ = 2 W * 59°C/W + 25°C = 143°C http://onsemi.com 2

NTMD5836NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Ch Min Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown V(BR)DSS Ch 1 40 V Voltage VGS = 0 V, ID = 250 (cid:3)A Ch 2 Drain−to−Source Breakdown V(BR)DSS Ch 1 146 mV/ Voltage Temperature Coefficient / TJ °C Ch 2 25 Zero Gate Voltage Drain Current IDSS Ch 1 1.0 (cid:3)A TJ = 25°C Ch 2 VGS = 0 V, VDS = 40 V Ch 1 100 TJ = 125°C Ch 2 Gate−to−Source Leakage Current IGSS Ch 1 (cid:2)100 nA VDS = 0 V, VGS = (cid:2)20 V Ch 2 ON CHARACTERISTICS (Note 9) Gate Threshold Voltage VGS(TH) Ch 1 1.0 1.8 3.0 V VGS = VDS, ID = 250 (cid:3)A Ch 2 1.0 1.8 3.0 Negative Threshold Temperature VGS(TH) / Ch 1 6.0 mV/°C Coefficient TJ Ch 2 6.0 Drain−to−Source On Resistance RDS(on) VGS = 10 V, ID = 10 A Ch 1 9.5 12 m(cid:2) VGS = 10 V, ID = 7 A Ch 2 16.2 20 VGS = 4.5 V, ID = 10 A Ch 1 13 16 m(cid:2) VGS = 4.5 V, ID = 7 A Ch 2 25.0 36.5 Forward Transconductance gFS VDS = 15 V, ID = 10 A Ch 1 10.5 S VDS = 15 V, ID = 7 A Ch 2 6.0 CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Ch 1 2120 pF Ch 2 730 Output Capacitance COSS VGS = 0 V, f = 1 MHz, VDS = Ch 1 315 20 V Ch 2 123 Reverse Transfer Capacitance CRSS Ch 1 225 Ch 2 84 9. Pulse Test: pulse width (cid:3) 300 (cid:3)s, duty cycle (cid:3) 2% 10.Switching characteristics are independent of operating junction temperatures http://onsemi.com 3

NTMD5836NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Ch Min Typ Max Unit CHARGES, CAPACITANCES & GATE RESISTANCE Total Gate Charge QG(TOT) VGS = 10V, VDS = 20V, ID = 10A Ch 1 36 50 nC VGS = 10 V, VDS = 20 V, ID = 7 A Ch 2 16 Ch 1 15 23 Ch 2 8.5 11 Threshold Gate Charge QG(TH) Ch 1 2.4 Ch 2 1.0 Gate−to−Source Charge QGS VGS = 4.5 V, VDS = 20 V, CH1: Ch 1 6.9 ID = 10 A, CH2: ID = 7 A Ch 2 2.8 Gate−to−Drain Charge QGD Ch 1 7.2 Ch 2 4.0 Plateau Voltage VGP Ch 1 3.2 V Ch 2 3.3 Gate Resistance RG Ch 1 1.2 (cid:2) Ch 2 2.1 SWITCHING CHARACTERISTICS (Note 10) Turn−On Delay Time td(ON) Ch 1 16 ns Ch 2 11.5 Rise Time tr Ch 1 22 VGS = 4.5 V, VDD = 20 V, CH1: Ch 2 14 ID = 10 A, CH2: ID = 7 A, RG = Turn−Off Delay Time td(OFF) 2.5 (cid:2) Ch 1 26 Ch 2 15.5 Fall Time tf Ch 1 8.5 Ch 2 3.5 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Ch 1 0.9 1.2 V VGS = 0 V, TJ = 25°C Ch 2 0.85 1.2 CH1: ID = 10 A, CH2: ID Ch 1 0.65 = 7 A TJ = 125°C Ch 2 0.73 Reverse Recovery Time tRR Ch 1 27 ns Ch 2 17 Charge Time Ta Ch 1 14 VGS = 0 V, dISD/dt = 100 A/(cid:3)s, Ch 2 11 Discharge Time Tb CH1: ID = 10 A, CH2: ID = 7 A Ch 1 13 Ch 2 6.0 Reverse Recovery Charge QRR Ch 1 19 nC Ch 2 9.0 9. Pulse Test: pulse width (cid:3) 300 (cid:3)s, duty cycle (cid:3) 2% 10.Switching characteristics are independent of operating junction temperatures http://onsemi.com 4

NTMD5836NL TYPICAL PERFORMANCE CURVES 70 70 10V 5.5 V TJ = 25°C VDS ≥ 20 V 60 6.5 V 60 3.9 V A) 8.5 V A) T ( 50 T ( 50 N N E E R 40 4.5 V R 40 R R U 3.5 V U N C 30 N C 30 TJ = 125°C AI AI R R D D, 20 3.1 V D D, 20 TJ = 25°C I I 10 10 TJ = −55°C 0 VGS = 2.5 V 0 0 1 2 3 4 5 2 3 4 5 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics − Figure 2. Transfer Characteristics − Channel 1 Channel 1 (cid:2)) (cid:2)) E ( 0.035 E ( 0.02 NC TJ = 25°C NC TJ = 25°C TA ID = 10 A TA S 0.03 S SI SI E E R R 0.015 CE 0.025 CE VGS = 4.5 V R R U U O O S 0.02 S VGS = 10 V − − O O 0.01 T T − − N N AI 0.015 AI R R D D n), n), o 0.01 o0.005 DS( 2 3 4 5 6 7 8 9 10 DS( 2 6 10 14 18 R R VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and Voltage − Channel 1 Gate Voltage − Channel 1 1.6 100000 ID = 10 A VGS = 0 V ED) VGS = 4.5 V CE RZ 1.4 DRAIN−TO−SOU S(on),SISTANCE (NORMALI 1.21 I, LEAKAGE (nA)DSS10000 TTJJ = = 1 15205°°CC DE RR 0.8 1000 −50 −25 0 25 50 75 100 125 150 10 20 30 40 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current Temperature − Channel 1 vs. Voltage − Channel 1 http://onsemi.com 5

NTMD5836NL TYPICAL PERFORMANCE CURVES 3000 10 TJ = 25°C QT 2500 VGS = 0 V V) V) pF) Ciss CE ( 8 CE ( E (2000 UR UR C O 6 O N S S TA1500 O− O− CI T T C, CAPA1050000 Coss V, GATE−GS 24 QGS QGD VIDG =S 1=0 2 A0 V V, DRAIN−DS Crss TJ = 25°C 0 0 0 10 20 30 40 0 5 10 15 20 25 30 35 40 DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation − Channel 1 Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge − Channel 1 1000 20 VDD = 20 V VGS = 0 V ID = 10 A A) TJ = 25°C VGS = 4.5 V T ( 15 N s) tr RE n R TIME ( 100 CE CU 10 t, R U O td(off) tf td(on) , SS 5 I 10 0 1 10 100 0.4 0.5 0.6 0.7 0.8 0.9 1 RG, GATE RESISTANCE ((cid:2)) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Figure 10. Diode Forward Voltage vs. Current Variation vs. Gate Resistance − Channel 1 − Channel 1 100 80 −mJ) ID = 39 A T (A) 10 1 (cid:3)s AIN−TOERGY ( 60 N RN RE 1 10 (cid:3)s E DE E UR 100 (cid:3)s LSCH 40 I, DRAIN CD00.0.11 VSTCGIN S=G =2L 52E°0 CP VULSREDS(on) LIMIT d1 cms S, SINGLE PURCE AVALAN 20 THERMAL LIMIT AU EO PACKAGE LIMIT S 0.001 0 0.1 1 10 100 25 50 75 100 125 150 VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy vs. Safe Operating Area − Channel 1 Starting Junction Temperature − Channel 1 http://onsemi.com 6

NTMD5836NL TYPICAL PERFORMANCE CURVES 50 50 10V 6.5 V VDS ≥ 5 V 4.5 V 8.5 V A) 40 5.5 V A) 40 T ( 4 V T ( N N RE 30 RE 30 R R U U C 3.6 V C AIN 20 AIN 20 TJ = 125°C R R D D, 10 D D, 10 TJ = 25°C I VGS = 3 V I TJ = −55°C TJ = 25°C 0 0 0 1 2 3 4 5 2 3 4 5 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics − Figure 2. Transfer Characteristics − Channel 2 Channel 2 (cid:2)) (cid:2)) E ( 0.05 E ( 0.03 NC TJ = 25°C NC TJ = 25°C STA ID = 7 A STA VGS = 4.5 V SI 0.04 SI E E R R 0.025 E E C C R R U 0.03 U O O S S − − O O 0.02 N−T 0.02 N−T VGS = 10 V AI AI R R D D on), 0.01 on),0.015 DS( 2 3 4 5 6 7 8 9 10 DS( 2 6 10 14 18 R R VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and Voltage − Channel 2 Gate Voltage − Channel 2 1.6 100000 VGS = 4.5 V VGS = 0 V CEED)1.4 ID = 7 A RZ DRAIN−TO−SOU S(on),SISTANCE (NORMALI01..821 I, LEAKAGE (nA)DSS101000000 TTJJ == 112550°°CC DE RR 0.6 100 −50 −25 0 25 50 75 100 125 150 5 15 25 35 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current Temperature − Channel 2 vs. Voltage − Channel 2 http://onsemi.com 7

NTMD5836NL TYPICAL PERFORMANCE CURVES 1200 10 TJ = 25°C QT F) 1000 VGS = 0 V E (V) 8 E (V) p C C CITANCE ( 680000 Ciss TO−SOUR 6 TO−SOUR PA E− 4 QGS QGD N− A 400 T AI C A R C, 200 Coss V, GGS 2 VIDD =S 7= A20 V V, DDS 0 Crss 0 TJ = 25°C 0 10 20 30 40 0 5 10 15 VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation − Channel 2 Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge 1000 VDD = 20 V 12 VGS = 0 V ID = 7 A A) TJ = 25°C VGS = 4.5 V T ( 10 N s) 100 tr RE 8 TIME (n td(off) CE CUR 6 t, 10 td(on) UR 4 O S tf I, S 2 1 0 1 10 100 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 RG, GATE RESISTANCE ((cid:2)) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Figure 10. Diode Forward Voltage vs. Current Variation vs. Gate Resistance − Channel 2 − Channel 2 E 100 C 20 R OU ID = 21 A CURRENT (A) 101 11 0(cid:3) (cid:3)ss E DRAIN−TO−SE ENERGY (mJ)1105 , DRAIN D 00.0.11 VSTCGIN S=G =2L 52E°0 CP VULSE dc 110 0m (cid:3)ss GLE PULSVALANCH 5 I RDS(on) LIMIT NA THERMAL LIMIT SI PACKAGE LIMIT S, 0.001 A 0 E 0.1 1 10 100 25 50 75 100 125 150 VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy vs. Safe Operating Area − Channel 2 Starting Junction Temperature http://onsemi.com 8

NTMD5836NL TYPICAL PERFORMANCE CURVES 100 D = 0.5 0.2 10 0.1 W) 0.05 °C/ 1 0.02 R(t) ( 0.01 0.1 SINGLE PULSE 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 t, PULSE TIME (s) Figure 13. Thermal Response http://onsemi.com 9

NTMD5836NL PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK NOTES: −X− 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. A 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) 8 5 PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL 1 IN EXCESS OF THE D DIMENSION AT −Y− 4 K 6. M75A1X−I0M1U TMH RMUA T7E51R−IA0L6 CAROEN DOIBTSIOONL.ETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.80 5.00 0.189 0.197 C NX 45(cid:3) B 3.80 4.00 0.150 0.157 SEATING C 1.35 1.75 0.053 0.069 PLANE D 0.33 0.51 0.013 0.020 −Z− G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 0.10 (0.004) J 0.19 0.25 0.007 0.010 H D M J K 0.40 1.27 0.016 0.050 M 0 (cid:3) 8 (cid:3) 0 (cid:3) 8 (cid:3) N 0.25 0.50 0.010 0.020 0.25 (0.010)M Z Y S X S SOLDERING FOOTPRINT* S 5.80 6.20 0.228 0.244 1.52 0.060 7.0 4.0 0.275 0.155 0.6 1.270 0.024 0.050 (cid:4) (cid:5) mm SCALE 6:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com NTMD5836NL/D 10