NTD4963N Power MOSFET 30 V, 44 A, Single N−Channel, DPAK/IPAK Features • Low R to Minimize Conduction Losses DS(on) • Low Capacitance to Minimize Driver Losses • http://onsemi.com Optimized Gate Charge to Minimize Switching Losses • Three Package Variations for Design Flexibility • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS V(BR)DSS RDS(ON) MAX ID MAX Compliant 9.6 m(cid:4) @ 10 V 30 V 44 A Applications 16 m(cid:4) @ 4.5 V • CPU Power Delivery D • DC−DC Converters • Recommended for High Side (Control) MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) G Parameter Symbol Value Unit Drain−to−Source Voltage VDSS 30 V S Gate−to−Source Voltage VGS ±20 V N−CHANNEL MOSFET Continuous Drain TA = 25°C ID 10.0 A 4 4 C(Nuortree n1t) R(cid:2)JA TA = 85°C 7.2 4 Power Dissipation TA = 25°C PD 1.64 W R(cid:2)JA (Note 1) 1 2 1 Continuous Drain TA = 25°C ID 8.1 A 3 2 3 12 C(Nuortree n2t) R(cid:2)JA Steady TA = 85°C 5.8 CASE 369AA CASE 369AC CASE3 369D Power Dissipation State TA = 25°C PD 1.1 W (BeDnPt ALKead) (Stra3i gIPhAt KLead) (StraIiPgAhtK Lead R(cid:2)JA (Note 2) STYLE 2 DPAK) Continuous Drain TC = 25°C ID 44 A C(Nuortree n1t) R(cid:2)JC TC = 85°C 32 MARKING DIAGRAMS & PIN ASSIGNMENTS Power Dissipation TC = 25°C PD 35.7 W 4 R(cid:2)JC (Note 1) Drain Pulsed Drain tp=10(cid:3)s TA = 25°C IDM 132 A Dr4ain Dr4ain Current W G W9N COTeupmrerrpeaentritn aLgtium Jreuitencdt iboyn Paancdk Sagtoerage TA = 25°C IDTmTSaJTx,PGkg −+531557 t5o °AC AYWW4963NG AYWW4963NG AY463 Source Current (Body Diode) IS 30 A 2 Drain to Source dV/dt dV/dt 6.0 V/ns 1Drain 3 1 2 3 GateDrainSource Single Pulse Drain−to−Source Avalanche EAS 33.8 mJ Gate Source 1 2 3 Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, GateDrainSource IL = 26 Apk, L = 0.1 mH, RG = 25 (cid:4)(cid:5) Lead Temperature for Soldering Purposes TL 260 °C A = Assembly Location (1/8” from case for 10 s) Y = Year WW = Work Week Stresses exceeding Maximum Ratings may damage the device. Maximum 4963N = Device Code Ratings are stress ratings only. Functional operation above the Recommended G = Pb−Free Package Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. © Semiconductor Components Industries, LLC, 2013 1 Publication Order Number: October, 2013 − Rev. 3 NTD4963N/D

NTD4963N THERMAL RESISTANCE MAXIMUM RATINGS Parameter Symbol Value Unit Junction−to−Case (Drain) R(cid:2)JC 4.1 °C/W Junction−to−TAB (Drain) R(cid:2)JC−TAB 3.5 Junction−to−Ambient – Steady State (Note 3) R(cid:2)JA 77 Junction−to−Ambient – Steady State (Note 4) R(cid:2)JA 118 3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu. 4. Surface−mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 (cid:3)A 30 V Drain−to−Source Breakdown Voltage V(BR)DSS/ 25 mV/°C Temperature Coefficient TJ Zero Gate Voltage Drain Current IDSS VGS = 0 V, TJ = 25°C 1.0 VDS = 24 V TJ = 125°C 10 (cid:3)A Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±20 V ±100 nA ON CHARACTERISTICS (Note 5) Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250 (cid:3)A 1.45 2.5 V Negative Threshold Temperature VGS(TH)/TJ 5 mV/°C Coefficient Drain−to−Source On Resistance RDS(on) VGS = 10 V ID = 30 A 8.2 9.6 ID = 15 A 8.2 m(cid:4) VGS = 4.5 V ID = 30 A 13.6 16 ID = 15 A 13.6 Forward Transconductance gFS VDS = 1.5 V, ID = 30 A 40 S CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance CISS 1035 Output Capacitance COSS VGS = 0 V, f = 1.0 MHz, VDS = 12 V 220 pF Reverse Transfer Capacitance CRSS 115 Total Gate Charge QG(TOT) 8.1 Threshold Gate Charge QG(TH) 1.2 VGS = 4.5 V, VDS = 15 V, ID = 30 A nC Gate−to−Source Charge QGS 3.5 Gate−to−Drain Charge QGD 3.5 Total Gate Charge QG(TOT) VGS = 10 V, VDS = 15 V, ID = 30 A 16.2 nC SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time td(ON) 12 RTuisren −TOimff eDelay Time td(OtrFF) VGIDS = = 1 45. 5A V, ,R VGD =S 3=. 01 5(cid:4) V, 2104 ns Fall Time tf 3 5. Pulse Test: pulse width (cid:2) 300 (cid:3)s, duty cycle (cid:2) 2%. 6. Switching characteristics are independent of operating junction temperatures. 7. Assume terminal length of 110 mils. http://onsemi.com 2

NTD4963N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time td(ON) 7.0 RTuisren −TOimff eDelay Time td(OtrFF) VGIDS == 1115. 5A ,V R, GV D=S 3 =.0 1 (cid:4)5 V, 1270 ns Fall Time tf 2 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD VGS = 0 V, TJ = 25°C 0.96 1.2 V IS = 30 A TJ = 125°C 0.83 Reverse Recovery Time tRR 17 Charge Time ta VGS = 0 V, dIS/dt = 100 A/(cid:3)s, 9 ns Discharge Time tb IS = 30 A 8 Reverse Recovery Charge QRR 6 nC PACKAGE PARASITIC VALUES Source Inductance (Note 7) LS 2.49 nH Drain Inductance, DPAK LD 0.0164 Drain Inductance, IPAK (Note 7) LD TA = 25°C 1.88 Gate Inductance (Note 7) LG 3.46 Gate Resistance RG 1.0 (cid:4) 5. Pulse Test: pulse width (cid:2) 300 (cid:3)s, duty cycle (cid:2) 2%. 6. Switching characteristics are independent of operating junction temperatures. 7. Assume terminal length of 110 mils. ORDERING INFORMATION Device Package Shipping† NTD4963NT4G DPAK 2500 / Tape & Reel (Pb−Free, Halide−Free) NTD4963N−1G IPAK 75 Units / Rail (Pb−Free, Halide−Free) NTD4963N−35G IPAK Trimmed Lead 75 Units / Rail (Pb−Free, Halide−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 3

NTD4963N TYPICAL PERFORMANCE CURVES 60 60 4.6 V thru 10 V VGS = 4.4 V VDS = 10 V A) 50 TJ = 25°C 4.2 V A) 50 T ( T ( N 40 4.0 V N 40 E E R R R R U 30 3.8 V U 30 C C AIN 3.6 V AIN TJ = 25°C R 20 R 20 D D , D 3.4 V , D I 10 I 10 23..82 VV TJ = 125°C TJ = −55°C 0 0 0 1 2 3 4 5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics (cid:4)) (cid:4)) CE ( 2E−02 CE (20E−03 ESISTAN1111....6879EEEE−−−−00002222 ITDJ == 3205 °AC ESISTAN15E−03 TJ = 25°C VGS = 4.5 V R R E 1.5E−02 E RC1.4E−02 RC U1.3E−02 U SO1.2E−02 SO10E−03 VGS = 10 V O−1.1E−02 O− RAIN−T1.089EEE−−−000332 RAIN−T 5E−03 D 7E−03 D , DS(on) 56EE−−00333 4 5 6 7 8 9 10, DS(on) 0E+0010 15 20 25 30 35 40 45 50 R R VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and D) Voltage Gate Voltage E Z LI A 1.8 10,000 RM VGS = 0 V TJ = 150°C NO 1.6 ID = 30 A CE ( VGS = 10 V A) 1,000 TJ = 125°C STAN 1.4 GE (n 100 RESI 1.2 EAKA E L 10 URC 1.0 , DSS TJ = 25°C O I S 1 − 0.8 O T − N 0.6 0.1 AI −50 −25 0 25 50 75 100 125 150 5 10 15 20 25 30 R D , n) TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) o S( Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current D R Temperature vs. Voltage http://onsemi.com 4

NTD4963N TYPICAL PERFORMANCE CURVES 1200 V) 10 Ciss VGS = 0 V TJ = 25°C E ( 9 QT G 1000 A F) LT 8 p O CE ( 800 E V 7 N C 6 A R CIT 600 OU 5 Qgs Qgd C, CAPA 400 Coss ATE−TO−S 423 ITDJ == 3205 °AC 200 Crss , GGS 1 VVDGDS == 1350 VA 0 V 0 0 5 10 15 20 25 30 0 2 4 6 8 10 12 14 16 18 QG, TOTAL GATE CHARGE (nC) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 8. Gate−to−Source and Drain−to−Source Figure 7. Capacitance Variation Voltage vs. Total Charge 1000 30 VDD = 15 V VGS = 0 V IVDG =S 1=5 1 A1.5 V NT (A) 25 TJ = 25°C s) 100 td(off) RRE 20 ME (n tr E CU 15 TI C t, UR 10 O 10 td(on) S , S I 5 tf 1 0 1 10 100 0.4 0.5 0.6 0.7 0.8 0.9 1.0 RG, GATE RESISTANCE ((cid:4)) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Figure 10. Diode Forward Voltage vs. Current Variation vs. Gate Resistance 1000 35 E VSiGnSg l=e 3P0u lVse RC ID = 26 A T (A) 100 TC = 25°C 10 (cid:3)s −SOUmJ) 30 EN 100 (cid:3)s TOY ( 25 URR 10 1 ms AIN−ERG 20 C RN N 10 ms DE AI 1 E E 15 R SH I, DD 0.1 RDS(on) LIMIT E PULLANC 10 LA THERMAL LIMIT dc NGAV 5 PACKAGE LIMIT SI 0.01 , S 0 0.1 1 10 100 A 25 50 75 100 125 150 E VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy vs. Safe Operating Area Starting Junction Temperature http://onsemi.com 5

NTD4963N PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA ISSUE B NOTES: C 1.DIMENSIONING AND TOLERANCING PER ASME A Y14.5M, 1994. E A 2.CONTROLLING DIMENSION: INCHES. 3.THERMAL PAD CONTOUR OPTIONAL WITHIN DI- MENSIONS b3, L3 and Z. b3 B c2 4.DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. L3 4 Z 5.DOIUMTEENRSMIOONSST DE XATNRDE ME EASR EO FD ETTHEER PMLIANSETDIC A TB OTHDEY. D H 6.DATUMS A AND B ARE DETERMINED AT DATUM 1 2 3 DETAIL A PLANE H. INCHES MILLIMETERS DIM MIN MAX MIN MAX L4 A 0.086 0.094 2.18 2.38 b2 A1 0.000 0.005 0.00 0.13 b c b 0.025 0.035 0.63 0.89 b2 0.030 0.045 0.76 1.14 e 0.005 (0.13) M C H b3 0.180 0.215 4.57 5.46 c 0.018 0.024 0.46 0.61 L2 GPLAAUNGEE C SPELAATNIENG cD2 00..203158 00..204254 50..9476 60..2621 E 0.250 0.265 6.35 6.73 e 0.090 BSC 2.29 BSC H 0.370 0.410 9.40 10.41 L A1 L 0.055 0.070 1.40 1.78 L1 L1 0.108 REF 2.74 REF L2 0.020 BSC 0.51 BSC DETAIL A L3 0.035 0.050 0.89 1.27 ROTATED 90(cid:2) CW L4 −−− 0.040 −−− 1.01 Z 0.155 −−− 3.93 −−− STYLE 2: SOLDERING FOOTPRINT* PIN 1.GATE 2.DRAIN 6.20 3.00 3.SOURCE 4.DRAIN 0.244 0.118 2.58 0.102 5.80 1.60 6.17 0.228 0.063 0.243 (cid:3) (cid:4) mm SCALE 3:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6

NTD4963N PACKAGE DIMENSIONS 3 IPAK, STRAIGHT LEAD CASE 369AC ISSUE O NOTES: 1..DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. B C 2..CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. V R E 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. INCHES MILLIMETERS DIM MIN MAX MIN MAX A A 0.235 0.245 5.97 6.22 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 SEATING PLANE D 0.027 0.035 0.69 0.88 W K EF 00..001387 00..002433 00..4964 01..5089 F G 0.090 BSC 2.29 BSC J H 0.034 0.040 0.87 1.01 G J 0.018 0.023 0.46 0.58 H K 0.134 0.142 3.40 3.60 D3 PL RV 00..108305 00..201550 40..5879 51..4267 0.13 (0.005) W W 0.000 0.010 0.000 0.25 IPAK (STRAIGHT LEAD DPAK) CASE 369D ISSUE C B C NOTES: 1. DIMENSIONING AND TOLERANCING PER V R E ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MILLIMETERS 4 Z DIM MIN MAX MIN MAX A 0.235 0.245 5.97 6.35 A S B 0.250 0.265 6.35 6.73 1 2 3 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.46 0.58 −T− F 0.037 0.045 0.94 1.14 SEATING G 0.090 BSC 2.29 BSC PLANE K H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.350 0.380 8.89 9.65 R 0.180 0.215 4.45 5.45 F J S 0.025 0.040 0.63 1.01 H V 0.035 0.050 0.89 1.27 Z 0.155 −−− 3.93 −−− D 3 PL STYLE 2: G 0.13 (0.005) M T PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com NTD4963N/D 7