NTD4858N Power MOSFET 25 V, 73 A, Single N−Channel, DPAK/IPAK Features • Trench Technology • Low RDS(on) to Minimize Conduction Losses http://onsemi.com • Low Capacitance to Minimize Driver Losses • Optimized Gate Charge to Minimize Switching Losses V(BR)DSS RDS(ON) MAX ID MAX • These are Pb−Free Devices 6.2 m(cid:4) @ 10 V 25 V 73 A Applications 9.3 m(cid:4) @ 4.5 V • VCORE Applications • D DC−DC Converters • High/Low Side Switching N−CHANNEL MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) G Parameter Symbol Value Unit S Drain−to−Source Voltage VDSS 25 V Gate−to−Source Voltage VGS ±20 V 4 4 Continuous Drain TA = 25°C ID 14 A C(Nuortree n1t) R(cid:2)JA TA = 85°C 10.9 4 PRo(cid:2)JwAe (rN Doitses i1p)ation TA = 25°C PD 2.0 W 1 2 3 1 2 3 123 Continuous Drain TA = 25°C ID 11.2 A DPAK IPAK IPAK C(Nuortree n2t) R(cid:2)JA Steady TA = 85°C 8.7 C(BAeSnEt 3L6e9aAdA) (SCtAraSiEgh 3t6 L9eAaDd) (SCtrAaSigEh 3t 6L9eDad State Power Dissipation TA = 25°C PD 1.3 W STYLE 2 STYLE 2 DPAK) STYLE 2 R(cid:2)JA (Note 2) Continuous Drain TC = 25°C ID 73 A MARKING DIAGRAMS C(Nuortree n1t) R(cid:2)JC TC = 85°C 56 & PIN ASSIGNMENTS 4 Drain PRo(cid:2)JwCe (rN Doitses i1p)ation TC = 25°C PD 54.5 W Dr4ain Dr4ain W G PCCuuulrrsrreeendnt t DLrimainited by Pactkpa=g1e0(cid:3)s TTAA == 2255°°CC IDmIDaxMPkg 14456 AA AYWW4858NG AYWW4858NG AYW4858N Operating Junction and Storage TJ, −55 to °C Temperature TSTG +175 2 Source Current (Body Diode) IS 45 A Ga1teDraiSnou3rce Gat1eDr2ain3Source 1 2 3 Drain to Source dV/dt dV/dt 6 V/ns GateDrainSource Single Pulse Drain−to−Source Avalanche EAS 112.5 mJ Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, A = Assembly Location* IL = 15 Apk, L = 1.0 mH, RG = 25 (cid:4)(cid:5) Y = Year WW = Work Week Lead Temperature for Soldering Purposes TL 260 °C 4858N = Device Code (1/8” from case for 10 s) G = Pb−Free Package Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be * The Assembly Location code (A) is front side assumed, damage may occur and reliability may be affected. optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: June, 2014 − Rev. 3 NTD4858N/D

NTD4858N THERMAL RESISTANCE MAXIMUM RATINGS Parameter Symbol Value Unit Junction−to−Case (Drain) R(cid:2)JC 2.75 °C/W Junction−to−TAB (Drain) R(cid:2)JC−TAB 3.5 Junction−to−Ambient – Steady State (Note 1) R(cid:2)JA 73.5 Junction−to−Ambient – Steady State (Note 2) R(cid:2)JA 116 1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 (cid:3)A 25 V Drain−to−Source Breakdown Voltage V(BR)DSS/ 22 mV/°C Temperature Coefficient TJ Zero Gate Voltage Drain Current IDSS VGS = 0 V, TJ = 25°C 1.0 VDS = 20 V TJ = 125°C 10 (cid:3)A Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±20 V ±100 nA ON CHARACTERISTICS (Note 3) Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250 (cid:3)A 1.45 2.5 V Negative Threshold Temperature VGS(TH)/TJ 5.3 mV/°C Coefficient Drain−to−Source On Resistance RDS(on) VGS = 10 V ID = 30 A 5.2 6.2 m(cid:4) VGS = 4.5 V ID = 30 A 7.3 9.3 Forward Transconductance gFS VDS = 1.5 V, ID = 15 A 55 S CHARGES AND CAPACITANCES Input Capacitance CISS 1563 Output Capacitance COSS VGS = 0 V, f = 1.0 MHz, VDS = 12 V 405 pF Reverse Transfer Capacitance CRSS 200 Total Gate Charge QG(TOT) 12.8 19.2 Threshold Gate Charge QG(TH) 1.3 VGS = 4.5 V, VDS = 15 V, ID = 30 A nC Gate−to−Source Charge QGS 4.7 Gate−to−Drain Charge QGD 5.2 Total Gate Charge QG(TOT) VGS = 10 V, VDS = 15 V, ID = 30 A 25.7 nC SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time td(ON) 12.6 RTuisren −TOimff eDelay Time td(OtrFF) VGIDS = = 1 45. 5A V, ,R VGD =S 3=. 01 5(cid:4) V, 2106..24 ns Fall Time tf 5.1 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: pulse width (cid:2) 300 (cid:3)s, duty cycle (cid:2) 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2

NTD4858N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) (continued) Parameter Symbol Test Condition Min Typ Max Unit SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time td(ON) 7.7 RTuisren −TOimff eDelay Time td(OtrFF) VGIDS == 1115. 5A ,V R, GV D=S 3 =.0 1 (cid:4)5 V, 1273..38 ns Fall Time tf 2.8 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD VGS = 0 V, TJ = 25°C 0.87 1.2 V IS = 30 A TJ = 125°C 0.73 Reverse Recovery Time tRR 11.6 Charge Time ta VGS = 0 V, dIS/dt = 100 A/(cid:3)s, 7.8 ns Discharge Time tb IS = 30 A 3.7 Reverse Recovery Charge QRR 3.0 nC PACKAGE PARASITIC VALUES Source Inductance LS 2.49 nH Drain Inductance, DPAK LD 0.0164 Drain Inductance, IPAK LD TA = 25°C 1.88 Gate Inductance LG 3.46 Gate Resistance RG 0.7 (cid:4) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: pulse width (cid:2) 300 (cid:3)s, duty cycle (cid:2) 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3

NTD4858N TYPICAL PERFORMANCE CURVES 90 90 10 V 3.8 V TJ = 25°C VDS ≥ 10 V 80 80 S) 4 V S) P 70 3.6 V P 70 M M A A T ( 60 T ( 60 N 3.4 V N E 50 E 50 R R R R U 40 U 40 C 3.2 V C N 30 N 30 RAI RAI TJ = 125°C D 20 3.0 V D 20 I, D 10 2.8 V I, D 10 TJ = 25°C TJ = −55°C 0 0 0 1 2 3 4 5 1 2 3 4 5 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics (cid:4)) (cid:4)) E (0.040 E ( 0.010 C C STAN0.035 TIDJ == 3205 °AC STAN 0.009 TJ = 25°C ESI0.030 ESI 0.008 VGS = 4.5 V R R CE 0.025 CE 0.007 R R OU0.020 OU 0.006 O−S0.015 O−S 0.005 VGS = 11.5 V T T − − N0.010 N 0.004 AI AI R R D0.005 D 0.003 , DS(on) 02 3 4 5 6 7 8 9 10 11, DS(on)0.00210 20 30 40 50 60 70 80 90 R R VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and Voltage Gate Voltage 1.8 10000 E NC ID = 30 A VGS = 0 V A ST 1.6 VGS = 10 V 1000 TJ = 150°C ESI A) −TO−SOURCE RNORMALIZED) 111...024 , LEAKAGE (nDSS 11000 TJ = 125°C AIN( 0.8 I 1 TJ = 25°C R D , on) 0.6 0.1 S( −50 −25 0 25 50 75 100 125 150 175 5 10 15 20 25 D R TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current Temperature vs. Drain Voltage http://onsemi.com 4

NTD4858N TYPICAL PERFORMANCE CURVES 2000 10 1800 Ciss VTGJ S= =2 50° VC OLTS) QT 1600 V 8 F) E ( NCE (p 11240000 OLTAG 6 VGS A V APACIT 1080000 Coss URCE 4 Q1 Q2 C 600 O C, −S 400 TO 2 ID = 30 A 200 Crss ATE− VTJD D= =2 51°5C V 0 G 0 0 2.5 5 7.5 10 12.5 15 17.5 20 , S 0 4 8 12 16 20 24 28 DRAIN−TO−SOURCE VOLTAGE (VOLTS) VG QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge 1000 30 VDD = 15 V VGS = 0 V ID = 30 A PS) 25 TJ = 25°C VGS = 11.5 V M s) 100 ttdf(off) ENT (A 20 E (n tr RR 15 M U t, TI 10 td(on) RCE C 10 U O , SS 5 I 1 0 1 10 100 0.5 0.6 0.7 0.8 0.9 RG, GATE RESISTANCE (OHMS) VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Figure 10. Diode Forward Voltage vs. Current Variation vs. Gate Resistance 1000 120 E MPS) OURC 100 ID = 15 A URRENT (A 11000 1100 0(cid:3) s(cid:3)s RAIN−TO−SNERGY (mJ) 6800 DRAIN C 1 VSTCGIN S=G =2L 52E°0 CP VU LSE 11d 0cm mss PULSE DNCHE E 40 I, D RTHDSE(RonM) ALILM LITIMIT GLE VALA 20 NA PACKAGE LIMIT SI 0.10.1 1 10 100 S, 025 50 75 100 125 150 175 A VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) E TJ, JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy vs. Safe Operating Area Starting Junction Temperature http://onsemi.com 5

NTD4858N TYPICAL PERFORMANCE CURVES E C N TA 1.0 S D = 0.5 SI E R L A 0.2 RMD) NSIENT THE(NORMALIZE 0.1 000..0.0125 0.01 P(pk) RDPU (cid:2)CJLCUS(RtE) V =TE RrS(At )A IRNP(cid:2) PSJCLHYO FWONR POWER RA SINGLE PULSE t1 READ TIME AT t1 E T t2 TJ(pk) − TC = P(pk) R(cid:2)JC(t) V DUTY CYCLE, D = t1/t2 TI C 0.01 FE 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 EF t, TIME ((cid:3)s) r(t), Figure 13. Thermal Response ORDERING INFORMATION Device Package Shipping† NTD4858NT4G DPAK 2500 / Tape & Reel (Pb−Free) NTD4858N−1G IPAK 75 Units / Rail (Pb−Free) NTD4858N−35G IPAK Trimmed Lead 75 Units / Rail (3.5 ± 0.15 mm) (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6

NTD4858N PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA ISSUE B NOTES: C 1.DIMENSIONING AND TOLERANCING PER ASME A Y14.5M, 1994. E A 2.CONTROLLING DIMENSION: INCHES. 3.THERMAL PAD CONTOUR OPTIONAL WITHIN DI- MENSIONS b3, L3 and Z. b3 B c2 4.DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. L3 4 D Z 5.DOIUMTEENRSMIOONSST DE XATNRDE ME EASR EO FD ETTHEER PMLIANSETDIC A TB OTHDEY. H 6.DATUMS A AND B ARE DETERMINED AT DATUM 1 2 3 DETAIL A PLANE H. INCHES MILLIMETERS DIM MIN MAX MIN MAX L4 A 0.086 0.094 2.18 2.38 b2 A1 0.000 0.005 0.00 0.13 b c b 0.025 0.035 0.63 0.89 b2 0.030 0.045 0.76 1.14 e 0.005 (0.13) M C H b3 0.180 0.215 4.57 5.46 c 0.018 0.024 0.46 0.61 L2 GPLAAUNGEE C SPELAATNIENG cD2 00..203158 00..204254 50..9476 60..2621 E 0.250 0.265 6.35 6.73 e 0.090 BSC 2.29 BSC H 0.370 0.410 9.40 10.41 L A1 L 0.055 0.070 1.40 1.78 L1 L1 0.108 REF 2.74 REF L2 0.020 BSC 0.51 BSC DETAIL A L3 0.035 0.050 0.89 1.27 ROTATED 90(cid:2) CW L4 −−− 0.040 −−− 1.01 Z 0.155 −−− 3.93 −−− STYLE 2: SOLDERING FOOTPRINT* PIN 1.GATE 2.DRAIN 6.20 3.00 3.SOURCE 4.DRAIN 0.244 0.118 2.58 0.102 5.80 1.60 6.17 0.228 0.063 0.243 (cid:3) (cid:4) mm SCALE 3:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7

NTD4858N PACKAGE DIMENSIONS 3.5 MM IPAK, STRAIGHT LEAD CASE 369AD ISSUE B E A NOTES: 1..DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. L2 E3 A1 E2 2..CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. D2 4. DIMENSIONS D AND E DO NOT INCLUDE D MOLD GATE OR MOLD FLASH. L1 MILLIMETERS DIM MIN MAX A 2.19 2.38 L A1 0.46 0.60 T A2 0.87 1.10 SEATING b 0.69 0.89 PLANE b1 A1 b1 0.77 1.10 E2 D 5.97 6.22 2X e A2 D2 4.80 −−− E 6.35 6.73 3X b E2 4.57 5.45 D2 0.13 M T E3 4.45 5.46 e 2.28 BSC L 3.40 3.60 L1 −−− 2.10 L2 0.89 1.27 STYLE 2: PIN 1. GATE OPTIONAL 2. DRAIN CONSTRUCTION 3. SOURCE 4. DRAIN http://onsemi.com 8

NTD4858N PACKAGE DIMENSIONS IPAK CASE 369D ISSUE C B C NOTES: 1. DIMENSIONING AND TOLERANCING PER V R E ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MILLIMETERS 4 Z DIM MIN MAX MIN MAX A 0.235 0.245 5.97 6.35 A S B 0.250 0.265 6.35 6.73 1 2 3 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.46 0.58 −T− F 0.037 0.045 0.94 1.14 SEATING G 0.090 BSC 2.29 BSC PLANE K H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.350 0.380 8.89 9.65 R 0.180 0.215 4.45 5.45 F J S 0.025 0.040 0.63 1.01 H V 0.035 0.050 0.89 1.27 Z 0.155 −−− 3.93 −−− D 3 PL G 0.13 (0.005) M T STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com NTD4858N/D 9

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