NTD18N06L, NTDV18N06L Power MOSFET 18 A, 60 V, Logic Level N−Channel DPAK Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. www.onsemi.com Features • AEC Q101 Qualified − NTDV18N06L V(BR)DSS RDS(on) TYP ID MAX • These Devices are Pb−Free and are RoHS Compliant 60 V 54 m(cid:2)(cid:5)5.0 V 18 A (Note 1) Typical Applications • Power Supplies D • Converters • Power Motor Controls • N−Channel Bridge Circuits G MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) S Rating Symbol Value Unit 4 Drain−to−Source Voltage VDSS 60 Vdc Drain−to−Gate Voltage (RGS = 10 M(cid:2)) VDGR 60 Vdc 1 2 Gate−to−Source Voltage Vdc 3 − Continuous VGS ±15 − Non−repetitive (tp(cid:2)10 ms) VGS ±20 DPAK CASE 369C Drain Current STYLE 2 − Continuous @ TA = 25°C ID 18 Adc − Continuous @ TA = 100°C ID 10 − Single Pulse (tp(cid:2)10 (cid:3)s) IDM 54 Apk MARKING DIAGRAM & PIN ASSIGNMENT Total Power Dissipation @ TA = 25°C PD 55 W Derate above 25°C 0.36 W/°C Total Power Dissipation @ TA = 25°C (Note 2) 2.1 W 4 Operating and Storage Temperature Range TJ, Tstg −55 to °C Drain +175 W SinEgnlee rPgyu l−se S Dtarratiinng− tTo−J S=o 2u5r°cCe Avalanche EAS 72 mJ AYW18N6LG (VDD = 50 Vdc, VGS = 5.0 Vdc, L = 1.0 mH, IL(pk) = 12 A, VDS = 60 Vdc) 2 Thermal Resistance °C/W 1 3 Drain − Junction−to−Case R(cid:4)JC 2.73 Gate Source − Junction−to−Ambient (Note 1) R(cid:4)JA 100 − Junction−to−Ambient (Note 2) R(cid:4)JA 71.4 A = Assembly Location* Maximum Lead Temperature for Soldering TL 260 °C 18N6L = Device Code Purposes, 1/8″ from case for 10 seconds Y = Year WW = Work Week Stresses exceeding those listed in the Maximum Ratings table may damage the G = Pb−Free Device device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. * The Assembly Location code (A) is front side 1. When surface mounted to an FR−4 board using the minimum recommended optional. In cases where the Assembly Location is pad size. stamped in the package, the front side assembly 2. When surface mounted to an FR−4 board using the 0.5 sq in drain pad size. code may be blank. ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: November, 2018 − Rev. 8 NTD18N06L/D

NTD18N06L, NTDV18N06L ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Note 3) V(BR)DSS Vdc (VGS = 0 Vdc, ID = 250 (cid:3)Adc) 60 70 − Temperature Coefficient (Positive) − 57.6 − mV/°C Zero Gate Voltage Drain Current IDSS (cid:3)Adc (VDS = 60 Vdc, VGS = 0 Vdc) − − 1.0 (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) − − 10 Gate−Body Leakage Current (VGS = ±15 Vdc, VDS = 0 Vdc) IGSS − − ±100 nAdc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) VGS(th) Vdc (VDS = VGS, ID = 250 (cid:3)Adc) 1.0 1.8 2.0 Threshold Temperature Coefficient (Negative) − 5.2 − mV/°C Static Drain−to−Source On−Resistance (Note 3) RDS(on) m(cid:2) (VGS = 5.0 Vdc, ID = 9.0 Adc) − 54 65 Static Drain−to−Source On−Resistance (Note 3) VDS(on) Vdc (VGS = 5.0 Vdc, ID = 18 Adc) − 1.0 1.3 (VGS = 5.0 Vdc, ID = 9.0 Adc, TJ = 150°C) − 0.86 − Forward Transconductance (Note 3) (VDS = 7.0 Vdc, ID = 9.0 Adc) gFS − 13.5 − mhos DYNAMIC CHARACTERISTICS Input Capacitance Ciss − 482 675 pF Output Capacitance (VDS = 2f5 = V 1d.c0, MVHGSz) = 0 Vdc, Coss − 166 230 Transfer Capacitance Crss − 56 80 SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time td(on) − 9.9 20 ns Rise Time (VDD = 30 Vdc, ID = 18 Adc, tr − 79 160 VGS = 5.0 Vdc, Turn−Off Delay Time RG = 9.1 (cid:2)) (Note 3) td(off) − 19 40 Fall Time tf − 38 80 Gate Charge QT − 11 22 nC (VVDGS S= = 4 85 .V0 dVcd, cID) (=N o1t8e A3d)c, Q1 − 3.2 − Q2 − 6.5 − SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 18 Adc, VGS = 0 Vdc) (Note 3) VSD − 0.94 1.15 Vdc (IS = 18 Adc, VGS = 0 Vdc, TJ = 150°C) − 0.83 − Reverse Recovery Time trr − 41 − ns d(IISS /=d t1 =8 1A0d0c ,A V/(cid:3)GsS) =(N 0o tVed 3c), ta − 26 − tb − 15 − Reverse Recovery Stored Charge QRR − 0.057 − (cid:3)C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: Pulse Width ≤300 (cid:3)s, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. ORDERING INFORMATION Device Package Shipping† NTD18N06LT4G DPAK 2500 / Tape & Reel (Pb−Free) NTDV18N06LT4G DPAK 2500 / Tape & Reel (Pb−Free) STD18N06LT4G−VF01 DPAK 2500 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 2

NTD18N06L, NTDV18N06L 40 40 VGS = 10 V 5.5 V 5 V VDS ≥ 10 V S) S) P 8 V P M 30 M 30 A A T ( 6 V 4.5 V T ( N N E E R R R 20 4 V R 20 U U C C N N AI 3.5 V AI DR 10 DR 10 TJ = 25°C I, D 3 V I, D TJ = 100°C TJ = −55°C 0 0 0 1 2 3 4 1.6 2.4 3.2 4 4.8 5.6 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics (cid:2)) (cid:2)) NCE ( 0.12 VGS = 5 V NCE ( 0.12 SISTA 0.1 TJ = 100°C SISTA 0.1 VGS = 10 V E E E R 0.08 E R 0.08 OURC 0.06 TJ = 25°C OURC 0.06 TJ = 100°C TO−S 0.04 TJ = −55°C TO−S 0.04 TJ = 25°C AIN− AIN− TJ = −55°C R 0.02 R 0.02 D D , DS(on) 00 10 20 30 40 , DS(on) 00 10 20 30 40 R R ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Figure 4. On−Resistance versus Drain Current Gate−to−Source Voltage and Gate Voltage CE 2 10000 N ID = 9 A VGS = 0 V A SIST 1.8 VGS = 5 V TJ = 150°C RE 1.6 A)1000 RCE ZED)1.4 GE (n N−TO−SOU(NORMALI1.12 , LEAKADSS 11000 TJ = 100°C AI I R D 0.8 , n) o S( 0.6 1 RD −50 −25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current Temperature versus Voltage www.onsemi.com 3

NTD18N06L, NTDV18N06L POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted The capacitance (C ) is read from the capacitance curve at iss by recognizing that the power MOSFET is charge a voltage corresponding to the off−state condition when controlled. The lengths of various switching intervals ((cid:6)t) calculating t and is read at a voltage corresponding to the d(on) are determined by how fast the FET input capacitance can on−state when calculating t . d(off) be charged by current from the generator. At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET The published capacitance data is difficult to use for source lead, inside the package and in the circuit wiring calculating rise and fall because drain−gate capacitance which is common to both the drain and gate current paths, varies greatly with applied voltage. Accordingly, gate produces a voltage at the source which reduces the gate drive charge data is used. In most cases, a satisfactory estimate of current. The voltage is determined by Ldi/dt, but since di/dt average input current (I ) can be made from a G(AV) is a function of drain current, the mathematical solution is rudimentary analysis of the drive circuit so that complex. The MOSFET output capacitance also t = Q/I G(AV) complicates the mathematics. And finally, MOSFETs have During the rise and fall time interval when switching a finite internal gate resistance which effectively adds to the resistive load, V remains virtually constant at a level resistance of the driving source, but the internal resistance GS known as the plateau voltage, V . Therefore, rise and fall is difficult to measure and, consequently, is not specified. SGP times may be approximated by the following: The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching t = Q x R /(V − V ) r 2 G GG GSP performance is affected by the parasitic circuit elements. If t = Q x R /V f 2 G GSP the parasitics were not present, the slope of the curves would where maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize V = the gate drive voltage, which varies from zero to V GG GG common inductance in the drain and gate circuit loops and R = the gate drive resistance G is believed readily achievable with board mounted and Q2 and VGSP are read from the gate charge curve. components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which During the turn−on and turn−off delay times, gate current is approximates an optimally snubbed inductive load. Power not constant. The simplest calculation uses appropriate MOSFETs may be safely operated into an inductive load; values from the capacitance curves in a standard equation for however, snubbing reduces switching losses. voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] t = R C In (V /V ) d(off) G iss GG GSP 1400 Ciss TJ = 25°C 1200 VDS = 0 V VGS = 0 V F) p1000 E ( C N 800 Crss A T CI PA 600 Ciss A C C, 400 Coss 200 0 Crss 10 5 0 5 10 15 20 25 VGS VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation www.onsemi.com 4

NTD18N06L, NTDV18N06L S) 8 1000 T L O V E ( 6 G LTA QT VGS s) 100 tr E VO 4 Q1 Q2 ME (n tf URC t, TI td(off) SO 10 td(on) O− 2 VDS = 30 V −T ID = 18 A ID = 18 A TE TJ = 25°C VGS = 5 V GA 0 1 , S 0 2 4 6 8 10 12 1 10 100 VG QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE ((cid:2)) Figure 8. Gate−To−Source and Drain−To−Source Figure 9. Resistive Switching Time Voltage versus Total Charge Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS 20 PS) VTJG =S =2 50° CV M 16 A T ( N E 12 R R U C E 8 C R U O S 4 , S I 0 0.6 0.68 0.76 0.84 0.92 1 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define reliable operation, the stored energy from circuit inductance the maximum simultaneous drain−to−source voltage and dissipated in the transistor while in avalanche must be less drain current that a transistor can handle safely when it is than the rated limit and adjusted for operating conditions forward biased. Curves are based upon maximum peak differing from those specified. Although industry practice is junction temperature and a case temperature (T ) of 25°C. to rate in terms of energy, avalanche energy capability is not C Peak repetitive pulsed power limits are determined by using a constant. The energy rating decreases non−linearly with an the thermal response data in conjunction with the procedures increase of peak current in avalanche and peak junction discussed in AN569, “Transient Thermal Resistance − temperature. General Data and Its Use.” Although many E−FETs can withstand the stress of Switching between the off−state and the on−state may drain−to−source avalanche at currents up to rated pulsed traverse any load line provided neither rated peak current current (I ), the energy rating is specified at rated DM (I ) nor rated voltage (V ) is exceeded and the continuous current (I ), in accordance with industry custom. DM DSS D transition time (t,t) do not exceed 10 (cid:3)s. In addition the total The energy rating must be derated for temperature as shown r f power averaged over a complete switching cycle must not in the accompanying graph (Figure 12). Maximum energy at exceed (TJ(MAX) − TC)/(R(cid:4)JC). currents below rated continuous ID can safely be assumed to A Power MOSFET designated E−FET can be safely used equal the values indicated. in switching circuits with unclamped inductive loads. For www.onsemi.com 5

NTD18N06L, NTDV18N06L SAFE OPERATING AREA 100 E 80 C PS) VSGINSG =L 1E5 P VU LSE 10 (cid:3)s OUR ID = 12 A T (AM 10 TC = 25°C TO−SmJ) 60 EN 100 (cid:3)s N−Y ( R AIG UR 1 ms DRER 40 C E N RAIN 1 10 ms dc PULSCHE E , DD RDS(on) LIMIT LE AN 20 I THERMAL LIMIT NGAL PACKAGE LIMIT SIAV 0.1 , S 0 0.1 1 10 100 A 25 50 75 100 125 150 175 E VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus Safe Operating Area Starting Junction Temperature E C N A T S 1.0 ESI D = 0.5 R L A RMD) 0.2 THELIZE 0.1 NSIENT (NORMA 0.1 00..0025 P(pk) RD (cid:4)CJCU(Rt) V=E rS(t )A RP(cid:4)PJCLY FOR POWER A PULSE TRAIN SHOWN R 0.01 VE T SINGLE PULSE t1 t2 RTJE(pAkD) − T TIMC E= APT(p tk1) R(cid:4)JC(t) CTI DUTY CYCLE, D = t1/t2 FE 0.01 F 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 E r(t), t, TIME ((cid:3)s) Figure 13. Thermal Response di/dt IS trr ta tb TIME tp 0.25 IS IS Figure 14. Diode Reverse Recovery Waveform www.onsemi.com 6

NTD18N06L, NTDV18N06L PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F NOTES: A 1.DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. E C 2.CONTROLLING DIMENSION: INCHES. A 3.THERMAL PAD CONTOUR OPTIONAL WITHIN DI- b3 B MENSIONS b3, L3 and Z. c2 4.DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL 4 NOT EXCEED 0.006 INCHES PER SIDE. L3 Z 5.DIMENSIONS D AND E ARE DETERMINED AT THE D DETAIL A H 6.DOAUTTUEMRSM OA SATN EDX BT RAERME EDSE OTEFR TMHIEN EPDLA ASTT DICA TBUOMDY. 1 2 3 PLANE H. 7.OPTIONAL MOLD FEATURE. L4 INCHES MILLIMETERS NOTE 7 b2 c BOTTOM VIEW DIM MIN MAX MIN MAX A 0.086 0.094 2.18 2.38 e SIDE VIEW A1 0.000 0.005 0.00 0.13 b b 0.025 0.035 0.63 0.89 0.005 (0.13) M C b2 0.028 0.045 0.72 1.14 TOP VIEW b3 0.180 0.215 4.57 5.46 c 0.018 0.024 0.46 0.61 c2 0.018 0.024 0.46 0.61 H Z Z D 0.235 0.245 5.97 6.22 E 0.250 0.265 6.35 6.73 e 0.090 BSC 2.29 BSC L2 GPLAAUNGEE C SPELAATNIENG HL 00..035750 00..047100 19..4400 101..4718 L1 0.114 REF 2.90 REF L2 0.020 BSC 0.51 BSC L A1 BOTTOM VIEW L3 0.035 0.050 0.89 1.27 L1 ALTERNATE L4 −−− 0.040 −−− 1.01 CONSTRUCTIONS Z 0.155 −−− 3.93 −−− DETAIL A ROTATED 90(cid:2) CW STYLE 2: SOLDERING FOOTPRINT* PIN 1.GATE 2.DRAIN 3.SOURCE 6.20 3.00 4.DRAIN 0.244 0.118 2.58 0.102 5.80 1.60 6.17 0.228 0.063 0.243 (cid:3) (cid:4) mm SCALE 3:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative ◊ www.onsemi.com NTD18N06L/D 7

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