NLAS7242 High-Speed USB 2.0 (480 Mbps) DPDT Switches The NLAS7242 is a DPDT switch optimized for high−speed USB 2.0 applications within portable systems. It features ultra−low on capacitance, C = 7.5 pF (typ), and a bandwidth above 950 MHz. It ON is optimized for applications that use a single USB interface connector hhttttpp::////oonnsseemmii..ccoomm to route multiple signal types. The C and R of both channels are ON ON suitably low to allow the NLAS7242 to pass any speed USB data or MARKING audio signals going to a moderately resistive terminal such as an DIAGRAM external headset. The device is offered in a UQFN10 1.4 mm x 1.8 mm package. Features UQFN10 AD M(cid:2) • CASE 488AT (cid:2) Optimized Flow−Through Pinout 1 • R : 5.0 (cid:2) Typ @ V = 4.2 V ON CC • CON: 7.5 pF Typ @ VCC = 3.3 V AD = Device Code • V Range: 1.65 V to 4.5 V M = Date Code CC • (cid:2) = Pb−Free Device Typical Bandwidth: 950 MHz • (Note: Microdot may be in either location) 1.4 mm x 1.8 mm x 0.50 mm UQFN10 • OVT on Common Signal Pins D+/D− up to 5.25 V • 8 kV HBM ESD Protection on All Pins • ORDERING INFORMATION This is a Pb−Free Device Device Package Shipping† Typical Applications • NLAS7242MUTBG UQFN0 3000/Tape & Reel High Speed USB 2.0 Data (Pb−Free) • Mobile Phones • †For information on tape and reel specifications, Portable Devices including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. NLAS7242 HS USB XCVR R O T C E N N O FS USB C XCVR or B S AUDIO U AMP Figure 1. Application Diagram © Semiconductor Components Industries, LLC, 2009 1 Publication Order Number: August, 2009 − Rev. 4 NLAS7242/D

NLAS7242 HSD2+ HSD2− 7 6 OE 8 5 HSD1+ VCC 9 4 HSD1− CONTROL S 10 3 GND 1 2 D+ D− Figure 2. Pin Connections and Logic Diagram (Top View) Table 1. PIN DESCRIPTION Table 2. TRUTH TABLE Pin Function HSD1+, HSD2+, OE S HSD1− HSD2− S Control Input OE Output Enable 1 X OFF OFF 0 0 ON OFF HSD1+, HSD1−, HSD2+, Data Ports 0 1 OFF ON HSD2−, D+, D− MAXIMUM RATINGS Symbol Pins Parameter Value Unit VCC VCC Positive DC Supply Voltage −0.5 to +5.5 V VIS HSDn+, Analog Signal Voltage −0.5 to VCC + 0.3 V HSDn− D+, D− −0.5 to +5.25 VIN S, OE Control Input Voltage, Output Enable Voltage −0.5 to +5.5 V ICC VCC Positive DC Supply Current 50 mA TS Storage Temperature −65 to +150 °C IIS_CON HSDn+, Analog Signal Continuous Current−Closed Switch (cid:2)300 mA HSDn−, D+, D− IIS_PK HSDn+, Analog Signal Continuous Current 10% Duty Cycle (cid:2)500 mA HSDn−, D+, D− IIN S, OE Control Input Current, Output Enable Current (cid:2)20 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol Pins Parameter Min Max Unit VCC Positive DC Supply Voltage 1.65 4.5 V VIS HSDn+, Analog Signal Voltage GND VCC V HSDn− D+, D− GND 4.5 VIN S, OE Control Input Voltage, Output Enable Voltage GND VCC V TA Operating Temperature −40 +85 °C Minimum and maximum values are guaranteed through test or design across the Recommended Operating Conditions, where applicable. Typical values are listed for guidance only and are based on the particular conditions listed for section, where applicable. These conditions are valid for all values found in the characteristics tables unless otherwise specified in the test conditions. ESD PROTECTION Symbol Parameter Value Unit ESD Human Body Model − All Pins 8.0 kV http://onsemi.com 2

NLAS7242 DC ELECTRICAL CHARACTERISTICS CONTROL INPUT, OUTPUT ENABLE VOLTAGE (Typical: T = 25°C) −40°C to +85°C Symbol Pins Parameter Test Conditions VCC (V) Min Typ Max Unit VIH S, OE Control Input, Output 2.7 1.25 − − V Enable HIGH Voltage 3.3 1.3 (See Figure 11) 4.2 1.4 VIL S, OE Control Input, Output 2.7 − − 0.35 V Enable LOW Voltage 3.3 0.4 (See Figure 11) 4.2 0.5 IIN S, OE Current Input, Output 0 ≤ VIS ≤ VCC 1.65 − 4.5 − − ±1.0 (cid:3)A Enable Leakage Current SUPPLY CURRENT AND LEAKAGE (Typical: T = 25°C, VCC = 3.3 V) −40°C to +85°C Symbol Pins Parameter Test Conditions VCC (V) Min Typ Max Unit ICC VCC Quiescent Supply Current 0 ≤ VIS ≤ VCC; ID = 0 A 1.65 − 3.6 − − 1.0 (cid:3)A 0 ≤ VIS ≤ VCC − 0.5 V 3.6 − 4.5 − − 1.0 IOZ OFF State Leakage 0 ≤ VIS ≤ VCC 1.65 − 4.5 − ±0.1 ±1.0 (cid:3)A IOFF D+, D− Power OFF Leakage 0 ≤ VIS ≤ VCC 0 − − ±1.0 (cid:3)A Current LIMITED VIS SWING ON RESISTANCE (Typical: T = 25°C) −40°C to +85°C Symbol Pins Parameter Test Conditions VCC (V) Min Typ Max Unit RON On−Resistance (Note 1) ION = 8 mA 2.7 − 6.0 8.6 (cid:2) VIS = 0 V to 0.4 V 3.3 5.5 7.6 4.2 5.0 7.0 RFLAT On−Resistance Flatness ION = 8 mA 2.7 − 0.55 − (cid:2) (Notes 1 and 2) VIS = 0 V to 0.4 V 3.3 0.30 4.2 0.20 (cid:4)RON On−Resistance Matching ION = 8 mA 2.7 − 0.60 − (cid:2) (Notes 1 and 3) VIS = 0 V to 0.4 V 3.3 0.60 4.2 0.60 1. Guaranteed by design. 2. Flatness is defined as the difference between the maximum and minimum value of On−Resistance as measured over the specified analog signal ranges. 3. (cid:4)RON = RON(max) − RON(min) between HSD1+ and HSD1− or HSD2+ and HSD2−. FULL VIS SWING ON RESISTANCE (Typical: T = 25°C) −40°C to +85°C Symbol Pins Parameter Test Conditions VCC (V) Min Typ Max Unit RON On−Resistance ION = 8 mA 2.7 − 10 13.5 (cid:2) VIS = 0 V to VCC 3.3 8.0 9.75 4.2 7.0 8.50 RFLAT On−Resistance Flatness ION = 8 mA 2.7 − 4.5 − (cid:2) (Notes 4 and 5) VIS = 0 V to VCC 3.3 3.0 4.2 2.5 (cid:4)RON On−Resistance ION = 8 mA 2.7 − 0.60 − (cid:2) (Note 4 and 6) VIS = 0 V to VCC 3.3 0.60 4.2 0.60 4. Guaranteed by design. 5. Flatness is defined as the difference between the maximum and minimum value of On−Resistance as measured over the specified analog signal ranges. 6. (cid:4)RON = RON(max) − RON(min) between HSD1+ and HSD1− or HSD2+ and HSD2−. http://onsemi.com 3

NLAS7242 AC ELECTRICAL CHARACTERISTICS TIMING/FREQUENCY (Typical: T = 25°C, VCC = 3.3 V, RL = 50 (cid:2), CL = 35 pF, f = 1 MHz) −40(cid:2)C to +85(cid:2)C Symbol Pins Parameter Test Conditions VCC (V) Min Typ Max Unit tON Closed to Open Turn−ON Time 1.65 − 4.5 − 13.0 30.0 ns (See Figures 4 and 5) tOFF Open to Closed Turn−OFF Time 1.65 − 4.5 − 12.0 25.0 ns (See Figures 4 and 5) TBBM Break−Before−Make 1.65 − 4.5 2.0 − − ns Time (See Figure 3) BW −3 dB Bandwidth CL = 5 pF 1.65 − 4.5 − 950 − MHz (See Figure 10) ISOLATION (Typical: T = 25°C, VCC = 3.3 V, RL = 50 (cid:2), CL = 5 pF) −40(cid:2)C to +85(cid:2)C Symbol Pins Parameter Test Conditions VCC (V) Min Typ Max Unit OIRR Open OFF−Isolation f = 240 MHz 1.65 − 4.5 − −22 − dB (See Figure 6) XTALK HSDn+ to HSDn− Non−Adjacent Channel f = 240 MHz 1.65 − 4.5 − −24 − dB Crosstalk CAPACITANCE (Typical: T = 25°C, VCC = 3.3 V, RL = 50 (cid:2), CL = 5 pF) −40(cid:2)C to +85(cid:2)C Symbol Pins Parameter Test Conditions Min Typ Max Unit CIN S, OE Control Pin, Output Enable VCC = 0 V, f = 1 MHz − 1.5 − pF Input Capacitance VCC = 0 V, f = 10 MHz − 1.0 − CON D+ to ON Capacitance VCC = 3.3 V; OE = 0 V, f = 1 MHz − 7.5 − HSD1+ or S = 0 V or 3.3 V HSD2+ VCC = 3.3 V; OE = 0 V, f = 10 MHz − 6.5 − S = 0 V or 3.3 V COFF HSD1n or OFF Capacitance VCC = VIS = 3.3 V; − 3.8 − HSD2n OE = 0 V, S = 3.3 V or 0 V, f = 1 MHz VCC = VIS = 3.3 V; − 2.0 − OE = 0 V, S = 3.3 V or 0 V, f = 10 MHz http://onsemi.com 4

NLAS7242 DUT VCC VCC Output Input 0.1 (cid:3)F VOUT GND 50 (cid:2) 35 pF tBMM Output 50 % OF VOLTAGE DROOP DROOP Switch Select Pin Figure 3. t (Time Break−Before−Make) BBM VCC DUT Input 50% 50% VCC Output 0 V 0.1 (cid:3)F VOUT VOH Open 50 (cid:2) 35 pF 90% 90% Output VOL Input tON tOFF Figure 4. t /t ON OFF VCC VCC DUT Input 50% 50% 50 (cid:2) 0 V Output VOUT VOH Open 35 pF Output 10% 10% VOL Input tOFF tON Figure 5. t /t ON OFF http://onsemi.com 5

NLAS7242 50 (cid:2) DUT Reference Input Transmitted Output 50 (cid:2) Generator 50 (cid:2) Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction. (cid:3) (cid:4) VOUT VISO = Off Channel Isolation = 20 Log VIN for VIN at 100 kHz (cid:3) (cid:4) VOUT VONL = On Channel Loss = 20 Log VIN for VIN at 100 kHz to 50 MHz Bandwidth (BW) = the frequency 3 dB below VONL VCT = Use VISO setup and test to all other switch analog input/outputs terminated with 50 (cid:2) Figure 6. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/V ONL DETAILED DESCRIPTION High Speed (480Mbps) USB 2.0 Optimized Over Voltage Tolerant The NLAS7242 is a DPDT switch designed for USB The NLAS7242 features over voltage tolerant I/O applications within portable systems. The R and C of protection on the common signal pins D+/D−. This allows ON ON both switches are maintained at industry−leading low levels the switch to interface directly with a USB connector. The in order to ensure maximum signal integrity for USB 2.0 D+/D− pins can withstand a short to V , up to 5.25 V, BUS high speed data communication. The NLAS7242 switch can continuous DC current for up to 24 hours as specified in the be used to switch between high speed (480Mbps) USB USB 2.0 specification. This protection is achieved without signals and a variety of audio or data signals such as full the need for any external resistors or protection devices. speed USB, UART or even a moderately resistive audio terminal. http://onsemi.com 6

NLAS7242 NLAS7242 Figure 7. Board Schematic http://onsemi.com 7

NLAS7242 Figure 8. Signal Quality Figure 9. Near End Eye Diagram http://onsemi.com 8

NLAS7242 Near End Test Data: Min Max Consecutive jitter range −54.37 73.21 ps Std. Paired JK jitter range −59.14 59.56 ps −200 ps +200 ps Paired KJ jitter range −50.79 34.57 ps Consecutive jitter range −74.43 81.65 ps N.C. Paired JK jitter range −61.60 58.55 ps −200 ps +200 ps Paired KJ jitter range −55.31 48.43 ps Consecutive jitter range −82.55 80.33 ps N.O. Paired JK jitter range −53.50 71.65 ps −200 ps +200 ps Paired KJ jitter range −62.60 47.30 ps 0 −0.5 −1 B) d −1.5 E ( D −2 U T NI −2.5 G A −3 M −3.5 −4 −4.5 1.0E+6 10.0E+6 100.0E+6 1.0E+9 FREQUENCY (Hz) Figure 10. Magnitude vs. Frequency @ V = 3.3 V, All Temperatures CC ICC Leakage Current as a Function of VIN Voltage (25(cid:2)C) 2.50E−03 2.00E−03 4.2 V 3.3 V 1.50E−03 C 1.00E−03 C I 2.7 V 5.00E−04 0.00E+00 −5.00E−04 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 VIN (V) Figure 11. I vs. V , Select Pin, All V ’s, 25(cid:2)C CC IN CC http://onsemi.com 9

NLAS7242 PACKAGE DIMENSIONS UQFN10 1.4x1.8, 0.4P CASE 488AT−01 ISSUE A EDGE OF PACKAGE NOTES: D A 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS ÉÉ 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM L1 FROM TERMINAL. ÉÉ 4. COPLANARITY APPLIES TO THE EXPOSED PAD E AS WELL AS THE TERMINALS. PIN 1 REFERENCE DETAIL A MILLIMETERS 0.10 C Bottom View DIM MIN MAX 2X (Optional) A 0.45 0.60 A1 0.00 0.05 0.10 C A3 0.127 REF 2X B EXPOSED Cu MOLD CMPD b 0.15 0.25 TOP VIEW D 1.40 BSC E 1.80 BSC ÉÉÉÉ e 0.40 BSC 0.05 C A A3 L 0.30 0.50 ÉÉ L1 0.00 0.15 L3 0.40 0.60 A1 0.05 C DETAIL B 10X A1 C SEATING Side View MOUNTING FOOTPRINT* PLANE SIDE VIEW (Optional) 1.700 9 X 3 5 e/2 0.0669 0.563 9 XL 0.0221 0.663 6 0.0261 e 1 0.200 0.0079 10 10 X 0.10 C A B 1 L3 b 2.100 0.05 C NOTE 3 0.0827 BOTTOM VIEW 0.400 0.0157 PITCH 10 X 0.225 (cid:3) (cid:4) 0.0089 mm SCALE 20:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operat- ing parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associ- ated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5773−3850 Sales Representative http://onsemi.com NLAS7242/D 10

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