NIS5132 Series +12 Volt Electronic Fuse The NIS5132 is a cost effective, resettable fuse which can greatly enhance the reliability of a hard drive or other circuit from both catastrophic and shutdown failures. It is designed to buffer the load device from excessive input voltage which can damage sensitive circuits. It also includes an overvoltage http://onsemi.com clamp circuit that limits the output voltage during transients but does not shut the unit down, thereby allowing the load circuit to continue 3.6 AMP, 12 VOLT operation. Two thermal options are available, latching and auto−retry. ELECTRONIC FUSE Features • Integrated Power Device • Power Device Thermally Protected • No External Current Shunt Required • DFN10 9 V to 18 V Input Range CASE 485C • 44 m(cid:2) Typical • Internal Charge Pump • MARKING DIAGRAM Internal Undervoltage Lockout Circuit • Internal Overvoltage Clamp (MN1 and MN2 versions) 1 Pin Function • 32 1 GND ESD Ratings: Human Body Model (HBM); 2000 V AYW(cid:2) 2 dv/dt (cid:2) Machine Model (MM); 200 V 3 Enable/Fault • These Devices are Pb−Free and are RoHS Compliant 4 ILIMIT 5 NC 6−10 SOURCE Typical Applications • 11 (flag) VCC Hard Drives • Mother Board Power Management 32 = Latching Version with VClamp 32B = Latching Version without VClamp 32H = Auto−Retry Version with VClamp A = Assembly Location Y = Year W = Work Week (cid:2) = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the ordering information section on page 10 of this data sheet. © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: July, 2014 − Rev. 10 NIS5132/D

NIS5132 Series VCC Charge Enable Pump ENABLE/ FAULT SOURCE Thermal Current Shutdown Limit ILIMIT UVLO dv/dt Voltage dv/dt Clamp* Control (*MN1 and MN2 versions) GND Figure 1. Block Diagram Table 1. FUNCTIONAL PIN DESCRIPTION Pin Function Description 1 Ground Negative input voltage to the device. This is used as the internal reference for the IC. 2 dv/dt The internal dv/dt circuit controls the slew rate of the output voltage at turn on. It has an internal capacitor that allows it to ramp up over a period of 2 ms. An external capacitor can be added to this pin to increase the ramp time. If an additional time delay is not required, this pin should be left open. 3 Enable/Fault The enable/fault pin is a tri−state, bidirectional interface. It can be used to enable or disable the output of the device by pulling it to ground using an open drain or open collector device. If a thermal fault occurs, the voltage on this pin will go to an intermediate state to signal a monitoring circuit that the device is in thermal shutdown. It can also be connected to another device in this family to cause a simultaneous shutdown during thermal events. 4 ILimit A resistor between this pin and the source pin sets the overload and short circuit current limit levels. 6−10 Source This pin is the source of the internal power FET and the output terminal of the fuse. 11 (belly pad) VCC Positive input voltage to the device. MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage, operating, steady−state (VCC to GND, Note 1) VIN −0.6 to 18 V Transient (100 ms) −0.6 to 25 Thermal Resistance, Junction−to−Air (cid:3)JA °C/W 0.1 in2 copper (Note 2) 227 0.5 in2 copper (Note 2) 95 Thermal Resistance, Junction−to−Lead (Pin 1) (cid:3)JL 27 °C/W Thermal Resistance, Junction−to−Case (cid:3)JC 20 °C/W Total Power Dissipation @ TA = 25°C Pmax 1.3 W Derate above 25°C 10.4 mW/°C Operating Temperature Range (Note 3) TJ −40 to 150 °C Nonoperating Temperature Range TJ −55 to 155 °C Lead Temperature, Soldering (10 Sec) TL 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Negative voltage will not damage device provided that the power dissipation is limited to the rated allowable power for the package. 2. 1 oz. copper, double−sided FR4. 3. Thermal limit is set above the maximum thermal rating. It is not recommended to operate this device at temperatures greater than the maximum ratings for extended periods of time. http://onsemi.com 2

NIS5132 Series ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 12 V, CL = 100 (cid:4)F, dv/dt pin open, RLIMIT = 10 (cid:2), Tj = 25°C unless otherwise noted.) Characteristics Symbol Min Typ Max Unit POWER FET Delay Time (enabling of chip to ID = 100 mA with 1 A resistive load) Tdly 220 (cid:4)s Kelvin ON Resistance (Note 4) RDSon 35 44 55 m(cid:2) TJ = 140°C (Note 5) 62 Off State Output Voltage Voff 190 300 mV (VCC = 18 Vdc, VGS = 0 Vdc, RL = (cid:2)) Output Capacitance (VDS = 12 Vdc, VGS = 0 Vdc, f = 1 MHz) 250 pF Continuous Current (TA = 25°C, 0.5 in2 pad) (Note 5) ID 3.6 A (TA = 80°C, minimum copper) ID 1.7 THERMAL LATCH Shutdown Temperature (Note 5) TSD 150 175 200 °C Thermal Hysteresis (Decrease in die temperature for turn on, does not apply THyst 45 °C to latching parts) UNDER/OVERVOLTAGE PROTECTION Output Clamping Voltage (Overvoltage Protection) (VCC = 18 V) (Note 6) VClamp 14 15 16.2 V Undervoltage Lockout (Turn on, voltage going high) VUVLO 7.7 8.5 9.3 V UVLO Hysteresis VHyst − 0.80 − V CURRENT LIMIT Kelvin Short Circuit Current Limit (RLimit = 15.4 (cid:2), Note 7) ILim−SS 2.75 3.44 4.25 A Kelvin Overload Current Limit (RLimit = 15.4 (cid:2), Note 7) ILim−OL 4.6 A dv/dt CIRCUIT Output Voltage Ramp Time (Enable to VOUT = 11.7 V) tslew 0.5 0.9 1.8 ms Maximum Capacitor Voltage Vmax VCC V ENABLE/FAULT Logic Level Low (Output Disabled) Vin−low 0.35 0.58 0.81 V Logic Level Mid (Thermal Fault, Output Disabled) Vin−mid 0.82 1.4 1.95 V Logic Level High (Output Enabled) Vin−high 1.96 2.64 3.30 V High State Maximum Voltage Vin−max 3.40 4.30 5.2 V Logic Low Sink Current (Venable = 0 V) Iin−low −17 −25 (cid:4)A Logic High Leakage Current for External Switch (Venable = 3.3 V) Iin−leak 1.0 (cid:4)A Maximum Fanout for Fault Signal (Total number of chips that can be Fan 3.0 Units connected to this pin for simultaneous shutdown) TOTAL DEVICE Bias Current (Operational) IBias 1. 8 2.5 mA Bias Current (Shutdown) IBias 1.0 mA Minimum Operating Voltage (Notes 5 and 8) Vmin 7.6 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse test: Pulse width 300 (cid:4)s, duty cycle 2%. 5. Verified by design. 6. VClamp only in MN1 & MN2 versions. 7. Refer to explanation of short circuit and overload conditions in application note AND8140. 8. Device will shut down prior to reaching this level based on actual UVLO trip point. http://onsemi.com 3

NIS5132 Series 60 50(cid:3)C 50 25(cid:3)C 40 W) R ( E 30 W O P 20 80(cid:3)C 10 0 0.1 1 10 100 1000 10000 100000 TIME (ms) Figure 2. Power Dissipation vs. Thermal Trip Time 11 10 +12 V VCC 9 8 SOURCE 7 6 NIS5132 RS 4 ILIMIT 3 ENABLE GND dv/dt LOAD ENABLE 1 2 GND Figure 3. Application Circuit with Direct Current Sensing 11 10 +12 V VCC 9 8 SOURCE 7 6 NIS5132 RS 4 ILIMIT 3 ENABLE GND dv/dt LOAD ENABLE 1 2 GND Figure 4. Application Circuit with Kelvin Current Sensing http://onsemi.com 4

NIS5132 Series VCC VCC SOURCE SOURCE RS NIS5135 NIS5132 ILIMIT ILIMIT ENABLE ENABLE dv/dt GND GND dv/dt LOAD LOAD ENABLE Figure 5. Common Thermal Shutdown http://onsemi.com 5

NIS5132 Series 9 0.86 8.8 0.84 8.6 0.82 8.4 V) V) 0.8 O ( 8.2 T ( L S V Y 0.78 U H 8 0.76 7.8 0.74 7.6 7.4 0.72 −50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 6. UVLO Turn−On Figure 7. UVLO Hysteresis 15.3 1.05 15.2 15.1 1 s) V) 15 m E ( E ( AG 14.9 TIM 0.95 LT P O 14.8 M V A R 14.7 0.9 14.6 14.5 0.85 −50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 8. Output Clamping Voltage Figure 9. Output Voltage dv/dt Rate (MN1 & MN2 only) 1600 1200 A) m T ( N 800 E R R U C 400 0 0.5 0.6 0.7 0.8 FORWARD VOLTAGE (V) Figure 10. Input Transient Response Figure 11. Body Diode Forward Characteristics http://onsemi.com 6

NIS5132 Series 9 10 8 −40°C OL T (A) 7 0°C T (A) SC EN 25°C EN 1 R R R 6 50°C R U U C C 85°C 5 4 0.1 0 0.5 1 1.5 2 10 100 1000 COPPER AREA (in2) Rlimit ((cid:2)) Figure 12. Thermal Limit vs. Copper Area and Figure 13. Current Limit vs. R for Direct sense Ambient Temperature Current Sensing 4.5 10 4 OL OL 3.5 A) 3 A) SC T (2.5 SC T ( N N E E 1 R 2 R R R U U C1.5 C 1 0.5 0 0.1 −50 0 50 100 150 1 10 100 TEMPERATURE (°C) Rsense ((cid:2)) Figure 14. Direct Current Sensing Levels vs. Figure 15. Current Limit vs. R for Kelvin sense Temperature for 27 (cid:2) Sense Resistor Current Sensing 6 4 5.5 3.5 OL A) 5 OL A) 3 ENT (4.5 ENT ( 2.5 R R R R U U C 4 SC C 2 SC 3.5 1.5 3 1 −40 −20 0 20 40 60 80 100 −40 −20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. Kelvin Current Sensing Levels vs. Figure 17. Kelvin Current Sensing Levels vs. Temperature for 15 (cid:2) Sense Resistor Temperature for 33 (cid:2) Sense Resistor http://onsemi.com 7

NIS5132 Series 55 (cid:2)) m E ( 50 C N A T S SI E R 45 N O 40 7.0 9.0 11 13 15 VCC (V) Figure 18. On Resistance vs. V CC APPLICATION INFORMATION Basic Operation actively limiting the current and the gate is at an intermediate This device is a self−protected, resettable, electronic fuse. level. For a more detailed description of this circuit please It contains circuits to monitor the input voltage, output refer to application note AND8140. voltage, output current and die temperature. There are two methods of biasing the current limit circuit On application of the input voltage, the device will apply for this device. They are shown in the two application the input voltage to the load based on the restrictions of the figures. Direct current sensing connects the sense resistor controlling circuits. The dv/dt of the output voltage will be between the current limit pin and the load. This method controlled by the internal dv/dt circuit. The output voltage includes the bond wire resistance in the current limit circuit. will slew from 0 V to the rated output voltage in 2 ms, unless This resistance has an impact on the current limit levels for additional capacitance is added to the dv/dt pin. a given resistor and may vary slightly depending on the The device will remain on as long as the temperature does impedance between the sense resistor and the source pins. not exceed the 175°C limit that is programmed into the chip. The on resistance of the device will be slightly lower in this The current limit circuit does not shut down the part but will configuration since all five source pins are connected in reduce the conductivity of the FET to maintain a constant parallel and therefore, the effective bond wire resistance is current at the internally set current limit level. The input one fifth of the resistance for any given pin. overvoltage clamp also does not shutdown the part, but will The other method is Kelvin sensing. This method uses one limit the output voltage to 15 V in the event that the input of the source pins as the connection for the current sense exceeds that level. resistor. This connection senses the voltage on the die and An internal charge pump provides bias for the gate voltage therefore any bond wire resistance and external impedance of the internal n−channel power FET and also for the current on the board have no effect on the current limit levels. In this limit circuit. The remainder of the control circuitry operates configuration the on resistance is slightly increased relative between the input voltage (VCC) and ground. to the direct sense method since only four of the source pins are used for power. Current Limit The current limit circuit uses a SENSEFET along with a Overvoltage Clamp (MN1 & MN2 Versions) reference and amplifier to control the peak current in the The overvoltage clamp consists of an amplifier and device. The SENSEFET allows for a small fraction of the reference. It monitors the output voltage and if the input load current to be measured, which has the advantage of voltage exceeds 15 V, the gate drive of the main FET is reducing the losses in the sense resistor as well as increasing reduced to limit the output. This is intended to allow the value and decreasing the power rating of the sense operation through transients while protecting the load. If an resistor. Sense resistors are typically in the tens of ohms overvoltage condition exists for many seconds, the device range with power ratings of several milliwatts making them may overheat due to the voltage drop across the FET very inexpensive chip resistors. combined with the load current. In this event, the thermal The current limit circuit has two limiting values, one for protection circuit would shut down the device. overload events which are defined as the mode of operation in which the gate is high and the FET is fully enhanced. The short circuit mode of operation occurs when the device is http://onsemi.com 8

NIS5132 Series Undervoltage Lockout When this pin is low, the output of the fuse will be turned off. The undervoltage lockout circuit uses a comparator with When this pin is high the output of the fuse will be hysteresis to monitor the input voltage. If the input voltage turned−on. If a thermal fault occurs, this pin will be pulled drops below the specified level, the output switch will be low to an intermediate level by an internal circuit. switched to a high impedance state. To use as a simple enable pin, an open drain or open collector device should be connected to this pin. Due to its dv/dt Circuit tri−state operation, it should not be connected to any type of The dv/dt circuit brings the output voltage up under a logic with an internal pullup device. linear, controlled rate regardless of the load impedance If the chip shuts down due to the die temperature reaching characteristics. An internal ramp generator creates a linear its thermal limit, this pin will be pulled down to an ramp, and a control circuit forces the output voltage to intermediate level. This signal can be monitored by an follow that ramp, scaled by a factor. external circuit to communicate that a thermal shutdown has The default ramp time is approximately 2 ms. This can be occurred. If this pin is tied to another device in this family modified by adding an external capacitor at the dv/dt pin. (NIS5132 or NIS5135), a thermal shutdown of one device This pin includes an internal current source of will cause both devices to disable their outputs. Both devices approximately 85 nA. Since the current level is very low, it will turn on once the fault is removed for the auto−retry is important to use a ceramic cap or other low leakage devices. capacitor. Aluminum electrolytic capacitors are not For the latching thermal device, the outputs will be recommended for this circuit. enabled after the enable pin has been pulled to ground with The ramp time from 0 to the nominal output voltage can an external switch and then allowed to go high or after the be determined by the following equation, where t is in input power has been recycled. For the auto retry devices, seconds: both devices will restart as soon as the die temperature of the (cid:6) (cid:8) t0(cid:3)12(cid:4)24e6(cid:5) 50pF(cid:7)Cext device in shutdown has been reduced to the lower thermal limit. The thermal options are listed in the ordering table. t C (cid:4) 0−12(cid:3)50pF ext 24e6 Thermal Protection The NIS5132 includes an internal temperature sensing Where: circuit that senses the temperature on the die of the power C is in Farads FET. If the temperature reaches 175°C, the device will shut t is in seconds down, and remove power from the load. Output power can Any time that the unit shuts down due to a fault, enable be restored by either recycling the input power or toggling shut−down, or recycling of input power, the timing capacitor the enable pin. Power will automatically be reapplied to the will be discharged and the output voltage will ramp from 0 load for auto−retry devices once the die temperature has at turn on. been reduced by 45°C. The thermal limit has been set high intentionally, to Enable/Fault The Enable/Fault pin is a multi−function, bidirectional pin increase the trip time during high power transient events. It that can control the output of the chip as well as send is not recommended to operate this device above 150°C for information to other devices regarding the state of the chip. extended periods of time. Figure 19. Fault/Enable Signal Levels http://onsemi.com 9

NIS5132 Series 4.3 V Startup 12 (cid:4)A Blanking* Enable SD 2.64 V + En/Fault − 1.4 V − 0.58 V + Thermal Reset SD Thermal Shutdown Thermal SD (*MN1 and MN2 versions) Figure 20. Enable/Fault Simplified Circuit ORDERING INFORMATION Device Features Package Shipping† NIS5132MN1TXG Thermal Latching with VClamp DFN10 3000 / Tape & Reel (Pb−Free) NIS5132MN2TXG Thermal Auto−Retry with VClamp DFN10 3000 / Tape & Reel (Pb−Free) NIS5132MN3TXG Thermal Latching without VClamp DFN10 3000 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 10

NIS5132 Series PACKAGE DIMENSIONS DFN10, 3x3, 0.5P CASE 485C ISSUE C D A EDGE OF PACKAGE NOTES: 1. DIMENSIONING AND TOLERANCING PER B ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN L1 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED ÇÇÇ PAD AS WELL AS THE TERMINALS. E DETAIL A 5. TERMINAL b MAY HAVE MOLD COMPOUND ÇÇÇ Bottom View MATERIAL ALONG SIDE EDGE. MOLD PIN 1 (Optional) FLASHING MAY NOT EXCEED 30 MICRONS REFERENCEÇÇÇ 6. ODENTTAOI LBSO AT TAONMD SBU SRHFOAWCE O OPFT ITOENRAML IVNIAELW bS. FOR END OF TERMINAL LEAD AT EDGE OF 2X 0.15 C EXPOSED Cu PACKAGE. TOP VIEW MOLD CMPD 7. FOR DEVICE OPN CONTAINING W OPTION, 2X 0.15 C ÉÉÉ DETAIL B ALTERNATE CONSTRUCTION IS NOT APPLICABLE. ÉÉÉ A3 MILLIMETERS DETAIL B (A3) DIM MIN MAX 0.10 C A 0.80 1.00 A1 A1 0.00 0.05 A DETAIL B A3 0.20 REF 10X 0.08 C SEATING Side View Db 0.31.800 BS0.C30 PLANE (Optional) SIDE VIEW A1 D2 2.40 2.60 C E 3.00 BSC E2 1.70 1.90 e 0.50 BSC D2 DETAIL A SOLDERING FOOTPRINT* K 0.19 TYP 10X L e L 0.35 0.45 L1 0.00 0.03 1 5 2.6016 E2 10X K 2.1746 1.8508 3.3048 10 6 10Xb 0.10 C A B BOTTOM VIEW 0.05 C NOTE 3 10X 0.5651 10X 0.3008 0.5000 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com NIS5132/D 11

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: NIS5132MN2TXG NIS5132MN1TXG