NCV8501 Series Micropower 150 mA LDO Linear Regulators with ENABLE, DELAY, RESET, and Monitor FLAG http://onsemi.com The NCV8501 is a family of precision micropower voltage regulators. Their output current capability is 150 mA. The family has output voltage options for adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, and 10 V. SO−8 8 The output voltage is accurate within ±2.0% with a maximum D SUFFIX 1 CASE 751 dropout voltage of 0.6 V at 150 mA. Low quiescent current is a feature drawing only 90 (cid:2)A with a 100 (cid:2)A load. This part is ideal for any and all battery operated microprocessor equipment. SOIC 16 LEAD Microprocessor control logic includes an active RESET (with WIDE BODY DELAY), and a FLAG monitor which can be used to provide an early 16 EXPOSED PAD warning signal to the microprocessor of a potential impending RESET 1 PDW SUFFIX signal. The use of the FLAG monitor allows the microprocessor to CASE 751AG finish any signal processing before the RESET shuts the microprocessor down. The active RESET circuit operates correctly at an output voltage as MARKING DIAGRAMS low as 1.0 V. The RESET function is activated during the power up SOW−16 sequence or during normal operation if the output voltage drops SO−8 E PAD outside the regulation limits. 16 8 The regulator is protected against reverse battery, short circuit, and 8501x thermal overload conditions. The device can withstand load dump ALYW 8501x transients making it suitable for use in automotive environments. The (cid:2) AWLYYWWG device has also been optimized for EMC conditions. 1 1 Features x = Voltage Ratings as Indicated Below: • Output Voltage Options: Adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, 10 V A = Adjustable • ±2.0% Output 2 = 2.5 V 3 = 3.3 V • Low 90 (cid:2)A Quiescent Current 5 = 5.0 V • 8 = 8.0 V Fixed or Adjustable Output Voltage 0 = 10 V • Active RESET A = Assembly Location • ENABLE WL, L = Wafer Lot • YY, Y = Year 150 mA Output Current Capability WW, W = Work Week • Fault Protection G or (cid:2) = Pb−Free Package ♦ +60 V Peak Transient Voltage ♦ −15 V Reverse Voltage ORDERING INFORMATION ♦ Short Circuit See detailed ordering and shipping information in the package ♦ Thermal Overload dimensions section on page 14 of this data sheet. • Early Warning through FLAG/MON Leads • NCV Prefix for Automotive and Other Applications Requiring Site and Change Control • These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2009 1 Publication Order Number: January, 2009 − Rev. 29 NCV8501/D

NCV8501 Series PIN CONNECTIONS, ADJUSTABLE OUTPUT SO−8 SOW−16 E PAD 1 8 1 16 VIN VOUT VADJ FLAG MON VADJ VOUT NC NC NC ENABLE FLAG NC GND NC GND NC NC NC NC VIN NC MON ENABLE PIN CONNECTIONS, FIXED OUTPUT SO−8 SOW−16 E PAD 1 8 1 16 VIN VOUT FLAG RESET MON FLAG VOUT NC NC NC ENABLE RESET NC GND DELAY GND NC NC NC NC VIN DELAY MON ENABLE VBAT VIN VOUT VDD 10 (cid:2)F 10 (cid:2)F r NCV8501 o RFLG RRST ss 10 k 10 k e DELAY c MON o r p CDELAY ro c Mi VADJ (Adjustable ENABLE Output Only) FLAG RESET I/O I/O GND Figure 1. Application Diagram http://onsemi.com 2

NCV8501 Series MAXIMUM RATINGS* Rating Value Unit VIN (dc) −15 to 45 V Peak Transient Voltage (46 V Load Dump @ VIN = 14 V) 60 V Operating Voltage 45 V VOUT (dc) −0.3 to 16 V Voltage Range (RESET, FLAG) −0.3 to 10 V Input Voltage Range (MON) −0.3 to 10 V Input Voltage Range (VAOJ) −0.3 to 16 Input Voltage Range (ENABLE) −0.3 to 10** V ESD Susceptibility (Human Body Model) 2.0 kV Junction Temperature, TJ −40 to +150 °C Storage Temperature, TS −55 to 150 °C Package Thermal Resistance, SO−8: Junction−to−Case, R(cid:3)JC 45 °C/W Junction−to−Ambient, R(cid:3)JA 165 °C/W Package Thermal Resistance, SOW−16 E PAD: Junction−to−Case, R(cid:3)JC 15 °C/W JJuunnccttiioonn−−ttoo−−PAimn,b Rie(cid:3)nJtP, R(N(cid:3)JoAte 1) 5365 °°CC//WW Lead Temperature Soldering: Reflow: (SMD styles only) (Note 2) 260 Peak °C (Note 3) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *During the voltage range which exceeds the maximum tested voltage of VIN, operation is assured, but not specified. Wider limits may apply. Thermal dissipation must be observed closely. **Reference Figure 15 for switched−battery ENABLE application. 1. Measured to pin 16. 2. 150 second maximum above 217°C. 3. −5°C / +0°C allowable conditions. http://onsemi.com 3

NCV8501 Series ELECTRICAL CHARACTERISTICS (IOUT = 1.0 mA, ENABLE = 5.0 V, −40°C ≤ TJ ≤ 150°C; VIN dependent on voltage option (Note 4); unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Output Stage Output Voltage for 2.5 V Option 6.5 V < VIN < 16 V, 100 (cid:2)A ≤ IOUT ≤ 150 mA 2.450 2.5 2.550 V 5.5 V < VIN < 26 V, 100 (cid:2)A ≤ IOUT ≤ 150 mA 2.425 2.5 2.575 V Output Voltage for 3.3 V Option 7.3 V < VIN < 16 V, 100 (cid:2)A ≤ IOUT ≤ 150 mA 3.234 3.3 3.366 V 5.5 V < VIN < 26 V, 100 (cid:2)A ≤ IOUT ≤ 150 mA 3.201 3.3 3.399 V Output Voltage for 5.0 V Option 9.0 V < VIN < 16 V, 100 (cid:2)A ≤ IOUT ≤ 150 mA 4.90 5.0 5.10 V 6.0 V < VIN < 26 V, 100 (cid:2)A ≤ IOUT ≤ 150 mA 4.85 5.0 5.15 V Output Voltage for 8.0 V Option 9.0 V < VIN < 26 V, 100 (cid:2)A ≤ IOUT ≤ 150 mA 7.76 8.0 8.24 V Output Voltage for 10 V Option 11 V < VIN < 26 V, 100 (cid:2)A ≤ IOUT ≤ 150 mA 9.7 10 10.3 V Output Voltage for Adjustable Option VOUT = VADJ (Unity Gain) 6.5 V < VIN < 16 V, 100 (cid:2)A < IOUT < 150 mA 1.254 1.280 1.306 V 5.5 V < VIN < 26 V, 100 (cid:2)A < IOUT < 150 mA 1.242 1.280 1.318 V Dropout Voltage (VIN − VOUT) IOUT = 150 mA − 400 600 mV (5.0 V, 8.0 V, 10 V, and IOUT = 1.0 mA − 100 150 mV Adj. > 5.0 V Options Only) Load Regulation VIN = 14 V, 5.0 mA ≤ IOUT ≤ 150 mA −30 5.0 30 mV Line Regulation [VOUT(Typ) + 1.0] < VIN < 26 V, IOUT = 1.0 mA − 15 60 mV Quiescent Current, Low Load IOUT = 100 (cid:2)A, VIN = 12 V, MON = VOUT 2.5 V Option − 90 125 (cid:2)A 3.3 V Option − 90 125 (cid:2)A 5.0 V Option − 90 125 (cid:2)A 8.0 V Option − 100 150 (cid:2)A 10 V Option Adjustable Option − 100 150 (cid:2)A − 50 75 (cid:2)A Quiescent Current, Medium Load IOUT = 75 mA, VIN = 14 V, MON = VOUT − 4.0 6.0 mA All Options Quiescent Current, High Load IOUT = 150 mA, VIN = 14 V, MON = VOUT − 12 19 mA All Options Quiescent Current, (IQ) ENABLE = 0 V, VIN = 12 V − 12 30 (cid:2)A Sleep Mode Current Limit − 151 300 − mA Short Circuit Output Current VOUT = 0 V 40 190 − mA Thermal Shutdown (Guaranteed by Design) 150 180 − °C Reset Function (RESET) RESET Threshold for 2.5 V Option 5.5 V ≤ VIN ≤ 26 V (Note 5) HIGH (VRH) VOUT Increasing 2.28 2.350 0.98 × VOUT V LOW (VRL) VOUT Decreasing 2.25 2.300 0.97 × VOUT V RESET Threshold for 3.3 V Option 5.5 V ≤ VIN ≤ 26 V (Note 5) HIGH (VRH) VOUT Increasing 3.00 3.102 0.98 × VOUT V LOW (VRL) VOUT Decreasing 2.97 3.036 0.97 × VOUT V RESET Threshold for 5.0 V Option HIGH (VRH) VOUT Increasing 4.55 4.70 0.98 × VOUT V LOW (VRL) VOUT Decreasing 4.50 4.60 0.97 × VOUT V RESET Threshold for 8.0 V Option HIGH (VRH) VOUT Increasing 7.05 7.52 0.98 × VOUT V LOW (VRL) VOUT Decreasing 7.00 7.36 0.97 × VOUT V 4. Voltage range specified in the Output Stage of the Electrical Characteristics in boldface type. 5. For VIN ≤ 5.5 V, a RESET = Low may occur with the output in regulation. http://onsemi.com 4

NCV8501 Series ELECTRICAL CHARACTERISTICS (IOUT = 1.0 mA, ENABLE = 5.0 V, −40°C ≤ TJ ≤ 150°C; VIN dependent on voltage option (Note 4); unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Reset Function (RESET) RESET Threshold for 10 V Option HIGH (VRH) VOUT Increasing 8.60 9.40 0.98 × VOUT V LOW (VRL) VOUT Decreasing 8.50 9.20 0.97 × VOUT V Output Voltage Low (VRLO) 1.0 V ≤ VOUT ≤ VRL, RRESET = 10 k − 0.1 0.4 V DELAY Switching Threshold (VDT) − 1.4 1.8 2.2 V DELAY Low Voltage VOUT < RESET Threshold Low(min) − − 0.1 V DELAY Charge Current DELAY = 1.0 V, VOUT > VRH 1.5 2.5 3.5 (cid:2)A DELAY Discharge Current DELAY = 1.0 V, VOUT = 1.5 V 5.0 − − mA FLAG/Monitor Monitor Threshold Increasing and Decreasing 1.10 1.20 1.31 V Hysteresis − 20 50 100 mV Input Current MON = 2.0 V −0.5 0.1 0.5 (cid:2)A Output Saturation Voltage MON = 0 V, IFLAG = 1.0 mA − 0.1 0.4 V Voltage Adjust (Adjustable Output only) Input Current VADJ = 1.28 V −0.5 − 0.5 (cid:2)A ENABLE Input Threshold Low − − 0.5 V High 3.0 − − V Input Current ENABLE = 5.0 V − 1.0 5.0 (cid:2)A 4. Voltage range specified in the Output Stage of the Electrical Characteristics in boldface type. 5. For VIN ≤ 5.5 V, a RESET = Low may occur with the output in regulation. http://onsemi.com 5

NCV8501 Series PACKAGE PIN DESCRIPTION, ADJUSTABLE OUTPUT Package Pin Number SOW−16 SO−8 E PAD Pin Symbol Function 1 7 VIN Input Voltage. 2 8 MON Monitor. Input for early warning comparator. If not needed connect to VOUT. 3 9 ENABLE ENABLE control for the IC. A high powers the device up. 4 3−6, 10−12, NC No connection. 14, 15 5 13 GND Ground. All GND leads must be connected to Ground. 6 16 FLAG Open collector output from early warning comparator. 7 1 VADJ Voltage Adjust. A resistor divider from VOUT to this lead sets the output voltage. 8 2 VOUT ±2.0%, 150 mA output. PACKAGE PIN DESCRIPTION, FIXED OUTPUT Package Pin Number SOW−16 SO−8 E PAD Pin Symbol Function 1 7 VIN Input Voltage. 2 8 MON Monitor. Input for early warning comparator. If not needed connect to VOUT. 3 9 ENABLE ENABLE control for the IC. A high powers the device up. 4 10 DELAY Timing capacitor for RESET function. 5 13 GND Ground. All GND leads must be connected to Ground. 6 16 RESET Active reset (accurate to VOUT ≥ 1.0 V) 7 1 FLAG Open collector output from early warning comparator. 8 2 VOUT ±2.0%, 150 mA output. − 3−6, 11, 12, NC No connection. 14, 15 http://onsemi.com 6

NCV8501 Series TYPICAL PERFORMANCE CHARACTERISTICS 5.01 3.35 VOUT = 5.0 V VOUT = 3.3 V VIN = 14 V 3.34 VIN = 14 V IOUT = 5.0 mA IOUT = 5.0 mA 3.33 5.00 3.32 V) V) (T (T 3.31 U U O O V V 3.30 4.99 3.29 3.28 4.98 3.27 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 Temperature (°C) Temperature (°C) Figure 2. Output Voltage vs. Temperature Figure 3. Output Voltage vs. Temperature 1.2 14 VIN = 12 V VIN = 12 V 12 1.0 +125°C 10 0.8 +125°C +25°C mA) mA) 8 +25°C 0.6 (Q −40°C (Q 6 I I 0.4 −40°C 4 0.2 2 0 0 0 5 10 15 20 25 0 15 30 45 60 75 90 105 120 135 140 IOUT (mA) IOUT (mA) Figure 4. Quiescent Current vs. Output Current Figure 5. Quiescent Current vs. Output Current 7 120 T = 25°C T = 25°C 6 100 IOUT = 100 (cid:2)A 5 IOUT = 100 mA 80 A) 4 A) I (mQ 3 (cid:2)I (Q 60 2 IOUT = 50 mA 49 20 1 IOUT = 10 mA 0 0 6 8 10 12 14 16 18 20 22 24 26 6 8 10 12 14 16 18 20 22 24 26 VIN (V) VIN (V) Figure 6. Quiescent Current vs. Input Voltage Figure 7. Quiescent Current vs. Input Voltage http://onsemi.com 7

NCV8501 Series TYPICAL PERFORMANCE CHARACTERISTICS 450 16 VIN = 12 V 400 14 oltage (mV) 233505000 +125°C +25°C −40°C (cid:2)Current (A) 11802 out V 200 cent 6 p 150 s o e Dr 100 Qui 4 50 VOUT = 5.0 V, 8.0 V, or 10 V 2 0 0 0 25 50 75 100 125 150 −40 −25 −10 5 20 35 50 65 80 95 110 125 IOUT (mA) Temperature (°C) Figure 8. Dropout Voltage vs. Output Current Figure 9. Sleep Mode I vs. Temperature Q 1000 1000 Unstable Region Unstable Region CVout = 10 (cid:2)F 100 100 10 V CVout = 0.1 (cid:2)F (cid:4)SR () 10 2.5 V 3.3 V 5 V8 V (cid:4)R () 10 E S 1.0 E 1.0 Stable Region Stable Region 0.1 0.1 CVOUT = 10 (cid:2)F 0.01 0.01 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 110 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) Figure 10. Output Stability with Output Figure 11. Output Stability with Output Voltage Change Capacitor Change 70 Iout = 10 mA 60 Iout = 80 mA 50 B) d ( 40 30 Iout = 150 mA 20 0.1 1.0 10 100 (kHz) Figure 12. Audio Frequency Power Supply Rejection Ratio http://onsemi.com 8

NCV8501 Series VOUT VIN Current Source ENABLE (Circuit Bias) IBIAS Current Limit Sense + + − IBIAS VBG + − Error Amplifier RESET + VBG Fixed Voltage only 1.8 V − Thermal Protection 3.0 (cid:2)A VADJ Bandgap 20 k Delay IBIAS Reference VBG Adjustable GND Version only VBG IBIAS FLAG + MON − Figure 13. Block Diagram http://onsemi.com 9

NCV8501 Series CIRCUIT DESCRIPTION REGULATOR CONTROL FUNCTIONS The DELAY lead provides source current (typically 2.5 (cid:2)A) The NCV8501 contains the microprocessor compatible to the external DELAY capacitor during the following control function RESET (Figure 14). proceedings: 1.During Power Up (once the regulation threshold has been verified). 2.After a reset event has occurred and the device is VIN back in regulation. The DELAY capacitor is discharged when the regulation (RESET threshold) RESET VOUT has been violated. This is a latched incident. The Threshold capacitor will fully discharge and wait for the DELAY DELAY device to regulate before going through the delay Threshold RESET (VDT) time event again. FLAG/Monitor Function Td Td An on−chip comparator is provided to perform an early Figure 14. Reset and Delay Circuit Wave Forms warning to the microprocessor of a possible reset signal. The RESET Function reset signal typically turns the microprocessor off A RESET signal (low voltage) is generated as the IC instantaneously. This can cause unpredictable results with powers up until V is within 6.0% of the regulated output the microprocessor. The signal received from the FLAG pin OUT voltage, or when V drops out of regulation,and is lower will allow the microprocessor time to complete its present OUT than 8.0% below the regulated output voltage. Hysteresis is task before shutting down. This function is performed by a included in the function to minimize oscillations. comparator referenced to the bandgap reference. The actual The RESET output is an open collector NPN transistor, trip point can be programmed externally using a resistor controlled by a low voltage detection circuit. The circuit is divider to the input monitor (MON) (Figure 16). The typical functionally independent of the rest of the IC thereby threshold is 1.20 V on the MON pin. guaranteeing that the RESET signal is valid for V as low OUT as 1.0 V. VBAT VIN VOUT VCC ENABLE Function NCV8501 COUT (cid:2)P The part stays in a low I sleep mode when the ENABLE Q MON FLAG I/O pin is held low. The part has an internal pull down if the pin is left floating. This is intended for failure modes only. An RADJ RESET RESET external connection (active pulldown, resistor, or switch) for DELAY GND normal operation is recommended. The integrity of the ENABLE pin allows it to be tied directly to the battery line through an external resistor. It will Figure 16. FLAG/Monitor Function withstand load dump potentials in this configuration. Voltage Adjust Figure 17 shows the device setup for a user configurable VBAT VIN VOUT output voltage. The feedback to the VADJ pin is taken from NCV8501 a voltage divider referenced to the output voltage. The loop 10 k is balanced around the Unity Gain threshold (1.28 V ENABLE typical). GND ≈5.0 V VOUT NCV8501 15 k COUT Figure 15. ENABLE Function VADJ 1.28 V DELAY Function 5.1 k The reset delay circuit provides a programmable (by external capacitor) delay on the RESET output lead. Figure 17. Adjustable Output Voltage http://onsemi.com 10

NCV8501 Series APPLICATION NOTES VIN VOUT NCV8501 MJD31C 0C.1IN (cid:2)*F NCV8501 RRST 1C0O (cid:2)UFT** VIN VOUT RESET VADJ >1 Amp 5.0 V VBAT C2 R1 0.1 (cid:2)F 294 k C1 47 (cid:2)F R2 *CIN required if regulator is located far from the power supply filter 100 k **COUT required for stability. Capacitor must operate at minimum temperature expected Figure 20. Test and Application Circuit Showing Output Compensation Figure 18. Additional Output Current Adding Capability SETTING THE DELAY TIME Figure 18 shows how the adjustable version of parts can The delay time is controlled by the Reset Delay Low be used with an external pass transistor for additional current Voltage, Delay Switching Threshold, and the Delay Charge capability. The setup as shown will provide greater than 1 Current. The delay follows the equation: Amp of output current. (cid:3)CDELAY(Vdt(cid:4)ResetDelayLowVoltage)(cid:5) tDELAY(cid:2) DelayChargeCurrent FLAG MONITOR Example: Figure 19 shows the FLAG Monitor waveforms as a result Using C = 33 nF. of the circuit depicted in Figure 16. As the output voltage DELAY Assume reset Delay Low Voltage = 0. falls (V ), the Monitor threshold is crossed. This causes OUT Use the typical value for V = 1.8 V. the voltage on the FLAG output to go low sending a warning dt Use the typical value for Delay Charge Current = 2.5 (cid:2)A. signal to the microprocessor that a RESET signal may occur imn icar osphroocrte spsoerr ihoads otof ctoimmep.l eTteW tAheR NfuINnGct ioisn itth eis ctiumrree ntthlye tDELAY(cid:2)(cid:3)33n2F.(51.(cid:2)8A(cid:4)0)(cid:5)(cid:2)23.8ms working on and get ready for the RESET shutdown signal. STABILITY CONSIDERATIONS VOUT The output or compensation capacitor helps determine three main characteristics of a linear regulator: start−up delay, load transient response and loop stability. The capacitor value and type should be based on cost, MON availability, size and temperature constraints. The value for the output capacitor C shown in Figure 20 OUT FLAG Monitor should work for most applications, however it is not Ref. Voltage necessarily the optimized solution. RESET FLAG TWARNING Figure 19. FLAG Monitor Circuit Waveform http://onsemi.com 11

NCV8501 Series UNDERSTANDING THE NCV8501 ENABLE PIN CALCULATING POWER DISSIPATION IN A INPUT CURRENT SINGLE OUTPUT LINEAR REGULATOR The maximum power dissipation for a single output VCC regulator (Figure 22) is: R2 D1 PD(max)(cid:2)[VIN(max)(cid:4)VOUT(min)]IOUT(max) 1.2M (cid:6)VIN(max)IQ (eq. 1) ~3.85V N1 where: D2 D3 V is the maximum input voltage, IN(max) ENABLE R1 D4 Internal VOUT(min) is the minimum output voltage, 20K P1 proawiler IOUT(max) is the maximum output current for the D5 application, and I is the quiescent current the regulator consumes at D6 Q Z1 11V Z2 7V Internal IOUT(max). reference 5μA Z3 1.25V Once the value of PD(max) is known, the maximum (max) GND permissible value of R(cid:3)JA can be calculated: R(cid:5)JA(cid:2)150C(cid:4)TA (eq. 2) Figure 21. NCV8501 Enable Function Equivalent PD Circuit The value of R(cid:3)JA can then be compared with those in the Z1, R1, and Z2 provide ESD and overvoltage protection. package section of the data sheet. Those packages with Note that, for ENABLE pin voltages in excess of 10 V, an R(cid:3)JA’s less than the calculated value in Equation 2 will keep external series resistor is required to limit the current into the die temperature below 150°C. Z1. In some cases, none of the packages will be sufficient to For ENABLE pin voltages less than +7 V, the 5 (cid:2)A dissipate the heat generated by the IC, and an external (maximum value) current source dominates the input heatsink will be required. current, as the opposing P1 base current is negligible by comparison. IIN IOUT inpFuotr cEuNrrAenBt LisE g pivine nv oblyt:ages between +7 V and +11 V, the VIN REGSUMLAARTTOR® VOUT 5 (cid:2)A + ((V − 7) / 20 k(cid:4)) ENABLE }Control For ENABLE pin voltages in excess of 10 V (Z1 Features breakover voltage can be as low as 10 V), the input current is dominated by the external series resistor. For the case IQ where V = 12 V; R = 10 k(cid:4), the input current can ENABLE EXT be up to (2 V/10 k(cid:4)), = 200 (cid:2)A. Figure 22. Single Output Regulator with Key The ENABLE threshold is that voltage required to Performance Parameters Labeled achieve ~3.85 V at the base of N1, or approximately (3.85 V − 2 Vbe). At +20°C, this threshold is ~2.55 V. At −40°C, it 100 can be as high as 3 V. If the value of R is increased to ~200 k(cid:4), to reduce W) ENABLE input cuErrXeTnt, then the worst−case drop across °C/ 90 RmneEaMeXxdiTa mt xom u ecmfuofs enEtcs NtibidveAe erB a ttdLhhdreEee s5dthh (cid:2)orteAolsd h 3c=ou lrV3dr. e V ntAo t+ t s dVi(n5eEkt Ne(cid:2).rAAmB *iLn E2e 2 <t0 h7 ek V (cid:4),e w)ffee cotnivlye al Resistance,mbient, R, ((cid:3)JA8700 == 34 .V1 V+ 1.1 V Thermon to A 60 ncti 50 u J 40 0 200 400 600 800 Copper Area (mm2) Figure 23. 16 Lead SOW (Exposed Pad), (cid:2)JA as a Function of the Pad Copper Area (2 oz. Cu Thickness), Board Material = 0.0625(cid:2) G−10/R−4 http://onsemi.com 12

NCV8501 Series HEATSINKS where: A heatsink effectively increases the surface area of the R(cid:3)JC = the junction−to−case thermal resistance, package to improve the flow of heat away from the IC and R(cid:3)CS = the case−to−heatsink thermal resistance, and into the surrounding air. R(cid:3)SA = the heatsink−to−ambient thermal resistance. Each material in the heat flow path between the IC and the R(cid:3)JC appears in the package section of the data sheet. Like outside environment will have a thermal resistance. Like R(cid:3)JA, it too is a function of package type. R(cid:3)CS and R(cid:3)SA are series electrical resistances, these resistances are summed to functions of the package type, heatsink and the interface determine the value of R(cid:3)JA: between them. These values appear in heatsink data sheets R(cid:3)JA(cid:2)R(cid:3)JC(cid:6)R(cid:3)CS(cid:6)R(cid:3)SA (eq. 3) of heatsink manufacturers. http://onsemi.com 13

NCV8501 Series ORDERING INFORMATION Device Output Voltage Package Shipping† NCV8501DADJG SO−8 Adjustable 98 Units/Rail (Pb−Free) NCV8501DADJR2G SO−8 Adjustable 2500 Tape & Reel (Pb−Free) NCV8501PDWADJG SOW−16 Exposed Pad Adjustable 47 Units/Rail (Pb−Free) NCV8501PDWADJR2G SOW−16 Exposed Pad Adjustable 1000 Tape & Reel (Pb−Free) NCV8501D25G SO−8 2.5 V 98 Units/Rail (Pb−Free) NCV8501D25R2G SO−8 2.5 V 2500 Tape & Reel (Pb−Free) NCV8501PDW25G SOW−16 Exposed Pad 2.5 V 47 Units/Rail (Pb−Free) NCV8501PDW25R2G SOW−16 Exposed Pad 2.5 V 1000 Tape & Reel (Pb−Free) NCV8501D33G SO−8 3.3 V 98 Units/Rail (Pb−Free) NCV8501D33R2G SO−8 3.3 V 2500 Tape & Reel (Pb−Free) NCV8501PDW33G SOW−16 Exposed Pad 3.3 V 47 Units/Rail (Pb−Free) NCV8501PDW33R2G SOW−16 Exposed Pad 3.3 V 1000 Tape & Reel (Pb−Free) NCV8501D50G SO−8 5.0 V 98 Units/Rail (Pb−Free) NCV8501D50R2G SO−8 5.0 V 2500 Tape & Reel (Pb−Free) NCV8501PDW50G SOW−16 Exposed Pad 5.0 V 47 Units/Rail (Pb−Free) NCV8501PDW50R2G SOW−16 Exposed Pad 5.0 V 1000 Tape & Reel (Pb−Free) NCV8501D80G SO−8 8.0 V 98 Units/Rail (Pb−Free) NCV8501D80R2G SO−8 8.0 V 2500 Tape & Reel (Pb−Free) NCV8501PDW80G SOW−16 Exposed Pad 8.0 V 47 Units/Rail (Pb−Free) NCV8501PDW80R2G SOW−16 Exposed Pad 8.0 V 1000 Tape & Reel (Pb−Free) NCV8501D100G SO−8 10 V 98 Units/Rail (Pb−free) NCV8501D100R2G SO−8 10 V 2500 Tape & Reel (Pb−Free) NCV8501PDW100G SOW−16 Exposed Pad 10 V 47 Units/Rail (Pb−Free) NCV8501PDW100R2G SOW−16 Exposed Pad 10 V 1000 Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. http://onsemi.com 14

NCV8501 Series PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 NOTES: −X− ISSUE AJ 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. A 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) 8 5 PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL 1 IN EXCESS OF THE D DIMENSION AT −Y− 4 K 6. M75A1X−I0M1U TMH RMUA T7E51R−IA0L6 CAROEN DOIBTSIOONL.ETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES DIM MIN MAX MIN MAX C NX 45(cid:3) A 4.80 5.00 0.189 0.197 B 3.80 4.00 0.150 0.157 SEATING PLANE C 1.35 1.75 0.053 0.069 −Z− D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC 0.10 (0.004) H 0.10 0.25 0.004 0.010 H D M J J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 (cid:3) 8 (cid:3) 0 (cid:3) 8 (cid:3) N 0.25 0.50 0.010 0.020 0.25 (0.010)M Z Y S X S S 5.80 6.20 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 4.0 0.275 0.155 0.6 1.270 0.024 0.050 (cid:7) (cid:8) mm SCALE 6:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 15

NCV8501 Series PACKAGE DIMENSIONS SOIC 16 LEAD WIDE BODY, EXPOSED PAD PDW SUFFIX CASE 751AG−01 ISSUE A −U− A M NOTES: 16 9 1. DIMENSIONING AND TOLERANCING PER ANSI P Y14.5M, 1982. B 2. CONTROLLING DIMENSION: MILLIMETER. 0.25 (0.010) M W M 1 R x 45(cid:3) 3. DIMENSION A AND B DO NOT INCLUDE MOLD 8 PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER −W− SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE PIN 1 I.D. G 14 PL 0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION DETAIL E AT MAXIMUM MATERIAL CONDITION. 6. 751R-01 OBSOLETE, NEW STANDARD 751R-02. TOP SIDE MILLIMETERS INCHES DIM MIN MAX MIN MAX C A 10.15 10.45 0.400 0.411 −T− F B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 0.10 (0.004) T D16 PL K SEATING D 0.35 0.49 0.014 0.019 PLANE F 0.50 0.90 0.020 0.035 0.25 (0.010) M T U S W S J G 1.27 BSC 0.050 BSC H 3.45 3.66 0.136 0.144 J 0.25 0.32 0.010 0.012 H DETAIL E K 0.00 0.10 0.000 0.004 L 4.72 4.93 0.186 0.194 M 0 (cid:3) 7 (cid:3) 0 (cid:3) 7 (cid:3) SOLDERING FOOTPRINT* P 10.05 10.55 0.395 0.415 1 8 R 0.25 0.75 0.010 0.029 EXPOSED PAD 0.350 L Exposed 0.175 Pad 16 9 0.050 BACK SIDE CL 0.188 0.200 0.376 CL 0.074 0.024 0.150 DIMENSIONS: INCHES *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5773−3850 Sales Representative http://onsemi.com NCV8501/D 16

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: NCV8501D100 NCV8501D100G NCV8501D100R2 NCV8501D100R2G NCV8501D25 NCV8501D25G NCV8501D25R2 NCV8501D25R2G NCV8501D33 NCV8501D33G NCV8501D33R2 NCV8501D33R2G NCV8501D50 NCV8501D50G NCV8501D50R2 NCV8501D50R2G NCV8501D80 NCV8501D80G NCV8501D80R2 NCV8501D80R2G NCV8501DADJR2G NCV8501PDW33R2G NCV8501PDW50R2G NCV8501PDW80 NCV8501PDW80G NCV8501PDW80R2 NCV8501PDW80R2G NCV8501PDWADJ NCV8501PDWADJG NCV8501PDWADJR2