NCV7356 Single Wire CAN Transceiver The NCV7356 is a physical layer device for a single wire data link capable of operating with various Carrier Sense Multiple Access with Collision Resolution (CSMA/CR) protocols such as the Bosch Controller Area Network (CAN) version 2.0. This serial data link network is intended for use in applications where high data rate is not www.onsemi.com required and a lower data rate can achieve cost reductions in both the physical media components and in the microprocessor and/or MARKING DIAGRAMS dedicated logic devices which use the network. 8 8 The network shall be able to operate in either the normal data rate 1 V7356 mode or a high−speed data download mode for assembly line and ALYW SOIC−8 (cid:2) service data transfer operations. The high−speed mode is only D SUFFIX 1 intended to be operational when the bus is attached to an off−board CASE 751 service node. This node shall provide temporary bus electrical loads 14 which facilitate higher speed operation. Such temporary loads should 14 NCV7356G be removed when not performing download operations. AWLYWW 1 The bit rate for normal communications is typically 33 kbit/s, for SOIC−14 1 high−speed transmissions like described above a typical bit rate of D SUFFIX A = Assembly Location 83 kbit/s is recommended. The NCV7356 features undervoltage CASE 751A WL, L = Wafer Lot lockout, timeout for faulty blocked input signals, output blanking Y = Year time in case of bus ringing and a very low sleep mode current. WW, W = Work Week The device is compliant with GMW3089V2.4 (cid:2) or G = Pb−Free Package General Motors Corporation specification. PIN CONNECTIONS Features TxD 1 8 GND • Fully Compatible with J2411 Single Wire CAN Specification MODE0 2 7 CANH • 60 (cid:2)A (max) Sleep Mode Current MODE1 3 6 LOAD • Operating Voltage Range 5.0 to 27 V RxD 4 5 VBAT • Up to 100 kbps High−Speed Transmission Mode (Top View) • Up to 40 kbps Bus Speed GND 1 14 GND • Selective BUS Wake−Up TxD 2 13 NC • Logic Inputs Compatible with 3.3 V and 5 V Supply Systems MODE0 3 12 CANH • Control Pin for External Voltage Regulators (14 Pin Package Only) MODE1 4 11 LOAD • Standby to Sleep Mode Timeout RxD 5 10 VBAT • Low RFI Due to Output Wave Shaping NC 6 9 INH • Fully Integrated Receiver Filter GND 7 8 GND • Bus Terminals Short−Circuit and Transient Proof (Top View) • Loss of Ground Protection ORDERING INFORMATION • Protection Against Load Dump, Jump Start Device Package Shipping† • Thermal Overload and Short Circuit Protection NCV7356D1G SOIC−8 98 Units / Rail • ESD Protection of 4.0 kV on CANH Pin (2.0 kV on Any Other Pin) (Pb−Free) • Undervoltage Lock Out NCV7356D1R2G SOIC−8 2500 Tape & Reel (Pb−Free) • Bus Dominant Timeout Feature • NCV7356D2G SOIC−14 55 Units / Rail Internally Fused Leads in SO−14 Package (Pb−Free) • NCV Prefix for Automotive and Other Applications Requiring NCV7356D2R2G SOIC−14 2500 Tape & Reel Unique Site and Control Change Requirements; AEC−Q100 (Pb−Free) Qualified and PPAP Capable †For information on tape and reel specifications, • including part orientation and tape sizes, please These Devices are Pb−Free and are RoHS Compliant refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: January, 2017 − Rev. 13 NCV7356/D

NCV7356 VBAT NCV7356 5 V Supply Biasing and and References VBAT Monitor Reverse −IIL_TxD Current Protection RC−OSC 3.6 V (max)* Pull−Up Voltage Wave Shaping CAN Driver CANH TxD Time Out Feedback Loop RL Input Filter MODE0 LOAD MODE CONTROL MODE1 Loss of Receive Ground Comparator Detection RxD Reverse RxD Blanking Current Time Filter Protection GND *Not tested in production, guaranteed by design. Figure 1. 8−Pin Package Block Diagram www.onsemi.com 2

NCV7356 VBAT INH NCV7356 5 V Supply Biasing and and References VBAT Monitor Reverse −IIL_TxD Current Protection RC−OSC 3.6 V (max)* Pull−Up Voltage Wave Shaping CAN Driver CANH TxD Time Out Feedback Loop RL Input Filter MODE0 LOAD MODE CONTROL MODE1 Loss of Receive Ground Comparator Detection RxD Reverse RxD Blanking Current Time Filter Protection GND *Not tested in production, guaranteed by design. Figure 2. 14−Pin Package Block Diagram www.onsemi.com 3

NCV7356 PACKAGE PIN DESCRIPTION SOIC−8 SOIC−14 Symbol Description 1 2 TxD Transmit data from microprocessor to CAN. 2 3 MODE0 Operating mode select input 0. 3 4 MODE1 Operating mode select input 1. 4 5 RxD Receive data from CAN to microprocessor. 5 10 VBAT Battery input voltage. 6 11 LOAD Resistor load (loss of ground detection low side switch). 7 12 CANH Single wire CAN bus pin. 8 1, 7, 8, 14 GND Ground − 6, 13 NC No Connection (Note 1) − 9 INH Control pin for external voltage regulator (high voltage high side switch) (14 pin package only) 1. PWB terminal 13 can be connected to ground which will allow the board to be assembled with either the 8 pin package or the 14 pin package. www.onsemi.com 4

NCV7356 Electrical Specification All voltages are referenced to ground (GND). Positive permanent damage of the device but exceeding any of these currents flow into the IC. The maximum ratings given in limits may do so. Long term exposure to limiting values the table below are limiting values that do not lead to a may affect the reliability of the device. MAXIMUM RATINGS Rating Symbol Condition Min Max Unit Supply Voltage, Normal Operation VBAT − −0.3 18 V Short−Term Supply Voltage, Transient VBAT.LD Load Dump; t < 500 ms − 40 V (peak) Jump Start; t < 1.0 min − 27 V Transient Supply Voltage VBAT.TR1 ISO 7637/1 Pulse 1 (Note 2) −50 − V Transient Supply Voltage VBAT.TR2 ISO 7637/1 Pulses 2 (Note 2) − 100 V Transient Supply Voltage VBAT.TR3 ISO 7637/1 Pulses 3A, 3B −200 200 V CANH Voltage VCANH VBAT < 27 V −20 V 40 VBAT = 0 V −40 Transient Bus Voltage VCANHTR1 ISO 7637/1 Pulse 1 (Note 3) −50 − V Transient Bus Voltage VCANHTR2 ISO 7637/1 Pulses 2 (Note 3) − 100 V Transient Bus Voltage VCANHTR3 ISO 7637/1 Pulses 3A, 3B (Note 3) −200 200 V DC Voltage on Pin LOAD VLOAD Via RT > 2.0 k(cid:3) −40 40 V DC Voltage on Pins TxD, MODE1, MODE0, RxD VDC − −0.3 7.0 V ESD Capability of CANH VESDBUS Human Body Model −4000 4000 V (Note 4) (with respect to VBAT and GND) Eq. to Discharge 100 pF with 1.5 k(cid:3) ESD Capability of Any Other Pin VESD Human Body Model −2000 2000 V (Note 4) Eq. to Discharge 100 pF with 1.5 k(cid:3) Maximum Latchup Free Current at Any Pin ILATCH − −500 500 mA Storage Temperature TSTG − −55 150 °C Junction Temperature TJ − −40 150 °C Peak Reflow Soldering Temperature: Pb−Free, 60 s to 150 s above 217°C (Note 5) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. ISO 7637 test pulses are applied to VBAT via a reverse polarity diode and >1.0 (cid:2)F blocking capacitor. 3. ISO 7637 test pulses are applied to CANH via a coupling capacitance of 1.0 nF. 4. ESD measured per Q100−002 (EIA/JESD22−A114−A). 5. For additional information, please see or download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. TYPICAL THERMAL CHARACTERISTICS Test Condition, Typical Value Parameter Min Pad Board 1(cid:2) Pad Board Unit SOIC−8 Junction−to−Lead (psi−JL7, (cid:4)JL8) or Pins 6−7 57 (Note 6) 51 (Note 7) °C/W Junction−to−Ambient (R(cid:5)JA, (cid:5)JA) 187 (Note 6) 128 (Note 7) °C/W SOIC−14 Junction−to−Lead (psi−JL8, (cid:4)JL8) 30 (Note 8) 30 (Note 9) °C/W Junction−to−Ambient (R(cid:5)JA, (cid:5)JA) 122 (Note 8) 84 (Note 9) °C/W 6. 1 oz copper, 53 mm2 coper area, 0.062″ thick FR4. 7. 1 oz copper, 716 mm2 coper area, 0.062″ thick FR4. 8. 1 oz copper, 94 mm2 coper area, 0.062″ thick FR4. 9. 1 oz copper, 767 mm2 coper area, 0.062″ thick FR4. www.onsemi.com 5

NCV7356 ELECTRICAL CHARACTERISTICS (VBAT = 5.0 to 27 V, TA = −40 to +125°C, unless otherwise specified.) Characteristic Symbol Condition Min Typ Max Unit GENERAL Undervoltage Lock Out VBATuv − 3.5 − 4.8 V Supply Current, Recessive, IBATN VBAT = 18 V, Not High Speed Mode − 5.0 6.0 mA All Active Modes TxD Open High Speed Mode − − 8.0 Normal Mode Supply Current, IBATN VBAT = 27 V, MODE0 = MODE1 = H, − 30 35 mA Dominant (Note 11) TxD = L, RL = 200 (cid:3) High−Speed Mode Supply Current, IBATN VBAT = 16 V, MODE0 = H, MODE1 = L, − 70 75 mA Dominant (Note 11) TxD = L, RL = 75 (cid:3) Wake−Up Mode Supply Current, IBATW VBAT = 27 V, − 60 75 mA Dominant (Note 11) MODE0 = L, MODE1 = H, TxD = L, RL = 200 (cid:3) Sleep Mode Supply Current (Note 10) IBATS VBAT = 13 V, TA = 85°C, − 30 60 (cid:2)A TxD, RxD, MODE0, MODE1 Open Thermal Shutdown (Note 11) TSD − 155 − 180 °C Thermal Recovery (Note 11) TREC − 126 − 150 °C CANH Bus Output Voltage Voh RL > 200 (cid:3), Normal Mode 4.4 − 5.1 V 6.0 V < VBAT < 27 V Bus Output Voltage Voh RL > 200 (cid:3), Normal High−Speed Mode 3.4 − 5.1 V Low Battery 5.0 V < VBAT < 6.0 V Bus Output Voltage Voh RL > 75 (cid:3), High−Speed Mode 4.2 − 5.1 V High−Speed Mode 8.0 V < VBAT < 16 V HV Fixed Wake−Up VohWuFix Wake−Up Mode, RL > 200 (cid:3), 9.9 − 12.5 V Output High Voltage 11.4 V < VBAT < 27 V HV Offset Wake−Up VohWuOffset Wake−Up Mode, RL > 200 (cid:3), VBAT –1.5 − VBAT V Output High Voltage 5.0 V < VBAT < 11.4 V Recessive State Vol Recessive State or Sleep Mode, −0.20 − 0.20 V Output Voltage RL = 6.5 k(cid:3) Bus Short Circuit Current −ICAN_SHORT VCANH = 0 V, VBAT = 27 V, TxD = 0 V 50 − 350 mA Bus Leakage Current ILKN_CAN Loss of Ground, VCANH = 0 V −50 − 10 (cid:2)A During Loss of Ground (Note 12) Bus Leakage Current, Bus Positive ILKP_CAN TxD High −10 − 10 (cid:2)A Bus Input Threshold Vih Normal, High−Speed Mode, HVWU 2.0 2.1 2.2 V 6.0 (cid:2) VBAT (cid:2) 27 V Bus Input Threshold Low Battery Vihlb Normal, VBAT = 5.0 V to 6.0 V 1.6 1.7 2.2 V Fixed Wake−Up from Sleep VihWuFix Sleep Mode, VBAT > 10.9 V 6.6 − 7.9 V Input High Voltage Threshold (Note 11) Offset Wake−Up from Sleep VihWuOffset Sleep Mode VBAT −4.3 − VBAT −3.25 V Input High Voltage Threshold (Note 11) LOAD Voltage on Switched Ground Pin VLOAD_1mA ILOAD = 1.0 mA − − 0.1 V Voltage on Switched Ground Pin VLOAD ILOAD = 5.0 mA − − 0.5 V Voltage on Switched Ground Pin VLOAD_LOB ILOAD = 7.0 mA, VBAT = 0 V − − 1.0 V Load Resistance During Loss of RLOAD_LOB VBAT = 0 RL −10% − RL +35% (cid:3) Battery 10.Characterization data supports IBATS < 65 (cid:2)A with conditions VBAT = 18 V, TA = 125°C 11.Thresholds not tested in production, guaranteed by design. 12.Leakage current in case of loss of ground is the summary of both currents ILKN_CAN and ILKN_LOAD. www.onsemi.com 6

NCV7356 ELECTRICAL CHARACTERISTICS (continued) (VBAT = 5.0 to 27 V, TA = −40 to +125°C, unless otherwise specified.) Characteristic Symbol Condition Min Typ Max Unit TXD, MODE0, MODE1 High Level Input Voltage Vih 6.0 < VBAT < 27 V 2.0 − − V Low Level Input Voltage Vil 6.0 < VBAT < 27 V − − 0.8 V TxD Pullup Current −IIL_TXD TxD = L, MODE0 and 1 = H 10 − 50 (cid:2)A 5.0 < VBAT < 27 V MODE0 and 1 Pulldown Resistor RMODE_pd 10 − 50 k(cid:3) RXD Low Level Output Voltage Vol_rxd IRxD = 2.0 mA − − 0.4 V High Level Output Leakage Iih_rxd VRxD = 5.0 V −10 − 10 (cid:2)A RxD Output Current Irxd VRxD = 5.0 V − − 70 mA INH (14 Pin Package Only) High Level Output Voltage Voh_INH IINH = −180 (cid:2)A VBAT −0.8 VBAT −0.5 VBAT V Leakage Current IINH_lk MODE0 = MODE1 = L, INH = 0 V −5.0 − 5.0 (cid:2)A Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. TYPICAL CHARACTERISTICS 35 35 30 30 T T N N E 25 E 25 R R R R U U C 20 C 20 Y Y L L PP 15 PP 15 U U S S , T 10 , T 10 A A B B V V 5 5 VBAT = 27 V 0 0 5 10 15 20 25 −40 −20 0 20 40 60 80 100 120 VBAT TEMPERATURE (°C) Figure 3. Normal Mode Supply Current Figure 4. Normal Mode Supply Current Dominant vs. V Dominant vs. Temperature BAT 60 A) (cid:2) NT ( 50 E R R U 40 C Y L P 30 P U S E 20 D O M P 10 E E L S 0 −40 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 5. Sleep Mode Supply Current vs. Temperature www.onsemi.com 7

NCV7356 TIMING MEASUREMENT LOAD CONDITIONS Normal and High Voltage Wake−Up Mode High−Speed Mode min load / min tau 3.3 k(cid:3) / 540 pF Additional 140 (cid:3) tool resistance to ground in parallel min load / max tau 3.3 k(cid:3) / 1.2 nF max load / min tau 200 (cid:3) / 5.0 nF Additional 120 (cid:3) tool resistance to ground in parallel max load / max tau 200 (cid:3) / 20 nF ELECTRICAL CHARACTERISTICS (5.0 V ≤ VBAT ≤ 27 V, −40°C ≤ TA ≤ 125°C, unless otherwise specified.) AC CHARACTERISTICS (See Figures 6, 7, and 8) Characteristic Symbol Condition Min Typ Max Unit Transmit Delay in Normal and Wake−Up Mode, tTr Min and Max Loads per Timing 2.0 − 6.3 (cid:2)s Bus Rising Edge (Notes 13, 14) Measurement Load Conditions Transmit Delay in Wake−Up Mode to VihWU, tTWUr Min and Max Loads per Timing 2.0 − 18 (cid:2)s Bus Rising Edge (Notes 13, 15) Measurement Load Conditions Transmit Delay in Normal Mode, tTf Min and Max Loads per Timing 1.8 − 10 (cid:2)s Bus Falling Edge (Notes 16, 17) Measurement Load Conditions Transmit Delay in Wake−Up Mode, tTWU1f Min and Max Loads per Timing 3.0 − 13.7 (cid:2)s Bus Falling Edge (Notes 16, 17) Measurement Load Conditions Transmit Delay in High−Speed Mode, tTHSr Min and Max Loads per Timing 0.1 − 1.5 (cid:2)s Bus Rising Edge (Notes 13, 18) Measurement Load Conditions Transmit Delay in High−Speed Mode, tTHSf Min and Max Loads per Timing 0.04 − 3.0 (cid:2)s Bus Falling Edge (Notes 17, 19) Measurement Load Conditions Receive Delay, All Active Modes (Note 20) tDR CANH High to Low Transition 0.3 − 1.0 (cid:2)s Receive Delay, All Active Modes (Note 20) tRD CANH Low to High Transition 0.3 − 1.0 (cid:2)s Input Minimum Pulse Length, tmpDR CANH High to Low Transition 0.1 − 1.0 (cid:2)s All Active Modes (Note 18) tmpRD CANH Low to High Transition 0.1 − 1.0 Wake−Up Filter Time Delay tWUF See Figure 7 10 − 70 (cid:2)s Receive Blanking Time, After TxD L−H Transition trb See Figure 8 0.5 − 6.0 (cid:2)s TxD Timeout Reaction Time ttout Normal and High−Speed Mode − 17 − ms TxD Timeout Reaction Time ttoutwu Wake−Up Mode − 17 − ms Delay from Normal to High−Speed and tdnhs − − − 30 ms High Voltage Wake−Up Mode Delay from High−Speed and High Voltage tdhsn − − − 30 ms Wake−Up to Normal Mode Delay from Normal to Standby Mode tdsby VBAT = 6.0 V to 27 V − − 500 (cid:2)s Delay from Sleep to Normal Mode tdsnwu VBAT = 6.0 V to 27 V − − 50 ms Delay from Sleep to High Voltage Mode tdshv VBAT = 6.0 V to 27 V − − 50 ms Delay from Standby to Sleep Mode (Note 21) tdsleep VBAT = 6.0 V to 27 V 100 250 500 ms 13.Minimum signal delay time is measured from the TxD voltage threshold to CANH = 1.0 V. (cid:6) load should be min per the Timing Measurement Load Conditions table. 14.Maximum signal delay time is measured from the TxD voltage threshold to CANH = 3.5 V at VBAT = 27 V, CANH = 2.8 V at VBAT = 5.0 V. (cid:6) load should be max per the Timing Measurement Load Conditions table. 15.Maximum signal delay time is measured from the TxD voltage threshold to CANH = 9.2 V. Vihwumax = Vihwufix, max + Vgoff = 7.9 V + 1.3 V = 9.2 V. (cid:6) load should be max per the Timing Measurement Load Conditions table. 16.Minimum signal delay time is measured from the TxD voltage threshold to CANH = 3.5 V at VBAT = 27 V, CANH = 2.8 V at VBAT = 5.0 V. (cid:6) load should be min per the Timing Measurement Load Conditions table. 17.Maximum signal delay time is measured from the TxD voltage threshold to CANH = 1 V. (cid:6) load should be max per the Timing Measurement Load Conditions table. 18.Maximum signal delay time is measured from the TxD voltage threshold to CANH = 3.5 V. (cid:6) load should be max per the Timing Measurement Load Conditions table. 19.Minimum signal delay time is measured from the TxD voltage threshold to CANH = 3.5 V. (cid:6) load should be min per the Timing Measurement Load Conditions table. 20.Receive delay time is measured from the rising / falling edge crossing of the nominal Vih value on CANH to the falling (Vcmos_il_max) / rising (Vcmos_ih_min) edge of RxD. This parameter is tested by applying a square wave signal to CANH. The minimum slew rate for the bus rising and falling edges is 50 V/(cid:2)s. The low level on bus is always 0 V. For normal mode and high−speed mode testing the high level on bus is 4 V. For HVWU mode testing the high level on bus is VBAT − 2 V. Relaxation of this non−critical parameter from 0.15 (cid:2)s to 0.10 (cid:2)s may be addressed in future revisions of GMW3089. 21.Tested on 14 Pin package only. www.onsemi.com 8

NCV7356 BUS LOADING REQUIREMENTS Characteristic Symbol Min Typ Max Unit Number of System Nodes − 2 − 32 − Network Distance Between Any Two ECU Nodes Bus Length − − 60 m Node Series Inductor Resistance (If required) Rind − − 3.5 (cid:3) Ground Offset Voltage Vgoff − − 1.3 V Ground Offset Voltage, Low Battery Vgofflowbat − 0.1 x VBAT 0.7 V Device Capacitance (Unit Load) Cul 135 150 300 pF Network Total Capacitance Ctl 396 − 19000 pF Device Resistance (Unit Load) Rul 6435 6490 6565 (cid:3) Device Resistance (Min Load) Rmin 2000 − − (cid:3) Network Total Resistance Rtl 200 − 4596 (cid:3) Network Time Constant (Note 22) (cid:6) 1.0 − 4.0 (cid:2)s Network Time Constant in High−Speed Mode (cid:6) − − 1.5 (cid:2)s High−Speed Mode Network Resistance to GND Rload 75 − 135 (cid:3) 22.The network time constant incorporates the bus wiring capacitance. The minimum value is selected to limit radiated emission. The maximum value is selected to ensure proper communication modes. Not all combinations of R and C are possible. TIMING DIAGRAMS VTxD 50% t tTr tTf VCANH t tRD tDR VRxD 50% t Figure 6. Input/Output Timing www.onsemi.com 9

NCV7356 TIMING DIAGRAMS VCANH Vih + Vgoff t tWU tWU tWUF VRxD wake−up tWU < tWUF interrupt t Figure 7. Wake−Up Filter Time Delay VTxD 50% t VCANH Vih t VRxD 50% t tRB Figure 8. Receive Blanking Time www.onsemi.com 10

NCV7356 FUNCTIONAL DESCRIPTION TxD Input Pin disabled in this mode. Bus transmitter drive circuits for TxD Polarity those nodes which are required to communicate in • high−speed mode are able to drive reduced bus resistance TxD = logic 1 (or floating) on this pin produces an in this mode. undriven or recessive bus state (low bus voltage) • TxD = logic 0 on this pin produces either a bus normal High Voltage Wake−Up Mode or a bus high voltage dominant state depending on the This bus includes a selective node awake capability, transceiver mode state (high bus voltage) which allows normal communication to take place among If the TxD pin is driven to a logic low state while the sleep some nodes while leaving the other nodes in an undisturbed mode (Mode 0 = 0 and Mode 1 = 0) is activated, the sleep state. This is accomplished by controlling the signal transceiver can not drive the CANH pin to the dominant voltages such that all nodes must wake−up when they state. receive a higher voltage message signal waveform. The The transceiver provides an internal pull−up current on communication system communicates to the nodes the TxD pin (only in active modes [High−Speed Mode, information as to which nodes are to stay operational High Voltage Wake−Up, and Normal Mode]) which will (awake) and which nodes are to put themselves into a non cause the transmitter to default to the bus recessive state communicating low power “sleep” state. Communication when TxD is not driven. The internal current source at the lower, normal voltage levels shall not disturb the circuitry limits the voltage pull−up level to be compatible sleeping nodes. with 3.3 V logic. The TxD pull−up current source is not active in Sleep Mode. Normal Mode TxD input signals are standard CMOS logic levels. Transmission bit rate in normal communication is 33 Kbits/s. In normal transmission mode the NCV7356 Timeout Feature supports controlled waveform rise and overshoot times. In case of a faulty blocked dominant TxD input signal, Waveform trailing edge control is required to assure that the CANH output is switched off automatically after the high frequency components are minimized at the specified TxD timeout reaction time to prevent a dominant beginning of the downward voltage slope. The remaining bus. fall time occurs after the bus is inactive with drivers off and The transmission is continued by next TxD L to H is determined by the RC time constant of the total bus load. transition without delay. RxD Output Pin MODE0 and MODE1 Pins Logic data as sensed on the single wire CAN bus. The transceiver provides a weak internal pulldown RxD Polarity current on each of these pins which causes the transceiver • RxD = logic 1 on this pin indicates a bus recessive to default to sleep mode when they are not driven. The state (low bus voltage) mode input signals are standard CMOS logic level for • RxD = logic 0 on this pin indicates a bus normal or 3.3 V and 5 V supply voltages. See Electrical high voltage bus dominant state Characteristics table for timing limitations for mode changes. RxD in Sleep Mode RxD does not pass signals to the microprocessor while in MODE0 MODE1 Mode sleep mode until a valid wake−up bus voltage level is L L Sleep Mode received or the MODE0 and MODE 1 pins are not 0, 0 respectively. When the valid wake−up bus voltage signal H L High−Speed Mode awakens the transceiver, the RxD pin signals an interrupt L H High Voltage Wake−Up (logic 0). If there is no mode change within 250 ms (typ), H H Normal Mode the transceiver re−enters the sleep mode. When not in sleep mode all valid bus signals will be sent Sleep Mode out on the RxD pin. Transceiver is in low power state, waiting for wake−up RxD will be placed in the undriven or off state when in via high voltage signal or by mode pins change to any state sleep mode. other than 0,0. In this state, the CANH pin is not in the RxD Typical Load dominant state regardless of the state of the TxD pin. Resistance: 2.7 k(cid:3) Capacitance: < 25 pF High−Speed Mode This mode allows high−speed download with bit rates up to 100 Kbit/s. The output wave shapingaping circuit is www.onsemi.com 11

NCV7356 Bus LOAD Pin mode and can operate higher 75 (cid:3) loads for High−Speed Mode. The minimum output driver capability is 50 mA, but Bus LOAD Pin Description output shorts to ground can reach 350mA. The bus LOAD pin provides a network load impedance Normal CANH output voltages are between 4.4 V and program point for the CAN bus. The value of the resistor 5.1 V. These amplitudes increase to between 9.9 V and 12.5 V between the CANH and LOAD pins can be adjusted to for selective system IC selection in Wake−Up Mode. provide adequate impedance for the bus loading The CANH pin also acts as a bus read amplifier. The Bus requirements as dictated by the Single Wire CAN Wake−Up from Sleep Input Voltage Threshold is between Specification (J2411). 6.6 V and 7.9 V, but to maintain normal communication, The resistor between CANH and LOAD pins provides a the threshold is 2.1 V. pull down impedance for the CANH pin. The CANH driver is a pull−up amplifier with no sink capability. Wave Shaping in Normal and High Voltage Wake−Up The bus LOAD pin also provides the detection circuitry Mode for loss of ground detection to insure there are no loading Wave shaping is incorporated into the transmitter to effects on the bus should the ground connection be lost to minimize EMI radiated emissions. An important the NCV7356 device. During a system loss of ground contributor to emissions is the rise and fall times during event, CANH with the 6.49 k(cid:3) resistor between CANH and output transitions at the “corners” of the voltage waveform. LOAD will affect the bus with only between −50 (cid:2)A and The resultant waveform is one half of a sin wave of 10 (cid:2)A of current (Bus Leakage Current During Loss of frequency 50−65 kHz at the rising waveform edge and one Ground). quarter of this sin wave at falling or trailing edge. Resistor ground connection with internal open−on−loss− Wave Shaping in High−Speed Mode of−ground protection Wave shaping control of the rising and falling waveform When the ECU experiences a loss of ground condition, edges are disabled during high−speed mode. EMI this pin is switched to a high impedance state. emissions requirements are waived during this mode. The The ground connection through this pin is not interrupted waveform rise time in this mode is less than 1.0 (cid:2)s. in any transceiver operating mode including the sleep mode. The ground connection only is interrupted when Short Circuits there is a valid loss of ground condition. If the CAN BUS pin is shorted to ground for any duration This pin provides the bus load resistor with a path to of time, the current is limited as specified in the Electrical ground which contributes less than 0.1 V to the bus offset Characteristics Table until an overtemperature shutdown voltage when sinking the maximum current through one circuit disables the output high side drive source transistor unit load resistor. This path exists in all operating modes, preventing damage to the IC. including the sleep mode. Loss of Ground The transceiver’s maximum bus leakage current In case of a valid loss of ground condition, the LOAD pin contribution to V from the LOAD pin when in a loss of ol is switched into high impedance state. The CANH ground state is 50 (cid:2)A over all operating temperatures and transmission is continued until the undervoltage lock out 3.5 < V < 27 V. BAT voltage threshold is detected. VBAT Input Pin Loss of Battery In case of loss of battery (V = 0 or open) the Vehicle Battery Voltage BAT transceiver does not disturb bus communication. The The transceiver is fully operational as described in the maximum reverse current into the power supply system Electrical Characteristics Table over the range 6.0 V < VBAT < 18 V as measured between the GND pin and the (VBAT) doesn’t exceed 500 (cid:2)A. V pin. BAT INH Pin (14 pin package only) For 5.0 V < V < 6.0 V, the bus operates in normal Bat The INH pin is a high−voltage highside switch used to mode with reduced dominant output voltage and reduced control the ECU’s regulated microcontroller power supply. receiver input voltage. High voltage wake−up is not After power−on, the transceiver automatically enters an possible (dominant output voltage is the same as in normal intermediate standby mode, the INH output will go high or high−speed mode). (up to V ) turning on the external voltage regulator. The BAT The transceiver operates in normal mode when 18 V < external regulator provides power to the ECU. If there is no V < 27 V at 85°C for one minute. Bat mode change within 250 ms (typ), the transceiver re−enters the sleep mode and the INH output goes to logic 0 CAN BUS (floating). Input/Output Pin When the transceiver has detected a valid wake−up The CANH pin is composed of a pull−up amplifier (no condition (bus HVWU traffic which exceeds the wake−up sink capability) for driving the single−wire CAN bus. It is filter time delay) the INH output will become high (up to designed to drive a 200 (cid:3) load when operating in normal www.onsemi.com 12

NCV7356 V ) again and the same procedure starts as described V ). If the transceiver enters the sleep mode, INH goes BAT BAT after power−on. In case of a mode change into any active to logic 0 (floating) after 250 ms (typ) when no wake−up mode, the sleep timer is stopped and INH stays high (up to signal is present. HVWU Mode MODE0 MODE1 low high MODE0/1 => High High−Speed Mode MODE0 MODE1 VBATon high low MODE0&1 => Low Normal Mode MODE0 MODE1 high high MODE0/1 => High (If VCC_ECU on) V standby BAT after 250 ms MODE0/1 RxD CAN −> no mode change low high/low(1) float −> no valid wake−up wake−up request from Bus Sleep Mode MODE0/1 CAN low float (1) low after HVWU, high after VBAT on & VCCECU present Figure 9. State Diagram, 8 Pin Package www.onsemi.com 13

NCV7356 HVWU Mode MODE0 MODE1 INH low high VBAT MODE0/1 => High High−Speed Mode MODE0 MODE1 INH VBATon high low VBAT MODE0&1 => Low Normal Mode MODE0 MODE1 INH high high VBAT MODE0/1 => High (If VCC_ECU on) V standby BAT after 250 ms MODE0/1 INH RxD CAN −> no mode change −> no valid wake−up low VBAT high/low(1) float wake−up request from Bus Sleep Mode MODE0/1 INH/CAN low floating (1) low after HVWU, high after VBAT on & VCCECU present Figure 10. State Diagram, 14 Pin Package www.onsemi.com 14

NCV7356 MRA4004T3 VBAT * + VBAT_ECU Voltage Regulator VBAT +5 V 100 nF ECU Connector to Single Wire CAN Bus 100 pF + 2.7 k(cid:3) VBAT 1 k 5 4 47 (cid:2)H RxD 7 er CANH oll Contr 2 NCV7356 6.49 k(cid:3) 100 pF N MODE0 A C 3 MODE1 6 LOAD ESD Protection − 1 TxD NUP1105L 8 GND *Recommended capacitance at VBAT_ECU > 1.0 (cid:2)F (immunity to ISO7637/1 test pulses) Figure 11. Application Circuitry, 8 Pin Package www.onsemi.com 15

NCV7356 MRA4004T3 VBAT * + VBAT_ECU Voltage Regulator INH VBAT +5 V 100 nF ECU Connector to Single Wire CAN Bus 100 pF + 2.7 k(cid:3) VBAT 1 k 9 10 5 47 (cid:2)H RxD 12 er CANH Controll 3 NCV7356 6.49 k(cid:3) 100 pF N MODE0 A C 4 MODE1 11 LOAD ESD Protection − 2 TxD NUP1105L 1, 7, 8, 14 GND *Recommended capacitance at VBAT_ECU > 1.0 (cid:2)F (immunity to ISO7637/1 test pulses) Figure 12. Application Circuitry, 14 Pin Package www.onsemi.com 16

NCV7356 SOIC−8 Thermal Information Test Condition, Typical Value Min Pad Board 1(cid:2) Pad Board Parameter (Note 23) (Note 24) Unit Junction−to−Lead (psi−JL7, (cid:4)JL8) or Pins 6−7 57 51 °C/W Junction−to−Ambient (R(cid:5)JA, (cid:5)JA) 187 128 °C/W 23.1 oz copper, 53 mm2 coper area, 0.062″ thick FR4. 24.1 oz copper, 716 mm2 coper area, 0.062″ thick FR4. Package Construction with and without Mold Compound Various copper areas used for heat spreading Active Area (red) Lead #1 Figure 13. Internal construction of the Figure 14. Min pad is shown as the red traces. package simulation. 1(cid:2) pad includes the yellow area. Internal construction is shown for later reference. 190 180 170 160 1.0 oz. Cu W) C/150 ° (A140 J (cid:5) 2.0 oz. Cu 130 120 110 100 0 100 200 300 400 500 600 700 800 Copper Area (mm2) Figure 15. SOIC−8, (cid:2) as a Function of the Pad Copper JA Area Including Traces, Board Material www.onsemi.com 17

NCV7356 Table 1. SOIC−8 Thermal RC Network Models* 53 mm2 719 mm2 Copper Area 53 mm2 719 mm2 Copper Area Cauer Network Foster Network C’s C’s Units Tau Tau Units 5.86E−06 5.86E−06 W−s/C 1.00E−06 1.00E−06 sec 2.29E−05 2.29E−05 W−s/C 1.00E−05 1.00E−05 sec 6.98E−05 6.97E−05 W−s/C 1.00E−04 1.00E−04 sec 3.68E−04 3.68E−04 W−s/C 1.99E−04 1.99E−04 sec 3.75E−04 3.74E−04 W−s/C 1.00E−03 1.00E−03 sec 1.57E−03 1.56E−03 W−s/C 1.64E−02 1.64E−02 sec 2.05E−02 2.24E−02 W−s/C 5.60E−01 5.60E−01 sec 9.13E−02 7.35E−02 W−s/C 4.50E+00 4.50E+00 sec 2.64E−01 1.22E+00 W−s/C 7.61E+01 7.61E+01 sec 1.66E+01 9.74E+00 W−s/C 3.00E+01 3.00E+01 sec R’s R’s R’s R’s 0.22 0.22 C/W 1.30E−01 1.30E−01 C/W 0.50 0.50 C/W 2.82E−01 2.82E−01 C/W 1.30 1.30 C/W 8.91E−01 8.91E−01 C/W 1.80 1.79 C/W 0.17 0.18 C/W 0.95 0.96 C/W 1.88 1.88 C/W 7.43 7.37 C/W 7.15 7.24 C/W 31.19 31.59 C/W 19.80 16.27 C/W 59.97 47.70 C/W 30.1 54.7 C/W 75.79 28.63 C/W 14.1 23.3 C/W 4.41 6.15 C/W 109.0 21.3 C/W *Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in the Foster network are computed by the square root of time constant R(t) = 130 * sqrt(time(sec)). The constant is derived based on the active area of the device with silicon and epoxy at the interface of the heat generation. The Cauer networks generally have physical using circuit simulating tools, whereas Foster networks significance and may be divided between nodes to separate may be more easily implemented using mathematical tools thermal behavior due to one portion of the network from (for instance, in a spreadsheet program), according to the another. The Foster networks, though when sorted by time following formula: constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. R(t)(cid:3) (cid:7)n Ri(cid:4)1−e−t(cid:5)taui(cid:6) Both Foster and Cauer networks can be easily implemented i(cid:3)1 www.onsemi.com 18

NCV7356 Junction R1 R2 R3 Rn C1 C2 C3 Cn Time constants are not simple RC products. Ambient Amplitudes of mathematical solution are not the resistance values. (thermal ground) Figure 16. Grounded Capacitor Thermal Network (“Cauer” Ladder) Junction R1 R2 R3 Rn C1 C2 C3 Cn Each rung is exactly characterized by its RC−product time constant; Am- Ambient plitudes are the resistances (thermal ground) Figure 17. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder) 1000 Cu Area = 53 mm2 1.0 oz. Cu Area = 93 mm2 1.0 oz. 100 Cu Area = 719 mm2 1.0 oz. W) C/ 10 ° ((cid:5) R 1 0.1 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 Time (s) Figure 18. SOIC−8 Single Pulse Heating Curve 1000 100 D = 0.50 0.20 W) 0.10 °C/ 10 0.05 ((cid:5) R 0.02 1 0.01 Single Pulse 0.1 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 Time (s) Figure 19. SOIC−8 Thermal Duty Cycle Curves on 1(cid:2) Spreader Test Board www.onsemi.com 19

NCV7356 SOIC−14 Thermal Information Test Condition, Typical Value Min Pad Board 1(cid:2) Pad Board Parameter (Note 25) (Note 26) Unit Junction−to−Lead (psi−JL8, (cid:4)JL8) 30 30 °C/W Junction−to−Ambient (R(cid:5)JA, (cid:5)JA) 122 84 °C/W 25.1 oz copper, 94 mm2 coper area, 0.062″ thick FR4. 26.1 oz copper, 767 mm2 coper area, 0.062″ thick FR4. Figure 21. Min pad is shown as the red traces. Figure 20. Internal construction of the package 1 inch pad includes the yellow area. Pin 1, 7, 8 and simulation. 14 are connected to flag internally to the package and externally to the heat spreading area. 150 140 130 120 W) 1.0 oz. Cu C/ 110 ° (A 100 Sim 1.0 oz. (cid:5)J 2.0 oz. Cu Sim 2.0 oz. 90 80 70 60 0 100 200 300 400 500 600 700 800 900 Copper Area (mm2) Figure 22. SOIC−14, (cid:2) as a Function of the Pad Copper Area Including Traces, JA Board Material www.onsemi.com 20

NCV7356 Table 2. SOIC−14 Thermal RC Network Models* 96 mm2 767 mm2 Copper Area 96 mm2 767 mm2 Copper Area Cauer Network Foster Network C’s C’s Units Tau Tau Units 3.12E−05 3.12E−05 W−s/C 1.00E−06 1.00E−06 sec 1.21E−04 1.21E−04 W−s/C 1.00E−05 1.00E−05 sec 3.53E−04 3.50E−04 W−s/C 1.00E−04 1.00E−04 sec 1.19E−03 1.19E−03 W−s/C 0.028 0.001 sec 4.86E−03 5.05E−03 W−s/C 0.001 0.009 sec 2.17E−02 7.16E−03 W−s/C 0.280 0.047 sec 8.94E−02 3.51E−02 W−s/C 2.016 0.875 sec 0.304 0.262 W−s/C 16.64 7.53 sec 1.71 2.43 W−s/C 59.47 68.4 sec 411 W−s/C 92.221 sec R’s R’s R’s R’s 0.041 0.041 °C/W 2.44E−02 2.44E−02 °C/W 0.095 0.096 °C/W 5.28E−02 5.28E−02 °C/W 0.279 0.281 °C/W 1.67E−01 1.67E−01 °C/W 1.154 0.995 °C/W 3.5 0.7 °C/W 5.621 6.351 °C/W 0.7 0.1 °C/W 13.180 1.910 °C/W 8.7 5.8 °C/W 23.823 21.397 °C/W 15.9 16.4 °C/W 53.332 27.150 °C/W 31.9 27.1 °C/W 24.794 25.276 °C/W 61.3 29.0 °C/W 0.218 °C/W 4.3 °C/W *Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in the Foster network are computed by the square root of time constant R(t) = 24.4 * sqrt(time(sec)). The constant is derived based on the active area of the device with silicon and epoxy at the interface of the heat generation. The Cauer networks generally have physical using circuit simulating tools, whereas Foster networks significance and may be divided between nodes to separate may be more easily implemented using mathematical tools thermal behavior due to one portion of the network from (for instance, in a spreadsheet program), according to the another. The Foster networks, though when sorted by time following formula: constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. R(t)(cid:3) (cid:7)n Ri(cid:4)1−e−t(cid:5)taui(cid:6) Both Foster and Cauer networks can be easily implemented i(cid:3)1 Junction R1 R2 R3 Rn C1 C2 C3 Cn Time constants are not simple RC products. Ambient Amplitudes of mathematical solution are not the resistance values. (thermal ground) Figure 23. Grounded Capacitor Thermal Network (“Cauer” Ladder) Junction R1 R2 R3 Rn C1 C2 C3 Cn Each rung is exactly characterized by its RC−product time constant; Am- Ambient plitudes are the resistances (thermal ground) Figure 24. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder) www.onsemi.com 21

NCV7356 1000 Cu Area = 96 mm2 1.0 oz. 100 Cu Area = 767 mm2 1.0 oz. W) 10 C/ Cu Area = 767 mm2 1.0 oz. 1S2P ° ((cid:5) R 1 0.1 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 Time (s) Figure 25. SOIC−14 Single Pulse Heating 1000 D = 0.50 0.20 100 0.10 0.05 W) 10 C/ 0.01 ° R ((cid:5) 1 Cu Area = 717 mm2 1.0 oz. 0.1 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 PULSE DURATION (sec) Figure 26. SOIC−14 Thermal Duty Cycle Curves on 1(cid:2) Spreader Test Board www.onsemi.com 22

NCV7356 PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE K D A NOTES: B 1.DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2.CONTROLLING DIMENSION: MILLIMETERS. 14 8 3.DIMENSION b DOES NOT INCLUDE DAMBAR A3 PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. H E 4.DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. L 5.MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 1 7 DETAIL A MILLIMETERS INCHES 0.25 M B M 13Xb DIM MIN MAX MIN MAX A 1.35 1.75 0.054 0.068 0.25 M C A S B S A1 0.10 0.25 0.004 0.010 A3 0.19 0.25 0.008 0.010 h DETAIL A b 0.35 0.49 0.014 0.019 A D 8.55 8.75 0.337 0.344 X 45(cid:3) E 3.80 4.00 0.150 0.157 e 1.27 BSC 0.050 BSC H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 e A1 C SEATING M ML 0.400 (cid:3) 1.275 (cid:3) 0.0106 (cid:3) 0.0479 (cid:3) PLANE SOLDERING FOOTPRINT* 6.50 14X 1.18 1 1.27 PITCH 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 23

NCV7356 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK NOTES: −X− 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. A 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) 8 5 PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL 1 IN EXCESS OF THE D DIMENSION AT −Y− 4 K 6. M75A1X−I0M1U TMH RMUA T7E51R−IA06L CAROEN DOIBTSIOONL.ETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES DIM MIN MAX MIN MAX C NX 45(cid:3) A 4.80 5.00 0.189 0.197 B 3.80 4.00 0.150 0.157 SEATING PLANE C 1.35 1.75 0.053 0.069 −Z− D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC 0.10 (0.004) H 0.10 0.25 0.004 0.010 H D M J J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 (cid:3) 8 (cid:3) 0 (cid:3) 8 (cid:3) N 0.25 0.50 0.010 0.020 0.25 (0.010)M Z Y S X S S 5.80 6.20 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 4.0 0.275 0.155 0.6 1.270 0.024 0.050 (cid:4) (cid:6) mm SCALE 6:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative ◊ www.onsemi.com NCV7356/D 24

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