NCV4264-2 Linear Regulator, Low Dropout, Low I Q The NCV4264−2 is functionally and pin for pin compatible with NCV4264 with a lower quiescent current consumption. Its output www.onsemi.com stage supplies 100 mA with ±2.0% output voltage accuracy. Maximum dropout voltage is 500 mV at 100 mA load current. MARKING It is internally protected against 45 V input transients, input supply DIAGRAM reversal, output overcurrent faults, and excess die temperature. No external components are required to enable these features. TAB SOT−223 AYW ST SUFFIX V642x(cid:2) Features 2 CASE 318E (cid:2) • 1 3 3.3 V and 5.0 V Fixed Output • ±2.0% Output Accuracy, Over Full Temperature Range 1 • 60 (cid:2)A Maximum Quiescent Current at I = 100 (cid:2)A OUT 8 • 500 mV Maximum Dropout Voltage at 100 mA Load Current V642x 8 SOIC−8 Fused • Wide Input Voltage Operating Range of 4.5 V to 45 V CASE 751 ALYWX • 1 (cid:2) Internal Fault Protection 1 ♦ −42 V Reverse Voltage ♦ Short Circuit/Overcurrent x = 5 (5.0 V Version) = 3 (3.3 V Version) ♦ Thermal Overload • A = Assembly Location NCV Prefix for Automotive and Other Applications Requiring L = Wafer Lot Unique Site and Control Change Requirements; AEC−Q100 Y = Year Qualified and PPAP Capable W = Work Week • (cid:2) = Pb−Free Package This is a Pb−Free Device (Note: Microdot may be in either location) PIN CONNECTIONS (SOT−223) (SOIC−8 Fused) PIN FUNCTION PIN FUNCTION 1 VIN 1 NC 2,TAB GND 2, VIN 3 VOUT 3 GND 4. VOUT 5−8. NC ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: November, 2018 − Rev. 10 NCV4264−2/D

NCV4264−2 IN OUT 1.3 V + Reference Error Amp - Thermal Shutdown GND Figure 1. Block Diagram PIN FUNCTION DESCRIPTION Pin No. SOT−223 SOIC−8 Symbol Function 1 2 VIN Unregulated input voltage; 4.5 V to 45 V. 2 3 GND Ground; substrate. 3 4 VOUT Regulated output voltage; collector of the internal PNP pass transistor. TAB − GND Ground; substrate and best thermal connection to the die. − 1, 5−8 NC No Connection. OPERATING RANGE Rating Symbol Min Max Unit VIN, DC Input Operating Voltage (Note 3) VIN 4.5 +45 V Junction Temperature Operating Range TJ −40 +150 °C MAXIMUM RATINGS Rating Symbol Min Max Unit VIN, DC Input Voltage VIN −42 +45 V VOUT, DC Voltage VOUT −0.3 +18 V Storage Temperature Tstg −55 +150 °C Moisture Sensitivity Level SOT223 MSL 3 − SOIC−8 Fused 1 ESD Capability, Human Body Model (Note 1) VESDHB 4000 − V ESD Capability, Machine Model (Note 1) VESDMIM 200 − V Lead Temperature Soldering Tsld °C Reflow (SMD Styles Only), Lead Free (Note 2) − 265 pk Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device series incorporates ESD protection and is tested by the following methods: ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A 114C) ESD MM tested per AEC−Q100−003 (EIA/JESD22−A 115C) 2. Lead Free, 60 sec – 150 sec above 217°C, 40 sec max at peak. 3. See specific conditions for DC operating input voltage lower than 4.5 V in the ELECTRICAL CHRACTERISTICS table at page 3 www.onsemi.com 2

NCV4264−2 THERMAL RESISTANCE Parameter Symbol Min Max Unit Junction−to−Ambient SOT−223 R(cid:3)JA − 99 (Note 4) °C/W SOIC−8 Fused 145 Junction−to−Case SOT−223 R(cid:3)JC − 17 SOIC−8 Fused − ELECTRICAL CHARACTERISTICS (VIN = 13.5 V, TJ = −40°C to +150°C, unless otherwise noted.) Characteristic Symbol Test Conditions Min Typ Max Unit O5.u0t pVu Vt eVroslitoange VOUT 5.0 mA 6(cid:2).0 I OVU (cid:2)T (cid:2)VI N1 0(cid:2)0 m28A V (Note 5) 4.900 5.000 5.100 V O3.u3t pVu Vt eVroslitoange VOUT 5.0 mA 4(cid:2).5 I OVU (cid:2)T (cid:2)VI N1 0(cid:2)0 m28A V (Note 5) 3.234 3.300 3.366 V Output Voltage VOUT IOUT = 5 mA, VIN = 4 V (Note 7) 3.234 3.300 3.366 V 3.3 V Version Line Regulation (cid:4)VOUT vs. VIN IOUT = 5.0 mA −30 5.0 +30 mV 5.0 V Version 6.0 V (cid:2) VIN (cid:2) 28 V Line Regulation (cid:4)VOUT vs. VIN IOUT = 5.0 mA −30 5.0 +30 mV 3.3 V Version 4.5 V (cid:2) VIN (cid:2) 28 V Load Regulation (cid:4)VOUT vs. IOUT 1.0 mA (cid:2) IOUT (cid:2) 100 mA (Note 5) −40 5.0 +40 mV Dropout Voltage − 5.0 V Version VIN−VOUT IOUT = 100 mA (Notes 5 & 6) − 270 500 mV Dropout Voltage − 3.3 V Version VIN−VOUT IOUT = 100 mA (Notes 5 & 8) − − 1.266 V Quiescent Current Iq IOUT = 100 (cid:2)A (cid:2)A TJ = 25°C − 33 55 TJ = −40°C to +85°C − 33 60 TJ = −40°C to 150°C − 33 70 Active Ground Current IG(ON) IOUT = 50 mA (Note 5) − 1.5 4.0 mA Power Supply Rejection PSRR VRIPPLE = 0.5 VP−P, F = 100 Hz − 67 − dB Output Capacitor for Stability COUT IOUT = 0.1 mA to 100 mA 10 − − (cid:2)F 5.0 V Version ESR (Notes 5 & 7) − − 9.0 (cid:5) Output Capacitor for Stability COUT IOUT = 0.1 mA to 100 mA 22 − − (cid:2)F 3.3 V Version ESR (Notes 5 & 7) − − 16 (cid:5) PROTECTION Current Limit IOUT(LIM) VOUT = 4.5 V (5.0 V Version) (Note 5) 150 − 500 mA VOUT = 3.0 V (3.3 V Version) (Note 5) 150 − 500 Short Circuit Current Limit IOUT(SC) VOUT = 0 V (Note 5) 40 − 500 mA Thermal Shutdown Threshold TTSD (Note 7) 150 − 200 °C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. 1 oz., 100 mm2 copper area. 5. Use pulse loading to limit power dissipation. 6. Dropout voltage = (VIN–VOUT), measured when the output voltage has dropped 100 mV relative to the nominal value obtained with VIN = 13.5 V. 7. Not tested in production. Limits are guaranteed by design. 8. VDO = VIN − VOUT. For output voltage set to < 4.5 V, VDO will be constrained by the minimum input voltage. 4.5−45 V Vin Vout Output Input 4264−2 Cin COUT 100 nF 10 (cid:2)F − 5.0 V Version 22 (cid:2)F − 3.3 V Version GND Figure 2. Applications Circuit www.onsemi.com 3

NCV4264−2 TYPICAL CHARACTERISTIC CURVES − 5 V Version 10 Unstable Region 9 8 7 (cid:5)) 6 R ( 5 S E 4 3 2 Vin = 13.5 V 1 Stable Region Cout ≥ 10 (cid:2)F 0 0 25 50 75 100 125 150 OUTPUT CURRENT (mA) Figure 3. ESR Stability vs. Output Current (5 V Version) 12 0.4 A) 10 125°C A) 0.35 125°C 25°C m 25°C m T ( T ( 0.3 EN 8 −40°C EN 0.25 −40°C R R R R U 6 U 0.2 C C T T N N 0.15 E 4 E C C S S 0.1 E E UI 2 UI Q Q 0.05 VIN = 13.5 V VIN = 13.5 V 0 0 0 50 100 150 200 0 5 10 15 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) Figure 4. Quiescent Current vs. Output Current Figure 5. Quiescent Current vs. Output Current (5 V Version) (Light Load) (5 V Version) 0.45 5.10 0.40 125°C 5.08 GE (V) 00..3305 25°C E (V) 55..0046 A G T A 5.02 OL 0.25 −40°C LT V O 5.00 OUT 0.20 UT V 4.98 OP 0.15 UTP 4.96 DR 0.10 O 4.94 0.05 4.92 0 4.90 0 50 100 150 200 −50 0 50 100 150 OUTPUT CURRENT (mA) TEMPERATURE (°C) Figure 6. Dropout Voltage vs. Output Current Figure 7. Output Voltage vs. Temperature (5 V Version) (5 V Version) www.onsemi.com 4

NCV4264−2 TYPICAL CHARACTERISTIC CURVES − 5 V Version 180 6.0 160 5.0 mA) 140 V) NT ( 120 GE ( 4.0 E A R 100 LT UR VO 3.0 PUT C 6800 TA = 25°C TPUT 2.0 T U OU 40 O TA = 125°C 1.0 20 RL = 50 (cid:5) 0 0 0 10 20 30 40 50 0 2.0 4.0 6.0 8.0 10 INPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 8. Output Current vs. Input Voltage Figure 9. Output Voltage vs. Input Voltage (5 V Version) (5 V Version) 16 14 A) m T ( 12 N E 10 R R U C 8 T EN 6 SC RL = 50 (cid:5) E 4 UI Q 2 0 RL = 100 (cid:5) 0 10 20 30 40 50 INPUT VOLTAGE (V) Figure 10. Quiescent Current vs. Input Voltage (5 V Version) www.onsemi.com 5

NCV4264−2 TYPICAL CHARACTERISTIC CURVES − 3.3 V Version 10 3.6 9 125°C 3.3 A) 3.0 ENT (m 78 25°C GE (V) 22..47 RR 6 −40°C TA 2.1 NT CU 54 UT VOL 11..58 SCE 3 UTP 1.2 E O 0.9 UI 2 Q 0.6 Iout = 5 mA 1 Vin = 13.5 V 0.3 0 0 0 25 50 75 100 125 150 175 0 5 10 15 20 25 30 35 40 45 OUTPUT CURRENT (mA) INPUT VOLTAGE (V) Figure 11. Quiescent Current vs. Output Figure 12. Output Voltage vs. Input Voltage Current (3.3 V Version) (3.3 V Version) 8 3.366 3.355 7 A) 3.344 m ENT ( 65 GE (V)33..333232 RR TA3.311 NT CU 34 UT VOL33..238090 ESCE 2 Iout = 66 mA OUTP33..227687 UI Q 1 3.256 Vin = 13.5 V 3.245 Iout = 5 mA 0 Iout = 33 mA 3.234 0 5 10 15 20 25 30 35 40 45 −50 −25 0 25 50 75 100 125 150 INPUT VOLTAGE (V) TEMPERATURE (°C) Figure 13. Quiescent Current vs. Input Voltage Figure 14. Output Voltage vs. Temperature (3.3 V Version) (3.3 V Version) 150 180 (cid:2)T (A) 140 VIoiunt == 153 m.5A V mA) 150 RREN 130 RENT ( 120 CU UR 90 T C ESCEN 120 UTPUT 60 UI 110 O Q 30 100 0 −50 −25 0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 40 45 TEMPERATURE (°C) INPUT VOLTAGE (V) Figure 15. Quiescent Current vs. Temperature Figure 16. Output Current vs. Input Voltage (3.3 V Version) (3.3 V Version) www.onsemi.com 6

NCV4264−2 TYPICAL CHARACTERISTIC CURVES − 3.3 V Version 20 Unstable Region 15 (cid:5)) R ( 10 S E 5 Vin = 13.5 V Stable Region Cout ≥ 22 (cid:2)F 0 0 30 60 90 120 150 OUTPUT CURRENT (mA) Figure 17. ESR Stability vs. Output Current (3.3 V Version) www.onsemi.com 7

NCV4264−2 Circuit Description Calculating Power Dissipation in a Single Output The NCV4264−2 is functionally and pin for pin Linear Regulator compatible with NCV4264 with a lower quiescent current The maximum power dissipation for a single output consumption. Its output stage supplies 100 mA with regulator (Figure 2) is: (cid:3)2.0% output voltage accuracy. PD(max)(cid:5) (eq. 1) Maximum dropout voltage is 500 mV at 100 mA load (cid:6)VIN(max)(cid:7)VOUT(min)(cid:8)*IOUT(max)(cid:9)VIN(max)*Iq current. It is internally protected against 45 V input Where: transients, input supply reversal, output overcurrent faults, V is the maximum input voltage, and excess die temperature. No external components are IN(max) V is the minimum output voltage, required to enable these features. OUT(min) I is the maximum output current for the OUT(max) Regulator application, and Iq is the quiescent current the regulator The error amplifier compares the reference voltage to a consumes at IOUT(max). Once the value of PD(max) is known, sample of the output voltage (VOUT) and drives the base of the maximum permissible value of R(cid:3)JA can be calculated: a PNP series pass transistor by a buffer. The reference is a (150°C(cid:7)TA) bandgap design to give it a temperature−stable output. P(cid:3)JA(cid:5) (eq. 2) PD Saturation control of the PNP is a function of the load The value of R(cid:3)JA can then be compared with those in the current and input voltage. Oversaturation of the output package section of the data sheet. Those packages with power device is prevented, and quiescent current in the R(cid:3)JA’s less than the calculated value in Equation 2 will ground pin is minimized. keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat Regulator Stability Considerations The input capacitor C in Figure 2 is necessary for generated by the IC, and an external heat sink will be I1 compensating input line reactance. Possible oscillations required. The current flow and voltages are shown in the caused by input inductance and input capacitance can be Measurement Circuit Diagram. damped by using a resistor of approximately 1 (cid:5) in series Heat Sinks with C . The output or compensation capacitor, C I2 OUT A heat sink effectively increases the surface area of the helps determine three main characteristics of a linear package to improve the flow of heat away from the IC and regulator: startup delay, load transient response and loop into the surrounding air. Each material in the heat flow path stability. Tantalum, aluminum electrolytic, film, or between the IC and the outside environment will have a ceramic capacitors are all acceptable solutions, however, thermal resistance. Like series electrical resistances, these attention must be paid to ESR constraints. The capacitor resistances are summed to determine the value of R(cid:3)JA: manufacturer’s data sheet usually provides this information. The value for the output capacitor C R(cid:3)JA(cid:5)R(cid:3)JC(cid:9)R(cid:3)CS(cid:9)R(cid:3)SA (eq. 3) OUT shown in Figure 2 should work for most applications; Where: however, it is not necessarily the optimized solution. R(cid:3)JC = the junction−to−case thermal resistance, Stability is guaranteed at values of CQ (cid:4) 10 (cid:2)F, with an R(cid:3)CS = the case−to−heat sink thermal resistance, and ESR (cid:2) 9 (cid:5) for the 5.0 V Version, and C (cid:4) 22 (cid:2)F with Q R(cid:3)SA = the heat sink−to−ambient thermal resistance. an ESR (cid:2) 16 (cid:5) for the 3.3 V Version within the operating R(cid:3)JA appears in the package section of the data sheet. temperature range. Actual limits are shown in a graph in the Like R(cid:3)JA, it too is a function of package type. R(cid:3)CS and Typical Performance Characteristics section. R(cid:3)SA are functions of the package type, heat sink and the interface between them. These values appear in data sheets of heat sink manufacturers. Thermal, mounting, and heat sinking are discussed in the ON Semiconductor application note AN1040/D, available on the ON Semiconductor Website. www.onsemi.com 8

NCV4264−2 160 140 120 SOIC−8 Fused W) 100 °C/ 80 SOT223 A ( (cid:3)J 60 40 20 0 0 100 200 300 400 500 600 700 COPPER AREA (mm2) Figure 18. (cid:2)JA vs. Copper Spreader Area 1000 SOT223 SOIC−8 Fused 100 10 W) C/ 1 ° R(t) ( 0.1 0.01 0.001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 PULSE TIME (sec) Figure 19. R(t) vs. Pulse Time ORDERING INFORMATION Device* Package Shipping† NCV4264−2ST50T3G SOT−223 4000 / Tape & Reel (Pb−Free) NCV4264−2ST33T3G SOT−223 4000 / Tape & Reel (Pb−Free) NCV4264−2D33R2G SOIC−8 Fused 2500 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 9

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT−223 (TO−261) CASE 318E−04 ISSUE R SCALE 1:1 DATE 02 OCT 2018 (cid:2) (cid:2) Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98ASB42680B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: SOT−223 (TO−261) PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com

SOT−223 (TO−261) CASE 318E−04 ISSUE R DATE 02 OCT 2018 STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5: PIN 1.BASE PIN 1.ANODE PIN 1.GATE PIN 1.SOURCE PIN 1.DRAIN 2.COLLECTOR 2.CATHODE 2.DRAIN 2.DRAIN 2.GATE 3.EMITTER 3.NC 3.SOURCE 3.GATE 3.SOURCE 4.COLLECTOR 4.CATHODE 4.DRAIN 4.DRAIN 4.GATE STYLE 6: STYLE 7: STYLE 8: STYLE 9: STYLE 10: PIN 1.RETURN PIN 1.ANODE 1 CANCELLED PIN 1.INPUT PIN 1.CATHODE 2.INPUT 2.CATHODE 2.GROUND 2.ANODE 3.OUTPUT 3.ANODE 2 3.LOGIC 3.GATE 4.INPUT 4.CATHODE 4.GROUND 4.ANODE STYLE 11: STYLE 12: STYLE 13: PIN 1.MT 1 PIN 1.INPUT PIN 1.GATE 2.MT 2 2.OUTPUT 2.COLLECTOR 3.GATE 3.NC 3.EMITTER 4.MT 2 4.OUTPUT 4.COLLECTOR GENERIC MARKING DIAGRAM* AYW XXXXX(cid:2) (cid:2) 1 A = Assembly Location Y = Year W = Work Week XXXXX = Specific Device Code (cid:2) = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “(cid:2)”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98ASB42680B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: SOT−223 (TO−261) PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 8 ISSUE AK 1 DATE 16 FEB 2011 SCALE 1:1 NOTES: −X− 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. A 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) 8 5 PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL 1 IN EXCESS OF THE D DIMENSION AT −Y− 4 K 6. M75A1X−I0M1U TMH RMUA T7E51R−IA0L6 CAROEN DOIBTSIOONL.ETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.80 5.00 0.189 0.197 C NX 45(cid:2) B 3.80 4.00 0.150 0.157 SEATING C 1.35 1.75 0.053 0.069 PLANE D 0.33 0.51 0.013 0.020 −Z− G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 0.10 (0.004) J 0.19 0.25 0.007 0.010 H D M J K 0.40 1.27 0.016 0.050 M 0 (cid:2) 8 (cid:2) 0 (cid:2) 8 (cid:2) N 0.25 0.50 0.010 0.020 0.25 (0.010)M Z Y S X S S 5.80 6.20 0.228 0.244 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 8 8 8 8 XXXXX XXXXX XXXXXX XXXXXX 1.52 ALYWX ALY (cid:3)WX AYWW AY W(cid:3)W 0.060 1 1 1 1 IC IC Discrete Discrete (Pb−Free) (Pb−Free) 7.0 4.0 XXXXX = Specific Device Code XXXXXX= Specific Device Code 0.275 0.155 A = Assembly Location A = Assembly Location L = Wafer Lot Y = Year Y = Year WW = Work Week W = Work Week (cid:3) = Pb−Free Package (cid:3) = Pb−Free Package 0.6 1.270 *This information is generic. Please refer 0.024 0.050 to device data sheet for actual part marking. Pb−Free indicator, “G”, may (cid:2) (cid:3) mm or not be present. SCALE 6:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: 98ASB42564B Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped “CONTROLLED COPY” in red. NEW STANDARD: © Semiconductor Components Industries, LLC, 2002 http://onsemi.com Case Outline Number: October, D20E0S2C −R RIePvT. I0ON: SOIC−8, NB 1 PAGE 1 OFX 3XX

SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: STYLE 2: STYLE 3: STYLE 4: PIN 1. EMITTER PIN 1. COLLECTOR, DIE, #1 PIN 1. DRAIN, DIE #1 PIN 1. ANODE 2. COLLECTOR 2. COLLECTOR, #1 2. DRAIN, #1 2. ANODE 3. COLLECTOR 3. COLLECTOR, #2 3. DRAIN, #2 3. ANODE 4. EMITTER 4. COLLECTOR, #2 4. DRAIN, #2 4. ANODE 5. EMITTER 5. BASE, #2 5. GATE, #2 5. ANODE 6. BASE 6. EMITTER, #2 6. SOURCE, #2 6. ANODE 7. BASE 7. BASE, #1 7. GATE, #1 7. ANODE 8. EMITTER 8. EMITTER, #1 8. SOURCE, #1 8. COMMON CATHODE STYLE 5: STYLE 6: STYLE 7: STYLE 8: PIN 1. DRAIN PIN 1. SOURCE PIN 1. INPUT PIN 1. COLLECTOR, DIE #1 2. DRAIN 2. DRAIN 2. EXTERNAL BYPASS 2. BASE, #1 3. DRAIN 3. DRAIN 3. THIRD STAGE SOURCE 3. BASE, #2 4. DRAIN 4. SOURCE 4. GROUND 4. COLLECTOR, #2 5. GATE 5. SOURCE 5. DRAIN 5. COLLECTOR, #2 6. GATE 6. GATE 6. GATE 3 6. EMITTER, #2 7. SOURCE 7. GATE 7. SECOND STAGE Vd 7. EMITTER, #1 8. SOURCE 8. SOURCE 8. FIRST STAGE Vd 8. COLLECTOR, #1 STYLE 9: STYLE 10: STYLE 11: STYLE 12: PIN 1. EMITTER, COMMON PIN 1. GROUND PIN 1. SOURCE 1 PIN 1. SOURCE 2. COLLECTOR, DIE #1 2. BIAS 1 2. GATE 1 2. SOURCE 3. COLLECTOR, DIE #2 3. OUTPUT 3. SOURCE 2 3. SOURCE 4. EMITTER, COMMON 4. GROUND 4. GATE 2 4. GATE 5. EMITTER, COMMON 5. GROUND 5. DRAIN 2 5. DRAIN 6. BASE, DIE #2 6. BIAS 2 6. DRAIN 2 6. DRAIN 7. BASE, DIE #1 7. INPUT 7. DRAIN 1 7. DRAIN 8. EMITTER, COMMON 8. GROUND 8. DRAIN 1 8. DRAIN STYLE 13: STYLE 14: STYLE 15: STYLE 16: PIN 1. N.C. PIN 1. N−SOURCE PIN 1. ANODE 1 PIN 1. EMITTER, DIE #1 2. SOURCE 2. N−GATE 2. ANODE 1 2. BASE, DIE #1 3. SOURCE 3. P−SOURCE 3. ANODE 1 3. EMITTER, DIE #2 4. GATE 4. P−GATE 4. ANODE 1 4. BASE, DIE #2 5. DRAIN 5. P−DRAIN 5. CATHODE, COMMON 5. COLLECTOR, DIE #2 6. DRAIN 6. P−DRAIN 6. CATHODE, COMMON 6. COLLECTOR, DIE #2 7. DRAIN 7. N−DRAIN 7. CATHODE, COMMON 7. COLLECTOR, DIE #1 8. DRAIN 8. N−DRAIN 8. CATHODE, COMMON 8. COLLECTOR, DIE #1 STYLE 17: STYLE 18: STYLE 19: STYLE 20: PIN 1. VCC PIN 1. ANODE PIN 1. SOURCE 1 PIN 1. SOURCE (N) 2. V2OUT 2. ANODE 2. GATE 1 2. GATE (N) 3. V1OUT 3. SOURCE 3. SOURCE 2 3. SOURCE (P) 4. TXE 4. GATE 4. GATE 2 4. GATE (P) 5. RXE 5. DRAIN 5. DRAIN 2 5. DRAIN 6. VEE 6. DRAIN 6. MIRROR 2 6. DRAIN 7. GND 7. CATHODE 7. DRAIN 1 7. DRAIN 8. ACC 8. CATHODE 8. MIRROR 1 8. DRAIN STYLE 21: STYLE 22: STYLE 23: STYLE 24: PIN 1. CATHODE 1 PIN 1. I/O LINE 1 PIN 1. LINE 1 IN PIN 1. BASE 2. CATHODE 2 2. COMMON CATHODE/VCC 2. COMMON ANODE/GND 2. EMITTER 3. CATHODE 3 3. COMMON CATHODE/VCC 3. COMMON ANODE/GND 3. COLLECTOR/ANODE 4. CATHODE 4 4. I/O LINE 3 4. LINE 2 IN 4. COLLECTOR/ANODE 5. CATHODE 5 5. COMMON ANODE/GND 5. LINE 2 OUT 5. CATHODE 6. COMMON ANODE 6. I/O LINE 4 6. COMMON ANODE/GND 6. CATHODE 7. COMMON ANODE 7. I/O LINE 5 7. COMMON ANODE/GND 7. COLLECTOR/ANODE 8. CATHODE 6 8. COMMON ANODE/GND 8. LINE 1 OUT 8. COLLECTOR/ANODE STYLE 25: STYLE 26: STYLE 27: STYLE 28: PIN 1. VIN PIN 1. GND PIN 1. ILIMIT PIN 1. SW_TO_GND 2. N/C 2. dv/dt 2. OVLO 2. DASIC_OFF 3. REXT 3. ENABLE 3. UVLO 3. DASIC_SW_DET 4. GND 4. ILIMIT 4. INPUT+ 4. GND 5. IOUT 5. SOURCE 5. SOURCE 5. V_MON 6. IOUT 6. SOURCE 6. SOURCE 6. VBULK 7. IOUT 7. SOURCE 7. SOURCE 7. VBULK 8. IOUT 8. VCC 8. DRAIN 8. VIN STYLE 29: STYLE 30: PIN 1. BASE, DIE #1 PIN 1. DRAIN 1 2. EMITTER, #1 2. DRAIN 1 3. BASE, #2 3. GATE 2 4. EMITTER, #2 4. SOURCE 2 5. COLLECTOR, #2 5. SOURCE 1/DRAIN 2 6. COLLECTOR, #2 6. SOURCE 1/DRAIN 2 7. COLLECTOR, #1 7. SOURCE 1/DRAIN 2 8. COLLECTOR, #1 8. GATE 1 DOCUMENT NUMBER: 98ASB42564B Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped “CONTROLLED COPY” in red. NEW STANDARD: © Semiconductor Components Industries, LLC, 2002 http://onsemi.com Case Outline Number: October, D20E0S2C −R RIePvT. I0ON: SOIC−8, NB 2 PAGE 2 OFX 3XX

DOCUMENT NUMBER: 98ASB42564B PAGE 3 OF 3 ISSUE REVISION DATE AB ADDED STYLE 25. REQ. BY S. CHANG. 15 MAR 2004 AC ADDED CORRECTED MARKING DIAGRAMS. REQ. BY S. FARRETTA. 13 AUG 2004 AD CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY S. FARRETTA. 18 NOV 2004 AE UPDATED SCALE ON FOOTPRINT. REQ. BY S. WEST. 31 JAN 2005 AF UPDATED MARKING DIAGRAMS. REQ. BY S. WEST. ADDED STYLE 26. REQ. BY 14 APR 2005 S. CHANG. AG ADDED STYLE 27. REQ. BY S. CHANG. 30 JUN 2005 AH ADDED STYLE 28. REQ. BY S. CHANG. 09 MAR 2006 AJ ADDED STYLE 29. REQ. BY D. HELZER. 19 SEP 2007 AK ADDED STYLE 30. REQ. BY I. CAMBALIZA. 16 FEB 2011 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. © Semiconductor Components Industries, LLC, 2011 Case Outline Number: February, 2011 − Rev. 07AK 751

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