NCP5212A, NCP5212T Single Synchronous Step-Down Controller The NCP5212A/NCP5212T is a synchronous stepdown controller for high performance systems battery−power systems. The NCP5212A/NCP5212T includes a high efficiency PWM controller. A pin is provided to allow two devices in interleaved operation. An http://onsemi.com internal power good voltage monitor tracks the SMPS output. NCP5212A/NCP5212T also features soft−start sequence, UVLO for V and switcher, overvoltage protection, overcurrent protection, CC 1 undervoltage protection and thermal shutdown. The IC is packaged in QFN16 QFN16 CASE 485AP Features • 0.8% accuracy 0.8 V Reference • 4.5 V to 27 V Battery/Adaptor Voltage Range MARKING DIAGRAMS • Adjustable Output Voltage Range: 0.8 V to 3.3 V 16 16 • Synchronization Interleaving between Two NCP5212A/NCP5212Ts 1 1 • N5212 5212T Skip Mode for Power Saving Operation at Light Load ALYW(cid:2) ALYW(cid:2) • Lossless Inductor Current Sensing (cid:2) (cid:2) • Programmable Transient−Response−Enhancement (TRE) Control • NCP5212A NCP5212T Programmable Adaptive Voltage Positioning (AVP) • Input Supply Feedforward Control N5212/5212T Device Code • A = Assembly Location Internal Soft−Start L = Wafer Lot • Integrated Output Discharge (Soft−Stop) Y = Year • W = Work Week Build−in Adaptive Gate Drivers • (cid:2) = Pb−Free Package PGOOD Indication (Note: Microdot may be in either location) • Overvoltage, Undervoltage and Overcurrent Protections • Thermal Shutdown •• QFN16 Package GOOD WM H ST These Devices are Pb−Free and are RoHS Compliant P S D B 16 15 14 13 Typical Applications • Notebook Application VIN 1 12 VCCP • System Power VCC 2 NCP5212A/ 11 DL/TRESET NCP5212T SYN 3 10 PGND EN 4 9 CS+ 5 6 7 8 P B P o M F C V O O −/ C P/ CS R D I QFN16 (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 18 of this data sheet. © Semiconductor Components Industries, LLC, 2009 1 Publication Order Number: August, 2009 − Rev. 3 NCP5212A/D

NCP5212A, NCP5212T D O GO WN H ST P S D B TPAD 17 16 15 14 13 PGOOD IDRP/OCP Detection e AGND SThhuetdrmowaln OSC High SidDriver OvDeer tCecutrorernt AVP Control UVLO VIN 1 12 VCCP Control VCC UVLO Control NCP5212A/NCP5212T Control Logic, Protection, RAMP Generator and PWM Logic VCC 2 ENABLE Low Side 11 DL/TRESET MASTER Driver SLAVE ection PGH PGL UVP OVP SYN 3 Det CDIFF 10 PGND E + − + − + − + − R T & EN 4 CLoenvteroll OC VREF+10% VREF−10% VREF−20% VREF+15%H −ACSmueprnrleis+fienetr 9 CS+ C S DI + − VREF Error Amplifier 5 6 7 8 MP FB CP Vo O O −/ C RP/ CS D I Figure 1. Detail Block Diagram http://onsemi.com 2

NCP5212A, NCP5212T VIN 5V PGOOD D O GO WN H ST VOUT P S D B 16 15 14 13 VIN VCCP 1 12 VCC DL/TRESET 2 11 NCP5212A/NCP5212T SYN AGND PGND 3 10 GND EN_SKIP CS+ EN_SKIP 4 9 5 6 7 8 MP FB CP Vo O O −/ C RP/ CS D I Figure 2. Typical Application Circuit (Single Device Operation) http://onsemi.com 3

NCP5212A, NCP5212T VIN 5V PGOOD1 D O GO WN H ST VOUT1 P S D B 16 15 14 13 GND1 VIN VCCP 1 12 VCC 2 NCP5212A/ 11 DL/TRESET NCP5212T SYN AGND PGND 3 10 EN=VEN_Master EN Master CS+ 4 9 5 6 7 8 MP FB CP Vo O O −/ C RP/ CS D I PGOOD2 D O GO WN H ST VOUT2 P S D B 16 15 14 13 GND2 VIN VCCP 1 12 VCC NCP5212A/ DL/TRESET 2 11 NCP5212T SYN AGND PGND 3 10 EN=VEN_Slave EN Slave CS+ 4 9 5 6 7 8 MP FB CP Vo O O −/ C RP/ CS D I Figure 3. Typical Application Circuit (Dual Device Operation) http://onsemi.com 4

NCP5212A, NCP5212T PIN FUNCTION DESCRIPTION Pin No. Symbol Description 1 VIN Input voltage used for feed forward in switcher operation. 2 VCC Supply for analog circuit 3 SYN Synchronization interleaving use. 4 EN This pin serves as two functions. Enable: Logic control for enabling the switcher. MASTER/SLAVE: To program the device as MASTER or SLAVE mode at dual device operation. 5 COMP Output of the error amplifier. 6 FB Output voltage feed back. 7 IDRP/OCP Current limit programmable and setting for AVP. 8 CS−/Vo Inductor current differential sense inverting input. 9 CS+ Inductor current differential sense non−inverting input. 10 PGND Ground reference and high−current return path for the bottom gate driver. 11 DL/TRESET Gate driver output of bottom N−channel MOSFET. It also has the function for TRE threshold setting. 12 VCCP Supply for bottom gate driver. 13 BST Top gate driver input supply, a bootstrap capacitor connection between SWN and this pin. 14 DH Gate driver output of top N−channel MOSFET. 15 SWN Switch node between top MOSFET and bottom MOSFET. 16 PGOOD Power good indicator of the output voltage. High impendence if power good (in regulation). Low im- pendence if power not good. 17 TPAD Copper pad on bottom of IC used for heat sinking. This pin should be connected to the analog ground plane under the IC. ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit VCC Power Supply Voltage to AGND VCC −0.3, 6.0 V VIN Supply to AGND VIN −0.3, 30 V High−side Gate Drive Supply: BST to SWN VBST−VSWN, −0.3, 6.0 V High−side Gate Drive Voltage: DH to SWN VDH−VSWN, Low−side Gate Drive Supply: VCCP to PGND VCCP−VPGND, Low−side Gate Drive Voltage: DL to PGND VDL−VPGND, Input / Output Pins to AGND VIO −0.3, 6.0 V Switch Node SWN−PGND VSWN −5 V (< 100 ns) V 30 V High−Side Gate Drive/Low−Side Gate Drive Outputs DH, DL −3(DC) V PGND VPGND −0.3, 0.3 V Thermal Characteristics °C/W Thermal Resistance Junction−to−Ambient (QFN16 Package) R(cid:2)JA 48 Operating Junction Temperature Range (Note 1) TJ −40 to + 150 °C Operating Ambient Temperature Range TA − 40 to + 85 °C Storage Temperature Range Tstg − 55 to +150 °C Moisture Sensitivity Level MSL 1 − Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. 1. Internally limited by thermal shutdown, 150°C min. http://onsemi.com 5

NCP5212A, NCP5212T ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = VCCP = 5 V, TA =−40°C to 85°C, unless other noted) Characteristics Symbol Test Conditions Min Typ Max Unit SUPPLY VOLTAGE Input Voltage VIN 4.5 − 27 V VCC Operating Voltage VCC 4.5 5.0 5.5 V SUPPLY CURRENT VCC Quiescent Supply Current in IVCC_Master EN = VEN_Master, VFB forced above 1.5 2.5 mA Master operation regulation point. DH, DL are open VCC Quiescent Supply Current in IVCC_Slave EN = VEN_Slave, VFB forced above 1.5 2.5 mA Slave Operation regulation point, DH, DL are open VCC Shutdown Current IVCC_SD EN = VEN_Disable, VCC = 5 V, True 1 (cid:3)A Shutdown BST Quiescent Supply Current in IBST_Master EN = VEN_Master, VFB forced above 0.3 mA Master Operation regulation point, DH and DL are open, No boost trap diode BST Quiescent Supply Current in IBST_Slave EN = VEN_Slave, VFB forced above 0.3 mA Slave Operation regulation point, DH and DL are open No boost trap diode BST Shutdown Current IBST_SD EN = 0 V 1 (cid:3)A VCCP Shutdown Current IVCCP_SD EN = 0 V, VCCP = 5 V 1 (cid:3)A VIN Supply Current IVIN EN = 5V, VIN = 27 V 35 (cid:3)A VIN Shutdown Current IVIN_SD EN = 0 V, VIN = 27 V 1 (cid:3)A VOLTAGE−MONITOR Rising VCC Threshold VCCth+ Wake Up 4.05 4.25 4.48 V VCC UVLO Hysteresis VCCHYS 200 275 400 mV Rising VIN Threshold VINth+ Wake Up, Design Spec. (Note 2) 3.4 3.8 4.2 V VIN UVLO Hysteresis VINHYS (Note 2) 200 500 800 mV Power Good High Threshold VPGH PGOOD in from NCP5212A 105 110 115 % higher Vo (PGOOD goes NCP5212T 120 125 130 high) Power Good High Hysteresis VPGH_HYS PGOOD high hysteresis (PGOOD 5 % goes low) Power Good Low Threshold VPGL PGOOD in from lower Vo (PGOOD 80 85 90 % goes high) Power Good Low Hysteresis VPGL_HYS PGOOD low hysteresis (PGOOD goes −5 % low) Power Good High Delay Td_PGH After Tss, (Note 2) 1.25 ms Power Good Low Delay Td_PGL (Note 2) 1.5 (cid:3)s Output Overvoltage Rising Threshold OVPth+ With respect to NCP5212A 110 115 120 % Error Comparator Threshold of 0.8 V NCP5212T 125 130 135 Overvoltage Fault Propagation Delay OVPTblk FB forced 2% above trip threshold 1.5 (cid:3)s (Note 2) Output Undervoltage Trip Threshold UVPth With respect to Error Comparator 75 80 85 % Threshold of 0.8 V Output Undervoltage Protection UVPTblk (Note 2) − 8/fsw − s Blanking Time REFERENCE OUTPUT Internal Reference Voltage Vref 0.7936 0.8 0.8064 V 2. Guaranteed by design, not tested in production. http://onsemi.com 6

NCP5212A, NCP5212T ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = VCCP = 5 V, TA =−40°C to 85°C, unless other noted) Characteristics Symbol Test Conditions Min Typ Max Unit OSCILLATOR Operation Frequency FSW 270 300 330 kHz OVERCURRENT THRESHOLD Total Detection Time TDETECT Period of FB shorts to ground before 1.26 1.92 2.21 ms SS OCSET Detection Time T_OCDET (Note 2) 1.09 1.47 ms INTERNAL SOFT−START Soft−Start Time TSS 0.9 1.1 1.3 ms VOLTAGE ERROR AMPLIFIER DC Gain GAIN_VEA (Note 2) 88 dB Unity Gain Bandwidth BW_VEA (Note 2) 15 MHz Slew Rate SR_VEA COMP PIN TO GND = 100 pF 2.5 V/(cid:3)s (Note 2) FB Bias Current Ibias_FB 0.1 (cid:3)A Output Voltage Swing Vmax_EA Isource_EA = 2 mA 3.3 3.5 V Vmin_EA Isink_EA = 2 mA 0.15 0.3 V DIFFERENTIAL CURRENT SENSE AMPLIFIER CS+ and CS− Common−mode Input VCSCOM_MAX Refer to AGND 3.5 V Signal Range Input Bias Current CS_IIB −100 100 nA Input Signal Range CS_range −70 70 mV Offset Current at IDRP IDRP_offset (CS+) − (CS−) = 0 V −1.0 1.0 (cid:3)A [(CS+)−(CS−)] to IDRP Gain IDRP_GAIN (CS+) − (CS−) = TA = 25°C 0.475 0.525 0.575 (cid:3)A/mV (IDRP/((CS+) 10 mV, V(IDRP) = − (CS−))) 0.8 V TA = −40°C to 0.425 0.625 (cid:3)A/mV 85°C Current−Sense Bandwidth BW_CS At −3dB to DC Gain (Note 2) 20 MHz Maximum IDRP Output Voltage IDRP_Max (CS+) − (CS−) = 70 mV, Isource drops 2.5 V to 95% of the value when V(IDRP) = 0.8 V Minimum IDRP Output Voltage IDRP_Min 0 V IDRP Output current I_IDRP −1.0 35 (cid:3)A OVERCURRENT PROTECTION SETTING Overcurrent Threshold (OCTH) I_OCSET Sourced from OCP before soft−start, 21.6 24 26.4 (cid:3)A Detection Current Rocset = 16.7 k(cid:4) is connected from OCP to AGND or FB Ratio of OC Threshold over OCSET K_OCSET V((CS+) − (CS−)) / V_OCSET 0.1 − Votlage (Note 2) OCSET Voltage for Default Fixed OC VOCSET_DFT Rocset (cid:2) 2 k(cid:4) is connected from 100 mV Threshold OCP to AGND or FB OCSET Voltage for Adjustable OC VOCSET_ADJ Rocset = 8.3 ~ 25 k(cid:4) is connected 200 600 mV Threshold from OCP to AGND or FB OCSET Voltage for OC Disable VOCSET_DIS Rocset (cid:3) 35 k(cid:4) is connected from 720 mV OCP to AGND or FB Default Fixed OC Threshold V_OCTH_DFT (CS+) – (CS−), Pin OCP is shorted to 35 40 45 mV AGND or FB 2. Guaranteed by design, not tested in production. http://onsemi.com 7

NCP5212A, NCP5212T ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = VCCP = 5 V, TA =−40°C to 85°C, unless other noted) Characteristics Symbol Test Conditions Min Typ Max Unit OVERCURRENT PROTECTION SETTING Adjustable OC Threshold V_OCTH (CS+) – (CS−), VOCSET = 15 20 25 mV ((CS+)−(CS−)) During OC 200 mV threshold, set a voltage at pin VOCSET = 52 60 68 OCP 600 mV GATE DRIVERS DH Pull−HIGH Resistance RH_DH 200 mA Source current 1 (cid:4) DH Pull−LOW Resistance RL_DH 200 mA Sink current 1 (cid:4) DL Pull−HIGH Resistance RH_DL 200 mA Source current 1 (cid:4) DL Pull−LOW Resistance RL_DL 200 mA Sink current 0.5 (cid:4) DH Source Current Isource_DH (Note 2) 2.5 A DH Sink Current Isink_DH (Note 2) 2.5 A DL Source Current Isource_DL (Note 2) 2.5 A DL Sink Current Isink_DL (Note 2) 5 A Dead Time TD_LH DL−off to DH−on (Note 2) 20 ns TD_HL DH−off to DL−on (Note 2) 20 ns Negative Current Detection Threshold NCD_TH SWN − PGND, at EN = 5 V −1 mV SWN source leakage ISWN_SD EN = 0 V, SWN = 0 V 1 (cid:3)A Internal Resistor from DH to SWN R_DH_SWN (Note 2) 100 k(cid:4) CONTROL SECTION EN Logic Input Voltage for Disable VEN_Disable Set as Disable 0.7 1.0 1.3 V Hysteresis 150 200 250 mV EN Logic Input Voltage for MASTER VEN_Master Set as Master Mode 1.7 1.95 2.25 V Mode EN Logic Input Voltage for SLAVE VEN_Slave Set as Slave Mode 2.4 2.65 2.9 V Mode Hysteresis 100 175 250 mV EN Source Current IEN_SOURCE VEN = 0 V 0.1 (cid:3)A EN Sink Current IEN_SINK VEN = 5 V 0.1 (cid:3)A PGOOD Pin ON Resistance PGOOD_R I_PGOOD = 5 mA 100 (cid:4) PGOOD Pin OFF Current PGOOD_LK 1 (cid:3)A SYNC CONTROL SYNC pin leakage ISYNC_LK Set as Slave Mode, SYNC = 5 V 1 uA SYNC frequency F_SYNC (Note 2) 1.2 MHz Pulse Width PW_SYNC (Note 2) 416 ns Clock Level Low V_CLKL (Note 2) 0 V Clock Level High V_CLKH (Note 2) 5 V SYNC Driving Capability SYNC_CL Set as Master Mode, load capacitor 20 pF between SYNC and GND (Note 2) SYNC Source Current ISYNC SYNC shorts to ground 20 mApp OUTPUT DISCHARGE MODE Output Discharge On−Resistance Rdischarge EN = 0 V 20 35 (cid:4) Threshold for Discharge Off Vth_DisOff 0.2 0.3 0.4 V 2. Guaranteed by design, not tested in production. http://onsemi.com 8

NCP5212A, NCP5212T ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = VCCP = 5 V, TA =−40°C to 85°C, unless other noted) Characteristics Symbol Test Conditions Min Typ Max Unit TRE SETTING TRE Threshold Detection Current I_TRESET Sourced from DL in the short period 7.2 8 8.8 (cid:3)A before soft−start. (Rtre = 47 k(cid:4) is connected from DL to GND Detection Voltage for TRE Threshold VDL_TRE_1 Internal TRE_TH Rtre (cid:3) 75 k(cid:4) 500 600 700 mV Selection (Default) is set to 300 mV (Note 2) VDL_TRE_2 Internal TRE_TH Rtre = 44 − 50 k(cid:4) 300 450 is set to 500 mV (Note 2) VDL_TRE_3 TRE is Disabled Rtre (cid:2) 25 k(cid:4) 0 250 (Note 2) TRE Comparator Offset TRE_OS (Note 2) 10 mV Propagation Delay of TRE TD_PWM (Note 2) 20 ns Comparator THERMAL SHUTDOWN Thermal Shutdown Tsd (Note 2) 150 °C Thermal Shutdown Hysteresis Tsdhys (Note 2) 25 °C 2. Guaranteed by design, not tested in production. http://onsemi.com 9

NCP5212A, NCP5212T TYPICAL OPERATING CHARACTERISTICS 0.83 200 A) n 0.82 T ( 150 N V) RE E ( 0.81 R 100 G U A C OLT 0.80 WN 50 V O V ref0.79 UTD 0 B H F S V 0.78 N −50 PI C C 0.77 V −100 −40 −15 10 35 60 85 −40 −15 10 35 60 85 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) Figure 4. V Voltage vs Ambient Temperature Figure 5. V Shutdown Current vs Ambient ref CC Temperature 315 0.80 z) H k Y ( 310 0.70 C UEN 305 mV) 0.60 Q A/ E (cid:3) G FR 300 Gain ( 0.50 N _ CHI 295 DRP 0.40 WIT I S 290 0.30 W S F 285 0.20 −40 −15 10 35 60 85 −40 −15 10 35 60 85 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) Figure 6. Switching Frequency vs Ambient Figure 7. IDRP Gain vs Ambient Temperature Temperature 40 43 A) V) NT (n 30 D (m 42 E L R O R H U 20 S 41 C E N HR OW 10 C T 40 D O HUT 0 FIX 39 S T N UL PI −10 A 38 ST EF B D −20 37 −40 −15 10 35 60 85 −40 −15 10 35 60 85 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) Figure 8. BST Shutdown Current vs Ambient Figure 9. Default Fix OC Threshold vs Ambient Temperature Temperature http://onsemi.com 10

NCP5212A, NCP5212T TYPICAL OPERATING CHARACTERISTICS Top to Bottom: EN, SWN, Vo, PGOOD Top to Bottom: EN, SWN, Vo, PGOOD Figure 10. Powerup Sequence Figure 11. Powerdown Sequence Top to Bottom: SWN_Slave, Vo_Slave, SWN_Master, Top to Bottom: SWN_Slave, Vo_Slave, SWN_Master, Sync_clk Sync_clk Figure 12. From Unsync to Sync Figure 13. From Sync to Unsync Top to Bottom: SWN, Vo, Io Figure 14. Typical Transient http://onsemi.com 11

NCP5212A, NCP5212T DETAILED OPERATING DESCRIPTION General The NCP5212A/NCP5212T synchronous stepdown power controller contains a PWM controller for wide battery/adaptor voltage range applications The NCP5212A/NCP5212T includes power good voltage monitor, soft−start, overcurrent protection, undervoltage protection, overvoltage protection and thermal shutdown. The NCP5212A/NCP5212T features power saving function which can increase the efficiency at light load. It is ideal for battery operated systems. The IC is packaged in QFN16. Control Logic The internal control logic is powered by V . The device CC is controlled by an EN pin. The EN pin serves two functions. Top to Bottom: VIN AC Voltage, SWN_Slave, SWN_Master When voltage of EN is below VEN_Disable, it shuts down the device. When the voltage of EN is at the level of Figure 15. Two Devices are Unsynchronized VEN_Master, the device is operating as Master mode. When voltage level of EN is at VEN_Slave, the device is operating as Slave mode. It should be noted that no matter the device is operating either at Master or Slave mode, the device is operating in the manner of auto power saving condition such that it operates as skip mode automatically at light load. When EN is above VEN_Disable, the internal V is ref activated and power−on reset occurs which resets all the protection faults. Once V reaches its regulation voltage, an ref internal signal will wake up the supply undervoltage monitor which will assert a “GOOD” condition. In addition, the NCP5212A/NCP5212T continuously monitors V and CC V levels with undervoltage lockout (UVLO) function. IN Single Device Operation The device is operating as single device operation when Top to Bottom: VIN AC Voltage, SWN_Slave, SWN_Master the SYNC pin is pull to ground. Under this configuration, the device will use the internal clock for normal PWM Figure 16. Two Devices are in Interleaved Operation operation. Dual Device Operation (Master/Salve Mode) Transient Response Enhancement (TRE) The device is operating as Master/Slave mode if two For the conventional PWM controller in CCM, the fastest devices are tied up together. (Detail configuration please see response time is one switching cycle in the worst case. To the application schematic) One device is served as Master further improve transient response in CCM, a transient and another one is served as Slave. Once they already, they response enhancement circuitry is implemented inside the are synchronized to each other and they are operating as NCP5212A/NCP5212T. In CCM operation, the controller is “interleaved” mode such that the phase shift of their continuously monitoring the COMP pin output voltage of switching clocks is 180°. It has the benefit that the amount the error amplifier to detect the load transient events. The of ripple current at the V will be lower and hence lesser functional block diagram of TRE is shown below. IN bulk capacitors at V to save the confined PCB space and IN material cost. Figure 15 and Figure 16 show the difference COMP + when the devices are operating independently TRE (unsynchronized) and operating at interleaved mode R + (Synchronized). It can be seen that at the unsynchronized C condition, the system is obviously noisy because of high internal TRE_TH ripple voltage at V (ripple voltage directly reflects the IN amount of ripple current at VIN). Once the devices are Figure 17. Block Diagram of TRE Circuit operating at interleaving mode, the overall V ripple IN current is significantly reduced. http://onsemi.com 12

NCP5212A, NCP5212T Once the large transient occurs, the COMP signal may be Adaptive Voltage Positioning (AVP) large enough to exceed the threshold and then TRE “flag” For applications with fast transient currents, adaptive signal will be asserted in a short period which is typically voltage positioning can reduce peak−to−peak output voltage around one normal switching cycle. In this short period, the deviations due to load transients. With the use of AVP, the controller will be running at high frequency and hence has output voltage allows to have some controlled sag when load faster response. After that the controller comes back to current is applied. Upon removal of the load, the output normal switching frequency operation. We can program the voltage returns no higher than the original level, just internal TRE threshold (TRE_TH). For detail please see the allowing one output transient peak to be cancelled over a electrical table of “TRE Setting” section. Basically, the load step up and release cycle. The amount of AVP is recommend internal TRE threshold value is around 1.5 adjustable. times of peak−to−peak value of the COMP signal at CCM The behaviors of the Vo waveforms with or without AVP operation. The higher the internal TRE_TH, the lower are depicted at Figure 20. sensitivity to load transient. The TRE function can be disable by setting the Rtre which is connecting to DL/TRE pin to less than 25 k(cid:4). For system component saving, it is usually set as default value, that is, Rtre is open ((cid:3)75 k(cid:4)) and internal TRE_TH is 300 mV typical. Vo With AVP Vo Without AVP Figure 20. Adaptive Voltage Positioning Vo Rt FB + Rb COMP Rocp + Vref − IDRP IDRP/OCP L Rs1 CS+ Top to Bottom SWN, Vo, Transient Signal + DCR Cs Rs2 Gi CS− Figure 18. Transient Response with TRE Disable Figure 21. Configuration for AVP Function The Figure 21 shows how to realize the AVP function. A current path is connecting to the FB pin via Rocp resistor. Rocp is not actually for AVP function, indeed, Rocp is used for OCP threshold value programming. The IDRP/OCP pin has dual functions: OCP programming and AVP. At the IDRP/OCP pin, conceptually there is a current source which is modulated by current sensing amplifier. The output voltage V with AVP is: o V (cid:4)V 0(cid:5)I *R (eq. 1) O O O LL Where I is the load current, no load output voltage V0 is o o set by the external divider that is: Top to Bottom SWN, Vo, Transient Signal (cid:6) (cid:8) Rt V 0(cid:4) 1(cid:7) *V (eq. 2) Figure 19. Transient Response with TRE Enable O Rb ref http://onsemi.com 13

NCP5212A, NCP5212T The load line impendence R is given by: LL Rs2 R (cid:4)DCR*Gain_CS*Rt* (eq. 3) LL Rs1(cid:7)Rs2 Where DCR is inductor DC resistance. Gain_CS is a gain from [(CS+)−(CS−)] to IDRP Gain (At electrical table, the symbol is IDRP_GAIN), the typical value is 0.525 (cid:3)A/mV. The AVP function can be easily disable by shorting the Rocp resistor into ground. From the equation we can see that the value of “top” resistor Rt can affect the amount of R , so it is LL recommended to define the amount of R FRIST before LL defining the compensation component value. And if the user wants to fine tune the compensation network for optimizing Top to Bottom : SWN, Vo, PGOOD, Io the transient performance, it is NOT recommend to adjust Figure 23. Overcurrent Protection the value of Rt. Otherwise, both transient performance and AVP amount will be affected. The following diagram shows The NCP5212A/NCP5212T uses lossless inductor the typical waveform of AVP. Note that the Rt typical value should be above 1 k(cid:4). current sensing for acquiring current information. In addition, the threshold OCP voltage can be programmed to some desired value by setting the programming resistor Rocp. Vo Rt FB + Rb COMP + − Vref IDRP IDRP/OCP L Rs1 Rocp CS+ + DCR Cs CRSs−2 Gi Without AVP Top to Bottom: SWN, Vo, Transient Signal Vo Figure 22. Typical waveform of AVP Rt FB + Rb COMP Rocp Over Current Protection (OCP) +− Vref IDRP The NCP5212A/NCP5212T protects power system if IDRP/OCP over current event occurs. The current is continuously L Rs1 CS+ mcuorrneintot redli mbyit theth dreifsfheoreldn tiavl oclutargreen t VseOnsCinSgE Tc irccuaitn. Tbhee DCR Cs RsC2S− +Gi programmed by resistor ROCSET connecting at the IDRP/OCP pin. However, fixed default VOCSET can be With AVP achieved if ROCSET is less than 2 k(cid:4). Figure 24. OCP Configuration If the inductor current exceeds the current threshold continuously, the top gate driver will be turned off cycle by It should be noted that there are two configurations for cycle. If it happens over consecutive 16 clock cycles time Rocp resistor. If Adaptor Voltage Position (AVP) is used, the (16 x 1/f ), the device is latched off such that top and SW Rocp should be connected to FB pin. If AVP is not used, the bottom gate drivers are off. EN resets or power recycle the Rocp should be connected to ground. At the IDRP/OCP pin, device can exit the fault. The following diagram shows the there is a constant current(24 (cid:3)A typ.) flowing out during the typical behavior of OCP. http://onsemi.com 14

NCP5212A, NCP5212T programming stage at system start up. This is used to sense resets or power recycle the device can exit the fault. The the voltage level which is developed by a resistor Rocp so as following diagram shows the typical waveform when OVP to program the overcurrent detection threshold voltage. For event occurs. typical application, the V is set as default value(40 mV octh typ) by setting Rocp = 0 (cid:4), or directly short the IDRP/OCP pin to ground. It has the benefit of saving one component at application board. For other programming values of V , octh please refer to the electrical table of “Overcurrent Protection Setting” section. Guidelines for selecting OCP Trip Component 1.Choose the value of Rocp for V selection. octh 2.Define the DC value of OCP trip point(I ) OCP_DC that you want. The typical value is 1.5 to 1.8 times of maximum loading current. For example, if maximum loading is 10 A, then set OCP trip point at 15 A to 18 A. 3.Calculate the inductor peak current (I )which is pk Top to Bottom : SWN, DL, Vo, PGOOD estimated by the equation: Figure 25. Overvoltage Protection V *(V (cid:5)V ) I (cid:4)I (cid:7) o IN o (eq. 4) pk OCP_DC 2*V *f *L IN SW o Undervoltage Protection (UVP) 4.Check with inductor datasheet to find out the value An UVP circuit monitors the V voltage to detect under FB of inductor DC resistance DCR, then calculate the voltage event. The under voltage limit is 80% (typical) of the RS1, RS2 dividing factor k based on the equation: nominal V voltage. If the V voltage is below this FB FB V threshold over consecutive 8 clock cycles, an UV fault is set k(cid:4) octh (eq. 5) and the device is latched off such that both top and bottom I *DCR pk gate drives are off. EN resets or power recycle the device can 5.Select CS value between 100 nF to 200 nF. exit the fault. Typically, 100 nF will be used. 6.Calculate Rs1 value by the equation: L Rs1(cid:4) (eq. 6) k*DCR*Cs 7.Calculate Rs2 value by the equation: k*Rs1 Rs2(cid:4) (eq. 7) 1(cid:5)k 8.Hence, all the current sense components Rs1, Rs2, Cs had been found for taget I . OCP_DC 9.If Rs2 is not used (open), set k = 1, at that moment, the I will be restricted by: pk V I (cid:4) octh (eq. 8) pk DCR Top to Bottom : SWN, Vo, PGOOD Overvoltage Protection (OVP) Figure 26. Undervoltage Protection When V voltage is above OVPth+ of the nominal V FB FB voltage for over 1.5 (cid:3)s blanking time, an OV fault is set. At that moment, the top gate drive is turned off and the bottom Thermal Shutdown gate drive is turned on until the V below lower under The IC will shutdown if the die temperature exceeds FB voltage (UV) threshold and bottom gate drive is turned on 150°C. The IC restarts operation only after the junction again whenever V goes above upper UV threshold. EN temperature drops below 125°C. FB http://onsemi.com 15

NCP5212A, NCP5212T C28 R220 D22 C27 C26 VIN R224 R29 R7 M1 LED1 PGOOD C24 DH M3 PGND PGOOD M5 SWN R28 TPAD L1 C1 C2C216D23 VOUT U1 1D6 1N5 1H4 1T3 R22 R1 R25 R24 PGND RC2123 1 VINPGOO SW D VBSCCP12 C29 DL M4 R212 J21 R23 +5V 2 VCC DL/TRESET11 D21 C21 C22 NCP5212A/T R27 R26 M2 C212 PGNDPGND AGND R2 EN 3 SYN CP PGND10 SYNC JP3 4 ENCOMP FB IDRP/O CS−/VoCS+ 9 C25 5 6 7 8 R216 JP2 COMP FB C214 R213 R211 C213 R214C215 R215 C3 J2 R223 1 2 3 R210 PGND AGND 1−2 = OCP Only 3−2 = OCP + AVP Figure 27. Demo Board Schematic http://onsemi.com 16

NCP5212A, NCP5212T DEMO BOARD BILL OF MATERIAL BOM (See next tables for compensation network and power stage) Designator Qty Description Value Footprint Manufacturer Manufacturer P/N U1 1 Single Synchronous Stepdown − QFN 16PIN ON Semiconductor NCP5212MNR2G Controller R1 1 Chip Resistor, (cid:9)5% DNP − − − R2 1 Chip Resistor, (cid:9)5% 10k 0603 Panasonic ERJ3GEYJ103V R7 1 Chip Resistor, (cid:9)5% 1k 0603 Panasonic ERJ3GEYJ102V R21 1 Chip Resistor, (cid:9)5% 20 0603 Panasonic ERJ3GEYJR200V R22 1 Chip Resistor, (cid:9)5% 0 0603 Panasonic ERJ3GEYJR00V R23 1 Chip Resistor, (cid:9)5% 5.6 0603 Panasonic ERJ3GEYJR5R6V R26 1 Chip Resistor, (cid:9)5% 0 0603 Panasonic ERJ3GEYJR00V R27 1 Chip Resistor, (cid:9)5% DNP − − − R28 1 Chip Resistor, (cid:9)5% 0 0603 Panasonic ERJ3GEYJR00V R29 1 Chip Resistor, (cid:9)5% 5.6 0603 Panasonic ERJ3GEYJR5R6V R210 1 Chip Resistor, (cid:9)1% 1k 0603 Panasonic ERJ3EKF1001V R212 1 Chip Resistor DNP 0603 Panasonic ERJ3EKF2403V R216 1 Chip Resistor, (cid:9)5% 10k 0603 Panasonic ERJ3GEYJ103V R220 1 Chip Resistor, (cid:9)5% 0 0603 Panasonic ERJ3GEYJR00V R223 1 Chip Resistor, (cid:9)1% 1k 0603 Panasonic ERJ3EKF1001V R224 1 Chip Resistor, (cid:9)5% 100k 0603 Panasonic ERJ3GEYJ104V C3 1 − DNP − − − C21 1 MLCC Chip Capacitor, (cid:9)20% Temp 1 (cid:3)F 0805 Panasonic ECJ2FB1E105M Char: X5R, Rate V = 25 V, C22 1 MLCC Chip Capacitor, (cid:9)20% Temp 1 (cid:3)F 0805 Panasonic ECJ2FB1E105M Char: X5R, Rate V = 25 V C23 1 MLCC Chip Capacitor, (cid:9)10% Temp 15 nF 0805 Panasonic ECJ1VB1E153K Char: X7R, Rate V = 50 V C24 1 MLCC Chip Capacitor, (cid:9)10% Temp 100 nF 0603 Panasonic ECJ1VB1E104K Char: X7R, Rate V = 50 V C25 1 MLCC Chip Capacitor 100 nF 0603 Panasonic ECJ1VB1E104K Temp Char: X7R, (cid:9)10% Rate V = 50 V C26 1 MLCC Chip Capacitor 10 (cid:3)F 1206 Panasonic ECJ3YB1E106M Temp Char: X5R, (cid:9)20% Rate V = 25 V C27 1 MLCC Chip Capacitor 10 (cid:3)F 1206 Panasonic ECJ3YB1E106M Temp Char: X5R, (cid:9)20% Rate V = 25 V C28 1 MLCC Chip Capacitor 10 (cid:3)F 1206 Panasonic ECJ3YB1E106M Temp Char: X5R, (cid:9)20% Rate V = 25 V C29 1 MLCC Chip Capacitor 1 (cid:3)F 1206 Panasonic ECJ3YB1E105M Temp Char: X5R, (cid:9)20% Rate V = 25 V C212 1 DNP − − − C216 1 MLCC Chip Capacitor 1 (cid:3)F 0805 Panasonic ECJ2FB1E105M Temp Char: X5R, (cid:9)20% Rate V = 25 V M5 1 Power MOSFET 50 V, 200 mA Single − SOT−23 ON Semiconductor BSS138L N−Ch D21 1 − DNP − − − D22 1 30 V Schottky Diode − SOT−23 ON Semiconductor BAT54LT1 Vf = 0.35 V @ 10 mA D23 1 − DNP − − − SYNC, J21 2 SMB SMT Straight Socket − 5.1 x 5.1 mm Tyco Electonics RS Stock# 420−5401 JP2, JP3, J2, EN, 12 Pin Header Single Row − Pitch = 2.54 mm Betamax 2211S−40G−F1 FB, COMP, DH, DL, SWN, PGOOD, PGND, PGND LED1 1 Surface Mount LED − 0805 LUMEX SML−LX0805GC−TR Color = Green +5V, AGND, GND, 1 Terminal Pin − f = 1.74 mm HARWIN H2121−01 VOUT, VIN, PGND http://onsemi.com 17

NCP5212A, NCP5212T DEMO BOARD BILL OF MATERIAL (Vo = 1.1 V, Io = 18 A) Item Component Value Tol Footprint Manufacturer Manufacturer P/N R211 3k 1% 0603 Panasonic ERJ3EKF3001V R213 68k 1% 0603 Panasonic ERJ3EKF6802V R214 300 1% 0603 Panasonic ERJ3EKF3000V Compensation Network R215 8k 1% 0603 Panasonic ERJ3EKF8001V C213 24 pF 10% 0603 Panasonic ECJ1VC1H241K C214 470 pF 10% 0603 Panasonic ECJ1VB1H471K C215 820 pF 10% 0603 Panasonic ECJ1VB1H821K M1, M3 − − SOIC8−FL ON Semiconductor NTMFS4821N M2, M4 − − SOIC8−FL ON Semiconductor NTMFS4847N L1 0.56 (cid:3)H 20% 10x11.5 mm Cyntec PCMC104T−R56MN Power Stage & R24 DNP − − − − Current Sense R25 4k 1% 0603 Panasonic ERJ3EKF4301V C1, C2, C2A* 330 uF 20% 7343 Panasonic EEFSX0D331XR 6 m(cid:4) Sanyo 2TPLF330M6 *C2A is the capacitor soldered right beside of C2. DEMO BOARD BILL OF MATERIAL (Vo = 1.5 V, Io = 8 A) Item Component Value Tol Footprint Manufacturer Manufacturer P/N R211 5k 1% 0603 Panasonic ERJ3EKF5001V R213 75k 1% 0603 Panasonic ERJ3EKF7502V R214 1k 1% 0603 Panasonic ERJ3EKF1001V Compensation Network R215 5.6k 1% 0603 Panasonic ERJ3EKF5601V C213 9 pF 10% 0603 Panasonic ECJ1VC1H900K C214 270 pF 10% 0603 Panasonic ECJ1VB1H271K C215 330 pF 10% 0603 Panasonic ECJ1VB1H331K M1, M2 − − SO8 ON Semiconductor NTMS4705N M3, M4 DNP − − − − 10x11.5 mm Cyntec PCMC104T−1R0MN L1 1 (cid:3)H 20% 13x14x4.9mm WE 744315120 Power Stage & Current Sense R24 DNP − − − − R25 4.3k 1% 0603 Panasonic ERJ3EKF4301V C1, C2 220 (cid:3)F 20% 7343 Panasonic EEFUD0D221XR 12 m(cid:4) Sanyo 2R5TPL220MC ORDERING INFORMATION Device Package Shipping† NCP5212AMNTXG QFN16 3000 / Tape & Reel (Pb−Free) NCP5212TMNTXG QFN16 3000 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 18

NCP5212A, NCP5212T PACKAGE DIMENSIONS QFN16 4x4, 0.65P CASE 485AP−01 ISSUE A L L NOTES: 1. DIMENSIONING AND TOLERANCING PER D A ASME Y14.5M, 1994. B 2. CONTROLLING DIMENSION: MILLIMETERS. ÇÇ L1 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN PIN 1 ÇÇ 0.15 AND 0.30 MM FROM TERMINAL TIP. REFERENCE DETAIL A 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. ÇÇ E OPTIONAL LEAD CONSTRUCTIONS MILLIMETERS DIM MIN MAX A3 A 0.80 1.00 2X 0.15 C EXPOSED CÉu ÉMOLD CMPDÉÉÉ A1 0.00 0.05 TOP VIEW A3 0.20 REF 2X 0.15 C ÉÉÉÉ ÉÇÉÇÉÇ Db 0.42.500 BS0C.35 D2 2.00 2.20 (A3) A A1 E 4.00 BSC DETAIL B E2 2.00 2.20 0.10 C DETAIL B e 0.65 BSC OPTIONAL LEAD K 0.20 −−− CONSTRUCTIONS L 0.45 0.65 16X 0.08 C L1 −−− 0.15 NOTE 4 SIDE VIEW A1 C SEATING PLANE MOUNTING FOOTPRINT* DETAIL A D2 16X L 4.30 5 8 2.25 4 9 PKG E2 OUTLINE 1 1 12 16 13 16Xb 16X K e 0.10 C A B 0.65 BOTTOM VIEW 0.05 C NOTE 3 4.30 2.25 PITCH 16X 16X 0.78 0.35 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5773−3850 Sales Representative http://onsemi.com NCP5212A/D 19

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