ICGOO在线商城 > 集成电路(IC) > PMIC - 稳压器 - 线性 > NCP4624DMU30TCG
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NCP4624DMU30TCG产品简介:
ICGOO电子元器件商城为您提供NCP4624DMU30TCG由ON Semiconductor设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 NCP4624DMU30TCG价格参考¥2.15-¥2.15。ON SemiconductorNCP4624DMU30TCG封装/规格:PMIC - 稳压器 - 线性, Linear Voltage Regulator IC Positive Fixed 1 Output 3V 150mA 4-UDFN (1.0x1.0)。您可以下载NCP4624DMU30TCG参考资料、Datasheet数据手册功能说明书,资料中有NCP4624DMU30TCG 详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
产品目录 | 集成电路 (IC) |
描述 | IC REG LDO 3V 0.15A 4UDFN |
产品分类 | |
品牌 | ON Semiconductor |
数据手册 | |
产品图片 | |
产品型号 | NCP4624DMU30TCG |
rohs | 无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | - |
供应商器件封装 | 4-UDFN(1.0x1.0) |
其它名称 | NCP4624DMU30TCGOSCT |
包装 | 剪切带 (CT) |
安装类型 | 表面贴装 |
封装/外壳 | 4-UDFN 裸露焊盘 |
工作温度 | -40°C ~ 85°C |
标准包装 | 1 |
电压-跌落(典型值) | 0.61V @ 150mA |
电压-输入 | 最高 11V |
电压-输出 | 3V |
电流-输出 | 150mA |
电流-限制(最小值) | - |
稳压器拓扑 | 正,固定式 |
稳压器数 | 1 |
NCP4624 150 mA, Wide Input Range, LDO Linear Voltage Regulator The NCP4624 is a CMOS 150 mA LDO linear voltage regulator which features high input voltage range while maintaining low www.onsemi.com quiescent current 2 (cid:2)A typically. Several protection features like Current Limiting and Reverse Current Protection Circuit are fully MARKING integrated to create a versatile device suitable for the power source DIAGRAMS being in the standby−mode. A high maximum input voltage (11 V) and wide temperature range (−40°C to 85°C) makes the NCP4624 device with output capacitor as low as 0.1 (cid:2)F an ideal choice for industrial XXXMM applications also a portable equipments powered by 2−cell Li−ion SOT−23−5 CASE 1212 battery. 1 Features • Operating Input Voltage Range: 2.5 V to Set V + 6.5 V, Max. OUT 11 V 1 XX • MM Output Voltage Range: 1.2 to 5.5 V (available in 0.1 V steps) 1 UDFN4 • ±2% Output Voltage Accuracy CASE 517BR • Output Current: min. 150 mA • Line Regulation: 0.02%/V • Current Limit Circuit • XXXX M(cid:2) Available in SOT−23−5, UDFN4 1.0 x 1.0 mm and SC−88A Package SC−88A (cid:2) • Built−in Reverse Current Protection Circuit (SC−70−5/SOT−353) • CASE 419A 1 These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant XX, XXX, XXXX= Specific Device Code Typical Applications • M, MM = Date Code Home Appliances, Industrial Equipment A = Assembly Location • Cable Boxes, Satellite Receivers, Entertainment Systems Y = Year • W = Work Week Car Audio Equipment, Navigation Systems (cid:2) = Pb−Free Package • Notebook Adaptors, LCD TVs, Cordless Phones and Private LAN (Note: Microdot may be in either location) Systems • Battery−Powered Portable Communication Equipments NCP4624x ORDERING INFORMATION VIN VOUT See detailed ordering and shipping information in the package VIN VOUT dimensions section on page 15 of this data sheet. C1 C2 CE 0.1(cid:2)F GND 0.1(cid:2)F Figure 1. Typical Application Schematic © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: August, 2017 − Rev. 3 NCP4624/D
NCP4624 NCP4624xxxx NCP4624Dxx Vin Vout Vin Vout Vref Vref Current Limit Current Limit CE CE Reverse Detector Reverse Detector GND GND Figure 2. Simplified Schematic Block Diagram PIN FUNCTION DESCRIPTION Pin No. SOT−23−5 SC−88A UDFN 1x1 Pin Name Description 1 5 4 VIN Input pin 2 3 2 GND Ground pin 3 1 3 CE Chip enable pin (“H” active) 4 2 NC Non connected 5 4 1 VOUT Output pin *EP EP Exposed Pad (leave floating or connect to GND) ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage (Note 1) V −0.3 to 12 V IN Output Voltage VOUT −0.3 to VIN ≤ 11 V Chip Enable Input VCE −0.3 to VIN ≤ 11 V Power Dissipation SOT−23−5 PD 420 mW Power Dissipation uDFN 1.0 x 1.0 mm 400 Power Dissipation SC−88A 380 Junction Temperature T −40 to 150 °C J Storage Temperature T −55 to 125 °C STG ESD Capability, Human Body Model (Note 2) ESD 2000 V HBM ESD Capability, Machine Model (Note 2) ESD 200 V MM Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to Electrical Characteristics and Application Information for safe operating area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) Latchup Current Maximum Rating tested per JEDEC standard: JESD78. www.onsemi.com 2
NCP4624 THERMAL CHARACTERISTICS Rating Symbol Value Unit Thermal Characteristics, SOT−23−5 R(cid:3)JA 238 °C/W Thermal Resistance, Junction−to−Air Thermal Characteristics, uDFN 1x1 R(cid:3)JA 250 °C/W Thermal Resistance, Junction−to−Air Thermal Characteristics, SC−88A R(cid:3)JA 263 °C/W Thermal Resistance, Junction−to−Air ELECTRICAL CHARACTERISTICS −40°C ≤ TA ≤ 85°C; CIN = COUT = 0.1 (cid:2)F, unless otherwise noted. Typical values are at TA = +25°C. Parameter Test Conditions Symbol Min Typ Max Unit Operating Input Voltage 1.2 V < VOUT < 4.5 V VIN 2.5 Vset + V 6.5 4.5 V ≤ VOUT < 5.5 V 11 Output Voltage Ta = 25°C, VOUT > 1.5 V VOUT x0.99 x1.01 V −40°C < TA < 85°C, VOUT > 1.5V x0.982 x1.018 TA = 25°C, VOUT < 1.5 V −15 +15 mV −40°C < TA < 85°C, VOUT < 1.5V −28 +28 Output Voltage Temp. Coefficient VIN = VOUT + 2 V, IOUT = 100 (cid:2)A, TA = −40 to ±100 ppm/°C 105°C Line Regulation Set VOUT + 0.5 V < VIN < VIN max, IOUT = 1 mA LineReg 0.02 0.20 %/V Load Regulation VIN = VOUT + 2 V, 0.1mA < IOUT ≤ 150 mA LoadReg −35 −3 35 mV IOUT = 150 mA 1.2 V ≤ VOUT < 1.3 V VDO 1.68 2.59 V 1.3 V ≤ VOUT < 1.5 V 1.63 2.49 1.5 V ≤ VOUT < 1.8 V 1.48 2.23 Dropout Voltage 1.8 V ≤ VOUT < 2.3 V 1.16 2.19 2.3 V ≤ VOUT < 3.0 V 0.90 1.47 3.0 V ≤ VOUT < 4.0 V 0.61 1.05 4.0 V ≤ VOUT ≤ 5.5 V 0.39 0.76 Output Current IOUT 150 mA Short Current Limit VOUT = 0 V ISC 45 mA Quiescent Current Iout = 0 mA IQ 2.0 3.7 (cid:2)A Standby Current VIN = VIN max , VCE = 0 V ISTB 0.2 0.6 (cid:2)A CE Pin Pull−Down Current IPD 0.3 0.9 (cid:2)A CE Pin Threshold Voltage CE Input Voltage “H” VCEH 1.7 VIN V CE Input Voltage “L” VCEL 0 0.8 Reverse Current 0 V ≤ VIN < 11 V, VOUT > 1.5 V IREV 0 0.16 (cid:2)A Reverse Current Detection Offset 0 V ≤ VIN < 11 V, VOUT > 1.5 V VREV_DET 55 100 mV Reverse Current Release Offset 0 V ≤ VIN < 11 V, VOUT > 1.5 V VREV_REL 70 120 mV VIN = VOUT + 2.5 V, VOUT = 1.2 V PSRR 27 dB ΔVIN_PK−PK = 0.3 V, Power Supply Rejection Ratio IOUT = 50 mA, f = 1 kHz VOUT = 2.5 V 22 VOUT = 3.3 V 18 VOUT = 5.5 V 15 Output Noise Voltage VOUT = 1.2 V, IOUT = 30 mA, f = 100 Hz to 100 kHz VNOISE 105 (cid:2)Vrms Autodischarge NMOS Resist- VIN = 7.0 V, VCE = 0.0 V (D version only) RDSON 380 (cid:4) ance Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 3
NCP4624 TYPICAL CHARACTERISTICS 1.4 3.5 1.2 3 1 7.5 V 2.5 (V)T 0.8 VIN = 2.5 V 4.0 V (V)T 2 U U VO 0.6 5.5 V VO 1.5 VIN = 9.8 V 0.4 1 5.8 V 0.2 0.5 4.3 V 0 0 00 5500 110000 115500 220000 225500 330000 335500 440000 0 50 100 150 200 250 300 350 400 IOUT (mA) IOUT (mA) Figure 3. Output Voltage vs. Output Current Figure 4. Output Voltage vs. Output Current 1.2 V Version (T = 25(cid:2)C) 3.3 V Version (T = 25(cid:2)C) J J 6 1.4 1.2 5 VIN = 6.5 V 1 4 1 mA V) V) 0.8 IOUT = 50 mA (T 3 (T U U O O 0.6 V 11 V V 30 mA 2 0.4 1 0.2 0 0 00 5500 110000 115500 220000 225500 330000 335500 440000 0 1 2 3 4 5 6 7 IOUT (mA) VIN (V) Figure 5. Output Voltage vs. Output Current Figure 6. Output Voltage vs. Input Voltage 5.5 V Version (T = 25(cid:2)C) 1.2 V Version J 4 7 3.5 6 3 5 2.5 V) V) 4 (T 2 (T U U O O 3 V V 1.5 1 mA 1 mA 2 1 30 mA 30 mA 1 0.5 IOUT = 50 mA IOUT = 50 mA 0 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 11 VIN (V) VIN (V) Figure 7. Output Voltage vs. Input Voltage Figure 8. Output Voltage vs. Input Voltage 3.3 V Version 5.5 V Version www.onsemi.com 4
NCP4624 TYPICAL CHARACTERISTICS 1.22 3.33 3.32 1.21 3.31 V) V) (UT 1.2 (UT 3.3 O O V V 3.29 1.19 3.28 1.18 3.27 −40 −20 0 20 40 60 80 −40 −20 0 20 40 60 80 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 9. Output Voltage vs. Temperature, Figure 10. Output Voltage vs. Temperature, 1.2 V Version 3.3 V Version 5.51 2 5.5 A) (cid:2) 1.6 T ( 5.49 N E V) RR 1.2 (OUT 5.48 T CU V N 0.8 5.47 CE S E 5.46 UI 0.4 Q 5.45 0 −40 −20 0 20 40 60 80 0 1 2 3 4 5 6 7 8 TJ, JUNCTION TEMPERATURE (°C) VIN (V) Figure 11. Output Voltage vs. Temperature, Figure 12. Quiescent Current vs. Input 5.5 V Version Voltage, 1.2 V Version 2.5 2.5 A) 2 A) 2 (cid:2) (cid:2) T ( T ( N N E E R 1.5 R 1.5 R R U U C C T T N 1 N 1 E E C C S S E E UI 0.5 UI 0.5 Q Q 0 0 0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10 12 VIN (V) VIN (V) Figure 13. Quiescent Current vs. Input Figure 14. Quiescent Current vs. Input Voltage, 3.3 V Version Voltage, 5.5 V Version www.onsemi.com 5
NCP4624 TYPICAL CHARACTERISTICS 2 0.8 E (V) 1.6 TA = 85°C E (V) 0.6 G G TA 1.2 TA = −40°C TA L L O O T V TA = 25°C T V 0.4 TA = 85°C U 0.8 U PO PO TA = −40°C RO RO 0.2 TA = 25°C D 0.4 D 0 0 0 30 60 90 120 150 0 30 60 90 120 150 IOUT (mA) IOUT (mA) Figure 15. Dropout Voltage vs. Output Current, Figure 16. Dropout Voltage vs. Output Current, 1.2 V Version 3.3 V Version 0.5 6 E S 5 V) 0.4 OI VOLTAGE ( 0.3 TA = 85°C OLTAGE N√/Hz)s 34 ROPOUT 0.2 TA = 25T°AC = −40°C OUTPUT V(cid:2)(Vrm 2 D 0.1 , N 1 V 0 0 0 30 60 90 120 150 10 100 1k 10k 100k 1M IOUT (mA) FREQUENCY (Hz) Figure 17. Dropout Voltage vs. Output Current, Figure 18. Output Voltage Noise, 1.2 V Version, 5.5 V Version V = 2.5 V, I = 30 mA, C = C = 0.1 (cid:2)F IN OUT in out 12 14 E E 12 S 10 S OI OI N N GE 8 GE 10 Az) Az) TH TH 8 L√ L√ O/s 6 O/s V m V m T Vr T Vr 6 U(cid:2) U(cid:2) P( 4 P( UT UT 4 O O V, N 2 V, N 2 0 0 10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 19. Output Voltage Noise, 3.3 V Version, Figure 20. Output Voltage Noise, 5.5 V Version, V = 4.3 V, I = 30 mA, C = C = 0.1 (cid:2)F V = 6.5 V, I = 30 mA, C = C = 0.1 (cid:2)F IN OUT in out IN OUT in out www.onsemi.com 6
NCP4624 TYPICAL CHARACTERISTICS 70 60 60 50 50 40 B) 1 mA B) 1 mA d 40 d R ( R (30 R R S 30 30 mA S P P 30 mA 20 20 10 10 IOUT = 50 mA IOUT = 50 mA 0 0 10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 21. PSRR vs. Frequency, 1.2 V Version Figure 22. PSRR vs. Frequency, 3.3 V Version 60 50 1 mA 40 B) d R ( 30 R S 30 mA P 20 10 IOUT = 50 mA 0 10 100 1k 10k 100k 1M FREQUENCY (kHz) Figure 23. PSRR vs. Frequency, 5.5 V Version 4.0 3.5 3.0 2.5 (V)UT 11..68 (V)N O VI V 1.4 1.2 1.0 0.8 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 t (ms) Figure 24. Line Transients, 1.2 V Version, I = 1 mA OUT www.onsemi.com 7
NCP4624 TYPICAL CHARACTERISTICS 5.8 5.3 4.8 4.3 (V)UT 33..79 (V)N O VI V 3.5 3.3 3.1 2.9 2.7 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 t (ms) Figure 25. Line Transients, 3.3 V Version, I = 1 mA OUT 8.0 7.5 7.0 6.5 (V)UT 56..91 (V)N O VI V 5.7 5.5 5.3 5.1 4.9 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 t (ms) Figure 26. Line Transients, 5.5 V Version, I = 1 mA OUT 15 10 5 0 V) 1.8 A) (UT 1.6 (mT O U V 1.4 O I 1.2 1.0 0.8 0.6 0 40 80 120 160 200 240 280 320 360 400 t ((cid:2)s) Figure 27. Load Transients, 1.2 V Version, Load Step 1 mA to 10 mA, V = 2.5 V IN www.onsemi.com 8
NCP4624 TYPICAL CHARACTERISTICS 15 10 5 0 V) 3.9 A) (UT 3.7 (mT O U V 3.5 IO 3.3 3.1 2.9 2.7 0 40 80 120 160 200 240 280 320 360 400 t ((cid:2)s) Figure 28. Load Transients, 3.3 V Version, Load Step 1 mA to 10 mA, V = 4.3 V IN 15 10 5 0 V) 6.1 A) (UT 5.9 (mT O U V 5.7 IO 5.5 5.3 5.1 4.9 0 40 80 120 160 200 240 280 320 360 400 t ((cid:2)s) Figure 29. Load Transients, 5.5 V Version, Load Step 1 mA to 10 mA, V = 6.5 V IN 150 100 50 0 V) 2.4 A) (UT 2.0 (mT O U V 1.6 O I 1.2 0.8 0.4 0.0 0 40 80 120 160 200 240 280 320 360 400 t ((cid:2)s) Figure 30. Load Transients, 1.2 V Version, Load Step 50 mA to 100 mA, V = 2.5 V IN www.onsemi.com 9
NCP4624 TYPICAL CHARACTERISTICS 150 100 50 0 V) 4.5 A) (UT 4.1 (mT O U V 3.7 O I 3.3 2.9 2.5 2.1 0 40 80 120 160 200 240 280 320 360 400 t ((cid:2)s) Figure 31. Load Transients, 3.3 V Version, Load Step 50 mA to 100 mA, V = 4.3 V IN 150 100 50 0 V) 6.7 A) (UT 6.3 (mT O U V 5.9 O I 5.5 5.1 4.7 4.3 0 40 80 120 160 200 240 280 320 360 400 t ((cid:2)s) Figure 32. Load Transients, 5.5 V Version, Load Step 50 mA to 100 mA, V = 6.5 V IN 4.5 Chip Enable 3.0 1.5 0.0 V (V)OUT 01..92 IOUT = 1 mA V (V)CE 0.6 IOUT = 30 mA 0.3 IOUT = 150 mA 0.0 −0.3 0 40 80 120 160 200 240 280 320 360 400 t ((cid:2)s) Figure 33. Turn−on Behavior, 1.2 Version, V = 3 V IN www.onsemi.com 10
NCP4624 TYPICAL CHARACTERISTICS 6.6 Chip Enable 4.4 2.2 0.0 V) V) V (OUT 34..00 IOUT = 1 mA V (CE 2.0 IOUT = 30 mA 1.0 IOUT = 150 mA 0.0 1.0 0 40 80 120 160 200 240 280 320 360 400 t ((cid:2)s) Figure 34. Turn−on Behavior, 3.3 Version, V = 4.3 V IN 9.75 Chip Enable 6.50 3.25 0.00 V) V) V (OUT46..50 IOUT = 1 mA V (CE 3.0 IOUT = 30 mA 1.5 IOUT = 150 mA 0.0 −1.5 0 40 80 120 160 200 240 280 320 360 400 t ((cid:2)s) Figure 35. Turn−on Behavior, 5.5 Version, V = 6.5 V IN 4.5 3.0 1.5 Chip Enable 0.0 V) V) V (OUT 01..92 IOUT = 30 mA V (CE 0.6 IOUT = 150 mA 0.3 IOUT = 1 mA 0.0 −0.3 0 40 80 120 160 200 240 280 320 360 400 t ((cid:2)s) Figure 36. Turn−off Behavior, 1.2 Version, V = 3 V IN www.onsemi.com 11
NCP4624 TYPICAL CHARACTERISTICS 6.6 4.4 2.2 Chip Enable 0.0 V) V) V (OUT 34..00 IOUT = 30 mA V (CE 2.0 IOUT = 150 mA 1.0 IOUT = 1 mA 0.0 −1.0 0 40 80 120 160 200 240 280 320 360 400 t ((cid:2)s) Figure 37. Turn−off Behavior, 3.3 Version, V = 4.3 V IN 9.75 6.50 3.25 Chip Enable 0.00 V) V) V (OUT 46..50 IOUT = 30 mA V (CE 3.0 IOUT = 150 mA 1.5 IOUT = 1 mA 0.0 −1.5 0 40 80 120 160 200 240 280 320 360 400 t ((cid:2)s) Figure 38. Turn−off Behavior, 5.5 Version, V = 6.5 V IN www.onsemi.com 12
NCP4624 APPLICATION INFORMATION A typical application circuit for NCP4624 series is shown down current source which assure off state of LDO in case in the Figure 39. the CE pin will stay floating. If the enable function is not needed connect CE pin to VIN. NCP4624x The D version of the NCP4624 includes a transistor VIN VOUT VIN VOUT between VOUT and GND that is used for faster discharging C1 C2 of the output capacitor. This function is activated when the CE IC goes into disable mode. 0.1(cid:2)F GND 0.1(cid:2)F Thermal Consideration As a power across the IC increase, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent Figure 39. Typical Application Schematic upon board design and layout. Mounting pad configuration on the PCB, the board material, and also the ambient temperature affect the rate of temperature increase for the Input Decoupling Capacitor (C1) part. When the device has good thermal conductivity A 100 nF ceramic input decoupling capacitor should be through the PCB the junction temperature will be relatively connected as close as possible to the input and ground pin of low in high power dissipation applications. the NCP4624. Higher values and lower ESR improves line transient response. Reverse Current Protection Circuit Internal Reverse Current Circuitry stops the reverse Output Decoupling Capacitor (C2) current from VOUT pin to GND pin and VIN pin when A 100 nF ceramic output decoupling capacitor is V goes higher than V voltage or V voltage. V OUT IN SET SET sufficient to achieve stable operation of the IC. If tantalum means voltage given by voltage version. The parasitic diode capacitor is used, and its ESR is high, the loop oscillation of PMOS pass device is internally switched to reverse may result. The capacitor should be connected as close as direction before V becomes lower than V . The IN OUT possible to the output and ground pin. Larger values and operation coverage of the Reverse Current Protection lower ESR improves dynamic parameters. Circuit is V > 1.5 V. In order to avoid unstable behavior OUT a hysteresis is created by different threshold of detecting Enable Operation The enable pin CE may be used for turning the regulator voltage VREV_DET and releasing voltage VREV_REL. See Figures 40 and 41 for details of configuration. on and off. The IC is switched on when a high level voltage is applied to the CE pin. The enable pin has an internal pull Vin Vout Vin Vout Vref Vref Current Current CE Limit CE Limit Reverse Detector Reverse Detector GND GND Figure 40. Normal Operating Mode Figure 41. Reverse Current Protection Mode www.onsemi.com 13
NCP4624 ESR versus Output Current • The conditions when the device performs stable When using the NCP4624 devices, consider the following operation are marked as the hatched area in the charts. points: • The relation between Output Current I and ESR of OUT the output capacitor are shown below in Figures 42, 43 and 44. NCP4624xxx12xx, VIN = 2.5 V, NCP4624xxx33xx, VIN = 4.3 V, CIN = COUT = 0.1 (cid:2)F, TA = 25°C CIN = COUT = 0.1 (cid:2)F, TA = 25°C Figure 42. ESR vs. Load Current Figure 43. ESR vs. Load Current NCP4624xxx55xx, VIN = 6.5 V, CIN = COUT = 0.1 (cid:2)F, TA = 25°C Figure 44. ESR vs. Load Current www.onsemi.com 14
NCP4624 ORDERING INFORMATION Nominal Output Device Marking Voltage Feature Package Shipping NCP4624DMU12TCG 5A 1.2 V Enable High, UDFN4 10000 / Tape & Reel (Pb−Free) Auto discharge NCP4624DMU30TCG 5X 3.0 V Enable High, UDFN4 10000 / Tape & Reel (Pb−Free) Auto discharge NCP4624DMU33TCG 6A 3.3 V Enable High, UDFN4 10000 / Tape & Reel (Pb−Free) Auto discharge NCP4624DMU50TCG 6T 5.0 V Enable High, UDFN4 10000 / Tape & Reel (Pb−Free) Auto discharge NCP4624DSN12T1G F12 1.2 V Enable High, SOT−23−5 3000 / Tape & Reel (Pb−Free) Auto discharge NCP4624DSN18T1G F18 1.8 V Enable High, SOT−23−5 3000 / Tape & Reel (Pb−Free) Auto discharge NCP4624DSN33T1G F33 3.3 V Enable High, SOT−23−5 3000 / Tape & Reel (Pb−Free) Auto discharge NCP4624DSN50T1G F50 5.0 V Enable High, SOT−23−5 3000 / Tape & Reel (Pb−Free) Auto discharge NCP4624DSQ12T1G AT12 1.2. V Enable High, SC−88A 3000 / Tape & Reel (Pb−Free) Auto discharge NCP4624DSQ33T1G AT33 3.3 V Enable High, SC−88A 3000 / Tape & Reel (Pb−Free) Auto discharge †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 15
NCP4624 PACKAGE DIMENSIONS SOT−23 5−LEAD CASE 1212 ISSUE A NOTES: A 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. A D B A2 2. CONTROLLING DIMENSIONS: MILLIMETERS. 0.05 S A1 3. DATUM C IS THE SEATING PLANE. MILLIMETERS 5 4 DIM MIN MAX E L A --- 1.45 1 2 3 A1 0.00 0.10 E1 A2 1.00 1.30 L1 5Xb C b 0.30 0.50 c 0.10 0.25 e 0.10 M C B S A S C D 2.70 3.10 E 2.50 3.10 E1 1.50 1.80 e 0.95 BSC RECOMMENDED L 0.20 --- SOLDERING FOOTPRINT* L1 0.45 0.75 3.30 5X 0.85 5X 0.56 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 16
NCP4624 PACKAGE DIMENSIONS UDFN4 1.0x1.0, 0.65P CASE 517BR ISSUE O NOTES: D A 4XL3 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. B 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND c 0.18 REFEPRINE ONCNEE L2 typ 4. 0C.O20P LmAmN AFRRIOTMY ATEPRPLMIEINSA TLO. THE EXPOSED ÉÉ E PAD AS WELL AS THE TERMINALS. DETAIL A 2X 0.05 C ÉÉ MILLIMETERS DIM MIN MAX 2X 0.05 C A −−− 0.60 3X0.43 4X0.23 A1 0.00 0.05 TOP VIEW A3 0.10 REF b 0.20 0.30 0.05 C (A3) D 1.00 BSC D2 0.43 0.53 A E 1.00 BSC e 0.65 BSC 3X0.10 L 0.20 0.30 0.05 C L2 0.27 0.37 NOTE 4 SIDE VIEW A1 C SPELAATNIENG DETAIL B L3 0.02 0.12 RECOMMENDED e MOUNTING FOOTPRINT* e/2 DETAIL A 1 2 3XL 0.65 PITCH DETAIL B 2X 0.52 D2 D2 PACKAGE 45(cid:2) 4 3 OUTLINE 1.30 4Xb 0.05 M C A B BOTTOM VIEW NOTE 3 0.53 4X 0.30 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 17
NCP4624 PACKAGE DIMENSIONS SC−88A (SC−70−5/SOT−353) CASE 419A−02 ISSUE L A NOTES: 1. DIMENSIONING AND TOLERANCING G PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A−01 OBSOLETE. NEW STANDARD 419A−02. 4. DIMENSIONS A AND B DO NOT INCLUDE 5 4 MOLD FLASH, PROTRUSIONS, OR GATE BURRS. S −B− INCHES MILLIMETERS 1 2 3 DIM MIN MAX MIN MAX A 0.071 0.087 1.80 2.20 B 0.045 0.053 1.15 1.35 C 0.031 0.043 0.80 1.10 D 0.004 0.012 0.10 0.30 D 5 PL 0.2 (0.008) M B M G 0.026 BSC 0.65 BSC H --- 0.004 --- 0.10 J 0.004 0.010 0.10 0.25 N K 0.004 0.012 0.10 0.30 N 0.008 REF 0.20 REF S 0.079 0.087 2.00 2.20 J C K H SOLDER FOOTPRINT 0.50 0.0197 0.65 0.025 0.65 0.025 0.40 0.0157 1.9 (cid:2) (cid:3) 0.0748 mm SCALE 20:1 inches ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative ◊ www.onsemi.com NCP4624/D 18