NCP4304A, NCP4304B Secondary Side Synchronous Rectification Driver for High Efficiency SMPS Topologies www.onsemi.com The NCP4304A/B is a full featured controller and driver tailored to control synchronous rectification circuitry in switch mode power supplies. Due to its versatility, it can be used in various topologies such 8 as flyback, forward and Half Bridge Resonant LLC. 1 1 The combination of externally adjustable minimum on and off times SOIC−8 DFN8 helps to fight the ringing induced by the PCB layout and other D SUFFIX MN SUFFIX parasitic elements. Therefore, a reliable and noise less operation of the CASE 751 CASE 488AF SR system is insured. The extremely low turn off delay time, high sink current capability MARKING DIAGRAMS of the driver and automatic package parasitic inductance 8 compensation system allow to maximize synchronous rectification NCP 4304x MOSFET conduction time that enables further increase of SMPS ALYW (cid:2) 4304x efficiency. (cid:2) ALYW(cid:2) (cid:2) Finally, a wide operating V range combined with two versions of 1 CC driver voltage clamp eases implementation of the SR system in 24 V SOIC−8 DFN8 output applications. 4304x = Specific Device Code x = A or B Features A = Assembly Location • Self-Contained Control of Synchronous Rectifier in CCM, DCM, L = Wafer Lot Y = Year and QR Flyback Applications W = Work Week • Precise True Secondary Zero Current Detection with Adjustable (cid:2) = Pb−Free Package Threshold (*Note: Microdot may be in either location) • Automatic Parasitic Inductance Compensation Input • PINOUT INFORMATION Typically 40ns Turn off Delay from Current Sense Input to Driver • Zero Current Detection Pin Capability up to 200V VCC 1 8 DRV • Optional Ultrafast Trigger Interface for Further Improved MIN_TOFF 2 7 GND MIN_TON 3 6 COMP Performance in Applications that Work in Deep CCM TRIG/DIS 4 5 CS • Disable Input to Enter Standby or Low Consumption Mode • Adjustable Minimum On Time Independent of V Level (NOTE: For DFN the exposed pad must be either CC • unconnected or preferably connected to ground. Adjustable Minimum Off Time Independent of V Level CC The GND pin must be always connected to ground.) • 5A/2.5A Peak Current Sink/Source Drive Capability • Operating Voltage Range up to 30V ORDERING INFORMATION • Gate Drive Clamp of Either 12V (NCP4304A) or 6V (NCP4304B) Device Package Shipping† • Low Startup and Standby Current Consumption NCP4304ADR2G SOIC−8 2,500 / • Maximum Frequency of Operation up to 500kHz (Pb−Free) Tape & Reel • SOIC−8 Package NCP4304BDR2G SOIC−8 2,500 / • (Pb−Free) Tape & Reel These are Pb−Free Devices NCP4304AMNTWG DFN8 4,000 / (Pb−Free) Tape & Reel Typical Applications • Notebook Adapters NCP4304BMNTWG DFN8 4,000 / • (Pb−Free) Tape & Reel High Power Density AC/DC Power Supplies • †For information on tape and reel specifications, Gaming Consoles including part orientation and tape sizes, please • All SMPS with High Efficiency Requirements refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: March, 2016 − Rev. 6 NCP4304/D

NCP4304A, NCP4304B NCP4304 C2 RMIN_TOFF VCC DRV MIN_TOFF GND MIN_TON COMP RMIN_TON TRIG/DIS CS +Vbulk +Vout TR1 M1 M3 N2 + C4 LLC STAGE RTN CONTROL M2 N1 N3 M4 C1 NCP4304 C3 RMIN_TOFF VCC DRV MIN_TOFF GND MIN_TON COMP RMIN_TON TRIG/DIS CS D1 OK1 Figure 1. Typical Application Example – LLC Converter Vbulk + TR1 C1 R1 C2 +Vout D3 VCC M2 + C5 + D4 FLYBACK C3 GND CONTROL CIRCUITRY C4 DRV M1 RMIN_TOFF R3 VCC DRV FB CS MIN_TOFF GND MIN_TON COMP R2 R4 TRIG/DIS CS R5 RMIN_TON D5 OK1 R6 Figure 2. Typical Application Example − DCM or QR Flyback Converter www.onsemi.com 2

NCP4304A, NCP4304B PIN FUNCTION DESCRIPTION Pin No. Pin Name Function Pin Description 1 VCC Supplies the driver Supply terminal of the controller. Accepts up to 30 V continuously. 2 MIN_TOFF Minimum off time adjust Adjust the minimum off time period by connecting resistor to ground. 3 MIN_TON Minimum on time adjust Adjust the minimum on time period by connecting resistor to ground. 4 TRIG/DIS Forced reset input This ultrafast input turns off the SR MOSFET in CCM applications. Activates sleep mode if pulled up for more than 100 (cid:2)s. 5 CS Current sense of the SR This pin detects if the current flows through the SR MOSFET and/or its body MOSFET diode. Basic turn off detection threshold is 0 mV. A resistor in series with this pin can modify the turn off threshold if needed. 6 COMP Compensation inductance Use as a Kelvin connection to auxiliary compensation inductance. If SR connection MOSFET package parasitic inductance compensation is not used (like for SMT MOSFETs), connect this pin directly to GND pin. 7 GND IC ground Ground connection for the SR MOSFET driver and VCC decoupling capacitor. Ground connection for minimum ton, toff adjust resistors and trigger input. GND pin should be wired directly to the SR MOSFET source terminal/soldering point using Kelvin connection. 8 DRV Gate driver output Driver output for the SR MOSFET. VDD MINIMUM OFF toff_min Generator Start MIN_TOFF TIME GENERATOR T E S ble Blanking of CS VDD Ena toff_mdiunr, intogn_min 100 (cid:2)A DETECTION CS ZCD SET & & S Q DRV Out CS & DRIVER DRV COMPENSATION ZCD Reset & R Q OR VDD T E COMP 1k5 Enable RES V Set EnableV Reset VCC DRDR MANAGEMENT VCC UVLO MINIMUM ON MIN_TON TIME GENERATOR ton_min Generator Start VDD T10IM0 (cid:2)EsR Sleep Mode INV One shot GND S Q OR ZCD Reset R Q TRIG/DIS & INV 10 (cid:2)A VTH= 2 V Trigger Blanking One shot 120 ns INV 120 ns during DRV rising edge Figure 3. Internal Circuit Architecture www.onsemi.com 3

NCP4304A, NCP4304B MAXIMUM RATINGS Symbol Rating Value Unit VCC IC Supply Voltage −0.3 to 30 V VDRV Driver Output Voltage −0.3 to 17 V VCS Current Sense Input dc Voltage −4 to 200 V VCsdyn Current Sense Input Dynamic Voltage (tpw = 200 ns) −10 to 200 V VTRIG/DIS Trigger Input Voltage −0.3 to 10 V VMIN_TON, VMIN_TOFF MIN_TON and MIN_TOFF Input Voltage −0.3 to 10 V IMIN_TON, IMIN_TOFF MIN_TON and MIN_TOFF Current −10 to +10 mA VCOMP Static Voltage Difference between COMP and GND Pins (Internally Clamped) −3 to 10 V VCOMP_dyn Dynamic Voltage Difference between COMP and GND Pins (tpw = 200 ns) −10 to 10 V ICOMP Current into COMP Pin −5 to 5 mA R(cid:3)JA Thermal Resistance Junction-to-Air, SOIC − A/B Versions 180 °C/W R(cid:3)JA Thermal Resistance Junction-to-Air, DFN − A/B Versions, 50 mm2 − 1.0 oz. Copper 180 °C/W Spreader R(cid:3)JA Thermal Resistance Junction-to-Air, DFN − A/B Versions, 600 mm2 − 1.0 oz. Copper 80 °C/W Spreader TJmax Maximum Junction Temperature 150 °C TSmax Storage Temperature Range −60 to +150 °C TLmax Lead Temperature (Soldering, 10 s) 300 °C ESD Capability, Human Body Model except Pin VCS – Pin 5, HBM ESD Capability on 2 kV Pin 5 is 650 V per JEDEC Standard JESD22−A114E ESD Capability, Machine Model per JEDEC Standard JESD22−A115−A 200 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device meets latchup tests defined by JEDEC Standard JESD78. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 12 V, CDRV = 0 nF, RMIN_TON = RMIN_TOFF = 10 k(cid:4), VTRIG/DIS = 0 V, fCS = 100 kHz, DCCS = 50%, VCS_high = 4 V, VCS_low = −1 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit SUPPLY SECTION VCC_on Turn-on threshold level (VCC going up) 1 9.3 9.9 10.5 V VCC_off Minimum operating voltage after turn-on (VCC going down) 1 8.3 8.9 9.5 V VCC_hyste VCC hysteresis 1 0.6 1.0 1.4 V ICC1_A Internal IC consumption (no output load on pin 8, fSW = 500 kHz, 1 − 4.5 6.6 mA ICC1_B ton_min = 500 ns, toff_min = 620 ns) − 4.0 6.2 ICC2_A Internal IC consumption (CDRV = 1 nF on pin 8, fSW = 400 kHz, 1 − 9.0 12 mA ICC2_B ton_min = 500 ns, toff_min = 620 ns) − 6.5 9 ICC3_A Internal IC consumption (CDRV = 10 nF on pin 8, fSW = 400 kHz, 1 − 57.0 80 mA ICC3_B ton_min = 500 ns, toff_min = 620 ns) − 35.0 65 ICC_StartUp Startup current consumption (VCC = VCC_on − 0.1 V, no switching at 1 − 35 75 (cid:2)A CS pin) ICC_Disable_1 Current consumption during disable mode (No switching at CS pin, 1 − 45 90 (cid:2)A VTRIG/DIS = 5 V) ICC_Disable_2 Current consumption during disable mode (CS pin is switching, 1 − 200 330 (cid:2)A fSW = 500 kHz, VCS_high = 4 V, VCS_low =−1 V, VTRIG/DIS = 5 V) DRIVE OUTPUT tr_A Output voltage rise-time for A version (CDRV = 10 nF) 8 − 120 − ns tr_B Output voltage rise-time for B version (CDRV = 10 nF) 8 − 80 − ns tf_A Output voltage fall-time for A version (CDRV = 10 nF) 8 − 50 − ns tf_B Output voltage fall-time for B version (CDRV = 10 nF) 8 − 35 − ns Roh Driver source resistance (Note 1) 8 − 1.8 7 (cid:4) Rol Driver sink resistance 8 − 1 2 (cid:4) www.onsemi.com 4

NCP4304A, NCP4304B ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 12 V, CDRV = 0 nF, RMIN_TON = RMIN_TOFF = 10 k(cid:4), VTRIG/DIS = 0 V, fCS = 100 kHz, DCCS = 50%, VCS_high = 4 V, VCS_low = −1 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit DRIVE OUTPUT IDRV_pk(source) Output source peak current 8 − 2.5 − A IDRV_pk(sink) Output sink peak current 8 − 5 − A VDRV(min_A) Minimum drive output voltage for A version (VCC = VCC_off + 200 mV) 8 8.3 − − V VDRV(min_B) Minimum drive output voltage for B version (VCC = VCC_off + 200 mV) 8 4.5 − − V VDRV(CLMP_A) Driver clamp voltage for A version (12 < VCC < 28, CDRV = 1 nF) 8 10 12 14.3 V VDRV(CLMP_B) Driver clamp voltage for B version (12 < VCC < 28, CDRV = 1 nF) 8 5 6 8 V CS INPUT tpd_on The total propagation delay from CS input to DRV output turn on 5, 8 − 60 90 ns (VCS goes down from 4 V to −1 V, tf_CS = 5 ns, COMP pin connected to GND) tpd_off The total propagation delay from CS input to DRV output turn off 5, 8 − 40 55 ns (VCS goes up from −1 V to 4 V, tr_CS = 5 ns, COMP pin connected to GND), (Note 1) Ishift_CS Current sense input current source (VCS = 0 V) 5 95 100 105 (cid:2)A Vth_cs_on Current sense pin turn-on input threshold voltage 5, 8 −120 −85 −50 mV Vth_cs_off Current sense pin turn-off threshold voltage, COMP pin connected to 5, 8 −1 − 0 mV GND (Note 1) Gcomp Compensation inverter gain 5,6,8 −1 − ICS_Leakage Current Sense input leakage current, VCS = 200 V 5 − − 1 (cid:2)A TRIGGER/DISABLE INPUT tTRIG/DIS_pw_min Minimum trigger pulse width (Note 1) 4 30 − − ns VTRIG/DIS Trigger input threshold voltage (VTRIG/DIS goes up) 4 1.5 − 2.5 V tp_TRIG/DIS Propagation delay from trigger input to the DRV output 4 − 13 30 ns (VTRIG/DIS goes up from 0 to 5 V, tr_TRIG/DIS = 5 ns) tTRIG/DIS_light_load Light load turn off filter duration 4 70 100 130 (cid:2)s tTRIG/DIS_light_ IC operation recovery time when leaving light load disable mode 4 − − 10 (cid:2)s load_rec. (VTRIG/DIS goes down from 5 to 0 V, tf_TRIG/DIS = 5 ns) tTRIG/DIS_blank Blanking time of trigger during DRV rising edge (VCS < Vth_cs_on, 4 − 120 − ns single pulse on trigger tTRIG/DIS_pw = 50 ns) ITRIG/DIS Trigger input pull down current (VTRIG/DIS = 5 V) 4 − 10 − (cid:2)A ton_min AND toff_min ADJUST ton_min Minimum ton period (RMIN_TON = 0 (cid:4)) 3 − 130 − ns toff_min Minimum toff period (RMIN_TOFF = 0 (cid:4)) 2 560 600 690 ns ton_min Minimum ton period (RMIN_TON = 10 k(cid:4)) 3 0.9 1.0 1.1 (cid:2)s toff_min Minimum toff period (RMIN_TOFF = 10 k(cid:4)) 2 0.9 1.0 1.1 (cid:2)s ton_min Minimum ton period (RMIN_TON = 50 k(cid:4)) 3 − 4.8 − (cid:2)s toff_min Minimum toff period (RMIN_TOFF = 50 k(cid:4)) 2 − 4.8 − (cid:2)s ton_min Minimum ton period (RMIN_TON = 100 k(cid:4)) (Note 2) 3 8.64 9.6 10.56 (cid:2)s toff_min Minimum toff period (RMIN_TOFF = 100 k(cid:4)) (Note 2) 2 8.55 9.5 10.45 (cid:2)s Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. Guaranteed by design. 2. Guaranteed by design and verified by characterization, see Figure4. ton_min on RMIN_TON dependency. www.onsemi.com 5

NCP4304A, NCP4304B TYPICAL CHARACTERISTICS 10000 8000 6000 s) n (n mi _ n o t 4000 2000 0 0 10000 20000 30000 40000 50000 60000 70000 80000 90000 100000 RMIN_TON ((cid:2)) Figure 4. t on R Dependency on_min MIN_TON www.onsemi.com 6

NCP4304A, NCP4304B 9.890 8.880 8.870 9.880 8.860 9.870 8.850 (V)on9.860 (V)off8.840 C_9.850 C_8.830 C C V V 8.820 9.840 8.810 9.830 8.800 9.820 8.790 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 5. VCC Startup Voltage Figure 6. VCC Turn-off Voltage 1.040 44 1.035 42 1.030 40 V)1.025 (cid:2)A) (hyste1.020 (artup 38 VCC_1.015 CC_St 36 I 34 1.010 1.005 32 1.000 30 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. VCC Hysteresis Figure 8. Startup Current 12.0 12.065 11.9 12.060 11.8 12.055 11.7 V) V) (A 11.6 (A12.050 _ _ H) 11.5 H)12.045 V( V( R R D 11.4 D V V12.040 11.3 12.035 11.2 12.030 11.1 11.0 12.025 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 9. Driver High Level – A Version, Figure 10. Driver High Level – A Version, V = 12 V and C = 1 nF V = 12 V and C = 10 nF CC DRV CC DRV www.onsemi.com 7

NCP4304A, NCP4304B 7.0 7.70 6.9 7.65 6.8 7.60 6.7 7.55 V) 6.6 V) (B (B 7.50 _ 6.5 _ H) H) 7.45 V( 6.4 V( R R D D 7.40 V 6.3 V 7.35 6.2 6.1 7.30 6.0 7.25 5.9 7.20 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. Driver High Level – B Version, Figure 12. Driver High Level – B Version, V = 12 V and C = 1 nF V = 12 V and C = 10 nF CC DRV CC DRV 9.10 6.40 9.05 6.30 9.00 V) V) 6.20 (A) 8.95 (B) _ _ n n 6.10 mi mi V( 8.90 V( R R VD VD 6.00 8.85 5.90 8.80 8.75 5.80 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. Minimal Driver High Level − A Version, Figure 14. Minimal Driver High Level − B Version, V + 0.2 V and C = 0 nF V + 0.2 V and C = 0 nF CC_off DRV CC_off DRV 14.0 15.0 13.8 13.6 14.5 (V)A) 1133..24 (V)_A)14.0 _ P P 13.0 M M L L C V(C 12.8 RV(13.5 R D D 12.6 V V 12.4 13.0 12.2 12.0 12.5 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Driver Clamp Level − A Version, Figure 16. Driver Clamp Level − A Version, V = 28 V and C = 1 nF V = 28 V and C = 10 nF CC DRV CC DRV www.onsemi.com 8

NCP4304A, NCP4304B 7.1 8.4 7.0 8.2 6.9 V) 6.8 V) 8.0 (B) 6.7 (B) 7.8 _ _ P P M 6.6 M L L C C 7.6 V( 6.5 V( R R VD 6.4 VD 7.4 6.3 7.2 6.2 6.1 7.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. Driver Clamp Level − B Version, Figure 18. Driver Clamp Level − B Version, V = 28 V and C = 1 nF V = 28 V and C = 10 nF CC DRV CC DRV 60.0 45.0 40.0 50.0 35.0 40.0 30.0 ns) ns) 25.0 (_on30.0 (_off 20.0 d d p p t 20.0 t 15.0 10.0 10.0 5.0 0.0 0.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 19. CS to DRV Turn-on Propagation Figure 20. CS to DRV Turn-off Propagation Delay Delay 101.0 −40.0 −50.0 100.5 −60.0 100.0 (cid:2)A) mV)−70.0 (S99.5 (n C o hift_ _cs_−80.0 Is99.0 Vth−90.0 98.5 −100.0 98.0 −110.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 21. CS Pin Shift Current Figure 22. CS Turn-on Threshold www.onsemi.com 9

NCP4304A, NCP4304B 2.12 16.0 2.10 14.0 2.08 12.0 V) 2.06 ns) 10.0 (S (S DI 2.04 DI 8.0 G/ G/ RI RI T 2.02 T 6.0 V _ p t 2.00 4.0 1.98 2.0 1.96 0.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 23. Trigger Input Threshold Voltage Figure 24. Propagation Delay from Trigger Input to DRV Turn-off 101.5 9.210 9.205 101.0 s) (cid:2)_ (s)light_load100.5 (cid:2) (ght_load_rec999...112990050 DIS100.0 S_li G/ DI RI G/9.185 tT 99.5 TRI t 9.180 99.0 9.175 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 25. Light Load Transition Timer Figure 26. Light Load to Normal Operation Duration Recovery Time 18.0 165.0 16.0 164.0 14.0 163.0 12.0 162.0 (cid:2) (A)G/DIS 180..00 (ns)_min116601..00 RI on IT 6.0 t159.0 4.0 158.0 2.0 157.0 0.0 156.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 27. Trigger Input Pulldown Current Figure 28. Minimum on Time @ R = 0 (cid:2) MIN_TON www.onsemi.com 10

NCP4304A, NCP4304B 999.0 994.5 998.5 994.0 998.0 997.5 993.5 ns) 997.0 ns) 993.0 (n996.5 (n mi mi on_996.0 off_ 992.5 t t 995.5 992.0 995.0 991.5 994.5 994.0 991.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 29. Minimum On Time @ R = 10 k(cid:2) Figure 30. Minimum Off Time @ R = 10 k(cid:2) MIN_TON MIN_TOFF 4880 4940 4860 4920 4840 4900 4820 4880 s) 4800 s) n n 4860 (n 4780 (n mi mi4840 off_ 4760 on_ t t 4820 4740 4800 4720 4700 4780 4680 4760 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 31. Minimum Off Time @ R = 50 k(cid:2) Figure 32. Minimum On Time @ R = 50 k(cid:2) MIN_TOFF MIN_TON 625.0 5.00 620.0 4.95 615.0 4.90 s) 610.0 A) 4.85 n m (min605.0 (_A 4.80 off_600.0 CC1 4.75 t I 595.0 4.70 590.0 4.65 585.0 4.60 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 33. Minimum Off Time @ R = 0 (cid:2) Figure 34. Internal IC Consumption MIN_TOFF (A Version, No Load on Pin 8, f = 500 kHz, SW t = 500 ns, t = 620 ns) on_min off_min www.onsemi.com 11

NCP4304A, NCP4304B 4.200 9.35 4.180 9.30 4.160 4.140 9.25 A) A) m 4.120 m (B (A9.20 1_ 4.100 2_ C C C C I 4.080 I 9.15 4.060 9.10 4.040 4.020 9.05 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 35. Internal IC Consumption (B version, Figure 36. Internal IC Consumption (A Version, C = 0 nF, f = 500 kHz, C = 1 nF, f = 400 kHz, DRV SW DRV SW t = 500 ns, t = 620 ns) t = 500 ns, t = 620 ns) on_min off_min on_min off_min 7.60 52.8 52.7 7.40 52.6 7.20 52.5 A) A) m 7.00 m 52.4 (B (A 2_ 6.80 3_52.3 C C C C I I 52.2 6.60 52.1 6.40 52.0 6.20 51.9 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 37. Internal IC Consumption Figure 38. Internal IC Consumption (A Version, (B Version, C = 1 nF, f = 400 kHz, C = 10 nF, f = 400 kHz, DRV SW DRV SW t = 500 ns, t = 620 ns) t = 500 ns, t = 620 ns) on_min off_min on_min off_min 35.0 34.5 A) 34.0 m (B _ 3 C 33.5 C I 33.0 32.5 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 39. Internal IC Consumption (B Version, C = 10 nF, f = 400 kHz, DRV SW t = 500 ns, t = 620 ns) on_min off_min www.onsemi.com 12

NCP4304A, NCP4304B APPLICATION INFORMATION General Description To overcome issues after turn on and off events, the The NCP4304A/B is designed to operate either as NCP4304A/B provides adjustable minimum on time and off astandalone IC or as a companion IC to a primary side time blanking periods. Blanking times can be adjusted controller to help achieve efficient synchronous independently of IC V using resistors connected to GND. CC rectification in switch mode power supplies. This controller If needed, blanking periods can be modulated using features a high current gate driver along with high-speed additional components. logic circuitry to provide appropriately timed drive signals An ultrafast trigger input helps to implement synchronous to a synchronous rectification MOSFET. With its novel rectification systems in CCM applications (like CCM architecture, the NCP4304A/B has enough versatility to flyback or forward). The time delay from trigger input to keep the synchronous rectification efficient under any driver turn off event is 10 ns (typicaly). Additionally, the operating mode. trigger input can be used to disable the IC and activate a low The NCP4304A/B works from an available bias supply consumption standby mode. This feature can be used to with voltage range from 10.4 V to 28 V (typical). The wide decrease standby consumption of an SMPS. VCC range allows direct connection to the SMPS output Finally, the NCP4304A/B features a special input that can voltage of most adapters such as notebook and LCD TV be used to automatically compensate for SR MOSFET adapters. As a result, the NCP4304A/B simplifies circuit parasitic inductance effect. This technique achieves the operation compared to other devices that require specific maximum available on-time and thus optimizes efficiency bias power supplies (e.g. 5 V). The high voltage capability when a MOSFET in standard package (like TO−220 or of the VCC is also a unique feature designed to allow TO247) is used. If a SR MOSFET in SMT package with operation for a broader range of applications. negligible inductance is used, the compensation input is Precise turn off threshold of the current sense comparator connected to GND pin. together with accurate offset current source allows the user to adjust for any required turn off current threshold of the SR Zero Current Detection and Parasitic Inductance MOSFET switch using a single resistor. Compared to other Compensation Figure 40 shows the internal connection of the ZCD SR controllers that provide turn off thresholds in the range circuitry on the current sense input. The synchronous of −10 mV to −5 mV, the NCP4304A/B offers a turn off rectification MOSFET is depicted with it’s parasitic threshold of 0 mV that in combination with a low R SR DS(on) inductances to demonstrate operation of the compensation MOSFET significantly reduces the turn off current system. threshold and improves efficiency. +Vout SR MOSFET + LDRAIN LSOURCE LCOMP GND M1 DRV Vdd RSHIFT_CS + I1s0h0ift_(cid:2)CAS VREF = Vth_cs_on − ZCD SET Ishift_CS CS + − To Internal Logic + + − ZCD RESET Vth_cs_off − −1 COMP GND Figure 40. ZCD Sensing Circuitry Functionality www.onsemi.com 13

NCP4304A, NCP4304B When the voltage on the secondary winding of the SMPS The SR MOSFET is turned-off as soon as the voltage on reverses, the body diode of M1 starts to conduct current and the CS pin is higher than V . For the same ringing th_cs_off the voltage of M1’s drain drops approximately to −1 V. The reason, a minimum off time timer is asserted once the CS pin sources current of 100 (cid:2)A that creates a voltage drop turn‐off is detected. The minimum off time can be externally on the RSHIFT_CS resistor. Once the voltage on the CS pin adjusted using R resistor. MOSFET M1 conducts MIN_TOFF is lower than V threshold, M1 is turned on. Because when the secondary current decreases, therefore the turn-off th_cs_on of parasitic impedances, significant ringing can occur in the time depends on its R . The 0 mV threshold provides DS(on) application. To overcome sudden turn-off due to mentioned an optimum switching period usage while keeping enough ringing, the minimum conduction time of the SR MOSFET time margin for the gate turn off. The RSHIFT_CS resistor is activated. Minimum conduction time can be adjusted provides the designer with the possibility to modify using R resistor. (increase) the actual turn-off current threshold. MIN_TON VDS ISEC Vth_cs_off − (RSHIFT_CS ⋅ Ishift_CS) Vth_cs_on − (RSHIFT_CS ⋅ Ishift_CS) VDRV Blank ton_min toff_min The ton_min and toff_min are adjustable by RMIN_TON and RMIN_TOFF resistors. Figure 41. ZCD Comparators Thresholds and Blanking Periods Timing If no RSHIFT_CS resistor is used, the turn-on and turn-off If using a SR MOSFET in TO−220 package (or other thresholds are fully given by the CS input specification package which features leads), the parasitic inductance of (please refer to parametric table). Once non-zero the package leads causes a turn-off current threshold RSHIFT_CS resistor is used, both thresholds move down increase. This is because current that flows through the SR (i.e. higher MOSFET turn off current) as the CS pin offset MOSFET has quite high di(t)/dt that induces error voltage current causes a voltage drop that is equal to: on the SR MOSFET leads inductance. This error voltage, V (cid:2)RSHIFT_CS(cid:3)I (eq. 1) that is proportional to the secondary current derivative, RSHIFT_CS shift_CS shifts the CS input voltage to zero when significant current Final turn-on and turn-off thresholds can be then calculated still flows through the channel. Zero current threshold is thus as: detected when current still flows through the SR MOSFET (cid:5) (cid:6) channel – please refer to Figure 42 for better understanding. VCS_turn_on(cid:2)Vth_cs_on(cid:4) RSHIFT_CS(cid:3)Ishift_CS (eq. 2) As a result, the SR MOSFET is turned-off prematurely and VCS_turn_off(cid:2)Vth_cs_off(cid:4)(cid:5)RSHIFT_CS(cid:3)Ishift_CS(cid:6) (eq. 3) the efficiency of the SMPS is not optimized. Note that RSHIFT_CS impact on turn-on threshold is less critical compare to turn-off threshold. www.onsemi.com 14

NCP4304A, NCP4304B Figure 42. Waveforms from SR System Using MOSFET in TO−220 Package Without Parasitic Inductance Compensation – SR MOSFET Channel Conduction Time is Reduced Note that the efficiency impact of the error caused by The NCP4304A/B offers a way to compensate for parasitic inductance increases with lower R MOSFET parasitic inductances effect − refer to Figure 43. DS(on) MOSFETs and/or higher operating frequency. VDS ISEC VLDRAIN VRDS(on) VLSOURCE VLCOMP D S LDRAIN RDS(on) LSOURCE LCOMP CS GND COMP Figure 43. Package Parasitic Inductances Compensation Principle Dedicated input (COMP) offers the possibility to use an current sense comparator thus “sees” between its terminals external compensation inductance (wire strap or PCB). If a voltage that would be seen on the SR MOSFET channel the value of this compensation inductance is LCOMP = resistance in case the lead inductances wouldn’t exist. The LDRAIN+LSOURCE, the compensation voltage created current sense comparator of the NCP4304A/B is thus able to on this inductance is exactly the same as the sum of error detect the secondary current zero crossing very precisely. voltages created on drain and source parasitic inductances More over, the secondary current turn-off threshold is then i.e. V +V . The internal analog inverter di(t)/t independent thus the NCP4304A/B allows to increase LDRAIN LSOURCE (Figure 40) inverts compensation voltage V and operating frequency of the SR system. One should note that LCOMP offsets the current sense comparator turn-off threshold. The the parasitic resistance of compensation inductance should www.onsemi.com 15

NCP4304A, NCP4304B be as low as possible compared to the SR MOSFET channel compensated SR system can be seen in Figure 44. One can and leads resistance otherwise compensation is not efficient. see the conduction time has been significantly increased and Typical value of compensation inductance for a TO−220 turn-off current reduced. package is 7 nH. Waveforms from the application with Figure 44. Waveforms SR System Using MOSFET in TO−220 Package with Parasitic Inductance Compensation – SR MOSFET Channel Conduction Time is Optimized Note that using the compensation system is only comparator. Ideally the CS turn-off comparator should beneficial in applications that are using a low R detect voltage that is caused by secondary current directly on DS(on) MOSFET in non-SMT package. Using the compensation the SR MOSFET channel resistance. Practically this is not method allows for optimized efficiency with a standard possible because of the bonding wires, leads and soldering. TO−220 package that in turn results in reduced costs, as the To assure the best efficiency results, a Kelvin connection of SMT MOSFETs usually require reflow soldering process the SR controller to the power circuitry should be and more expensive PCB. implemented (i.e. GND pin should be connected to the SR From the above paragraphs and parameter tables it is MOSFET source soldering point and current sense pin evident that turn-off threshold precision is quite critical. If should be connected to the SR MOSFET drain soldering we consider a SR MOSFET with R of 1 m(cid:4), the 1 mV point). Any impact of PCB parasitic elements on the SR DS(on) error voltage on the CS pin results in a 1 A turn-off current controller functionality is then avoided. Figures 45 and 46 threshold difference. Thus the PCB layout is very critical show examples of SR system layouts using parasitic when implementing the SR system. Note that the CS turn-off inductance compensation (i.e. for low R MOSFET in DS(on) comparator as well as compensation inputs are referred to TO−220 package ) and not using compensation (i.e. for the GND pin. Any parasitic impedance (resistive or higher R MOSFET in TO−220 package or SMT DS(on) inductive − talking about m(cid:4) and nH values) can cause a package MOSFETs). high error voltage that is then evaluated by the CS www.onsemi.com 16

NCP4304A, NCP4304B NCP4304 Figure 45. Recommended Layout When Parasitic Figure 46. Recommended Layout When Parasitic Inductance Compensation is Used Inductance Compensation is Not Used Trigger/Disable Input (above 2.5 V) the driver is disabled immediately, except The NCP4304A/B features an ultrafast trigger input that during DRV rising edge when TRIG/DIS is blanked for exhibits a typically of 10 ns delay from its activation to the 120 ns. If the trigger signal is high for more than 100 (cid:2)s the turn-off of the SR MOSFET. The main purpose of this input driver enters standby mode. The IC consumption is reduced is to turn-off the SR MOSFET in applications operating in below 100 (cid:2)A during the standby mode. The device CCM mode via a signal coming from the primary side or recovers operation in 10 (cid:2)s when the trigger voltage is direct synchronization SR MOSFET turn-on and turn-off increased to exit standby mode. TRIG/DIS input is superior event according to primary controller signals. The to CS input except blanking period. TRIG/DIS signal NCP4304A/B operation can be disabled using the turns-OFF the SR MOSFET or disable its turn-ON if TRIG/DIS input. If the TRIG/DIS input is pulled high TRIG/DIS is pulled above V . TRIG/DIS 100 (cid:2)s SLEEP MODE R Timer VTRIG/DIS = 2 V Inv One Shot TRIG/DIS S Q DRV RESET OR 4 ZCD RESET Trigger Information R Q from the Primary A (cid:2)0 ZD 10 V AND Inv DRV SET ENABLE 1 Trigger Blanking Inv One Shot toff_min Generator Start 120 ns During DRV Rising Edge 120 ns GND Figure 47. Trigger Input Internal Circuitry www.onsemi.com 17

NCP4304A, NCP4304B Figure 48 depicts driver turn-ON events. Turn-ON of the pulled LOW and CS (V ) is still under V threshold DS th_cs_on SR MOSFET is possible if CS (V ) signal falls under then the DRV is turned-ON (t7 marker). DS V threshold and TRIG/DIS is pulled LOW (t1 to t3 Time markers t14 and t15 in Figure 48 demonstrate th_cs_on time interval). situation when CS (V ) is above V threshold and DS th_cs_on When the CS (V ) reached the V threshold and TRIG/DIS is pulled down. In this case the driver stays LOW DS th_cs_on TRIG/DIS is pulled HIGH the driver stays LOW (t6, t7 time (t12 to t15 marker). markers) if the TRIG/DIS is HIGH. If the TRIG/DIS is VDS Vth_cs_off Vth_cs_on TRIG/DIS DRV t0 t1t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 Figure 48. DRV Turn ON Events The TRIG/DIS input is blanked for 120 ns after DRV set spikes that are present on the TRIG/DIS input pin during the signal to avoid undesirable behavior during SR MOSFET SR MOSFET turn-on process. DRV response to the short turn-ON event. The blanking time in combination with high needle pulse on the TRIG/DIS pin is depicted in Figure 49 threshold voltage (2 V) prevent triggering on ringing and – this short pulse turns-on the DRV for 120 ns. VDS Vth_cs_off Vth_cs_on TRIG/DIS Disable of Trigger Min_ON_Time DRV t0 t1 120 ns t2 t3 Figure 49. Trigger Needle Pulse and Trigger Blank Sequence www.onsemi.com 18

NCP4304A, NCP4304B Advantage of the trigger blanking time during DRV performance of the trigger logic, could turn-OFF the SR turn-ON event is evident from Figure 50. Rising edge of the MOSFET in inappropriate time. Implementation of the DRV signal may cause additional spikes on the TRIG/DIS trigger blanking time period helps to avoid such situation. input. These spikes, in combination with ultra-fast VDS Vth_cs_off Vth_cs_on TRIG/DIS Disable of Trigger Min_ON_Time DRV t0 t1 120 ns t4 t5 t6 t2 t3 Figure 50. Trigger Blanking Masked-out Noise in Trigger Signal During Switch-ON Event Figure 51 depicts driver turn-OFF events in details. If the (t1−t2, t5–t6, t9–t10 markers). DRV is turned-OFF if CS CS (V ) stays below V threshold driver is (V ) signal reaches V threshold (t4 marker). The DS th_cs_off DS th_cs_off turned-OFF according to rising edge of the TRIG/DIS DRV ON-time is prolonged till minimum-ON time period signal. TRIG/DIS can turn-OFF the driver also during falling edge if the CS (V ) reaches V before DS th_cs_off minimum-ON time period (time marker t2 and t3 in minimum-ON time period elapsed (t7−t8, t11−t12 markers). Figure 51). Figure 54 depicts entering into the sleep mode. If the Figure 52 depicts another driver turn-OFF events in TRIG/DIS is pulled up for more than 100 (cid:2)s the details. Driver is turned-OFF according to the CS (V ) NCP4304A/B enters low consumption mode. The DRV DS signal (t2 marker) and only after minimum-ON time stays LOW (disabled) during entering sleep mode. elapsed. TRIG/DIS signal needs to be LOW during this Figure 55 shows sleep mode transition 2nd case – i.e. event. If the CS (V ) voltage reaches V threshold TRIG/DIS rising edge comes during the trigger blank DS th_cs_off before minimum-ON time period ends and TRIG/DIS pin is period. LOW the DRV is turned-OFF on the falling edge of the Figure 56 depicts entering into sleep mode and wake-up minimum-ON time period (t4 and t6 time markers in sequence. Figure 52). Figures 57 and 58 show wake-up situations in details. If Figure 53 depicts performance of the NCP4304A/B the NCP4304A/B is in sleep mode and TRIG/DIS is pulled controller when trigger pin is permanently pulled LOW. In LOW NCP4304A/B requires up to 10 (cid:2)s period to recover this case the DRV is turned ON and OFF according to the CS all internal circuitry to normal operation mode. The driver (V ) signal. The driver can be turned off only after is then enabled in the next cycle of CS (V ) signal only. DS DS minimum-ON time period elapsed. The driver is turned-ON TheDRV stays LOW during waking-up time period. in the time when CS (V ) reaches V threshold DS th_cs_on www.onsemi.com 19

NCP4304A, NCP4304B VDS Vth_cs_off Vth_cs_on TRIG/DIS Min_ON_Time DRV t0 t1 t2 t3 Figure 51. Driver Turn-OFF Events Based on the TRIG/DIS Input VDS Vth_cs_off Vth_cs_on TRIG/DIS Min_ON_Time DRV t0 t1 t2 t3 t4 t5 t6 Figure 52. Driver OFF Sequence Chart 2 www.onsemi.com 20

NCP4304A, NCP4304B VDS Vth_cs_off Vth_cs_on TRIG/DIS Min_ON_Time DRV t0 t1t2 t3 t4 t5 t6 t7 t8 t9 t11 t10 t12 Figure 53. TRIG/DIS is LOW Sequence Chart VDS Vth_cs_off Vth_cs_on TRIG/DIS Min_ON_Time Power Consumption 100 (cid:2)s DRV t0 t1 t2 t3 Figure 54. TRIG/DIS from LOW to HIGH Sequence 1 www.onsemi.com 21

NCP4304A, NCP4304B VDS Vth_cs_off Vth_cs_on TRIG/DIS Min_ON_Time Power Consumption 100 (cid:2)s 120 ns DRV t0 t1 t2 t3 Figure 55. TRIG/DIS from LOW to HIGH Sequence 2 VDS TRIG/DIS 100 (cid:2)s Power 10 (cid:2)s Consumption Sleep Mode DRV t0 t1 t2 t3 t4 Figure 56. Sleep Mode Sequence www.onsemi.com 22

NCP4304A, NCP4304B VDS Vth_cs_off Vth_cs_on TRIG/DIS 10 (cid:2)s Sleep Mode Power Wake Up Consumption Driver DRV LOW t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 Figure 57. Waking-up Sequence VDS Vth_cs_off Vth_cs_on Sleep TRIG/DIS Mode DRV T1 t0 t4 t5 t2 Waking-up Time Waked Up t1 t3 Figure 58. Wake-up Time Sequence www.onsemi.com 23

NCP4304A, NCP4304B Figure 59 shows IC behavior in case the trigger signal sequence elapses in time t4 the DRV is turned ON. In time features two pulses during one cycle of the V (CS) signal. t5 Trigger signal rises up and terminates this cycle of the CS DS TRIG/DIS enables driver at time t1 and DRV turns ON signal in time t5. Next cycle starts in time t6. Trigger enables because the V voltage is under V threshold DRV and V is under V threshold voltage so DRV DS th_cs_on DS th_cs_on voltage. The trigger signal and consequently DRV output turns ON in time t6. TRIG/DIS signal rises up to HIGH level fall down in time t2. The minimum OFF time generator is in time t7, consequently DRV turns OFF and this starts triggered in time t2. TRIG/DIS drops down to LOW level in minimum OFF time generator. Because minimum OFF time time t3 but there is still minimum OFF time sequence present period is longer then the rest of time to the end of cycle of so the DRV output stays low. When the minimum OFF time V − DRV is disabled. DS VDS Vth_cs_off Vth_cs_on TRIG/DIS Min_ON_Time Min_OFF_Time DRV t0 t1 t2 t3 t4 t5 t6 t7 t8 t9t10 Figure 59. IC Behavior when Multiple Trigger Pulses Appear on TRIG/DIS Input Note that the TRIG/DIS input is an ultrafast input that is transformer can be for instance prepared on a small toroidal sensitive even to very narrow voltage pulses. Thus it is wise ferrite core with diameter of 8 mm. Proper safety insulation to keep this input on a low impedance path and provide it between primary and secondary sides can be easily assured with a clean triggering signal in the time this input is enabled by using triple insulated wire for one or even both windings. by internal logic. The primary MOSFET gate voltage rising edge is delayed A typical application schematic of a CCM flyback by external circuitry consisting of transistors Q1, Q2 and converter with the NCP4304A/B driver can be seen in surrounding components. The primary MOSFET is thus Figure 60. In this application the trigger signal is taken turned-on with a slight delay so that the secondary controller directly from the flyback controller driver output and turns-off the SR MOSFET by trigger signal prior to the transmitted to the secondary side by pulse transformer TR2. primary switching. This method reduces the commutation Because the TRIG/DIS input is edge sensitive, it is not losses and the SR MOSFET drain voltage spike, which necessary to transmit the entire primary driver pulse to the results in improved efficiency. secondary. The coupling capacitor C5 is used to allow pulse It is also possible to use capacitive coupling (use transformer core reset and also to prepare a needle pulse additional capacitor with safety insulation) between the (apulse with width lower than 100 ns) to be transmitted to primary and secondary to transmit the trigger signal. We do the NCP4304A/B TRIG/DIS input. The advantage of needle not recommend this technique as the parasitic capacitive trigger pulse usage is that the required volt-second product currents between primary and secondary may affect the of the pulse transformer is very low and that allows the trigger signal and thus overall system functionality. designer to use very small and cheap magnetics. The trigger www.onsemi.com 24

NCP4304A, NCP4304B Vbulk + TR1 C2 R5 C3 +Vout D3 Delay Generator VCC M2 + C7 FLYBACK + D4 CONTROL R2 C4 GND CIRCUITRY DRV D1 Q2 Q1 C6 FB CS R3 M1 R1 R4 R9 VCC DRV C1 MIN_TOFF GND D2 R6 MIN_TON COMP D5 R7 R10 TRIG/DIS CS OK1 C5 TR2 R11 Figure 60. Typical Application Schematic when NCP4304A/B is Used in CCM Flyback Converter t and t Adjustment timers avoid false triggering on the CS input after the on_min off_min The NCP4304A/B offers adjustable minimum ON and MOSFET is turned on or off. The adjustment is based on an OFF time periods that ease the implementation of the internal timing capacitance and external resistors connected synchronous rectification system in a power supply. These to the GND pin – refer to Figure 61 for better understanding. Vdd To Internal Logic VREF + ton_min N O T − _ N MI + R I Discharge MIN_TON IRMIN_TON − Ct Switch RMIN_TON GND Figure 61. Internal Circuitry of ton_min Generator (toff_min Generator Works in the Same Way) Current through the RMIN_TON adjust resistor can be VREF calculated as: t (cid:2)C (cid:3) VREF (cid:2)C (cid:3) VREF V on_min t I t R (eq. 5) I (cid:2) REF (eq. 4) RMIN_TON MIN_TON RMIN_TON R MIN_TON (cid:2)C (cid:3)R t MIN_TON As the same current is used for the internal timing As can be seen from Equation 5, the minimum ON and capacitor (C) charging, one can calculate the minimum t OFF times are independent of the V or VCC level. The on-time duration using this equation. REF www.onsemi.com 25

NCP4304A, NCP4304B internal capacitor size would be too high if we would use minimum t and t blanking periods from measured on off directly I current thus this current is decreased by values in Figures 62 and 63. RMIN_TON the internal current mirror ratio. One can then estimate 6 6 5 5 4 4 s) s) (cid:3) (cid:3) (n 3 (n 3 mi mi _ _ on off t 2 t 2 1 1 0 0 0 10 20 30 40 50 60 0 10 20 30 40 50 60 RMIN_TON (k(cid:2)) RMIN_TOFF (k(cid:2)) Figure 62. MIN_TON Adjust Characteristic Figure 63. MIN_TOFF Adjust Characteristic The absolute minimum t duration is internally clamped to modulate blanking periods by using an external NPN on to 130 ns and minimum t duration to 600 ns in order to transistor − refer to Figure 64. The modulation signal can be off prevent any potential issues with the minimum t and/or t derived based on the load current or feedback regulator on off input being shorted to GND. voltage. Some applications may require adaptive minimum on and off time blanking periods. With NCP4304A/B it is possible Vdd To Internal Logic VREF + ton_min N O T − _ N MI + R I Discharge Modulation Current MIN_TON IRMIN_TON − Ct Switch RMIN_TON ton_min Modulation Voltage Input GND Figure 64. Possible Connection for t and t Modulation on_min off_min In LLC applications with a very wide operating frequency may then be too short. To overcome possible issues with the range it is necessary to have very short minimum on time and LLC operating under low line and light load conditions, one off time periods in order to reach the required maximum can prolong the minimum off time blanking period by using operating frequency. However, when a LLC converter resistors R and R connected from the DRAIN1 DRAIN2 operates under low frequency, the minimum off time period opposite SR MOSFET drain – refer to Figure 65. www.onsemi.com 26

NCP4304A, NCP4304B RDRAIN1 C2 RMIN_TOFF VCC DRV MIN_TOFF GND MIN_TON COMP RMIN_TON TRIG/DIS CS +Vbulk +Vout TR1 M1 M3 N2 + LLC LCOMP1 C4 STAGE RTN CONTROL M2 N1 LCOMP2 N3 M4 C1 RDRAIN2 C3 RMIN_TOFF VCC DRV Trig from Primary MIN_TOFF GND (Option for LLC) MIN_TON COMP TRIG/DIS CS RMIN_TON D1 OK1 Note: LCOMP1, 2 are optional for MOSFETs with leads. Figure 65. Possible Connection for t Prolongation in LLC Application with off_min Wide Operating Frequency Range Note that R and R should be designed in off process always starts before the drain to source voltage DRAIN1 DRAIN2 such a way that the maximum pulse current into the rises up significantly. Therefore, the MOSFET switch MIN_TOFF adjust pin is below 10 mA. Voltage on the always operates under Zero Voltage Switching (ZVS) MIN_TOFF and MIN_TON pins is clamped by internal conditions when implemented in a synchronous zener protection to 10 V. rectification system. The following steps show how to approximately calculate Power Dissipation Calculation the power dissipation and DIE temperature of the It is important to consider the power dissipation in the NCP4304A/B controller. Note that real results can vary due MOSFET driver of a SR system. If no external gate resistor to the effects of the PCB layout on the thermal resistance. is used and the internal gate resistance of the MOSFET is very low, nearly all energy losses related to gate charge are Step 1 – MOSFET Gate-to-Source Capacitance: dissipated in the driver. Thus it is necessary to check the SR During ZVS operation the gate to drain capacitance does driver power losses in the target application to avoid over not have a Miller effect like in hard switching systems temperature and to optimize efficiency. because the drain to source voltage is close to zero and its In SR systems the body diode of the SR MOSFET starts change is negligible. conducting before turn on because the V threshold th_cs_on level is below 0 V. On the other hand, the SR MOSFET turn www.onsemi.com 27

NCP4304A, NCP4304B 8000 VDS = 0 V VGS = 0 V 7000 pF) 6000 Ciss D ce ( 5000 pacitan 34000000 Crss Ciss CCirssss == CCggsd + Cgd G Cgd Cds Ca 2000 Coss = Cds + Cgd Cgs C, Coss 1000 Crss 0 S 10 0 10 20 30 40 VGS VDS Gate-to-Source or Drain-to-Source Voltage (V) Figure 66. Typical MOSFET Capacitance Dependency on V and V Voltage DS GS Therefore, the input capacitance of a MOSFET operating The total driving loss can be calculated using the selected in ZVS mode is given by the parallel combination of the gate gate driver clamp voltage and the input capacitance of the to source and gate to drain capacitances (i.e. C capacitance MOSFET: iss fQor give, no fg matoes tt oM sOoSuFrcEeT sv oonlt athgee )m. aTrhkee t tios tdael fginaetde fcohra hragred, PDRV_total(cid:2)VCC(cid:3)Vclamp(cid:3)Cg_ZVS(cid:3)fSW (eq. 6) g_total switching conditions. In order to accurately calculate the Where: driving losses in a SR system, it is necessary to determine the VCC is the supply voltage gate charge of the MOSFET for operation specifically in a Vclamp is the driver clamp voltage ZVS system. Some manufacturers define this parameter as Cg_ZVS is the gate to source capacitance of the Q . Unfortunately, most datasheets do not provide this MOSFET in ZVS mode g_ZVS data. If the Ciss (or Qg_ZVS) parameter is not available then fsw is the switching frequency of the target it will need to be measured. Please note that the input application capacitance is not linear (as shown Figure 66) and it needs The total driving power loss won’t only be dissipated in to be characterized for a given gate voltage clamp level. the IC, but also in external resistances like the external gate Step 2 – Gate Drive Losses Calculation: resistor (if used) and the MOSFET internal gate resistance Gate drive losses are affected by the gate driver clamp (Figure 67). Because NCP4304A/B features a clamped voltage. Gate driver clamp voltage selection depends on the driver, it’s high side portion can be modeled as a regular type of MOSFET used (threshold voltage versus channel driver switch with equivalent resistance and a series voltage resistance). The total power losses (driving loses and source. The low side driver switch resistance does not drop conduction losses) should be considered when selecting the immediately at turn-off, thus it is necessary to use an gate driver clamp voltage. Most of today’s MOSFETs for SR equivalent value (Rdrv_low_eq) for calculations. This method systems feature low R for 5 V V voltage and thus it simplifies power losses calculations and still provides DS(on) GS is beneficial to use the B version. However, there is still a big acceptable accuracy. Internal driver power dissipation can group of MOSFETs on the market that require higher gate then be calculated using Equation 7: to source voltage − in this case the A version should be used. www.onsemi.com 28

NCP4304A, NCP4304B VCC VCC + VCC − Vclamp − Rdrv_high_eq. DRV Rg_ext SR MOSFET Rdrv_low_eq. Rg_int GND Cg_ZVS Figure 67. Equivalent Schematic of Gate Drive Circuitry (cid:5) (cid:6) 1 Rdrv_low_eq (cid:5) (cid:6) P (cid:2) (cid:3)C (cid:3)V 2(cid:3)f (cid:3) (cid:7)C (cid:3)V (cid:3)f (cid:3) V (cid:4)V DRV_IC 2 g_ZVS clamp SW R (cid:7)R (cid:7)R g_ZVS clamp SW CC clamp drv_low_eq g_ext g_int (eq. 7) (cid:5) (cid:6) R 1 drv_high_eq (cid:7) (cid:3)C (cid:3)V 2(cid:3)f (cid:3) 2 g_ZVS clamp SW R (cid:7)R (cid:7)R drv_high_eq g_ext g_int Where: Step 4 – IC Die Temperature Arise Calculation: R is the Ddriver low side switch equivalent The die temperature can be calculated now that the total drv_low_eq resistance (1.55 (cid:4)) internal power losses have been determined (driver losses R is the driver high-side switch equivalent plus internal IC consumption losses). The SO−8 package drv_high_eq resistance (7 (cid:4)) thermal resistance is specified in the maximum ratings table R is the external gate resistor (if used) for a 35 (cid:2)m thin copper layer with no extra copper plates on g_ext R is the internal gate resistance any pin (i.e. just 0.5 mm trace to each pin with standard g_int of the MOSFET soldering points are used). The die temperature is calculated as: Step 3 – IC Consumption Calculation: (cid:5) (cid:6) In this step, power dissipation related to the internal IC TDIE(cid:2) PDRV_IC(cid:7)PICC (cid:3)R(cid:3)JA(cid:7)TA (eq. 9) consumption is calculated. This power loss is given by the I current and the IC supply voltage. The I current Where: CC CC depends on switching frequency and also on the selected PDRV_IC is the IC driver internal power dissipation ton_min and toff_min periods because there is current flowing PICC is the IC control internal power dissipation out from the MIN_TON and MIN_TOFF pins. The most R(cid:3)JA is the thermal resistance from junction to accurate method for calculating these losses is to measure ambient the ICC current when CDRV = 0nF and the IC is switching TA is the ambient temperature at the target frequency with given t and t adjust on_min off_min resistors. Refer also to Figure 68 for typical IC consumption charts when the driver is not loaded. IC consumption losses can be calculated as: P (cid:2)V (cid:3)I (eq. 8) ICC CC CC www.onsemi.com 29

NCP4304A, NCP4304B 180 160 W) A Version, m140 N ( VCC = 30 V O120 B Version, TI M100 VCC = 30 V U S N 80 O C A Version, ER 60 VCC = 12 V W 40 O B Version, P 20 VCC = 12 V 0 50 100 150 200 250 300 350 400 450 500 OPERATING FREQUENCY (kHz) Figure 68. IC Power Consumption as a Function of Frequency for C = 0 nF, R = R = 5 k(cid:2) DRV MIN_TON MIN_TOFF 400 350 W) m N ( 300 TIO 250 A Version, B Version, UM 200 VCC = 30 V VCC = 30 V S N O A Version, R C 150 VCC = 12 V E 100 W O P 50 B Version, VCC = 12 V 0 50 100 150 200 250 300 350 400 450 500 OPERATING FREQUENCY (kHz) Figure 69. IC Power Consumption as a Function of Frequency for C = 1 nF, R = R = 5 k(cid:2) DRV MIN_TON MIN_TOFF 800 A Version, W) 700 VCC = 30 V ON (m 600 VBC VCe =rs 3io0n V, TI 500 M U 400 S N O C 300 A Version, R WE 200 B Version, VCC = 12 V O VCC = 12 V P 100 0 50 100 150 200 250 300 350 400 450 500 OPERATING FREQUENCY (kHz) Figure 70. IC Power Consumption as a Function of Frequency for C = 10 nF, R = R = 5 k(cid:2) DRV MIN_TON MIN_TOFF www.onsemi.com 30

NCP4304A, NCP4304B PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK NOTES: −X− 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. A 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) 8 5 PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL 1 IN EXCESS OF THE D DIMENSION AT −Y− 4 K 6. 7M5A1X−I0M1U TMH RMUA T7E51R−IA0L6 CAROEN DOIBTSIOONL.ETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.80 5.00 0.189 0.197 C NX 45(cid:3) B 3.80 4.00 0.150 0.157 SEATING C 1.35 1.75 0.053 0.069 PLANE D 0.33 0.51 0.013 0.020 −Z− G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 0.10 (0.004) J 0.19 0.25 0.007 0.010 H D M J K 0.40 1.27 0.016 0.050 M 0 (cid:3) 8 (cid:3) 0 (cid:3) 8 (cid:3) N 0.25 0.50 0.010 0.020 0.25 (0.010)M Z Y S X S S 5.80 6.20 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 4.0 0.275 0.155 0.6 1.270 0.024 0.050 (cid:5) (cid:6) mm SCALE 6:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 31

NCP4304A, NCP4304B PACKAGE DIMENSIONS DFN8 4x4 CASE 488AF ISSUE C D A NOTES: B L L 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED ÉÉ L1 TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM TERMINAL TIP. PIN ONE E DETAIL A 4. COPLANARITY APPLIES TO THE EXPOSED REFERENCE ÉÉ OPTIONAL PAD AS WELL AS THE TERMINALS. 2X 0.15 C ÉÉ CONSTRUCTIONS 5. DCEOTNASILTSR UAC ATNIODN BS S FHOORW T EORPMTIIONNAALSL. MILLIMETERS 2X 0.15 C DIM MIN MAX TOP VIEW A3 A 0.80 1.00 EXPOSED CuÇÇMOLD CMPD ÉÉÉ A1 0.00 0.05 A3 0.20 REF DETAIL B ÇÉÇÉ ÉÇÉÇÉÇ b 0.25 0.35 0.10 C D 4.00 BSC ÇÇÇÇÇ D2 1.91 2.21 A A1 E 4.00 BSC 8X 0.08 C (A3) DETAIL B E2 2.09 2.39 ALTERNATE e 0.80 BSC NOTE 4 A1 C SEATING CONSTRUCTIONS K 0.20 −−− SIDE VIEW PLANE L 0.30 0.50 L1 −−− 0.15 D2 SOLDERING FOOTPRINT* DETAIL A 1ÇÇÇÇ4 8X L 2.21 8X 0.63 E2 ÇÇÇÇ K 8 5 8Xb 4.30 2.39 e 0.10 C A B PACKAGE OUTLINE 0.05 C NOTE 3 BOTTOM VIEW 8X 0.35 0.80 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative www.onsemi.com NCP4304/D 32

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