NCP3163, NCV3163 3.4 A, Step-Up/Down/ Inverting 50-300 kHz Switching Regulator The NCP3163 Series is a performance enhancement to the popular MC33163 and MC34163 monolithic DC−DC converters. These devices consist of an internal temperature compensated reference, http://onsemi.com comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch. This controller was MARKING specifically designed to be incorporated in step−down, step−up, or DIAGRAMS voltage−inverting applications with a minimum number of external 16 16 components. The NCP3163 comes in an exposed pad package which can greatly increase the power dissipation of the built in power switch. 1 NCx3163yPW Features SOIC−16W AWLYYWWG • Output Switch Current in Excess of 3.0 A EXPOSED PAD • 3.4 A Peak Switch Current PW SUFFIX • CASE 751AG 1 Frequency is Adjustable from 50 kHz to 300 kHz • Operation from 2.5 V to 40 V Input • Externally Adjustable Operating Frequency 1 18 • 18 Precision 2% Reference for Accurate Output Voltage Control • Driver with Bootstrap Capability for Increased Efficiency 18−LEAD DFN NCx3163y • Cycle−by−Cycle Current Limiting 1 MN SUFFIX AWLYYWW(cid:2) • (cid:2) Internal Thermal Shutdown Protection CASE 505 • Low Voltage Indicator Output for Direct Microprocessor Interface • Exposed Pad Power Package • NCx3163y = Specific Device Code Low Standby Current • x = P or V NCV Prefix for Automotive and Other Applications Requiring Site y = blank or B and Change Control A = Assembly Location • These are Pb−Free Devices WL = Wafer Lot YY = Year WW = Work Week Current G or (cid:2) = Pb−Free Package 8 - Limit 9 (Note: Microdot may be in either location) + Vin 7 10 + ORDERING INFORMATION Cin VCC See detailed ordering and shipping information in the package dimensions section on page 18 of this data sheet. 6 Oscillator 11 R *For additional information on our Pb−Free strategy 5 12 and soldering details, please download the Q ON Semiconductor Soldering and Mounting Thermal S Techniques Reference Manual, SOLDERRM/D. 4 13 VCC 3 14 2 + 15 + - + 1 + 16 - LVI VCC Vout + (Bottom View) CO Figure 1. Typical Buck Application Circuit © Semiconductor Components Industries, LLC, 2010 1 Publication Order Number: April, 2010 − Rev. 7 NCP3163/D

NCP3163, NCV3163 0.25 V Current IPKsense 8 - Limit 9 Driver Collector RSC + VCC 7 10 VCC Switch Collector Timing Capacitor 6 Oscillator Q1 11 CT Q2 Shutdown R RDT 5 12 Q 60 Thermal S Gnd 4 Latch 13 VCC Voltage Feedback 1 3 14 Switch Emitter 45 k 2.0 mA Voltage Feedback 2 2 + Feedback 15 + - Comparator 1.25 V + 15 k LVI Output 1 + 7.0 V 16 Bootstrap Input LVI - 1.125 V VCC + = Sink Only (Bottom View) - Positive True Logic Figure 2. Representative Block Diagram PIN FUNCTION DESCRIPTION SOIC16 DFN18 PIN NAME DESCRIPTION 1 15 LVI Output This pin will sink current when FB1 and FB2 are less than the LVI threshold (Vth). 2 16 Voltage Feedback 2 Connecting this pin to a resistor divider off of the output will regulate the application according to the Vout design equation in Figure 22. 3 17 Voltage Feedback 1 Connecting this pin directly to the output will regulate the device to 5.05 V. 4 18 GND Ground pin for all internal circuits and power switch. 6 1 Timing Capacitor Connect a capacitor to this pin to set the frequency. The addition of a parallel resist- or will decrease the maximum duty cycle and increase the frequency. 7 3 VCC Power pin for the IC. 8 4 Ipk Sense When (VCC−VIPKsense) > 250 mV the circuit resets the output driver on a pulse by pulse basis. 9 5 Drive Collector Voltage driver collector 10,11 6,7,8,9 Switch Collector Internal switch transistor collector 14,15 10,11,12,13 Switch Emitter Internal switch transistor emitter 16 14 Bootstrap Input Connect this pin to VCC for operation at low VCC levels. For some topologies, a series resistor and capacitor can be utilized to improve the converter efficiency. 5,12,13 2 No Connect These pins have no connection. Exposed Exposed Exposed Pad The exposed pad beneath the package must be connected to GND (pin 4). Addi- Pad Pad tionally, using proper layout techniques, the exposed pad can greatly enhance the power dissipation capabilities of the NCP3163. http://onsemi.com 2

NCP3163, NCV3163 MAXIMUM RATINGS (Note 1) Rating Symbol Value Unit Power Supply Voltage VCC 0 to +40 V Switch Collector Voltage Range VCSW −1.0 to +40 V Switch Emitter Voltage Range VESW −2.0 to +40 V Switch Collector to Emitter Voltage VCESW +40 V Switch Current ISW 3.4 A Driver Collector Voltage (Pin 8) VCC −1.0 to +40 V Driver Collector Current (Pin 8) ICC 150 mA Bootstrap Input Current Range IBST −100 to +100 mA Current Sense Input Voltage Range VIPKSNS (VCC − 7.0) to (VCC + 1.0) V Feedback and Timing Capacitor Input Voltage Range Vin −1.0 to +7.0 V Low Voltage Indicator Output Voltage Range VCLVI −1.0 to +40 V Low Voltage Indicator Output Sink Current ICLVI 10 mA Power Dissipation and Thermal Characteristics Thermal Characteristics °C/W Thermal Resistance, Junction−to−Case R(cid:2)JC 15 Thermal Resistance, Junction−to−Air R(cid:2)JA 56 Storage Temperature Range Tstg −65 to +150 °C Maximum Junction Temperature TJmax +150 °C Operating Ambient Temperature (Note 3) TA °C NCP3163 0 to +70 NCP3163B −40 to +85 NCV3163 −40 to +125 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL−STD−883, Method 3015. Machine Model Method 200 V. Charged Device Model 750 V for corner pins and 500 V for others (according to AEC−Q100). 2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. 3. Maximum package power dissipation limits must be observed. Maximum Junction Temperature must not be exceeded. 4. The pins which are not defined may not be loaded by external signals. PIN CONNECTIONS 1 16 LVI Output Bootstrap Input 2 15 Timing Capacitor 1 18 GND Voltage Feedback 2 3 14 Switch N/C 2 GND 17 Voltage Feedback 1 Voltage Feedback 1 4 13 Emitter VCC 3 16 Voltage Feedback 2 GND Ipk Sense 4 15 LVI Output 5 12 N/C Driver Collector 5 14 Bootstrap Input N/C 6 11 Switch Collector 6 13 Switch Emitter Timing Capacitor Switch Collector 7 12 Switch Emitter 7 10 Switch Collector VCC Switch Collector 8 EP Flag 11 Switch Emitter 8 9 Ipk Sense Driver Collector Switch Collector 9 10 Switch Emitter (Top View) Note: Pin 18 must be tied to EP Flag on PCB http://onsemi.com 3

NCP3163, NCV3163 ELECTRICAL CHARACTERISTICS (VCC = 15 V, Pin 16 = VCC, CT = 270 pF, RT = 15 k(cid:3), for typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies (Note 7), unless otherwise noted.) Characteristic Symbol Min Typ Max Unit OSCILLATOR Frequency fOSC kHz TA = 25°C, VCC = 15 V 225 250 275 Total Variation over VCC = 2.5 V to 40 V and Temperature 212 250 288 Charge Current Ichg − 225 − (cid:4)A Discharge Current Idischg − 25 − (cid:4)A Charge to Discharge Current Ratio NCP3163 Ichg/Idischg 8.0 9.0 10.5 − NCV3163 7.0 9.0 10.5 Sawtooth Peak Voltage VOSC(P) − 1.25 − V Sawtooth Valley Voltage VOSC(V) − 0.55 − V FEEDBACK COMPARATOR 1 Threshold Voltage Vth(FB1) V TA = 25°C 4.9 5.05 5.2 Total Variation over VCC = 2.5 V to 40 V and Temperature 4.85 − 5.25 Threshold Voltage − Line Regulation (VCC = 2.5 V to 40 V, TA = 25°C) REGline(FB1) − 0.008 0.03 %/V Input Bias Current (VFB1 = 5.05 V) IIB(FB1) − 100 200 (cid:4)A FEEDBACK COMPARATOR 2 Threshold Voltage Vth(FB2) V TA = 25°C, VCC = 15 V 1.225 1.25 1.275 Total Variation over VCC = 2.5 V to 40 V and Temperature 1.213 − 1.287 Threshold Voltage − Line Regulation (VCC = 2.5 V to 40 V, TA = 25°C) REGline(FB1) − 0.008 0.03 %/V Input Bias Current (VFB2 = 1.25 V) IIB(FB2) −0.4 − 0.4 (cid:4)A CURRENT LIMIT COMPARATOR Threshold Voltage Vth(Sense) mV TA = 25°C − 250 − Total Variation over VCC = 2.5 V to 40 V, and Temperature 225 − 270 Input Bias Current (VIpk (Sense) = 15 V) IIB(Sense) − 1.0 20 (cid:4)A DRIVER AND OUTPUT SWITCH (Note 6) Saturation Voltage (ISW = 2.5 A, Pins 14, 15 grounded) VCE(sat) V Non−Darlington (RPin 9 = 110 (cid:3) to VCC, ISW/IDRV ≈ 20) NCP3163 − 0.6 1.0 NCV3163 − 0.6 1.5 Darlington Connection (Pins 9, 10, 11 connected) NCP3163 − 1.0 1.4 NCV3163 − 1.0 1.5 Collector Off−State Leakage Current (VCE = 40 V) IC(off) − 0.02 100 (cid:4)A Bootstrap Input Current Source (VBS = VCC + 5.0 V) Isource(DRV) 0.5 2.0 4.0 mA Bootstrap Input Zener Clamp Voltage (IZ = 25 mA) VZ VCC + 6.0 VCC + 7.0 VCC + 9.0 V LOW VOLTAGE INDICATOR Input Threshold (VFB2 Increasing) Vth 1.07 1.125 1.18 V Input Hysteresis (VFB2 Decreasing) VH − 15 − mV Output Sink Saturation Voltage (Isink = 2.0 mA) VOL(LVI) − 0.15 0.4 V Output Off−State Leakage Current (VOH = 15 V) IOH − 0.01 5.0 (cid:4)A TOTAL DEVICE Standby Supply Current (VCC = 2.5 V to 40 V, Pin 8 = VCC, ICC − 6.0 10 mA Pins 6, 14, 15 = GND, remaining pins open) 5. Maximum package power dissipation limits must be observed. 6. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 7. Tlow = 0°C for NCP3163 Thigh = +70°C for NCP3163 = −40°C for NCP3163B = +85°C for NCP3163B = −40°C for NCV3163 = +125°C for NCV3163 http://onsemi.com 4

NCP3163, NCV3163 300 VCC = 15 V TA = 25°C 250 Hz) 200 Y (k Rt = 15 k(cid:3) C N UE 150 Q RE Rt = open F 100 50 0 100 200 300 400 500 600 700 CT, TIMER CAPACITANCE (pF) Figure 3. Oscillator Frequency vs. Timer Capacitance (C ) T %) 2.0 %) 4.0 E ( VCC = 15 V E ( VCC = 15 V NG CT = 620 pF NG 2.0 CT = 230 pF HA 0 HA RT = 20 k(cid:3) C C 0 Y Y C C N N E E -(cid:2)2.0 U U Q -(cid:2)2.0 Q E E R R -(cid:2)4.0 F F R R O O T T -(cid:2)6.0 A -(cid:2)4.0 A L L L L CI CI -(cid:2)8.0 S S O O , C-(cid:2)6.0 , C -(cid:2)10 OS -(cid:2)55 -(cid:2)25 0 25 50 75 100 125 OS -(cid:2)50 -(cid:2)25 0 25 50 75 100 125 Δf TA, AMBIENT TEMPERATURE (°C) Δf TEMPERATURE (°C) Figure 4. Oscillator Frequency Change vs. Figure 5. Oscillator Frequency Change vs. Temperature when only C is connected to Pin 6 Temperature when C and R are connected to Pin 6 T T T 140 V) 1300 m VCC = 15 V E ( μT ((cid:3)(cid:2)A) 120 VFB1 = 5.05 V OLTAG 1280 VCC = 15 V Vth Max = 1275 mV N V E D URR HOL 1260 Vth Typ = 1250 mV S C 100 ES A R NPUT BI 80 OR 2 TH 1240 Vth Min = 1225 mV , IB RAT 1220 II A P M 60 O 1200 -(cid:2)55 -(cid:2)25 TA, 0AMBIEN2T5 TEMPE5R0ATURE 7(°5C) 100 125 , CFB2) -(cid:2)55 -(cid:2)25 TA,0 AMBIEN2T5 TEMPE5R0ATURE7 (5°C) 100 125 h( Figure 6. Feedback Comparator 1 Input Bias Vt Figure 7. Feedback Comparator 2 Threshold Current vs. Temperature Voltage vs. Temperature http://onsemi.com 5

NCP3163, NCV3163 A) V) E (m 2.8 GE ( 7.6 NT SOURC 2.4 VPCinC 1 =6 1=5 V VCC + 5.0 V MP VOLTA 7.4 IZ = 25 mA E A URR R CL NPUT C 2.0 T ZENE 7.2 P I PU TRA 1.6 P IN 7.0 S A T R O T O S , Be (DRV) 1.-2(cid:2)55 -(cid:2)25 TA, A0MBIENT2 T5EMPER5A0TURE (7°C5) 100 125 V, BOOTZ 6.8-(cid:2)55 -(cid:2)25 TA, 0AMBIENT25 TEMPER50ATURE (7°5C) 100 125 c ur Figure 8. Bootstrap Input Current Figure 9. Bootstrap Input Zener Clamp o s I Source vs. Temperature Voltage vs. Temperature 0 1.2 V) VCC Darlington Configuration , SOURCE SATURATION (CE (sat)----(cid:2)(cid:2)0011....4826 BNooont-sBtroaoptpsetrda,p Ppiend 1, 6P i=n V1C6 C= +V 5C.EPPTC0Aiim nnV =ssit t742e,,5r 85°SC,,o 11,u 02(rNc,, i11on13tge == C2 VGu)rCNrCeDnt to GND V, SINK SATURATION (V)CE (sat) 10000.....08642 DarGCPPTliAiionrnn olg=ssluet on472cndt,,5o ,e58° rPCd, =S 1i,nE i2Vn(smN,kC 91oiiCnt,3tt gee1=, r0 1C2 1C,4)u 51o,r 1rVn1e f5SCing at=ou tFn ruGanrroNtaeimotcDent edVd CSCwitch, RPin9 = 110 (cid:3) to VCC V GND -(cid:2)2.0 0 0 0.8 1.6 2.4 3.2 0 0.8 1.6 2.4 3.2 IE, EMITTER CURRENT (A) IC, COLLECTOR CURRENT (A) Figure 10. Output Switch Source Saturation Figure 11. Output Switch Sink Saturation vs. Emitter Current vs. Collector Current 0 GND IC = 10 (cid:4)A AGE (V) 0.5 VTAC(cid:3)C=(cid:3)(cid:3)=2(cid:3)55° VC AGE (V) -(cid:2)0.4 N VOLT 0.4 ER VOLT -(cid:2)0.8 IC = 10 mA TURATIO 0.3 T -(cid:2)1.2 A 0.2 T S MI T E U , E VCC = 15 V TP V -(cid:2)1.6 Pins 7, 8, 9, 10, 16 = VCC OU 0.1 PPiinn s1 44, D6r i=v eGnN NDegative , VI) L -(cid:2)2.0 L ( 0 -(cid:2)55 -(cid:2)25 0 25 50 75 100 125 O 0 2.0 4.0 6.0 8.0 V TA, AMBIENT TEMPERATURE (°C) Isink, OUTPUT SINK CURRENT (mA) Figure 12. Output Switch Negative Emitter Figure 13. Low Voltage Indicator Output Sink Voltage vs. Temperature Saturation Voltage vs. Sink Current http://onsemi.com 6

NCP3163, NCV3163 V) 254 1.6 TAGE (m VCC = 15 V μNT ( A) 1.4 VVCIpCk (=S e1n5se V) = 15 V OL 252 RE V R D U ESHOL 250 BIAS C 1.2 R T H U 1.0 T P , nse) 248 IN,e) k Se Sens0.8 Vth (Ip 246 IIB (0.6 -(cid:2)55 -(cid:2)25 0 25 50 75 100 125 -(cid:2)55 -(cid:2)25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 14. Current Limit Comparator Threshold Figure 15. Current Limit Comparator Input Bias Voltage vs. Temperature Current vs. Temperature 8.0 7.2 VCC = 15 V A) A) Pins 7, 8, 16 = VCC T (m 6.0 T (m 6.4 PRienms a4i,n 6in, g1 4P i=n sG ONpDen N N E E R R R R U U C 4.0 C 5.6 Y Y L L P P P P SU Pins 7, 8, 16 = VCC SU , C 2.0 Pins 4, 6, 14 = GND , C4.8 C C I Remaining Pins Open I TA = 25°C 0 4.0 0 10 20 30 40 -(cid:2)55 -(cid:2)25 0 25 50 75 100 125 VCC, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C) Figure 16. Standby Supply Current Figure 17. Standby Supply Current vs. Supply Voltage vs. Temperature GE (V) 3.0 CT = 620 pF TA Pins 7,8 = VCC OL 2.6 Pins 4, 14 = GND LY V PPiinn 190 = = 1 1.00 0k(cid:3) (cid:3) t oto 1 155 V V P Pin 16 Open UP 2.2 S G N ATI 1.8 ER Pin 16 = VCC P O M 1.4 U M NI MI , n)1.-0(cid:2)55 -(cid:2)25 0 25 50 75 100 125 mi C( TA, AMBIENT TEMPERATURE (°C) C V Figure 18. Minimum Operating Supply Voltage vs. Temperature http://onsemi.com 7

NCP3163, NCV3163 INTRODUCTION The NCP3163 is a monolithic power switching regulator oscillator cycle, a partial cycle plus a complete cycle, optimized for DC−to−DC converter applications. The multiple cycles, or a partial cycle plus multiple cycles. combination of its features enables the system designer to directly implement step−up, step−down, and voltage− Oscillator The oscillator frequency and on−time of the output switch inverting converters with a minimum number of external are programmed by the value selected for timing capacitor components. Potential applications include cost sensitive C . Capacitor C is charged and discharged by a 9 to 1 ratio consumer products as well as equipment for the automotive, T T internal current source and sink, generating a negative going computer, and industrial markets. A representative block sawtooth waveform at Pin 6. As C charges, an internal diagram is shown in Figure 2. T pulse is generated at the oscillator output. This pulse is connected to the NOR gate center input, preventing output OPERATING DESCRIPTION switch conduction, and to the AND gate upper input, The NCP3163 operates as a fixed on−time, variable allowing the latch to be reset if the comparator output is low. off−time voltage mode ripple regulator. In general, this Thus, the output switch is always disabled during ramp−up mode of operation is somewhat analogous to a capacitor and can be enabled by the comparator output only at the start charge pump and does not require dominant pole loop of ramp−down. The oscillator peak and valley thresholds are compensation for converter stability. The Typical Operating 1.25V and 0.55 V, respectively, with a charge current of Waveforms are shown in Figure 19. The output voltage 225 (cid:4)A and a discharge current of 25 (cid:4)A, yielding a waveform shown is for a step−down converter with the maximum on−time duty cycle of 90%. A reduction of the ripple and phasing exaggerated for clarity. During initial maximum duty cycle may be required for specific converter converter startup, the feedback comparator senses that the configurations. This can be accomplished with the addition output voltage level is below nominal. This causes the of an external deadtime resistor (R ) placed across C . The DT T output switch to turn on and off at a frequency and duty cycle resistor increases the discharge current which reduces the controlled by the oscillator, thus pumping up the output filter on−time of the output switch. The converter output can be capacitor. When the output voltage level reaches nominal, inhibited by clamping C to ground with an external NPN T the feedback comparator sets the latch, immediately small−signal transistor. To calculate the frequency when terminating switch conduction. The feedback comparator only C is connected to Pin 6, use the equations found in T will inhibit the switch until the load current causes the output Figure 22. When R is also used, the frequency and T voltage to fall below nominal. Under these conditions, maximum duty cycle can be calculated with the NCP3163 output switch conduction can be inhibited for a partial design tool found at www.onsemi.com. 1 Comparator Output 0 1.25 V Timing Capacitor CT 0.55 V t 9t 1 Oscillator Output 0 On Output Switch Off Nominal Output Voltage Level Output Voltage Startup Quiescent Operation Figure 19. Typical Operating Waveforms http://onsemi.com 8

NCP3163, NCV3163 Feedback and Low Voltage Indicator Comparators output state is controlled by the highest voltage applied to Output voltage control is established by the Feedback either of the two noninverting inputs. comparator. The inverting input is internally biased at 1.25 V The Low Voltage Indicator (LVI) comparator is designed and is not pinned out. The converter output voltage is for use as a reset controller in microprocessor−based typically divided down with two external resistors and systems. The inverting input is internally biased at 1.125 V, monitored by the high impedance noninverting input at Pin 2. which sets the noninverting input thresholds to 90% of The maximum input bias current is ±0.4 (cid:4)A, which can cause nominal. The LVI comparator has 15 mV of hysteresis to an output voltage error that is equal to the product of the input prevent erratic reset operation. The Open Collector output is bias current and the upper divider resistance value. For capable of sinking in excess of 6.0 mA (see Figure 13). An applications that require 5.0 V, the converter output can be external resistor (RLVI) and capacitor (CDLY) can be used to directly connected to the noninverting input at Pin 3. The high program a reset delay time (tDLY) by the formula shown impedance input, Pin 2, must be grounded to prevent noise below, where V is the microprocessor reset input th(MPU) pickup. The internal resistor divider is set for a nominal threshold. Refer to Figure 20. (cid:3) (cid:2) voltage of 5.05 V. The additional 50 mV compensates for a 1 1.0% voltage drop in the cable and connector from the V converter output to the load. The Feedback comparator’s tDLY = RLVI ⋅ CDLY ⋅ In 1 − th(MPU) V out 3 14 + Feedback 2 + Comparator 15 - RLVI + 1.25 V Low Voltage 1 + 16 Indicator Output - CDLY LVI 1.125 V L Vout (Bottom View) CO Figure 20. Partial Application Schematic Showing Implementation of LVI Delay with R and C LVI DLY Current Limit Comparator, Latch and Thermal 200 ns. The parasitic inductance associated with R and the SC Shutdown circuit layout should be minimized. This will prevent With a voltage mode ripple converter operating under unwanted voltage spikes that may falsely trip the Current normal conditions, output switch conduction is initiated by Limit comparator. the oscillator and terminated by the Voltage Feedback Internal thermal shutdown circuitry is provided to protect comparator. Abnormal operating conditions occur when the the IC in the event that the maximum junction temperature converter output is overloaded or when feedback voltage is exceeded. When activated, typically at 170°C, the Latch sensing is lost. Under these conditions, the Current Limit is forced into the “Set” state, disabling the Output Switch. comparator will protect the Output Switch. This feature is provided to prevent catastrophic failures from The switch current is converted to a voltage by inserting accidental device overheating. It is not intended to be used a fractional ohm resistor, RSC, in series with VCC and output as a replacement for proper heatsinking. switch transistor Q . The voltage drop across R is 2 SC monitored by the Current Sense comparator. If the voltage Driver and Output Switch drop exceeds 250 mV with respect to V , the comparator To aid in system design flexibility and conversion CC will set the latch and terminate output switch conduction on efficiency, the driver current source and collector, and a cycle−by−cycle basis. This Comparator/Latch output switch collector and emitter are pinned out configuration ensures that the Output Switch has only a separately. This allows the designer the option of driving the single on−time during a given oscillator cycle. The output switch into saturation with a selected force gain or calculation for a value of R is: driving it near saturation when connected as a Darlington. SC The output switch has a typical current gain of 70 at 2.5 A 0.25V RSC(cid:4) and is designed to switch a maximum of 40 V collector to Ipk(Switch) emitter, with up to 3.4 A peak collector current. The Figures 14 and 15 show that the Current Sense comparator minimum value for R is: SC threshold is tightly controlled over temperature and has a 0.25V typical input bias current of 1.0 (cid:4)A. The propagation delay RSC(min)(cid:4) (cid:4)0.0735(cid:3) 3.4A from the comparator input to the Output Switch is typically http://onsemi.com 9

NCP3163, NCV3163 When configured for step−down or voltage−inverting low ESR capacitors. The equation below is used to calculate applications (see application notes at the end of this a minimum value bootstrap capacitor based on a minimum document) the inductor will forward bias the output rectifier zener voltage and an upper limit current source. when the switch turns off. Rectifiers with a high forward voltage drop or long turn−on delay time should not be used. CB(min)(cid:4)I (cid:5)(cid:5)Vt (cid:4)4.0mA4t.o0nV(cid:4)0.001ton If the emitter is allowed to go sufficiently negative, collector Parametric operation of the NCP3163 is guaranteed over current will flow, causing additional device heating and a supply voltage range of 2.5 V to 40 V. When operating reduced conversion efficiency. below 3.0 V, the Bootstrap Input should be connected to Figure 12 shows that by clamping the emitter to 0.5 V, the V . Figure 18 shows that functional operation down to collector current will be in the range 10 (cid:4)A over CC 1.7V at room temperature is possible. temperature. A 1N5822 or equivalent Schottky barrier rectifier is recommended to fulfill these requirements. Package A bootstrap input is provided to reduce the output switch The NCP3163 is contained in a heatsinkable 16−lead saturation voltage in step−down and voltage−inverting plastic package in which the die is mounted on a special heat converter applications. This input is connected through a tab copper alloy pad. This pad is designed to be soldered series resistor and capacitor to the switch emitter and is used directly to a GND connection on the printed circuit board to to raise the internal 2.0 mA bias current source above VCC. improve thermal conduction. Since this pad directly An internal zener limits the bootstrap input voltage to VCC contacts the substrate of the die, it is important that this pad +7.0 V. The capacitor’s equivalent series resistance must be always soldered to GND, even if surface mount heat limit the zener current to less than 100 mA. An additional sinking is not being used. Figure 21 shows recommended series resistor may be required when using tantalum or other layout techniques for this package. Vias to 2nd Layer Metal for Maximum Heat Sinking Exposed Pad 0.175 0.188 Minimum Recommended Exposed Copper 0.145 Flare Metal for Maximum Heat Sinking Figure 21. Layout Guidelines to Obtain Maximum Package Power Dissipation APPLICATIONS Figures 23 through 30 show the simplicity and flexibility equations for the key parameters. Additionally, a complete of the NCP3163. Three main converter topologies are application design aid for the NCP3163 can be found at demonstrated with actual test data shown below each of the www.onsemi.com. circuit diagrams. Figure 22 gives the relevant design http://onsemi.com 10

NCP3163, NCV3163 Calculation Step−Down Step−Up Voltage−Inverting (See Notteosn 1,2,3) Vout (cid:5) VF Vout (cid:5) VF Vin |Vout| (cid:5) VF toff Vin (cid:6) Vsat (cid:6) Vout Vin Vsat Vin (cid:6) Vsat ton ton ton t t t (cid:3) off (cid:2) (cid:3) off (cid:2) (cid:3) off (cid:2) ton ƒ ton (cid:5) 1 ƒ ton (cid:5) 1 ƒ ton (cid:5) 1 t t t off off off CT 32.143·10(cid:6)6(cid:6)20(cid:7)10(cid:6)12 32.143·10(cid:6)6(cid:6)20(cid:7)10(cid:6)12 32.143·10(cid:6)6(cid:6)20(cid:7)10(cid:6)12 f f f (cid:3) (cid:2) (cid:3) (cid:2) IL(avg) Iout Iout tton (cid:5) 1 Iout tton (cid:5) 1 off off (cid:5)I (cid:5)I (cid:5)I Ipk(Switch) IL(avg) (cid:5) L IL(avg) (cid:5) L IL(avg) (cid:5) L 2 2 2 0.25 0.25 0.25 RSC Ipk(Switch) Ipk(Switch) Ipk(Switch) (cid:3) (cid:2) (cid:3) (cid:2) (cid:3) (cid:2) V (cid:6) V (cid:6) V V (cid:6) V V (cid:6) V in sat out in sat in sat L (cid:5)I ton (cid:5)I ton (cid:5)I ton L L L (cid:3) (cid:2) Vripple(pp) (cid:5)IL 8ƒ1CO 2 (cid:5) (ESR)2 (cid:8) tonCOIout (cid:8) tonCOIout (cid:3) (cid:2) (cid:3) (cid:2) (cid:3) (cid:2) R R R Vout Vref R2 (cid:5) 1 Vref R2 (cid:5) 1 Vref R2 (cid:5) 1 1 1 1 The following Converter Characteristics must be chosen: Vin −Nominal operating input voltage. Vout −Desired output voltage. Iout −Desired output current. (cid:5)IL −Desired peak−to−peak inductor ripple current. For maximum output current it is suggested that (cid:5)IL be chosen to be less than 10% of the average inductor current IL(avg). This will help prevent Ipk (Switch) from reaching the current limit threshold set by RSC. If the design goal is to use a minimum inductance value, let (cid:5)IL = 2(IL(avg)). This will proportionally reduce converter output current capability. (cid:3) −Maximum output switch frequency. Vripple(pp) −Desired peak−to−peak output ripple voltage. For best performance the ripple voltage should be kept to a low value since it will directly affect line and load regulation. Capacitor CO should be a low equivalent series resistance (ESR) electrolytic designed for switching regulator applications. NOTES: 1. Vsat − Saturation voltage of the output switch, refer to Figures 10 and 11. NOTES: 2. VF − Output rectifier forward voltage drop. Typical value for 1N5822 Schottky barrier rectifier is 0.5 V. NOTES: 3. The calculated ton/toff must not exceed the minimum guaranteed oscillator charge to discharge ratio of 8, at the minimum NOTES: 3. operating input voltage. Figure 22. Design Equations http://onsemi.com 11

NCP3163, NCV3163 Current 0.25 V 8 - Limit 9 + RSC Vin Cin 7 VCC 10 6 Oscillator Q1 11 RT CT R Q2 5 Q 12 Thermal S 60 Latch 4 13 VCC 3 14 45 k R1 + Feedback 2 +- Comparator 15 D + 1.25 V 15 k 2.0 mA R2 1 + 16 - 7.0 V LVI 1.125 V VCC CB RB L Vout (Bottom View) CO Figure 23. Typical Buck Application Schematic Value of Components Name Value Name Value L 47 (cid:4)H R1 15 k(cid:3) D 2 A, 40 V Schottky Rectifier R2 24.9 k(cid:3) Cin 47 (cid:4)F, 35 V Rsc 80 m(cid:3), 1 W Cout 100 (cid:4)F, 10 V Cb 4.7 nF Ct 270 pF ±10% Rb 200 (cid:3) Rt 15 k(cid:3) Test Results for V = 3.3 V out Test Condition Results Line Regulation Vin = 8.0 V to 24 V, Iout = 2.5 A 13 mV Load Regulation Vin = 12 V, Iout = 0 to 2.5 A 25 mV Output Ripple Vin = 12 V, Iout = 0 to 2.5 A 100 mVpp Efficiency Vin = 12 V, Iout = 2.5 A 70.3% Short Circuit Current Vin = 12 V, RL = 0.1 (cid:3) 3.1 A Test Results for V = 5.05 V out Test Condition Results Line Regulation Vin = 10.2 V to 24 V, Iout = 2.5 A 54 mV Load Regulation Vin = 12 V, Iout = 0 to 2.5 A 28 mV Output Ripple Vin = 12 V, Iout = 0 to 2.5 A 150 mVpp Efficiency Vin = 12 V, Iout = 2.5 A 75.5% Short Circuit Current Vin = 12 V, RL = 0.1 (cid:3) 3.1 A http://onsemi.com 12

NCP3163, NCV3163 Figure 24. Buck Layout APPLICATION SPECIFIC CHARACTERISTICS 85 5.0 V Eff 80 %) 75 Y ( 3.3 V Eff C 70 N E CI 65 FI F E 60 55 50 0 0.5 1.0 1.5 2.0 2.5 Iout (A) Figure 25. Efficiency vs. Output Current for the Buck Demo Board at V = 12 V, T = 25(cid:2)C in A http://onsemi.com 13

NCP3163, NCV3163 Current L 0.25 V 8 - Limit 9 + RSC Vin + 7 10 Cin VCC 6 Oscillator Q1 11 RT CT R Q2 5 Q 12 Thermal S 60 Latch 4 13 VCC D 3 14 45 k 2 ++ Feedback 15 - Comparator + 1.25 V 15 k 2.0 mA 1 + 16 - 7.0 V LVI 1.125 V VCC + Vout R2 R1 (Bottom View) CO Figure 26. Typical Boost Application Schematic Value of Components for V = 24 V out Name Value Name Value L 33 (cid:4)H R1 42.2 k(cid:3) D 2 A, 40 V Schottky Rectifier R2 2.32 k(cid:3) Cin 330 (cid:4)F, 35 V Cout 330 (cid:4)F, 25 V Ct 270 pF ±10% Rsc 80 m(cid:3), 1 W Rt 15 k(cid:3) Test Results for V = 24 V out Test Condition Results Line Regulation Vin = 10 V to 20 V, Iout = 700 mA 90 mV Load Regulation Vin = 12 V, Iout = 0 to 700 mA 80 mV Output Ripple Vin = 12 V, Iout = 0 to 700 mA 300 mVpp Efficiency Vin = 12 V, Iout = 700 mA 83% Short Circuit Current Vin = 12 V, RL = 0.1 (cid:3) 3.1 A http://onsemi.com 14

NCP3163, NCV3163 Figure 27. Boost Demo Board Layout 86 84 %) 82 Y ( C N 80 E CI FI F 78 E 76 74 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Iout (A) Figure 28. Efficiency vs. Output Current for the Boost Demo Board at V = 12 V, T = 25(cid:2)C in A http://onsemi.com 15

NCP3163, NCV3163 Current 0.25 V 8 - Limit 9 RSC + Vin Cin + 7 VCC 10 6 Oscillator Q1 11 RT CT R Q2 5 Q 12 Thermal S 60 Latch 4 13 VCC 3 14 L 45 k 2 ++ Feedback 15 - Comparator RB + 1.25 V 15 k 2.0 mA CB 1 + 16 - 7.0 V LVI 1.125 V VCC D Vout R2 R1 (Bottom View) +CO Figure 29. Typical Voltage Inverting Application Schematic Value of Components for V = −15 V out Name Value Name Value L 47 (cid:4)H R1 1.07 k(cid:3) D 2 A, 40 V Schottky Rectifier R2 11.8 k(cid:3) Cin 270 (cid:4)F, 16 V Rsc 80 m(cid:3), 1 W Cout 2 X 270 (cid:4)F, 16 V Cb 4.7 nF Ct 150 pF ±10% Rb 200 (cid:3) Test Results for V = −15 V out Test Condition Results Line Regulation Vin = 7.0 V to 16 V, Iout = 500 mA 35 mV Load Regulation Vin = 12 V, Iout = 0 to 500 mA 20 mV Output Ripple Vin = 12 V, Iout = 0 to 500 mA 100 mVpp Efficiency Vin = 12 V, Iout = 500 mA 68% Short Circuit Current Vin = 12 V, RL = 0.1 (cid:3) 3.1 A http://onsemi.com 16

NCP3163, NCV3163 Figure 30. Voltage Inverting Demo Board Layout 70 66 %) Y ( 62 C N E CI 58 FI F E 54 50 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Iout (A) Figure 31. Efficiency vs. Output Current for the Voltage Inverting Demo Board at V = 12 V, T = 25(cid:2)C in A http://onsemi.com 17

NCP3163, NCV3163 ORDERING INFORMATION Device Package Shipping† NCP3163PWG SOIC−16 W Exposed Pad 47 Units / Rail (Pb−Free) NCP3163PWR2G SOIC−16 W Exposed Pad 1000 / Tape & Reel (Pb−Free) NCP3163BPWG SOIC−16 W Exposed Pad 47 Units / Rail (Pb−Free) NCP3163BPWR2G SOIC−16 W Exposed Pad 1000 / Tape & Reel (Pb−Free) NCP3163MNR2G DFN18 2500 / Tape & Reel (Pb−Free) NCP3163BMNR2G DFN18 2500 / Tape & Reel (Pb−Free) NCV3163PWG SOIC−16 W Exposed Pad 47 Units / Rail (Pb−Free) NCV3163PWR2G SOIC−16 W Exposed Pad 1000 / Tape & Reel (Pb−Free) NCV3163MNR2G DFN18 2500 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 18

NCP3163, NCV3163 PACKAGE DIMENSIONS SOIC 16 LEAD WIDE BODY, EXPOSED PAD PW SUFFIX CASE 751AG−01 ISSUE A −U− A M NOTES: 16 9 1. DIMENSIONING AND TOLERANCING PER ANSI P Y14.5M, 1982. B 2. CONTROLLING DIMENSION: MILLIMETER. 0.25 (0.010) M W M 1 R x 45(cid:4) 3. DIMENSION A AND B DO NOT INCLUDE MOLD 8 PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER −W− SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE PIN 1 I.D. G 14 PL 0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION DETAIL E AT MAXIMUM MATERIAL CONDITION. TOP SIDE 6. 751R-01 OBSOLETE, NEW STANDARD 751R-02. MILLIMETERS INCHES DIM MIN MAX MIN MAX C A 10.15 10.45 0.400 0.411 −T− F B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 0.10 (0.004) T D16 PL K SEATING D 0.35 0.49 0.014 0.019 PLANE F 0.50 0.90 0.020 0.035 0.25 (0.010) M T U S W S J G 1.27 BSC 0.050 BSC H 3.45 3.66 0.136 0.144 J 0.25 0.32 0.010 0.012 DETAIL E H K 0.00 0.10 0.000 0.004 L 4.72 4.93 0.186 0.194 M 0 (cid:4) 7 (cid:4) 0 (cid:4) 7 (cid:4) P 10.05 10.55 0.395 0.415 1 8 R 0.25 0.75 0.010 0.029 EXPOSED PAD L SOLDERING FOOTPRINT* 16 9 0.350 Exposed 0.175 Pad BACK SIDE 0.050 C L 0.188 0.200 0.376 CL 0.074 0.024 0.150 DIMENSIONS: INCHES *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 19

NCP3163, NCV3163 PACKAGE DIMENSIONS DFN18 CASE 505−01 ISSUE D A NOTES: D 1. DIMENSIONS AND TOLERANCING PER B ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PIN 1 LOCATION PAD AS WELL AS THE TERMINALS. E MILLIMETERS 2X DIM MIN MAX 0.15 C A 0.80 1.00 A1 0.00 0.05 2X A3 0.20 REF 0.15 C TOP VIEW b 0.18 0.30 D 6.00 BSC D2 3.98 4.28 0.10 C (A3) E 5.00 BSC E2 2.98 3.28 18X A e 0.50 BSC K 0.20 −−− 0.08 C A1 L 0.45 0.65 C SIDE VIEW SEATING PLANE SOLDERING FOOTPRINT* D2 e 5.30 18X 18X L 0.75 1 9 1 0.50 E2 PITCH 18X K 4.19 18 10 18X b 0.10 C A B BOTTOM VIEW 18X 0.05 C NOTE 3 0.30 3.24 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5773−3850 Sales Representative http://onsemi.com NCP3163/D 20

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: NCP3163BPWG NCP3163BPWR2G NCP3163PWG NCP3163PWR2G NCV3163PWR2G NCP3163BMNR2G NCV3163MNR2G