NCP3020A, NCP3020B, NCV3020A, NCV3020B Synchronous PWM Controller The NCP3020 is a PWM device designed to operate from a wide input range and is capable of producing an output voltage as low as 0.6 V. The NCP3020 provides integrated gate drivers and an internally set 300 kHz (NCP3020A) or 600 kHz (NCP3020B) oscillator. The www.onsemi.com NCP3020 also has an externally compensated transconductance error amplifier with an internally fixed soft−start. Protection features 8 include lossless current limit and short circuit protection, output overvoltage protection, output undervoltage protection, and input 1 undervoltage lockout. The NCP3020 is currently available in a SOIC−8 NB SOIC−8 package. CASE 751 Features • Input Voltage Range from 4.7 V to 28 V MARKING DIAGRAM • 300 kHz Operation (NCP3020B – 600 kHz) 8 • 3020x 0.6 V Internal Reference Voltage ALYW • Internally Programmed 6.8 ms Soft−Start (NCP3020B – 4.4 ms) (cid:2) • Current Limit and Short Circuit Protection 1 • Transconductance Amplifier with External Compensation 3020x = Specific Device Code • x = A or B Input Undervoltage Lockout A = Assembly Location • Output Overvoltage and Undervoltage Detection L = Wafer Lot • Y = Year NCV Prefix for Automotive and Other Applications Requiring Site W = Work Week and Change Controls (cid:2) = Pb−Free Package • This is a Pb−Free Device PIN CONNECTIONS VIN CIN VCC BST COMP HSDR CBST FB VSW VCC BST GND LSDR Q1 HSDR COMP L0 Vout ORDERING INFORMATION VSW Device Package Shipping† RC CC1 Q2 RFB1 NCP3020ADR2G SOIC−8 2500 / Tape & Reel FB LSDR C0 (Pb−Free) CC2 GND RFB2 RISET NCP3020BDR2G SOIC−8 2500 / Tape & Reel (Pb−Free) NCV3020ADR2G SOIC−8 2500 / Tape & Reel (Pb−Free) Figure 1. Typical Application Circuit NCV3020BDR2G SOIC−8 2500 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2013 1 Publication Order Number: December, 2018 − Rev. 7 NCP3020/D

NCP3020A, NCP3020B, NCV3020A, NCV3020B VCC INTERNAL BIAS POR/STARTUP BST VC THERMAL SD BOOST CLAMP LEVEL HSDR CLK/ SHIFT DMAX/ OSCILLATOR SOFT START VCC VSW RAMP GATE CURRENT SAMPLE & DRIVE LIMIT HOLD 1.5 V LOGIC ISET + VC COMP − REF PWM LSDR COMP OTA FB + − OOV BST_CHRG OUV + GND − Figure 2. NCP3020 Block Diagram PIN FUNCTION DESCRIPTION Pin Pin Name Description 1 VCC The VCC pin is the main voltage supply input. It is also used in conjunction with the VSW pin to sense current in the high side MOSFET. 2 COMP The COMP pin connects to the output of the Operational Transconductance Amplifier (OTA) and the positive terminal of the PWM comparator. This pin is used in conjunction with the FB pin to compensate the voltage mode control feedback loop. 3 FB The FB pin is connected to the inverting input of the OTA. This pin is used in conjunction with the COMP pin to compensate the voltage mode control feedback loop. 4 GND Ground Pin 5 LSDR The LSDR pin is connected to the output of the low side driver which connects to the gate of the low side N−FET. It is also used to set the threshold of the current limit circuit (ISET) by connecting a resistor from LSDR to GND. 6 VSW The VSW pin is the return path for the high side driver. It is also used in conjunction with the VCC pin to sense current in the high side MOSFET. 7 HSDR The HSDR pin is connected to the output of the high side driver which connects to the gate of the high side N−FET. 8 BST The BST pin is the supply rail for the gate drivers. A capacitor must be connected between this pin and the VSW pin. www.onsemi.com 2

NCP3020A, NCP3020B, NCV3020A, NCV3020B ABSOLUTE MAXIMUM RATINGS (measured vs. GND pin 8, unless otherwise noted) Rating Symbol VMAX VMIN Unit High Side Drive Boost Pin BST 45 −0.3 V Boost to VSW differential voltage BST−VSW 13.2 −0.3 V COMP COMP 5.5 −0.3 V Feedback FB 5.5 −0.3 V High−Side Driver Output HSDR 40 −0.3 V Low−Side Driver Output LSDR 13.2 −0.3 V Main Supply Voltage Input VCC 40 −0.3 V Switch Node Voltage VSW 40 −0.6 V Maximum Average Current Imax mA VCC, BST, HSDRV, LSDRV, VSW, GND 130 Operating Junction Temperature Range (Note 1) TJ −40 to +140 °C Maximum Junction Temperature TJ(MAX) +150 °C Storage Temperature Range Tstg −55 to +150 °C Thermal Characteristics (Note 2) SOIC−8 Plastic Package Thermal Resistance Junction−to−Air R(cid:2)JA 165 °C/W Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free RF 260 Peak °C (Note 3) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The maximum package power dissipation limit must not be exceeded. T (cid:3)T J(max) A P (cid:2) D R(cid:2)JA 2. When mounted on minimum recommended FR−4 or G−10 board 3. 60−180 seconds minimum above 237°C. www.onsemi.com 3

NCP3020A, NCP3020B, NCV3020A, NCV3020B ELECTRICAL CHARACTERISTICS (−40°C < TJ < +125°C, VCC = 12 V, for min/max values unless otherwise noted) Characteristic Conditions Min Typ Max Unit Input Voltage Range − 4.7 28 V SUPPLY CURRENT VCC Supply Current NCP3020A VFB = 0.55 V, Switching, VCC = 4.7 V − 5.5 8.0 mA VFB = 0.55 V, Switching, VCC = 28 V − 7.0 11 mA VCC Supply Current NCP3020B VFB = 0.55 V, Switching, VCC = 4.7 V − 5.9 10 mA VFB = 0.55 V, Switching, VCC = 28 V − 7.8 13 mA UNDER VOLTAGE LOCKOUT UVLO Rising Threshold VCC Rising Edge 4.0 4.3 4.7 V UVLO Falling Threshold VCC Falling Edge 3.5 3.9 4.3 V OSCILLATOR Oscillator Frequency NCP3020A TJ = +25°C, 4.7 V (cid:4) VCC (cid:4) 28 V 250 300 350 kHz TJ = −40°C to +125°C, 4.7 V (cid:4) VCC (cid:4) 28 V 240 300 360 kHz Oscillator Frequency NCP3020B TJ = +25°C, 4.7 V (cid:4) VCC (cid:4) 28 V 550 600 650 kHz TJ = −40°C to +125°C, 4.7 V (cid:4) VCC (cid:4) 28 V 530 600 670 kHz Ramp−Amplitude Voltage Vpeak − Valley (Note 4) − 1.5 − V Ramp Valley Voltage 0.46 0.70 0.88 V PWM Minimum Duty Cycle (Note 4) − 7.0 − % Maximum Duty Cycle NCP3020A 80 84 − % NCP3020B 75 80 − Soft Start Ramp Time NCP3020A VFB = VCOMP − 6.8 − ms NCP3020B − 4.4 − ERROR AMPLIFIER (GM) Transconductance 0.9 1.4 1.9 mS Open Loop dc Gain (Notes 4 and 6) − 70 − dB Output Source Current VFB = 545 mV 45 75 100 (cid:3)A Output Sink Current VFB = 655 mV 45 75 100 (cid:3)A FB Input Bias Current − 0.5 500 nA Feedback Voltage TJ = 25°C 0.591 0.6 0.609 V 4.7 V < VCC < VIN < 28 V, −40°C < TJ < +125°C 0.588 0.6 0.612 V COMP High Voltage VFB = 0.55 V 4.0 4.4 5.0 V COMP Low Voltage VFB = 0.65 V − 72 250 mV OUTPUT VOLTAGE FAULTS Feedback OOV Threshold 0.66 0.75 0.84 V Feedback OUV Threshold 0.42 0.45 0.48 V OVERCURRENT ISET Source Current 7.0 13 18 (cid:3)A Current Limit Set Voltage (Note 5) TJ = 25°C, RSET = 22.5 k(cid:4) 140 240 360 mV 4. Guaranteed by design. 5. The voltage sensed across the high side MOSFET during conduction. 6. This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal Ro of > 10 M(cid:4). 7. This is not a protection feature. www.onsemi.com 4

NCP3020A, NCP3020B, NCV3020A, NCV3020B ELECTRICAL CHARACTERISTICS (−40°C < TJ < +125°C, VCC = 12 V, for min/max values unless otherwise noted) Characteristic Conditions Min Typ Max Unit GATE DRIVERS AND BOOST CLAMP HSDRV Pullup Resistance TJ = 25°C, VCC = 8 V, VBST = 7.5 V, VSW = GND 5.0 11 20 (cid:4) 100 mA out of HSDR pin HSDRV Pulldown Resistance TJ = 25°C, VCC = 8 V, VBST = 7.5 V, VSW = GND 2.0 5.0 11.5 (cid:4) 100 mA into HSDR pin LSDRV Pullup Resistance TJ = 25°C, VCC = 8 V, VBST = 7.5 V, VSW = GND 5.0 9.0 16 (cid:4) 100 mA out of LSDR pin LSDRV Pulldown Resistance TJ = 25°C, VCC = 8 V, VBST = 7.5 V, VSW = GND 1.0 3.0 6.0 (cid:4) 100 mA into LSDR pin HSDRV Falling to LSDRV Rising De- VIN = 12 V, VSW = GND, VCOMP = 1.3 V 50 80 110 ns lay LSDRV Falling to HSDRV Rising De- VIN = 12 V, VSW = GND, VCOMP = 1.3 V 60 80 120 ns lay Boost Clamp Voltage VIN = 12 V, VSW = GND, VCOMP = 1.3 V 5.5 7.5 9.6 V THERMAL SHUTDOWN Thermal Shutdown (Notes 4 and 7) − 165 − °C Hysteresis (Notes 4 and 7) − 20 − °C 4. Guaranteed by design. 5. The voltage sensed across the high side MOSFET during conduction. 6. This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal Ro of > 10 M(cid:4). 7. This is not a protection feature. www.onsemi.com 5

NCP3020A, NCP3020B, NCV3020A, NCV3020B TYPICAL PERFORMANCE CHARACTERISTICS 95 3.28 9 V 90 3.275 15 V 18 V 18 V 85 %) 12 V 15 V 3.27 CY ( 80 V) 9 V EN (ut3.265 CI 75 Vo FI EF 70 3.26 12 V 65 Typical Application Circuit 3.255 Typical Application Circuit Figure 37 Figure 37 60 3.25 0 2 4 6 8 10 0 2 4 6 8 10 Iout (A) Iout (A) Figure 3. Efficiency vs. Output Current and Input Figure 4. Load Regulation vs. Input Voltage Voltage Input = 9 V, Output = 3.3 V, Load = 10 A Input = 18 V, Output = 3.3 V, Load = 10 A C4 (Green) = VIN, C2 (Red) = VOUT C4 (Green) = VIN, C2 (Red) = VOUT C1 (Yellow) = VSW, C3 (Blue) = HSDR C1 (Yellow) = VSW, C3 (Blue) = HSDR Figure 5. Switching Waveforms (V = 9 V) Figure 6. Switching Waveforms (V = 18 V) IN IN 606 340 330 NCP3020A 604 320 602 V) VCC = 12 V, 28 V z) 310 VCC = 12 V, 28 V m H (FB 600 (kW 300 V fS 290 VCC = 5 V 598 VCC = 5 V 280 596 270 594 260 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. Feedback Reference Voltage vs. Input Figure 8. Switching Frequency vs. Input Voltage Voltage and Temperature and Temperature (NCP3020A) www.onsemi.com 6

NCP3020A, NCP3020B, NCV3020A, NCV3020B TYPICAL PERFORMANCE CHARACTERISTICS 660 1.50 NCP3020B 1.45 640 1.40 1.35 VCC = 5 V 620 (kHz)W 600 VCC = 12 V, 28 V m (mS) 11..2350 VCC = 12 V, 28 V fS VCC = 5 V g 1.20 580 1.15 1.10 560 1.05 540 1.00 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 9. Switching Frequency vs. Input Voltage Figure 10. Transconductance vs. Input Voltage and Temperature (NCP3020B) and Temperature 4.4 800 760 4.3 V) UVLO Rising m 720 OOV, VCC = 5 − 28 V E ( 680 4.2 G A V) LT 640 O ( 4.1 VO 600 VL D U OL 560 4.0 H S 520 E 3.9 HR 480 OUV, VCC = 5 − 28 V UVLO Falling T 440 3.8 400 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. Input Undervoltage Lockout vs. Figure 12. Output Overvoltage and Undervoltage Temperature vs. Input Voltage and Temperature 7.5 9.0 7.0 8.5 VCC = 28 V A) 6.5 VCC = 28 V A) 8.0 m m G ( G ( 7.5 N 6.0 N HI VCC = 12 V HI 7.0 C C SWIT 5.5 VCC = 5 V SWIT 6.5 VCC = 4.7 V , CC 5.0 , CC 6.0 I I 4.5 5.5 NCP3020A NCP3020B 4.0 5.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. Supply Current vs. Input Voltage and Figure 14. Supply Current vs. Input Voltage and Temperature (NCP3020A) Temperature (NCP3020B) www.onsemi.com 7

NCP3020A, NCP3020B, NCV3020A, NCV3020B TYPICAL PERFORMANCE CHARACTERISTICS 1000 8.0 7.0 950 900 7.5 6.5 E (mV) 880500 (ms)art7.0 NCP3020A VCC = 5 V 6.0NCP30 EY VOLTAG 667705050000 VCC = 5 − 28 V 020A tSoft−St66..05 VCC = 12 V, 28 V 55..05Soft−Sta20B t ALL 550 CP3 NCP3020B rt (m V 500 N 5.5 VCC = 5 V 4.5s) 450 VCC = 12 V, 28 V 400 5.0 4.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Ramp Valley Voltage vs. Input Voltage Figure 16. Soft−Start Time vs. Input Voltage and and Temperature Temperature 14 13.8 (cid:3)A) 13.6 VCC = 12 V, 28 V (T E S13.4 I VCC = 5 V 13.2 13 −40 −25 −10 5 20 35 50 65 80 95 110 125 Input = 12 V, Output = 3.3 V, Load = 5 A TEMPERATURE (°C) CC12 ((YReeldlo)w =) H=S VDINR, ,C C43 ( G(Brleueen) )= = L VSODURT Figure 17. Current Limit Set Current vs. Figure 18. Soft−Start Waveforms Temperature Input = 12 V, Output = 3.3 V, Load = 5 A Input = 12 V C1 (Yellow) = VIN, C4 (Green) = VOUT C1 (Yellow) = FB, C3 (Blue) = LSDR C2 (Red) = HSDR, C3 (Blue) = LSDR C2 (Red) = HSDR, C4 (Green) = VIN Figure 19. Shutdown Waveforms Figure 20. Startup into a Current Limit www.onsemi.com 8

NCP3020A, NCP3020B, NCV3020A, NCV3020B DETAILED DESCRIPTION OVERVIEW and low−side MOSFET gate drives to prevent cross The NCP3020A/B operates as a 300/600 kHz, voltage conduction of the power MOSFET’s. mode, pulse width modulated, (PWM) synchronous buck converter. It drives high−side and low−side N−channel power POR and UVLO The device contains an internal Power On Reset (POR) and MOSFETs. The NCP3020 incorporates an internal boost input Undervoltage Lockout (UVLO) that inhibits the internal circuit consisting of a boost clamp and boost diode to provide supply voltage for the high side MOSFET gate driver. The logic and the output stage from operating until VCC reaches its NCP3020 also integrates several protection features including respective predefined voltage levels (4.3 V typical). input undervoltage lockout (UVLO), output undervoltage Startup and Shutdown (OUV), output overvoltage (OOV), adjustable high−side Once V crosses the UVLO rising threshold the device CC current limit (I and I ), and thermal shutdown (TSD). SET LIM begins its startup process. Closed−loop soft−start begins The operational transconductance amplifier (OTA) after a 400 (cid:3)s delay wherein the boost capacitor is charged, provides a high gain error signal from Vout which is and the current limit threshold is set. During the 400 (cid:3)s delay compared to the internal 1.5 V pk-pk ramp signal to set the the OTA output is set to just below the valley voltage of the duty cycle converter using the PWM comparator. The high internal ramp. This is done to reduce delays and to ensure a side switch is turned on by the positive edge of the clock consistent pre−soft−start condition. The device increases the cycle going into the PWM comparator and flip flop internal reference from 0 V to 0.6 V in 24 discrete steps following a non-overlap time. The high side switch is turned while maintaining closed loop regulation at each step. Each off when the PWM comparator output is tripped by the step contains 64 switching cycles. Some overshoot may be modulator ramp signal reaching a threshold level evident at the start of each step depending on the voltage established by the error amplifier. The gate driver stage loop phase margin and bandwidth. The total soft−start time incorporates fixed non− overlap time between the high−side is 6.8 ms for the NCP3020A and 4.4 ms for the NCP3020B. 25 mV Steps 0.6 V 24 Voltage Steps Internal Reference Voltage Internal Ramp OTA Output 0.7 V 0 V Figure 21. Soft−Start Details www.onsemi.com 9

NCP3020A, NCP3020B, NCV3020A, NCV3020B OOV and OUV the output is considered “undervoltage” and the device will The output voltage of the buck converter is monitored at initiate a restart. When the feedback pin voltage rises the feedback pin of the output power stage. Two between the reference voltages of comparator 1 and comparators are placed on the feedback node of the OTA to comparator 2 (0.45 < V < 0.75), then the output voltage FB monitor the operating window of the feedback voltage as is considered “Power Good.” Finally, if the feedback voltage shown in Figures 22 and 23. All comparator outputs are is greater than comparator 1 (V > 0.75 V), the output FB ignored during the soft−start sequence as soft−start is voltage is considered “overvoltage,” and the device will regulated by the OTA and false trips would be generated. latch off. To clear a latch fault, input voltage must be After the soft−start period has ended, if the feedback is recycled. Graphical representation of the OOV and OUV is below the reference voltage of comparator 2 (VFB < 0.45 V), shown in Figures 24 and 25. Soft Start Complete Vref*125% Comparator 1 Restart LOGIC FB Latch off Vref*75% Comparator 2 Vref = 0.6 V Figure 22. OOV and OUV Circuit Diagram Voov = Vref * 125% OOVP &Power Good=0 PowerNotgood High Hysteresis=5mV Power Good=1 Vref = 0.6 V Power Good=1 Hysteresis=5mV PowerNot GoodLow OUVP &Power Good =0 Vouv = Vref * 75% Figure 23. OOV and OUV Window Diagram www.onsemi.com 10

NCP3020A, NCP3020B, NCV3020A, NCV3020B 0.75 V(vref*125%) 0.6 V (vref*100%) 0.45 V(vref*75%) FB Voltage Latch off Reinitiate Softstart Softstart Complete Figure 24. Powerup Sequence and Overvoltage Latch 0.75 V(vref*125%) 0.6 V(vref*100%) 0.45 V(vref*75%) FB Voltage Latch off Reinitiate Softstart Softstart Complete Figure 25. Powerup Sequence and Undervoltage Soft−Start www.onsemi.com 11

NCP3020A, NCP3020B, NCV3020A, NCV3020B CURRENT LIMIT AND CURRENT LIMIT SET I block consists of a voltage comparator circuit which Limit compares the differential voltage across the V Pin and the CC Overview V Pin with a resistor settable voltage reference. The sense SW The NCP3020 uses the voltage drop across the High Side portion of the circuit is only active while the HS MOSFET MOSFET during the on time to sense inductor current. The is turned ON. VIN VCC VSense HSDR Ilim Out Itrip Ref VSW Switch Cap CONTROL Iset 13 uA LSDR 6 DAC/ Vset COUNTER RSet Itrip Ref−63 Steps, 6.51 mV/step Figure 26. I / I Block Diagram set Limit Current Limit Set prior to Soft−Start, the DAC counter increments the The ILimit comparator reference is set during the startup reference on the ISET comparator until it crosses the VSET sequence by forcing a typically 13 (cid:3)A current through the voltage and holds the DAC reference output to that count low side gate drive resistor. The gate drive output will rise value. This voltage is translated to the I comparator Limit to a voltage level shown in the equation below: during the I portion of the switching cycle through the Sense V (cid:2)I *R (eq. 1) switch cap circuit. See Figure 26. Exceeding the maximum set set set sense voltage results in no current limit. Steps 0 to 10 result Where I is 13 (cid:3)A and R is the gate to source resistor SET SET in an effective current limit of 0 mV. on the low side MOSFET. This resistor is normally installed to prevent MOSFET Current Sense Cycle leakage from causing unwanted turn on of the low side Figure 27 shows how the current is sampled as it relates MOSFET. In this case, the resistor is also used to set the to the switching cycle. Current level 1 in Figure 27 I trip level reference through the I DAC. The I represents a condition that will not cause a fault. Current Limit Limit set process takes approximately 350 (cid:3)s to complete prior to level 2 represents a condition that will cause a fault. The Soft−Start stepping. The scaled voltage level across the I sense circuit is allowed to operate below the 3/4 point of a SET resistor is converted to a 6 bit digital value and stored as the given switching cycle. A given switching cycle’s 3/4 Ton trip value. The binary ILimit value is scaled and converted to time is defined by the prior cycle’s Ton and is quantized in the analog I reference voltage through a DAC counter. 10 ns steps. A fault occurs if the sensed MOSFET voltage Limit The DAC has 63 steps in 6.51 mV increments equating to a exceeds the DAC reference within the 3/4 time window of maximum sense voltage of 403 mV. During the I period the switching cycle. set www.onsemi.com 12

NCP3020A, NCP3020B, NCV3020A, NCV3020B Trip: Vsense>Itrip Ref at 3/4 Point No Trip: Vsense<Itrip Ref at 3/4 Point Itrip Ref Vsense ¾ ¾ Current Level 1 Ton−2 Ton−1 3/4 Point Determined by Current Level 2 Prior Cycle 1/4 1/2 1/4 1/2 3/4 3/4 Ton−1 Ton Each switching cycle’s Ton is counted in 10 nS time steps. The 3/4 sample time value is held and used for the following cycle’s limit sample time Figure 27. I Trip Point Description Limit Soft−Start Current limit Boost Clamp Functionality During soft−start the I value is doubled to allow for The boost circuit requires an external capacitor connected SET inrush current to charge the output capacitance. The DAC between the BST and V pins to store charge for supplying SW reference is set back to its normal value after soft−start has the high and low−side gate driver voltage. This clamp circuit completed. limits the driver voltage to typically 7.5 V when V > 9 V, IN otherwise this internal regulator is in dropout and typically VSW Ringing VIN − 1.25 V. The I block can lose accuracy if there is excessive Limit The boost circuit regulates the gate driver output voltage V voltage ringing that extends beyond the 1/2 point of the SW and acts as a switching diode. A simplified diagram of the high−side transistor on−time. Proper snubber design and boost circuit is shown in Figure 28. While the switch node keeping the ratio of ripple current and load current in the is grounded, the sampling circuit samples the voltage at the 10−30% range can help alleviate this as well. boost pin, and regulates the boost capacitor voltage. The sampling circuit stores the boost voltage while the V is Current Limit SW high and the linear regulator output transistor is reversed A current limit trip results in completion of one switching biased. cycle and subsequently half of another cycle T to account on for negative inductor current that might have caused VIN negative potentials on the output. Subsequently the power MOSFETs are both turned off and a 4 soft−start time period 8.9V wait passes before another soft−start cycle is attempted. I vs Trip Point ave The average load trip current versus R value is shown Switch BST SET Sampling the equation below: Circuit (cid:6) (cid:7) I (cid:2)Iset(cid:5)Rset(cid:3)1 VIN(cid:3)VOUT(cid:5)VOUT(cid:5) 1 VSW AveTRIP R 4 L V F LSDR DS(on) IN SW (eq. 2) Where: L = Inductance (H) Figure 28. Boost Circuit I = 13 (cid:3)A SET R = Gate to Source Resistance ((cid:4)) SET R = On Resistance of the HS MOSFET ((cid:4)) DS(on) V = Input Voltage (V) IN V = Output Voltage (V) OUT F = Switching Frequency (Hz) SW www.onsemi.com 13

NCP3020A, NCP3020B, NCV3020A, NCV3020B Reduced sampling time occurs at high duty cycles where The boost ripple frequency is dependent on the output the low side MOSFET is off for the majority of the switching capacitance selected. The ripple voltage will not damage the period. Reduced sampling time causes errors in the device or (cid:8)12 V gate rated MOSFETs. regulated voltage on the boost pin. High duty cycle / input Conditions where maximum boost ripple voltage could voltage induced sampling errors can result in increased damage the device or (cid:8)12 V gate rated MOSFETs can be boost ripple voltage or higher than desired DC boost voltage. seen in Region 3 (Orange). Placing a boost capacitor that is Figure 29 outlines all operating regions. no greater than 10X the input capacitance of the high side The recommended operating conditions are shown in MOSFET on the boost pin limits the maximum boost Region 1 (Green) where a 0.1 (cid:3)F, 25 V ceramic capacitor voltage < 12 V. The typical drive waveforms for Regions 1, can be placed on the boost pin without causing damage to the 2 and 3 (green, yellow, and orange) regions of Figure 29 are device or MOSFETS. Larger boost ripple voltage occurring shown in Figure 30. over several switching cycles is shown in Region 2 (Yellow). Boost Voltage Levels Normal Operation Increased Boost Ripple Increased Boost Ripple (Still in Specification) Capacitor Optimization Required 28 26 Region3 24 22 22V e 20 g a 18 Region2 lt Maxi o 16 Region 1 Mmauxm V DDuutyty ut 14 CCyycclele p n 12 I 11.5V 10 8 71% 6 4 2 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 Duty Cycle Figure 29. Safe Operating Area for Boost Voltage with a 0.1 (cid:2)F Capacitor www.onsemi.com 14

NCP3020A, NCP3020B, NCV3020A, NCV3020B 7.5V VIN VBOOST 7.5V 0V Maximum Normal 7.5V VIN VBOOST 7.5V 0V Maximum Normal 7.5V VIN VBOOST 7.5V 0V Figure 30. Typical Waveforms for Region 1 (top), Region 2 (middle), and Region 3 (bottom) To illustrate, a 0.1 (cid:3)F boost capacitor operating at > 80% duty cycle and > 22.5 V input voltage will exceed the specifications for the driver supply voltage. See Figure 31. www.onsemi.com 15

NCP3020A, NCP3020B, NCV3020A, NCV3020B Boost Voltage 18 Voltage Ripple Maximum Allowable Voltage 16 Maximum Boost Voltage 14 12 V) e ( 10 g a Volt ost 8 o B 6 4 2 0 4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24.5 26.5 Input Voltage (V) Figure 31. Boost Voltage at 80% Duty Cycle Inductor Selection V (cid:10)V V When selecting the inductor, it is important to know the D(cid:2) OUT LSD (cid:11)D(cid:2) OUT V (cid:3)V (cid:10)V V input and output requirements. Some example conditions IN HSD LSD IN (eq. 5) are listed below to assist in the process. 3.3V (cid:12)27.5%(cid:2) 12V Table 1. DESIGN PARAMETERS The ratio of ripple current to maximum output current Design Parameter Example Value simplifies the equations used for inductor selection. The Input Voltage (VIN) 9 V to 18 V formula for this is given in Equation 6. Nominal Input Voltage (VIN) 12 V ra(cid:2) (cid:5)I (eq. 6) Output Voltage (VOUT) 3.3 V IOUT Input ripple voltage (VINRIPPLE) 300 mV The designer should employ a rule of thumb where the percentage of ripple current in the inductor lies between Output ripple voltage (VOUTRIPPLE) 50 mV 10% and 40%. When using ceramic output capacitors the Output current rating (IOUT) 10 A ripple current can be greater thus a user might select a higher Operating frequency (Fsw) 300 kHz ripple current, but when using electrolytic capacitors a lower ripple current will result in lower output ripple. Now, A buck converter produces input voltage (VIN) pulses that acceptable values of inductance for a design can be are LC filtered to produce a lower dc output voltage (VOUT). calculated using Equation 7. The output voltage can be changed by modifying the on time V relative to the switching period (T) or switching frequency. L(cid:2) OUT (cid:13)(1(cid:3)D)(cid:12)3.3(cid:3)H The ratio of high side switch on time to the switching period IOUT(cid:13)ra(cid:13)FSW (eq. 7) is called duty cycle (D). Duty cycle can also be calculated 3.3V using VOUT, VIN, the low side switch voltage drop VLSD, (cid:2) (cid:13)(1(cid:3)27.5%) and the High side switch voltage drop V . 10A(cid:13)24%(cid:13)300kHz HSD The relationship between ra and L for this design example 1 F(cid:2) (eq. 3) is shown in Figure 32. T T T D(cid:2) ON((cid:3)D(cid:9)(cid:2) OFF (eq. 4) T T www.onsemi.com 16

NCP3020A, NCP3020B, NCV3020A, NCV3020B 18 V (1(cid:3)D) 17 I (cid:2) OUT (eq. 11) 16 Vout = 3.3 V PP L (cid:13)F 15 18 V OUT SW 14 Ipp is the peak to peak current of the inductor. From this H)13 15 V (cid:3)CE (1112 edqeucraetiaosne si,t iesm cplehaars tihzaint gth eth reip ptrlaed ceu−roreffn t binectwreeaesne s days nLaOmUiTc AN190 12 V response and ripple current. T C 8 The power dissipation of an inductor consists of both U 7 D copper and core losses. The copper losses can be further N 6 L, I 45 9 V capatpergooxriimzeadti oinnt oo fd tch leo isnsdeus catnodr laocs sloess sceasn. Abe g mooadde f iurssitn ogr dtheer 3 2 DC resistance as they usually contribute to 90% of the losses 1 of the inductor shown below: 0 10% 15% 20% 25% 30% 35% 40% LP (cid:2)I 2(cid:13)DCR (eq. 12) CU RMS VIN, (V) The core losses and ac copper losses will depend on the Figure 32. Ripple Current Ratio vs. Inductance geometry of the selected core, core material, and wire used. To keep within the bounds of the parts maximum rating, Most vendors will provide the appropriate information to calculate the RMS current and peak current. make accurate calculations of the power dissipation then the (cid:14) total inductor losses can be capture buy the equation below: IRMS(cid:2)IOUT(cid:13) 1(cid:10)r1a22(cid:12)10.02A LPtot(cid:2)LPCU_DC(cid:10)LPCU_AC(cid:10)LPCore (eq. 13) (cid:14) (eq. 8) (0.24)2 (cid:2)10A(cid:13) 1(cid:10) Input Capacitor Selection 12 The input capacitor has to sustain the ripple current (cid:15) (cid:9) (cid:15) ra(cid:9) (0.24) produced during the on time of the upper MOSFET, so it IPK(cid:2)IOUT(cid:13) 1(cid:10) 2 (cid:12)11.2A(cid:2)10A(cid:13) 1(cid:10) 2 must have a low ESR to minimize the losses. The RMS value of this ripple is: (eq. 9) (cid:14) An inductor for this example would be around 3.3 (cid:3)H and Iin (cid:2)I (cid:13) D(cid:13)(1(cid:3)D) (eq. 14) RMS OUT should support an rms current of 10.02 A and a peak current D is the duty cycle, Iin is the input RMS current, and of 11.2 A. RMS I is the load current. The final selection of an output inductor has both OUT The equation reaches its maximum value with D = 0.5. mechanical and electrical considerations. From a Loss in the input capacitors can be calculated with the mechanical perspective, smaller inductor values generally following equation: correspond to smaller physical size. Since the inductor is often one of the largest components in the regulation system, (cid:15) (cid:9)2 a minimum inductor value is particularly important in PCIN(cid:2)ESRCIN(cid:13) IIN(cid:3)RMS (eq. 15) space−constrained applications. From an electrical PCIN is the power loss in the input capacitors and ESRCIN perspective, the maximum current slew rate through the is the effective series resistance of the input capacitance. output inductor for a buck regulator is given by Equation 10. Due to large dI/dt through the input capacitors, electrolytic or ceramics should be used. If a tantalum must be used, it SlewRate (cid:2)VIN(cid:3)VOUT(cid:12)2.6 A (cid:2)12V(cid:3)3.3V must by surge protected. Otherwise, capacitor failure could LOUT L (cid:3)s 3.3(cid:3)H occur. OUT (eq. 10) Input Start−up Current This equation implies that larger inductor values limit the To calculate the input startup current, the following regulator’s ability to slew current through the output equation can be used. inductor in response to output load transients. Consequently, C (cid:13)V output capacitors must supply the load current until the I (cid:2) OUT OUT (eq. 16) inductor current reaches the output load current level. This INRUSH t SS results in larger values of output capacitance to maintain I is the input current during startup, C is the total inrush OUT tight output voltage regulation. In contrast, smaller values of output capacitance, V is the desired output voltage, and OUT inductance increase the regulator’s maximum achievable t is the soft start interval. If the inrush current is higher than SS slew rate and decrease the necessary capacitance, at the the steady state input current during max load, then the input expense of higher ripple current. The peak−to−peak ripple fuse should be rated accordingly, if one is used. current for the NCP3020A is given by the following equation: www.onsemi.com 17

NCP3020A, NCP3020B, NCV3020A, NCV3020B Output Capacitor Selection In a typical converter design, the ESR of the output capacitor The important factors to consider when selecting an bank dominates the transient response. It should be noted output capacitor is dc voltage rating, ripple current rating, that (cid:5)VOUT−DISCHARGE and (cid:5)VOUT−ESR are out of output ripple voltage requirements, and transient response phase with each other, and the larger of these two voltages requirements. will determine the maximum deviation of the output voltage The output capacitor must be rated to handle the ripple (neglecting the effect of the ESL). current at full load with proper derating. The RMS ratings Conversely during a load release, the output voltage can given in datasheets are generally for lower switching increase as the energy stored in the inductor dumps into the frequency than used in switch mode power supplies but a output capacitor. The ESR contribution from Equation 18 multiplier is usually given for higher frequency operation. still applies in addition to the output capacitor charge which The RMS current for the output capacitor can be calculated is approximated by the following equation: below: (cid:15) (cid:9)2 I (cid:13)L CoRMS(cid:2)IO(cid:13)(cid:14)r1a2 (eq. 17) (cid:5)VOUT−CHG(cid:2) CTROAUNT(cid:13)VOOUUTT (eq. 23) The maximum allowable output voltage ripple is a Power MOSFET Selection combination of the ripple current selected, the output Power dissipation, package size, and the thermal capacitance selected, the equivalent series inductance (ESL) environment drive MOSFET selection. To adequately select and ESR. the correct MOSFETs, the design must first predict its power The main component of the ripple voltage is usually due dissipation. Once the dissipation is known, the thermal to the ESR of the output capacitor and the capacitance impedance can be calculated to prevent the specified selected. (cid:15) (cid:9) maximum junction temperatures from being exceeded at the 1 highest ambient temperature. V (cid:2)I (cid:13)ra(cid:13) ESR (cid:10) (eq. 18) ESR_C O Co 8(cid:13)F (cid:13)Co Power dissipation has two primary contributors: SW conduction losses and switching losses. The control or The ESL of capacitors depends on the technology chosen high−side MOSFET will display both switching and but tends to range from 1 nH to 20 nH where ceramic conduction losses. The synchronous or low−side MOSFET capacitors have the lowest inductance and electrolytic will exhibit only conduction losses because it switches into capacitors then to have the highest. The calculated nearly zero voltage. However, the body diode in the contributing voltage ripple from ESL is shown for the switch synchronous MOSFET will suffer diode losses during the on and switch off below: non−overlap time of the gate drivers. ESL(cid:13)I (cid:13)F V (cid:2) PP SW (eq. 19) Starting with the high−side or control MOSFET, the ESLON D power dissipation can be approximated from: V (cid:2)ESL(cid:13)IPP(cid:13)FSW (eq. 20) PD_CONTROL(cid:2)PCOND(cid:10)PSW_TOT (eq. 24) ESLOFF (1(cid:3)D) The first term is the conduction loss of the high−side The output capacitor is a basic component for the fast MOSFET while it is on. response of the power supply. In fact, during load transient, (cid:15) (cid:9)2 P (cid:2) I (cid:13)R (eq. 25) for the first few microseconds it supplies the current to the COND RMS_CONTROL DS(on)_CONTROL load. The controller immediately recognizes the load transient and sets the duty cycle to maximum, but the current Using the ra term from Equ(cid:14)ation 6, IRMS becomes: (cid:15) (cid:15) (cid:9)(cid:9) slope is limited by the inductor value. ra2 I (cid:2)I (cid:13) D(cid:13) 1(cid:10) (eq. 26) During a load step transient the output voltage initially RMS_CONTROL OUT 12 drops due to the current variation inside the capacitor and the The second term from Equation 24 is the total switching ESR (neglecting the effect of the effective series inductance loss and can be approximated from the following equations. (ESL)). (cid:5)V (cid:2)(cid:5)I (cid:13)ESR (eq. 21) PSW_TOT(cid:2)PSW(cid:10)PDS(cid:10)PRR (eq. 27) OUT−ESR TRAN Co A minimum capacitor value is required to sustain the The first term for total switching losses from Equation 27 current during the load transient without discharging it. The includes the losses associated with turning the control voltage drop due to output capacitor discharge is MOSFET on and off and the corresponding overlap in drain approximated by the following equation: voltage and current. (cid:15)I (cid:9)2(cid:13)L PSW(cid:2)PTON(cid:10)PTOFF (cid:5)VOUT−DISCHG(cid:2)C TR(cid:13)A(cid:15)NV (cid:3)OVUT (cid:9) (eq. 22) (cid:2)12(cid:13)(cid:15)IOUT(cid:13)VIN(cid:13)fSW(cid:9)(cid:13)(cid:15)tON(cid:10)tOFF(cid:9) (eq. 28) OUT IN OUT www.onsemi.com 18

NCP3020A, NCP3020B, NCV3020A, NCV3020B where: I : output current from the high−side gate drive (HSDR) G1 I : output current from the low−side gate drive (LSDR) Q Q G2 tON(cid:2) IGG1D(cid:2)(cid:15)VBST(cid:3)VTH(cid:9)(cid:16)G(cid:15)DRHSPU(cid:10)RG(cid:9) (eq. 29) 3ƒ0SW0 :k Hswzi tacnhdi nNgC fPre3q0u2e0nBc yi so 6f0 t0h ek Hcoznverter. NCP3020A is V : gate drive voltage for the high−side drive, typically BST and: 7.5 V. Q Q Q : gate charge plateau region, commonly specified in the tOFF(cid:2) IGG2D(cid:2)(cid:15)VBST(cid:3)VTH(cid:9)(cid:16)G(cid:15)DRHSPD(cid:10)RG(cid:9) (eq. 30) MVGODS: FgEaTte −datota−sshoeuertce voltage at the gate charge plateau TH Next, the MOSFET output capacitance losses are caused region by both the control and synchronous MOSFET but are Q : MOSFET output gate charge specified in the data OSS dissipated only in the control MOSFET. sheet P (cid:2)1(cid:13)Q (cid:13)V (cid:13)f (eq. 31) QRR: reverse recovery charge of the low−side or DS 2 OSS IN SW synchronous MOSFET, specified in the datasheet Finally the loss due to the reverse recovery time of the R : on resistance of the high−side, or DS(on)_CONTROL body diode in the synchronous MOSFET is shown as control, MOSFET follows: R : on resistance of the low−side, or DS(on)_SYNC P (cid:2)Q (cid:13)V (cid:13)f (eq. 32) synchronous, MOSFET RR RR IN SW NOL : dead time between the LSDR turning off and the LH The low−side or synchronous MOSFET turns on into zero HSDR turning on, typically 85 ns volts so switching losses are negligible. Its power NOL : dead time between the HSDR turning off and the HL dissipation only consists of conduction loss due to R DS(on) LSDR turning on, typically 75 ns and body diode loss during the non−overlap periods. P (cid:2)P (cid:10)P (eq. 33) Once the MOSFET power dissipations are determined, D_SYNC COND BODY the designer can calculate the required thermal impedance Conduction loss in the low−side or synchronous for each device to maintain a specified junction temperature MOSFET is described as follows: at the worst case ambient temperature. The formula for (cid:15) (cid:9)2 P (cid:2) I (cid:13)R (eq. 34) calculating the junction temperature with the package in free COND RMS_SYNC DS(on)_SYNC air is: where: (cid:14) (cid:15) (cid:15) (cid:9)(cid:9) TJ(cid:2)TA(cid:10)PD(cid:13)R(cid:2)JA I (cid:2)I (cid:13) (1(cid:3)D)(cid:13) 1(cid:10) ra2 (eq. 35) TJ: Junction Temperature RMS_SYNC OUT 12 T : Ambient Temperature A P : Power Dissipation of the MOSFET under analysis D The body diode losses can be approximated as: R(cid:2)JA: Thermal Resistance Junction−to−Ambient of the (cid:15) (cid:9) P (cid:2)V (cid:13)I (cid:13)f (cid:13) NOL (cid:10)NOL (eq. 36) MOSFET’s package BODY FD OUT SW LH HL As with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. Variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component Vth variations (i.e. worst case MOSFET R ). DS(on) Figure 33. MOSFET Switching Characteristics www.onsemi.com 19

NCP3020A, NCP3020B, NCV3020A, NCV3020B NOLHL NOLLH High−Side Logic Signal Low−Side Logic Signal td(on) tf RDSmax High−Side MOSFET RDS(on)min tr td(off) tr tf RDSmax Low−Side MOSFET RDS(on)min td(on) td(off) Figure 34. MOSFETs Timing Diagram Another consideration during MOSFET selection is their response. The goal of the compensation circuit is to provide delay times. Turn−on and turn−off times must be short a loop gain function with the highest crossing frequency and enough to prevent cross conduction. If not, there will be adequate phase margin (minimally 45°). The transfer conduction from the input through both MOSFETs to function of the power stage (the output LC filter) is a double ground. Therefore, the following conditions must be met. pole system. The resonance frequency of this filter is td(ON)_CONTROL(cid:10)NOLLH(cid:17)td(OFF)_SYNC(cid:10)tf_SYNC expressed as follows: 1 f (cid:2) and (eq. 37) P0 (cid:14) (eq. 38) 2(cid:13)(cid:6)(cid:13) L(cid:13)C OUT t(ON)_SYNC(cid:10)NOLHL(cid:17)td(OFF)_CONTROL(cid:10)tf_CONTROL Parasitic Equivalent Series Resistance (ESR) of the The MOSFET parameters, td(ON), tr, td(OFF) and tf are can output filter capacitor introduces a high frequency zero to be found in their appropriate datasheets for specific the filter network. Its value can be calculated by using the conditions. NOLLH and NOLHL are the dead times which following equation: were described earlier and are 85 ns and 75 ns, respectively. 1 f (cid:2) Feedback and Compensation Z0 2(cid:13)(cid:6)(cid:13)COUT(cid:13)ESR (eq. 39) The NCP3020 is a voltage mode buck convertor with a The main loop zero crossover frequency f0 can be chosen transconductance error amplifier compensated by an to be 1/10 − 1/5 of the switching frequency. Table 2 shows external compensation network. Compensation is needed to the three methods of compensation. achieve accurate output voltage regulation and fast transient Table 2. COMPENSATION TYPES Zero Crossover Frequency Condition Compensation Type Typical Output Capacitor Type fP0 < fZ0 < f0 < fS/2 Type II Electrolytic, Tantalum fP0 < f0 < fZ0 < fS/2 Type III Method I Tantalum, Ceramic fP0 < f0 < fS/2 < fZ0 Type III Method II Ceramic www.onsemi.com 20

NCP3020A, NCP3020B, NCV3020A, NCV3020B Compensation Type II f (cid:2)0.75(cid:13)f (eq. 44) Z1 P0 This compensation is suitable for electrolytic capacitors. f (cid:2)f Components of the Type II (Figure 35) network can be Z2 P0 (eq. 45) specified by the following equations: f (cid:2)f (eq. 46) P2 Z0 f f (cid:2) S (eq. 47) P3 2 Method II is better suited for ceramic capacitors that typically have the lowest ESR available: (cid:14) 1(cid:3)sin(cid:2)max f (cid:2)f (cid:13) (eq. 48) Z2 0 1(cid:10)sin(cid:2)max (cid:14) 1(cid:10)sin(cid:2)max f (cid:2)f (cid:13) (eq. 49) P2 0 1(cid:3)sin(cid:2)max f (cid:2)0.5(cid:13)f (eq. 50) Z1 Z2 Figure 35. Type II Compensation f (cid:2)0.5(cid:13)f (eq. 51) P3 S 2(cid:13)(cid:6)(cid:13)f (cid:13)L(cid:13)V (cid:13)V (cid:2)max is the desired maximum phase margin at the zero RC1(cid:2) ESR0(cid:13)V (cid:13)VRAMP(cid:13)gmOUT (eq. 40) crossover frequency, ƒ0. It should be 45° − 75°. Convert IN ref degrees to radians by the formula: 1 (cid:15) (cid:9) CC1(cid:2)0.75(cid:13)2(cid:13)(cid:6)(cid:13)fP0(cid:13)RC1 (eq. 41) (cid:2)max(cid:2)(cid:2)maxdegress(cid:13) 23(cid:13)60(cid:6) :Units(cid:2)radians (eq. 52) 1 The remaining calculations are the same for both methods. C (cid:2) (eq. 42) C2 (cid:6)(cid:13)RC1(cid:13)fS R (cid:17)(cid:17) 2 (eq. 53) V (cid:3)V C1 gm R1(cid:2) OUT ref(cid:13)R2 (eq. 43) 1 Vref CC1(cid:2)2(cid:13)(cid:6)(cid:13)f (cid:13)R (eq. 54) VRAMP is the peak−to−peak voltage of the oscillator ramp Z1 C1 and gm is the transconductance error amplifier gain. 1 C (cid:2) (eq. 55) Capacitor CC2 is optional. C2 2(cid:13)(cid:6)(cid:13)f (cid:13)R P3 C1 Compensation Type III 2(cid:13)(cid:6)(cid:13)f (cid:13)L(cid:13)V (cid:13)C Tantalum and ceramics capacitors have lower ESR than C (cid:2) 0 RAMP OUT (eq. 56) FB1 V (cid:13)R electrolytic, so the zero of the output LC filter goes to a IN C1 higher frequency above the zero crossover frequency. This 1 R (cid:2) (eq. 57) requires a Type III compensation network as shown in FB1 2(cid:6)(cid:13)C (cid:13)f FB1 P2 Figure 36. 1 There are two methods to select the zeros and poles of this R1(cid:2) (cid:3)R (eq. 58) compensation network. Method I is ideal for tantalum 2(cid:13)(cid:6)(cid:13)CFB1(cid:13)fZ2 FB1 output capacitors, which have a higher ESR than ceramic: V R2(cid:2) ref (cid:13)R1 (eq. 59) V (cid:3)V OUT ref If the equation in Equation 60 is not true, then a higher value of R must be selected. C1 R1(cid:13)R2(cid:13)R FB1 (cid:17) 1 (eq. 60) R1(cid:13)R (cid:10)R2(cid:13)R (cid:10)R1(cid:13)R2 gm FB1 FB1 Figure 36. Type III Compensation www.onsemi.com 21

NCP3020A, NCP3020B, NCV3020A, NCV3020B TYPICAL APPLICATION CIRCUIT 9−18V CIN−1/2 CIN−3/4 CIN−5 CBST D1 VCC BST A RG Q1 HSDR 0 2 RGS 0 COMP 3 3.3 uH 3.3V P VSW C RC Cc1 N Q2 RFB1 RFB3 FB LSDR Cc2 GND RISET CFB COUT−1 COUT−2/3 RFB2 Figure 37. Typical Application, V = 9 − 18 V, V = 3.3 V, I = 10 A IN OUT OUT Special Note Reference Designator Value The NCP3020/NCV3020 are dedicated for current CIN−1 470 (cid:3)F sensing across high−side MOSFET via VCC pin and VSW CIN−2 470 (cid:3)F pin, as shown in Figure 26. Therefore, the VCC pin must CIN−3 22 (cid:3)F connect to the VIN voltage, i.e., the drain of high−side MOSFET as shown in Figure 37 above. In other words, the CIN−4 22 (cid:3)F NCP3020/NCV3020 does not support separated VCC CIN−5 1 (cid:3)F voltage and VIN voltage, regardless any current limit setting CC1 33 pF in LSDR pin. Using a lower VCC voltage than the VIN voltage, such as VCC=12V and VIN=20V, may damage the CC2 8.2 nF NCP3020/NCV3020. Disconnecting the VCC pin supply, CFB 1.8 nF while VIN is still presented, risks the NCP3020/NCV3020 COUT1 470 (cid:3)F of being damaged as well. COUT2 22 (cid:3)F COUT3 22 (cid:3)F CBST 0.1 (cid:3)F RC 4.75 k(cid:4) RG 8.06 (cid:4) RGS 1.0 k(cid:4) RISET 22.1 k(cid:4) RFB1 4.53 k(cid:4) RFB2 1.0 k(cid:4) RFB3 2.49 k(cid:4) Q1 NTMFS4841N Q2 NTMFS4935 D1 BAT54 www.onsemi.com 22

NCP3020A, NCP3020B, NCV3020A, NCV3020B PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK NOTES: −X− 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. A 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) 8 5 PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL 1 IN EXCESS OF THE D DIMENSION AT −Y− 4 K 6. 7M5A1X−I0M1U TMH RMUA T7E51R−IA0L6 CAROEN DOIBTSIOONL.ETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES DIM MIN MAX MIN MAX C NX 45(cid:3) A 4.80 5.00 0.189 0.197 B 3.80 4.00 0.150 0.157 SEATING PLANE C 1.35 1.75 0.053 0.069 −Z− D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC 0.10 (0.004) H 0.10 0.25 0.004 0.010 H D M J J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 (cid:3) 8 (cid:3) 0 (cid:3) 8 (cid:3) N 0.25 0.50 0.010 0.020 0.25 (0.010)M Z Y S X S S 5.80 6.20 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 4.0 0.275 0.155 0.6 1.270 0.024 0.050 (cid:15) (cid:9) mm SCALE 6:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada For additional information, please contact your local Email: orderlit@onsemi.com Sales Representative ◊ www.onsemi.com NCP3020/D 23

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