NCP1587, NCP1587A Low Voltage Synchronous Buck Controller The NCP1587 and NCP1587A are low cost PWM controllers designed to operate from a 5 V or 12 V supply. These devices are capable of producing an output voltage as low as 0.8 V. These 8−pin devices provide an optimal level of integration to reduce size and cost http://onsemi.com of the power supply. The NCP1587/A provide a 1 A gate driver design and an internally set 275 kHz (NCP1587) and 200kHz (NCP1587A) MARKING DIAGRAM oscillator. In addition to the 1 A gate drive capability, other efficiency 8 enhancing features of the gate driver include adaptive non−overlap SOIC−8 1587x circuitry. The devices also incorporate an externally compensated 8 D SUFFIX ALYW error amplifier and a capacitor programmable soft−start function. 1 CASE 751 (cid:2) Protection features include programmable short circuit protection and 1 under voltage lockout (UVLO). The NCP1587/A comes in an 8−pin 1587x= Specific Device Code SOIC package. (x = A for NCP1587A, blank for NCP1587) Features A = Assembly Location • L = Wafer Lot Input Voltage Range from 4.5 to 13.2 V Y = Year • 275 kHz (NCP1587) and 200 kHz (NCP1587A) Internal Oscillator W = Work Week • Boost Pin Operates to 30 V (cid:2) = Pb−Free Device • Voltage Mode PWM Control • 0.8 V ±1.0 % Internal Reference Voltage PIN CONNECTIONS • Adjustable Output Voltage • BST 1 8 PHASE Capacitor Programmable Soft−Start • Internal 1 A Gate Drivers TG 2 7 COMP/DIS • 80% Max Duty Cycle GND 3 6 FB • Input Under Voltage Lockout • BG 4 5 VCC Programmable Current Limit • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS (Top View) Compliant Applications ORDERING INFORMATION • Graphics Cards Device Package Shipping† • Desktop Computers NCP1587DR2G SOIC−8 2500/Tape & Reel • (Pb−Free) Servers / Networking • DSP & FPGA Power Supply NCP1587ADR2G SOIC−8 2500/Tape & Reel • (Pb−Free) DC−DC Regulator Modules †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: May, 2012 − Rev. 5 NCP1587/D

NCP1587, NCP1587A 12 V 3.3 V VCC BST FB COMP/DIS TG PHASE VOUT BG GND Figure 1. Typical Application Diagram POR UVLO 5 VCC VOCTH FAULT LATCH SCP + - FB 6 - GM + FAULT 1 BST + R - PWM 0.8 V OUT Q 2 TG (VREF) S 8 PHASE + - Clock 2 V + Ramp - VCC COMP/DIS OSC BG 7 4 Rset OSC 3 FAULT GND Figure 2. Detailed Block Diagram http://onsemi.com 2

NCP1587, NCP1587A PIN FUNCTION DESCRIPTION Pin No. Symbol Description 1 BST Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to BST pin). Connect a capacitor (CBST) between this pin and the PHASE pin. Typical values for CBST range from 0.1 (cid:2)F to 1 (cid:2)F. Ensure that CBST is placed near the IC. 2 TG Top gate MOSFET driver pin. Connect this pin to the gate of the top N−Channel MOSFET. 3 GND IC ground reference. All control circuits are referenced to this pin. 4 BG Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N−Channel MOSFET. 5 VCC Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1 (cid:2)F capacitor to GND. Ensure that this decoupling capacitor is placed near the IC. 6 FB This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to compensate the voltage−control feedback loop. Connect this pin to the output resistor divider (if used) or dir- ectly to Vout. 7 COMP/DIS Compensation Pin. This is the output of the error amplifier (EA) and the non−inverting input of the PWM com- parator. Use this pin in conjunction with the FB pin to compensate the voltage−control feedback loop. The com- pensation capacitor also acts as a soft−start capacitor. Pull this pin low for disable. 8 PHASE Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top MOSFET. ABSOLUTE MAXIMUM RATINGS Pin Name Symbol VMAX VMIN Main Supply Voltage Input VCC 15 V −0.3 V Bootstrap Supply Voltage Input BST 35 V wrt/PGND −0.3 V 40 V < 50 ns wrt/PGND −0.3 V 15 V wrt/SW −0.3 V Switching Node (Bootstrap Supply Return) PHASE 35 V −5.0 V 40 V < 50 ns −10 V for < 200 ns High−Side Driver Output (Top Gate) TG 30 V wrt/GND −0.3 V wrt/PHASE 15 V wrt/PHASE −2 V < 200 ns wrt/PHASE Low−Side Driver Output (Bottom Gate) BG 15 V −0.3 V −5.0 V for < 200 ns Feedback FB 5.5 V −0.3 V COMP/DISABLE COMP/DIS 5.5 V −0.3 V MAXIMUM RATINGS Rating Symbol Value Unit Thermal Resistance, Junction−to−Ambient R(cid:3)JA 165 °C/W Thermal Resistance, Junction−to−Case R(cid:3)JC 45 °C/W NCP1587A Operating Junction Temperature Range TJ 0 to 125 °C NCP1587A Operating Ambient Temperature Range TA 0 to 70 °C Storage Temperature Range Tstg −55 to +150 °C Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 3

NCP1587, NCP1587A ELECTRICAL CHARACTERISTICS (0(cid:3)C < TA < 70(cid:3)C; 4.5 V < VCC < 13.2 V, 4.5 V < [BST−PHASE] < 13.2 V, 4.5 V < BST < 30 V, 0 V < PHASE < 21 V, CTG = CBG = 1.0 nF, for min/max values unless otherwise noted.) Characteristic Conditions Min Typ Max Unit Input Voltage Range − 4.5 − 13.2 V Boost Voltage Range − 4.5 − 26.5 V Supply Current Quiescent Supply Current VFB = 1.0 V, No Switching, VCC = 13.2 V 1.0 − 8.0 mA Boost Quiescent Current VFB = 1.0 V, No Switching, VCC = 13.2 V 0.1 − 1.0 mA Under Voltage Lockout UVLO Threshold VCC Rising Edge 3.8 − 4.2 V UVLO Hysteresis − − 350 − mV Switching Regulator VFB Feedback Voltage, TA = 0 to 70°C 792 800 808 mV Control Loop in Regulation Oscillator Frequency NCP1587 TA = 0 to 70°C 250 275 300 kHz NCP1587A 180 200 220 Ramp−Amplitude Voltage 0.8 1.1 1.4 V Minimum Duty Cycle 0 − − % Maximum Duty Cycle 70 75 80 % Error Amplifier (GM) Transconductance 3.0 − 4.4 mmho Open Loop DC Gain 55 70 − DB Output Source Current VFB < 0.8 V 80 120 − (cid:2)A Output Sink Current VFB > 0.8 V 80 120 − Input Bias Current − 0.1 1.0 (cid:2)A Soft−Start SS Source Current VFB < 0.8 V 8.49 11 13.3 (cid:2)A Switch Over Threshold VFB = 0.8 V − 100 − % of Vref Gate Drivers Upper Gate Source − 1.0 − A Upper Gate Sink − 1.0 − A VCC = 12 V, VTG = VBG = 2.0 V Lower Gate Source − 1.0 − A Lower Gate Sink − 2.0 − A TG Falling to BG Rising Delay VCC = 12 V, TG < 2.0 V, BG > 2.0 V − 40 90 ns BG Falling to TG Rising Delay VCC = 12 V, BG < 2.0 V, TG > 2.0 V − 35 90 ns Enable Threshold 0.3 0.4 0.5 V Over−Current Protection OCSET Current Source Sourced from BG pin, before SS 9.89 10 11.1 (cid:2)A OC Switch−Over Threshold − 700 − mV Fixed OC Threshold − −375 − mV http://onsemi.com 4

NCP1587, NCP1587A TYPICAL CHARACTERISTICS (T = 25°C unless otherwise noted) A 5.0 203 4.7 z) 202 h K Y ( A) 4.4 NC 201 m E I (CC 4.1 REQU 200 VCC = 12 V F , W S 3.8 F 199 VCC = 5 V 3.5 198 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 3. I vs. Temperature Figure 4. Oscillator Frequency (F ) vs. CC SW Temperature A) 14 375 (cid:2) T ( N RE 13 V) 365 R m CU 12 D ( G L 355 N O CI 11 SH R E OU HR 345 S 10 T T P R C STA 9 S 335 T F O 8 325 S 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. Soft Start Sourcing Current vs. Figure 6. SCP Threshold vs. Temperature Temperature 808 806 V) 804 m CE ( 802 N E R 800 E F E 798 R V, ref 796 794 792 0 10 20 30 40 50 60 70 TJ, JUNCTION TEMPERATURE (°C) Figure 7. Reference Voltage (V ) vs. ref Temperature http://onsemi.com 5

NCP1587, NCP1587A DETAILED OPERATING DESCRIPTION General External Enable/Disable The NCP1587 and NCP1587A are PWM controllers When the Comp pin voltage falls or is pulled externally intended for DC−DC conversion from 5.0 V & 12 V buses. below the 400 mV threshold, it disables the PWM Logic and The devices have a 1 A internal gate driver circuit designed the gate drive outputs. In this disabled mode, the operational to drive N−channel MOSFETs in a synchronous−rectifier transconductance amplifier (EOTA) output source current is buck topology. The output voltage of the converter can be reduced and limited to the Soft−Start mode of 10 (cid:2)A. precisely regulated down to 800 mV ±1.0% when the V FB pin is tied to V . The switching frequency, is internally set Normal Shutdown Behavior OUT Normal shutdown occurs when the IC stops switching to 275 kHz (NCP1587) and 200 kHz (NCP1587A). A high because the input supply reaches UVLO threshold. In this gain operational transconductance error amplifier (OTA) is case, switching stops, the internal SS is discharged, and all used. GATE pins go low. The switch node enters a high impedance Duty Cycle and Maximum Pulse Width Limits state and the output capacitors discharge through the load In steady state DC operation, the duty cycle will stabilize with no ringing on the output voltage. at an operating point defined by the ratio of the input to the output voltage. The devices can achieve an 80% duty cycle. External Soft−Start The NCP1587/A features an external soft−start function, There is a built in off−time which ensures that the bootstrap which reduces inrush current and overshoot of the output supply is charged every cycle. Both parts can allow a 12 V voltage. Soft−start is achieved by using the internal current to 0.8 V conversion at 275 kHz (NCP1587) and 200 kHz source of 10 (cid:2)A (typ), which charges the external integrator (NCP1587A). capacitor of the transconductance amplifier. Figure 8 is a Input Voltage Range (VCC and BST) typical soft−start sequence. This sequence begins once VCC The input voltage range for both V and BST is 4.5 V to surpasses its UVLO threshold and OCP programming is CC 13.2V with respect to GND and PHASE, respectively. complete. During soft−start, as the Comp Pin rises through Although BST is rated at 13.2 V with respect to PHASE, it 400 mV, the PWM Logic and gate drives are enabled. When can also tolerate 26.4 V with respect to GND. the feedback voltage crosses 800 mV, the EOTA will be given control to switch to its higher regulation mode output current of 120 (cid:2)A. 4.2 V VCC 0.9 V Comp 0.8 V Vfb 550 mV BG 50 mV OCP Program ming TG Vout UVLO POR SS NORMAL Figure 8. Soft−Start Implementation http://onsemi.com 6

NCP1587, NCP1587A UVLO go through a Power On Reset (POR) cycle to reset the OCP Undervoltage Lockout (UVLO) is provided to ensure that fault. unexpected behavior does not occur when V is too low to CC support the internal rails and power the converter. For the Drivers NCP1587/A, the UVLO is set to permit operation when The NCP1587 and NCP1587A include gate drivers to converting from a 5.0 input voltage. switch external N−channel MOSFETs. This allows the devices to address high−power as well as low−power Overcurrent Threshold Setting conversion requirements. The gate drivers also include NCP1587/A can easily program an Overcurrent adaptive non−overlap circuitry. The non−overlap circuitry Threshold ranging from 50 mV to 550 mV, simply by adding increase efficiency, which minimizes power dissipation, by a resistor (RSET) between BG and GND. During a short minimizing the body diode conduction time. period of time following VCC rising over UVLO threshold, A detailed block diagram of the non−overlap and gate an internal 10 (cid:2)A current (IOCSET) is sourced from BG pin, drive circuitry used in the chip is shown in Figure 9. determining a voltage drop across R . This voltage OCSET drop will be sampled and internally held by the device as Overcurrent Threshold. The OC setting procedure overall FAULT 1 BST time length is about 6 ms. Connecting a R resistor OCSET between BG and GND, the programmed threshold will be: 2 TG IOCth(cid:2)IOCSET(cid:3)ROCSET (eq. 1) RDS(on) 8 PHASE RSET values range from 5 k(cid:4) to 55 k(cid:4). In case R OCSET + is not connected, the device switches the OCP threshold to - a fixed 375 mV value: an internal safety clamp on BG is 2 V triggered as soon as BG voltage reaches 700 mV, enabling the 375 mV fixed threshold and ending OC setting phase. + The current trip threshold tolerance is ±25 mV. The accuracy - VCC of the set point is best at the highest set point (550 mV). The BG accuracy will decrease as the set point decreases. 4 Current Limit Protection Rset In case of a short circuit or overload, the low−side (LS) 3 FAULT GND FET will conduct large currents. The controller will shut down the regulator in this situation for protection against Figure 9. Block Diagram overcurrent. The low−side R sense is implemented at DS(on) the end of each of the LS−FET turn−on duration to sense the Careful selection and layout of external components is over current trip point. While the LS driver is on, the Phase required, to realize the full benefit of the onboard drivers. voltage is compared to the internally generated OCP trip The capacitors between V and GND and between BST CC voltage. If the phase voltage is lower than OCP trip voltage, and SWN must be placed as close as possible to the IC. The an overcurrent condition occurs and a counter is initiated. current paths for the TG and BG connections must be When the counter completes, the PWM logic and both optimized. A ground plane should be placed on the closest HS−FET and LS−FET are turned off. The controller has to layer for return currents to GND in order to reduce loop area and inductance in the gate drive circuit. http://onsemi.com 7

NCP1587, NCP1587A APPLICATION SECTION Input Capacitor Selection The above calculation includes the delay from comp The input capacitor has to sustain the ripple current rising to when output voltage starts becomes valid. produced during the on time of the upper MOSFET, so it To calculate the time of output voltage rising to when it must have a low ESR to minimize the losses. The RMS value reaches regulation; (cid:5)V is the difference between the comp of this ripple is: voltage reaching regulation and 0.9 V. (cid:6) Iin (cid:2)I D(cid:4)(1(cid:5)D) , RMS OUT Output Capacitor Selection where D is the duty cycle, Iin is the input RMS current, The output capacitor is a basic component for the fast RMS & I is the load current. The equation reaches its response of the power supply. In fact, during load transient, OUT maximum value with D = 0.5. Loss in the input capacitors for the first few microseconds it supplies the current to the can be calculated with the following equation: load. The controller immediately recognizes the load P (cid:2)ESR (cid:4)Iin 2, transient and sets the duty cycle to maximum, but the current CIN CIN RMS slope is limited by the inductor value. where PCIN is the power loss in the input capacitors & During a load step transient the output voltage initial ESRCIN is the effective series resistance of the input drops due to the current variation inside the capacitor and the capacitance. Due to large dI/dt through the input capacitors, ESR. ((neglecting the effect of the effective series electrolytic or ceramics should be used. If a tantalum must inductance (ESL)): be used, it must by surge protected. Otherwise, capacitor (cid:5)V (cid:2)(cid:5)I (cid:4)ESR failure could occur. OUT−ESR OUT COUT where VOUT-ESR is the voltage deviation of VOUT due to the Calculating Input Start-up Current effects of ESR and the ESR is the total effective series COUT To calculate the input start up current, the following resistance of the output capacitors. equation can be used. A minimum capacitor value is required to sustain the I (cid:2)COUT(cid:4)VOUT , current during the load transient without discharging it. The inrush t voltage drop due to output capacitor discharge is given by SS the following equation: where I is the input current during start-up, C is the inrush OUT (cid:5)I 2(cid:4)L total output capacitance, VOUT is the desired output voltage, (cid:5)V (cid:2) OUT OUT , and tSS is the soft start interval. OUT−DISCHARGE 2(cid:4)COUT(cid:4)(VIN(cid:4)D(cid:5)VOUT) If the inrush current is higher than the steady state input where VOUT-DISCHARGE is the voltage deviation of VOUT current during max load, then the input fuse should be rated due to the effects of discharge, L is the output inductor OUT accordingly, if one is used. value & V is the input voltage. IN Calculating Soft Start Time It should be noted that ΔVOUT-DISCHARGE and To calculate the soft start time, the following equation can ΔVOUT-ESR are out of phase with each other, and the larger of these two voltages will determine the maximum deviation be used. of the output voltage (neglecting the effect of the ESL). (C (cid:7)C )*(cid:5)V t (cid:2) p c ss Iss Inductor Selection Where C is the compensation as well as the soft start Both mechanical and electrical considerations influence c capacitor, the selection of an output inductor. From a mechanical perspective, smaller inductor values generally correspond to C is the additional capacitor that forms the second pole. p smaller physical size. Since the inductor is often one of the I is the soft start current ss largest components in the regulation system, a minimum (cid:5)V is the comp voltage from zero to until it reaches inductor value is particularly important in space-constrained regulation: ((d * ramp) + 0.9) applications. From an electrical perspective, the maximum (cid:5)V current slew rate through the output inductor for a buck regulator is given by: V (cid:5)V 900 mV SlewRate (cid:2) IN OUT LOUT L OUT This equation implies that larger inductor values limit the Vcomp regulator’s ability to slew current through the output inductor in response to output load transients. Consequently, output capacitors must supply the load current until the Vout inductor current reaches the output load current level. This results in larger values of output capacitance to maintain http://onsemi.com 8

NCP1587, NCP1587A tight output voltage regulation. In contrast, smaller values of Figure 10 shows a typical Type II transconductance error inductance increase the regulator’s maximum achievable amplifier (EOTA). The compensation network consists of slew rate and decrease the necessary capacitance, at the the internal error amplifier and the impedance networks ZIN expense of higher ripple current. The peak-to-peak ripple (R , R ) and external Z (R , C and C ). The 1 2 FB c c p current for NCP1587 is given by the following equation: compensation network has to provide a closed loop transfer V (1(cid:5)D) function with the highest 0 dB crossing frequency to have Ipk(cid:5)pkLOUT(cid:2)L OU(cid:4)T 275kHz , fast response (but always lower than FSW/8) and the highest OUT gain in DC conditions to minimize the load regulation. A where Ipk-pkLOUT is the peak to peak current of the output. stable control loop has a gain crossing with -20 dB/decade From this equation it is clear that the ripple current increases slope and a phase margin greater than 45°. Include as LOUT decreases, emphasizing the trade-off between worst-case component variations when determining phase dynamic response and ripple current. margin. Loop stability is defined by the compensation network around the EOTA, the output capacitor, output Feedback and Compensation inductor and the output divider. Figure 11 shows the open The NCP1587 allows the output of the DC-DC converter loop and closed loop gain plots. to be adjusted from 0.8 V to 5.0 V via an external resistor divider network. The controller will try to maintain 0.8 V at Compensation Network Frequency: the feedback pin. Thus, if a resistor divider circuit was The inductor and capacitor form a double pole at the placed across the feedback pin to VOUT, the controller will frequency regulate the output voltage proportional to the resistor divider network in order to maintain 0.8 V at the FB pin. FLC(cid:2)2(cid:6)(cid:4)(cid:6)1L (cid:4)C o o VOUT The ESR of the output capacitor creates a “zero” at the frequency, R1 F (cid:2) 1 FB ESR 2(cid:6)(cid:4)ESR(cid:4)Co The zero of the compensation network is formed as, R2 F (cid:2) 1 Z 2(cid:6)(cid:4)R C c c The pole of the compensation network is calculated as, The relationship between the resistor divider network above and the output voltage is sh(cid:8)own in the follo(cid:9)wing equation: Fp(cid:2)2(cid:6)(cid:4)R1c(cid:4)Cp V R (cid:2)R (cid:4) REF 2 1 V (cid:5)V OUT REF Resistor R1 is selected based on a design tradeoff between efficiency and output voltage accuracy. For high values of R1 there is less current consumption in the feedback network, However the trade off is output voltage accuracy due to the bias current in the error amplifier. The output voltage error of this bias current can be estimated using the following equation (neglecting resistor tolerance): 0.1(cid:2)A(cid:4)R Error%(cid:2) 1(cid:4)100% V REF Once R1 has been determined, R2 can be calculated. Figure 11. Gain Plot of the Error Amplifier R1 EA Thermal Considerations The power dissipation of the NCP1587 varies with the Gm MOSFETs used, V , and the boost voltage (V ). The CC BST Cc Cp + R2 average MOSFET gate current typically dominates the Rc Vref − control IC power dissipation. The IC power dissipation is determined by the formula: P (cid:2)(I (cid:4)V )(cid:7)P (cid:7)P IC CC CC TG BG Figure 10. Type II Transconductance Error Where: Amplifier http://onsemi.com 9

NCP1587, NCP1587A P = control IC power dissipation, IC I = IC measured supply current, CC V = IC supply voltage, CC P = top gate driver losses, TG P = bottom gate driver losses. BG The upper (switching) MOSFET gate driver losses are: P (cid:2)Q (cid:4)f (cid:4)V TG TG SW BST Where: Figure 12. Components to be Considered for Q = total upper MOSFET gate charge at VBST, TG Layout Specifications f = the switching frequency, SW V = the BST pin voltage. BST DESIGN EXAMPLE I: Type II Compensation The lower (synchronous) MOSFET gate driver losses are: (Electrolytic Cap. with large ESR) P (cid:2)Q (cid:4)f (cid:4)V Switching Frequency FSW = 275 KHz BG BG SW CC Output Capacitance R = 45 m(cid:4)/Each ESR Where: Output Capacitance C = 2×1800 (cid:2)F out QBG = total lower MOSFET gate charge at VCC. Output Inductance Lout = 1 (cid:2)H The junction temperature of the control IC can then be Input Voltage V = 12 V in calculated as: Output Voltage V = 1.6 V out TJ(cid:2)TA(cid:7)PIC(cid:4)(cid:3)JA Choose the loop gain crossover frequency; Where: F (cid:2)1(cid:4)F (cid:2)55KHz co 5 sw T = the junction temperature of the IC, J T = the ambient temperature, The corner frequency of the output filter is calculated below; A ICθ pJAac =ka tghee. junction−to−ambient thermal resistance of the FLC(cid:2)2(cid:4)(cid:6)(cid:4)(cid:6)1(cid:2)1H(cid:4)3600(cid:2)F(cid:2)2.65KHz The package thermal resistance can be obtained from the Check that the ESR zero frequency is not too high; specifications section of this data sheet and a calculation can be made to determine the IC junction temperature. However, F (cid:2) 1 (cid:10)Fco it should be noted that the physical layout of the board, the ESR 2(cid:4)(cid:6)(cid:4)R (cid:4)C 10 ESR O proximity of other heat sources such as MOSFETs and F (cid:2) 1 (cid:2)2KHz inductors, and the amount of metal connected to the IC, ESR 2(cid:4)(cid:6)(cid:4)45m(cid:4)(cid:4)(1800(cid:2)F(cid:4)2) impact the temperature of the device. Use these calculations 2 If ESR zero is larger than F /10, Type III compensation as a guide, but measurements should be taken in the actual co is necessary. application. Choose C for the crossover frequency and the soft start C Layout Considerations C (cid:2)100nF As in any high frequency switching converter, layout is C very important. Switching current from one power device to The compensation capacitor (CC) is related to the loop another can generate voltage transients across the gain magnitude, zero position and the soft start. By adjusting impedances of the interconnecting bond wires and circuit the value of this compensation capacitor, the crossover traces. These interconnecting impedances should be frequency and the soft start time can be adjusted. minimized by using wide, short printed circuit traces. The Zero of the compensation network is calculated as follows; critical components should be located as close together as F (cid:2)F (cid:2)2.65KHz possible using ground plane construction or single point Z LC grounding. The figure below shows the critical power R (cid:2) 1 C 2(cid:4)(cid:6)(cid:4)F (cid:4)C components of the converter. To minimize the voltage z C overshoot the interconnecting wires indicated by heavy lines (cid:2) 1 (cid:2)600.6(cid:4) 2(cid:4)(cid:6)(cid:4)2.65kHz(cid:4)100nF should be part of ground or power plane in a printed circuit board. The components shown in the figure below should be Pole of the compensation network is calculated as follows; located as close together as possible. Please note that the F (cid:2)F (cid:2)275KHz p sw capacitors C and C each represent numerous physical IN OUT C (cid:2) 1 capacitors. It is desirable to locate the NCP1587 within 1 p 2(cid:4)(cid:6)(cid:4)F (cid:4)R p C inch of the MOSFETs, Q1 and Q2. The circuit traces for the (cid:2) 1 (cid:2)963.6pF MOSFETs’ gate and source connections from the NCP1587 2(cid:4)(cid:6)(cid:4)275kHz(cid:4)600.6 must be sized to handle up to 2 A peak current. The recommended compensation values are; R = 604, C C = 100 nF, C = 1000 pF C P http://onsemi.com 10

NCP1587, NCP1587A Blue curve: Gain-Frequency Red curve: Gain-Frequency (Phase margin = 61.417 degree, Gain margin = 9.347 dB) Figure 13. Closed-loop Voltage Loop-gain of the NCP1587 DESIGN EXAMPLE II: Type III Compensation F (Oscon Cap. with small ESR; Do not place RC, CC, CP) FZ1(cid:2) 1L0C(cid:2)470Hz Switching Frequency F = 275 KHz Output Capacitance RsEwSR = 7 m(cid:4)/Each RC1(cid:2)2(cid:4)(cid:6)(cid:4)F1z1(cid:4)CC1 Output Capacitance Cout = 2×560 (cid:2)F (cid:2) 1 (cid:2)11.3k(cid:4) Output Inductance L = 1 (cid:2)H 2(cid:4)(cid:6)(cid:4)470Hz(cid:4)30nF out Input Voltage Vin = 12 V RC1 should be much larger than 2/gm in order to get the Output Voltage Vout = 1.6 V stable system with transconductance amplifier. (cid:2) choose Choose the loop gain crossover frequency; RC1 = 12.1 k(cid:4) 2nd zero; F (cid:2)1(cid:4)F (cid:2)55KHz co 5 sw Choose R3 for the crossover frequency. R3 should be much larger than 2/gm for the stable system. The corner frequency of the output filter is calculated below; R3(cid:2)10k(cid:4) FLC(cid:2)2(cid:4)(cid:6)(cid:4)(cid:6)1(cid:2)1H(cid:4)1120(cid:2)F(cid:2)4.7KHz F (cid:2)F (cid:2)4.7KHz z2 LC Check the ESR zero frequency; C20(cid:2) 1 F (cid:2) 1 2(cid:4)(cid:6)(cid:4)Fz2(cid:4)R3 ESR 2(cid:4)(cid:6)(cid:4)RESR(cid:4)CO (cid:2) 1 (cid:2)3.4nF 2(cid:4)(cid:6)(cid:4)4.7KHz(cid:4)10k(cid:4) F (cid:2) 1 (cid:2)40.6KHz ESR 2(cid:4)(cid:6)(cid:4)7m(cid:4)(cid:4)560(cid:2)F Choose C20 = 3.3 nF Choose C for the soft start Poles of the compensation network are calculated as follows; C1 1st pole; C (cid:2)33nF C1 Choose R4 to cancel the output capacitor ESR zero. The compensation capacitor (C ) is related to the loop C1 F (cid:2)F (cid:2)40.6KHz gain magnitude, one zero position and the soft start. By P1 ESR adjusting the value of this compensation capacitor, the R4(cid:2) 1 crossover frequency and the soft start time can be adjusted. 2(cid:4)(cid:6)(cid:4)F (cid:4)C20 P1 Zeros of the compensation network are calculated as follows; (cid:2) 1 (cid:2)1.2k(cid:4) 2(cid:4)(cid:6)(cid:4)40.6kHz(cid:4)3.3n 1st zero; http://onsemi.com 11

NCP1587, NCP1587A After choose R4 value, adjust R4 to get enough phase Choose C = 47 pF P1 margin (cid:2) R4 = 665 (cid:4) The recommended compensation values are; 2nd pole; R2 = 10 k(cid:4), R3 = 10 k(cid:4), R4 = 665 (cid:4), Choose C to eliminate the noise; P1 RC1 = 12.1 k(cid:4), CC1 = 33 nF, CP1= 47 pF, F (cid:2)F (cid:2)275KHz P2 sw C20 = 3.3 nF C (cid:2) 1 P1 2(cid:4)(cid:6)(cid:4)F (cid:4)R P2 C1 (cid:2) 1 (cid:2)48.23pF 2(cid:4)(cid:6)(cid:4)275kHz(cid:4)12k(cid:4) Blue curve: Gain-Frequency Red curve: Gain-Frequency (Phase margin = 80.285 degree, Gain margin = 19.362 dB) Figure 14. Closed-loop Voltage Loop-gain of the NCP1587 http://onsemi.com 12

NCP1587, NCP1587A VOUT TP102 TP103 OUTPUTP7 TP9 GND GND UT VO C1710uF C1610uF C24DNP + C15DNP TP100 TP104 +C131800uF+ ODE +C121800uF N _ TCH (cid:2)(cid:4)(cid:5)DNP (cid:2)(cid:4)(cid:5)1uH SWI L2(cid:2) L1(cid:2) R8DNP C21DNP C2510uF DUAL PLACEMENT SITE Q9Q10DDDNPDNPSO8−FLSO8−FL GG SS Q12Q11DDDNPDNPSO8−FLSO8−FL G SS DUAL PLACEMENT SITE TP20Vinn ++C22C4C23C510uF1500uF10uFDNPTP113D DUAL PLACEMENT SITEDUAL PLACEMENT SITE Q4Q2Q3Q1NTD4815NTD4815NTD4815NTD4815IPAKDPAKIPAKDPAK Q7Q8Q5Q6NTD4806NTD4806NTD4806NTD4806IPAKDPAKIPAKDPAK G DUAL PLACEMENT SITEDUAL PLACEMENT SITE C19C1810uF10uF i N V G 1CR116LT1BAS1 3 TGTP99 TP101 BST1C110.1uF TGR720Note : gatinglength sSWITCH_NODE8Note : gatinglength shoBGR64G0 R6390BGTP107 TP108 TP109 TP110 TP111 TP112 R110 U1 BST TG 1587 PHASE (cid:2)(cid:2)(cid:2)(cid:3)B (cid:4)0 C91uF C81uF 5 7CCOMPCVRc1DNP NCP Cc1DNPD6NFB(cid:2)(cid:2)(cid:2)(cid:2)G 3 R55.11 R9(cid:2)(cid:2)(cid:2) TP93 COMP Cp1DNP FB C20DNP R4DNP P K TP94 1 COMTP97 TP98 RcCC6040.1uF Cp100pF FBTP105 TP106 R21.02K R31.02 MH4 H3 C M Vbst VC H2 M TP1tTP2D TP95CTP96D MH1 s N C N b G V G Figure 15. Demo Board PCB Layout V http://onsemi.com 13

NCP1587, NCP1587A Bill of Materials Item Number Part Reference Value Quantity MFG 1 C4 1500 (cid:2)F 1 PANASONIC 2 C5 DNP 1 - 3 C8,C9 1 (cid:2)F 2 TAIYO YUDEN 4 C11 0.1 (cid:2)F 1 AVX 5 C12,C13 1800 (cid:2)F 2 PANASONIC 6 C15,C24 DNP 2 - 7 C16,C17,C18,C19,C22,C23,C25 10 (cid:2)F 7 PANASONIC 8 C20,CC1,CP1 DNP 3 - 9 C21 DNP 1 - 10 CC 0.1 (cid:2)F 1 TDK 11 CR1 BAS116LT1 1 ON SEMICONDUCTOR 12 CP 100 pF 1 PANASONIC 13 J9 20PIN 2ROW 1 MOLEX 14 J23 5PIN 1 PASTERNACK ENTERPRISES 15 L1 1 (cid:2)H 1 PANASONIC 16 L2 DNP 1 - 17 Q1,Q2 NTD4815 2 ON SEMICONDUCTOR 18 Q3,Q4 NTD4815 2 ON SEMICONDUCTOR 19 Q5,Q6 NTD4806 2 ON SEMICONDUCTOR 20 Q7,Q8 NTD4806 2 ON SEMICONDUCTOR 21 Q9,Q10,Q11,Q12 DNP 4 - 22 Q17,Q18,Q19,Q20,Q21,Q22,Q23,Q24,Q25,Q26, NTHS5404T1 24 ON SEMICONDUCTOR Q27,Q28,Q29,Q30,Q31,Q32,Q33,Q34,Q35,Q36, Q37,Q38,Q39,Q40 23 R1 10 1 PANASONIC 24 R2,R3 1.02 K 2 DALE 25 R4,RC1 DNP 2 - 26 R5 5.11 1 DALE 27 R6,R7,R639 0 3 PANASONIC 28 R8 DNP 1 - 29 R9 0 1 DALE 30 R551,R552,R553,R569,R570,R571,R584,R585, 100 K 24 DALE R586,R599,R600,R601,R608,R609,R610,R617, R618,R619,R626,R627,R628,R635,R636,R637 31 R602,R603,R604,R605,R606,R607,R611,R612, 0.56 24 PANASONIC R613,R614,R615,R616,R620,R621,R622,R623, R624,R625,R629,R630,R631,R632,R633,R634 32 R638 49.9 1 DALE 33 RC 604 1 DALE 34 TP97,TP98,TP99,TP100,TP101,TP102,TP103, TP 16 KEYSTONE TP104,TP105,TP106,TP107,TP108,TP109, TP110,TP111,TP112 35 U1 NCP1587 1 ON SEMICONDUCTOR http://onsemi.com 14

NCP1587, NCP1587A Figure 16. Gate Waveforms 20 A Load Sustaining Figure 17. Over Current Protection (12.4 A DC Trip) Figure 18. Start-up Sequence Figure 19. Transient Response 0-10 A Load Step NCP1587 Efficiency 90 88 86 84 82 %) 80 y ( 78 c 76 n e 74 ci Effi 7702 68 66 64 62 60 0 2 4 6 8 10 12 14 16 Load Current (A) Figure 20. Efficiency vs. Load Current http://onsemi.com 15

NCP1587, NCP1587A PACKAGE DIMENSIONS SOIC−8 D SUFFIX CASE 751−07 NOTES: −X− ISSUE AK 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. A 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) 8 5 PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL 1 IN EXCESS OF THE D DIMENSION AT −Y− 4 K 6. 7M5A1X−I0M1U TMH RMUA T7E51R−IA0L6 CAROEN DOIBTSIOONL.ETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES DIM MIN MAX MIN MAX C NX 45(cid:3) A 4.80 5.00 0.189 0.197 B 3.80 4.00 0.150 0.157 SEATING PLANE C 1.35 1.75 0.053 0.069 −Z− D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC 0.10 (0.004) H 0.10 0.25 0.004 0.010 H D M J J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 (cid:3) 8 (cid:3) 0 (cid:3) 8 (cid:3) N 0.25 0.50 0.010 0.020 0.25 (0.010) M Z Y S X S S 5.80 6.20 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 4.0 0.275 0.155 0.6 1.270 0.024 0.050 (cid:8) (cid:9) mm SCALE 6:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com NCP1587/D 16

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