NCP1093, NCP1094 Integrated IEEE 802.3at PoE-PD Interface Controller Description The NCP1093 and NCP1094 are members of ONSemiconductor’s high power HIPO(cid:2) Power over Ethernet Powered Device (PoE−PD) product family and integrate an IEEE 802.3at PoE−PD interface www.onsemi.com controller. Both variants incorporate the required functions such as detection, DFN10 classification, under voltage lockout, inrush and operational current MN SUFFIX limit. A power good and NCLASS_AT signal have been added to CASE 485C guarantee proper enabling/disabling of the DC−DC controller for both type−I and type−II operation. In addition, the NCP1093 offers a PIN CONFIGURATION programmable under−voltage while the NCP1094 provides an 1 auxiliary pin for applications supporting auxiliary supplies. INRUSH VPORTP The NCP1093 and NCP1094 are fabricated in a robust high voltage CLASS NCLASS_AT DET EP** * process and integrate a rugged vertical N−channel DMOS suitable for VPORTN1 PGOOD the most demanding environments and capable of withstanding harsh VPORTN2 RTN environments such as hot swap and cable ESD events. The NCP1093 and NCP1094 complement ONSemiconductor’s (Top View) ASSP portfolio in industrial devices and can be combined with stepper *NCP1093 = UVLO motor drivers, CAN bus drivers and other high−voltage interfacing NCP1094 = AUX ** Exposed pad should be devices to offer complete solutions to the industrial and security connected to VPORTN market. Features MARKING DIAGRAMS • Fully Supports IEEE 802.3af/at Specifications NCP10 NCP10 • Programmable Classification Current 93MN 94MN • ALYW(cid:3) ALYW(cid:3) Support Two Event Classification−Signature (cid:3) (cid:3) • Adjustable Under Voltage Lock Out (NCP1093 Only) • Open−Drain Power Good Indicator NCP109xMN = Specific Device Code • A = Assembly Location 120 mA Typical Inrush Current Limit L = Wafer Lot • 680 mA Typical Operational Current Limit Y = Year • W = Work Week Pass Switch Disabling Input for Rear Auxiliary Supply Operation (cid:3) = Pb−Free Package (NCP1094 Only) (Note: Microdot may be in either location) • Over−temperature Protection • Industrial Temperature Range −40°C to 85°C with Full Operation up ORDERING INFORMATION to 125°C Junction Temperature Device Package Shipping† • 0.6 (cid:2) Hot−swap Pass−switch • NCP1093MNG DFN10 120 Units / Tube Vertical N−channel DMOS Pass−switch Offers the Robustness of (Pb−Free) Discrete MOSFETs NCP1093MNRG DFN10 3000 / Tape & Reel • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS (Pb−Free) Compliant NCP1094MNG DFN10 120 Units / Tube (Pb−Free) NCP1094MNRG DFN10 3000 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: April, 2017 − Rev. 4 NCP1093/D

NCP1093, NCP1094 VPORTP THERMAL SHUTDOWN DETECTION INTERNAL SUPPLY & VOLTAGE REFERENCE DET nCLASS_AT DUAL EVENT CLASSIFICATION INDICATOR CLASS CLASSIFICATION VPORT UVLO MONITOR EXTERNAL UVLO SELECTION NCP1093 only OPERATIONAL CURRENT LIMIT IEEE Interface Shutdown AUX (AUX supply priority) HOT SWAP SWITCH NCP1094 only INRUSH CONTROL & CURRENT INRUSH CURRENT LIMIT LIMIT BLOCKS PGOOD POWER GOOD INDICATOR VPORTN RTN Figure 1. NCP1093/94 Functional Block Diagram www.onsemi.com 2

NCP1093, NCP1094 Simplified Application Diagrams RJ−45 VPORTP Data Rdet Pairs DB1 DET PGOOD Rclass e CLASS d To DC−DC n e p Converter Z_li Clin NCP1093 C Rinrush INRUSH Ruvlo1 RTN DB2 UVLO Spare Pairs Ruvlo2 NCLASS_AT VPORTN Figure 2. Typical Application Circuit using the NCP1093 with External UVLO Setting RJ−45 VAUX (+) VPORTP Data Rdet Pairs DB1 DET PGOOD Rclass e CLASS d To DC−DC n e p Converter Z_li Clin NCP1094 C Rinrush INRUSH RTN DB2 AUX Spare Pairs NCLASS_AT VPORTN VAUX (−) Figure 3. Typical Application Circuit using the NCP1094 www.onsemi.com 3

NCP1093, NCP1094 Table 1. PIN DESCRIPTION Pin No. Name NCP1093 NCP1094 Type Description INRUSH 1 1 Output Current limit programming pin. Connect a resistor between INRUSH and VPORTN. CLASS 2 2 Output Classification current programming pin. Connect a resistor between CLASS and VPORTN. DET 3 3 Output, Detection pin. Connect a 24.9 k(cid:2) resistor between DET and VPORTP for a Open Drain valid PD detection signature. VPORTN1 4 4 Ground Negative input power. Connected to the source of the internal pass−switch VPORTN2 5 5 Ground Negative input power. Connected to the source of the internal pass−switch RTN 6 6 Ground DC−DC controller power return. Connected to the drain of the internal pass− switch PGOOD 7 7 Output, Open Drain Power Good Indicator. Pin is in HZ mode when the power good Open Drain signal is active. UVLO 8 − Input Undervoltage lockout input. Voltage with respect to VPORTN. Connect a resist- or−divider from VPORTP to UVLO to VPORTNx to set an external UVLO threshold. AUX − 8 Input Auxiliary Pin. When this pin is pulled up, the Pass Switch is disabled and allows a supply transition from PSE to the rear auxiliary supply connected between VPORTP and RTN. NCLASS_AT 9 9 Output Active low enable signal used to verify high power operation VPORTP 10 10 Input Positive input power. Voltage with respect to VPORTN. Exposed Pad EP EP Ground Exposed pad should be connected to VPORTN. Table 2. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Units Conditions VPORTP Input power supply −0.3 72 V Voltage with respect to VPORTN RTN Analog ground supply 2 −0.3 72 V Pass−switch in off−state (voltage with respect to VPORTN) CLASS Analog output −0.3 72 V Voltage with respect to VPORTN INRUSH Analog output −0.3 3.6 V Voltage with respect to VPORTN AUX Analog input −0.3 72 V Voltage with respect to VPORTN UVLO Analog input −0.3 3.6 V Voltage with respect to VPORTN PGOOD Analog output −0.3 72 V Voltage with respect to RTN TA Ambient temperature −40 85 °C TJ Junction temperature − 125 °C TJ, TSD Junction temperature − 175 °C Thermal shutdown condition (Note 1) TSTG Storage Temperature −55 150 °C T(cid:3)JA Thermal Resistance, 50 °C/W DFN−10 Junction to Air (Note 2) ESD−HBM Human Body Model 2 kV per EIA−JESD22−A114 standard ESD−CDM Charged Device Model 500 V per ESD−STM5.3.1 standard ESD−MM Machine Model 200 V per EIA−JESD22−A115−A standard LU Latch−up ±100 mA per JEDEC Standard JESD78 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Tj−TSD allowed during error conditions only. It is assumed that this maximum temperature condition does not occur more than 1 hour cumulative during the useful life for reliability reasons. 2. Low (cid:3)JA is obtained with 2S2P test board (2 signal − 2 plane). High (cid:3)JA is obtained with double sideboard with minimum pad area and natural convection. Refer to Jedec JESD51 for details. The exposed pad must be connected to the VPORTN ground pin. www.onsemi.com 4

NCP1093, NCP1094 Recommended Operating Conditions Operating conditions define the limits for functional operation and parametric characteristics of the device. Note that the functionality of the device outside the operating conditions described in this section is not warranted. Operating outside the recommended operating conditions for extended periods of time may affect device reliability. Table 3. OPERATING CONDITIONS (All values are with respect to VPORTN unless otherwise noted.) Symbol Parameter Min Typ Max Units Conditions INPUT SUPPLY VPORT Input supply voltage 0 − 57 V VPORT = VPORTP – VPORTN SIGNATURE DETECTION Offset_det1 I(VPORTP) + I(RTN) − 2 5 (cid:4)A VPORTP = RTN = 1.9 V Rdet = 24.9 K(cid:2) Sleep_det1 I(VPORTP) + I(RTN) − 15 21 (cid:4)A VPORTP = RTN = 9.8 V Rdet = 24.9 K(cid:2) Offset_det2 I(VPORTP) + I(RTN) + I(DET) 73 77 81 (cid:4)A VPORTP = RTN = 1.9 V Rdet = 24.9 K(cid:2) Sleep_det2 I(VPORTP) + I(RTN) + I(DET) 390 400 412 (cid:4)A VPORTP = RTN = 9.8 V Rdet = 24.9 K(cid:2) CLASSIFICATION Vcl_on Classification current turn−on lower 9.8 11.3 13 V VPORTP rising threshold Vcl_off Classification current turn−off upper 21 − 24 V VPORTP rising threshold Vclass_reg Classification buffer output voltage − 9.8 − V 13 V < VPORTP < 21 V Icl_bias I(vportp) quiescent current during − 600 − (cid:4)A I(class) excluded classification 13 V < VPORTP < 21 V Iclass0 Class 0: Rclass 4420 (cid:2) (Note 3) 0 − 4 mA 13 V < VPORTP < 21 V Iclass1 Class 1: Rclass 953 (cid:2) (Note 3) 9 − 12 mA 13 V < VPORTP < 21 V Iclass2 Class 2: Rclass 549 (cid:2) (Note 3) 17 − 20 mA 13 V < VPORTP < 21 V Iclass3 Class 3: Rclass 357 (cid:2) (Note 3) 26 − 30 mA 13 V < VPORTP < 21 V Iclass4 Class 4: Rclass 255 (cid:2) (Note 3) 36 − 44 mA 13 V < VPORTP < 21 V V_mark Mark event voltage range 5.4 9.7 V VPORTP falling I_mark I(VPORTP) + I(Rdet) during mark event 0.5 − 2 mA 5.4 V ≤ VPORTP ≤ 9.7 V range dR_mark Input signature during mark event − − 12 k(cid:2) (Note 4) Vreset Classification Reset range 4.3 4.9 5.4 V VPORTP falling NCLASS_AT 2 EVENT CLASSIFICATION INDICATOR Inclass I(NCLASS_AT) sinking current − − 5 mA Nclass_low NCLASS_AT voltage output low − 0.2 0.5 V I(NCLASS_AT) = 2 mA UVLO − INTERNAL SETTING − NCP1093/94 Vuvlo_on Default turn on voltage − 37 40 V VPORTP rising Vuvlo_off Default turn off voltage 29.6 31 − V VPORTP falling Vhyst_int UVLO internal hysteresis − 6 − V Uvlo_filter UVLO On / Off filter time − 100 − (cid:4)s For information only 3. A tolerance of 1% on the Rclass resistor is included in the min/max values. 4. Measured with the 2 Point Measurement defined in the IEEE 802.3af standard with 5.4 V and 9.7 V the extreme values for V2 & V1. www.onsemi.com 5

NCP1093, NCP1094 Table 3. OPERATING CONDITIONS (All values are with respect to VPORTN unless otherwise noted.) Symbol Parameter Min Typ Max Units Conditions UVLO − EXTERNAL SETTING – NCP1093 ONLY Vuvlo_pr UVLO external programming range 25 − 50 V VPORTP rising Vuvlo_on2 External UVLO turn on voltage 1.14 1.2 1.26 V Vhyst_off2 External UVLO turn off voltage 0.95 1 1.05 V Uvlo_ipd UVLO internal pull down current − 2.5 − (cid:4)A AUXILIARY SUPPLY SETTING – NCP1094 ONLY Aux_h AUX input high level voltage 3.1 − V Aux_l AUX input low level voltage − − 0.6 V Aux_pd AUX internal pull down resistor 100 − − k(cid:2) For information only PASS−SWITCH AND CURRENT LIMITING Ron Pass−switch Rds−on − 0.6 1 (cid:2) Measured with I(RTN) = 200mA I_inrush Inrush current with Rinrush = 169 k(cid:2) 75 120 170 mA Measured at RTN−VPORTN = 3 V I_ilim Operating current limit with Rinrush = 610 680 800 mA Current limit threshold 169k(cid:2) POWER GOOD INDICATOR Vds_pgood_on RTN−VPORTN threshold voltage 0.8 1 1.2 V RTN−VPORTN falling required for power good status Vds_pgood_off RTN−VPORTN latchoff threshold 9 10 11 V RTN−VPORTN rising voltage Pgood_filter PGOOD filter time 100 (cid:4)s Rising and falling / for information only Ipgood I(PGOOD) sinking current − − 5 mA Vpgood_low PGOOD voltage output low − 0.2 0.5 V I(PGOOD) = 2 mA Voltage with respect to RTN CURRENT CONSUMPTION IvportP I(VPORTP) internal current − 600 900 (cid:4)A VPORTP = 48 V consumption THERMAL SHUTDOWN TSD Thermal shutdown threshold 150 − − °C Tj Tj = junction temperature Thyst Thermal hysteresis − 15 − °C Tj Tj = junction temperature THERMAL RATINGS Ta Ambient temperature −40 − 85 °C Tj Junction temperature − − 125 °C 3. A tolerance of 1% on the Rclass resistor is included in the min/max values. 4. Measured with the 2 Point Measurement defined in the IEEE 802.3af standard with 5.4 V and 9.7 V the extreme values for V2 & V1. www.onsemi.com 6

NCP1093, NCP1094 Description of Operation Under Voltage Lock Out (UVLO) The NCP1093/94 incorporate a fixed under voltage lock Powered Device Interface out (UVLO) circuit which monitors the input voltage and The integrated PD interface supports the IEEE 802.3af determines when to turn on the pass switch and charge the defined operating modes: detection signature, current dc−dc converter input capacitor before the power up of the source classification, undervoltage lockout, inrush and application. operating current limits. The following sections give an The NCP1093 offers a fixed or adjustable Vuvlo_on overview of these previous processes. threshold depending if the UVLO pin is used or not. In Figure5, the UVLO pin is strapped to ground and the Detection Vuvlo_on threshold is defined by the internal level. During the detection phase, the incremental equivalent resistance seen by the PSE through the cable must be in the IEEE 802.3af standard specification range (23.70 k(cid:2) to VPORTP 26.30k(cid:2)) for a PSE voltage from 2.7 V to 10.1 V. In order to compensate for the non−linear effect of the diode bridge and satisfy the specification at low PSE voltage, the VPORT UVLO NCP1093/94 present a suitable impedance in parallel with the 24.9 k(cid:2) Rdet external resistor. For some types of diodes (especially Schottky diodes), it may be necessary to adjust this external resistor. VPORTN1,2 The Rdet resistor has to be inserted between VPORTP and DET pins. During the detection phase, the DET pin is pulled Figure 5. Default Internal UVLO Configuration to ground and goes in high impedance mode (open−drain) (NCP1093 only) once the device exit this mode, reducing thus the current To define the UVLO threshold externally, the ULVO pin consumption on the cable. must be connected to the center of an external resistor Classification divider between VPORTP and VPORTN as shown in Once the PSE device has detected the PD device, the Figure6. classification process begins. In classification, the PD In order to guarantee the detection signature, the regulates a constant current source that is set by the external equivalent input resistor made of the Ruvlo1, Ruvlo2 and resistor RCLASS value on the CLASS pin. Figure 4 shows Rdet should be equal to 24.9 k(cid:2). the schematic overview of the classification block. The current source is defined as: VPORTP 9.8V Iclass(cid:2) Rdet Rclass Ruvlo1 VPORTP Class_enable VPORT DET VPORTP UVLO EN 1.2 V Ruvlo2 VPORTN1,2 NCP1093 CLASS 9.8 V Figure 6. Default Internal UVLO Configuration (NCP1093 only) For a Vuvlo_on desired turn−on voltage threshold, Ruvlo1 and Ruvlo2 can be calculated using the following equations: VPORTN 24.9k(cid:3)Rdet Ruvlo(cid:2) Rdet(cid:4)24.9k Figure 4. Classification Block Diagram The NCP1093/94 is able to detect a dual event with Ruvlo1(cid:5)Ruvlo2(cid:2)Ruvlo classification generated by a type 2 PSE, and flag it using its and Ruvlo2(cid:2) 1.2 (cid:3)Ruvlo nCLASS_AT open drain indicator. Vuvlo_on With: Power Mode Vuvlo_on: Desired Turn−On voltage threshold When the classification hand−shake is completed, the PSE and PD devices move into the operating mode. www.onsemi.com 7

NCP1093, NCP1094 Example for a Targeted Uvlo_on of 35 V: and the PD application against excessive transient current Let’s start with a Rdet of 30.1kΩ. This gives a Ruvlo of and failure on the dc−dc converter output. 144kΩ made with a Ruvlo2 of 4.99kΩ and a Ruvlo1 of Once the input supply reached the Vulvo_on level, the 140kΩ (closest values from E96 series). Note that there is charge of Cpd capacitor starts with a current limitation set to a pull down current of 2.5(cid:4)A typ on the UVLO. Assuming to the INRUSH level. When this capacitor is fully charged, the previous example, this pull down current will create a the current limit switches without any spikes from the inrush (non critical) systematic offset of 350mV on the Uvlon_on current to the operational current level and the power good level of 35V. indicator on PGOOD pin is turned on. The capacitor is The external UVLO hysteresis on the NCP1093 is about considered to be fully charged once the following conditions 15percent typical. are satisfied: 1.The drain−source voltage of the Pass Switch has Inrush and Operational Current Limitations decreased below the Vds_pgood_on level (typical Both inrush and operational current limit are defined by 1V) an external Rinrush resistor connected between INRUSH 2.The gate−source voltage of the Pass Switch is and VPORTN. The low inrush current limit allows smooth sufficiently high (above 2 V typical) which means charge of large dc−dc converter input capacitor by limiting the current in the pass switch has decreased below the power dissipation over the internal pass switch. In power the current limit. mode, the operational current limit protects the pass switch This mechanism is depicted in the following Figure 7. PGOOD Pgood_on Inrush current limit 0 Operational current limit 1 Pgood_on Delay 100 (cid:4)S V D & D VDDA1 VDDA1 A 1 1 V / 10 V detector 2 V RTN Vds_pgood comparator Vgs_pgood comparator RTN VPORTNx Pass Switch Sense Resistor Figure 7. Inrush and Operational Current Limitation Selection Mechanism The operational current limit and the power good PGOOD Indicator indicator stays active as long as RTN voltage stays below the The NCP1093/94 integrate a Power Good indicator vds_pgood_off threshold (10 V typical) and the input supply circuitry indicating the end of the dc−dc converter input stay above the Vulvo_off level. Therefore, fast and large capacitor charge, and the enabling of the operational current voltage step lower than 10 V are tolerated on the input limit. This indicator is implemented on the PGOOD pin without interruption of the converter controller. Higher which goes in open drain state when active and which is input transient will not affect the behavior if RTN does not pulled to ground during turn off. exceed 10 V for more than 100 (cid:4)S. Such input voltage steps A possible usage of this PGOOD pin is illustrated in may be introduced by a PSE which is switched to a higher Figure8. During the inrush phase, the converter controller power supply. In case RTN is still above 10 V after this delay, is forced in standby mode due to the PGOOD pin forcing low the power good is turned off and the pass switch current limit the under voltage lock out pin of the controller. Once the Cpd falls back to the inrush level. capacitor is fully charged, PGOOD goes in open drain state, allowing the start up sequence of the converter controller. www.onsemi.com 8

NCP1093, NCP1094 VPORTP Rdet VDD DET PGOOD UVLO NCP103x Rclass DC−DC Converter CLASS Cpd Controller NCP109x OVLO GATE Rinrush INRUSH VSS RTN VPORTN Figure 8. Power GOOD Implementation NCLASS_AT Dual Event Classification Indicator nCLASS_AT will be pulled low to RTN (ground connection The nCLASS AT active low open drain output pin should of the DC/DC controller converter). be used to notify to the microprocessor of the Powered Otherwise, nCLASS_AT will be in high impedance mode. Device that the PSE did a one or two event Hardware The following Scheme illustrates how the nCLass_AT pin Classification. may be configured with the processor of the Powered If a 2 event Hardware classification has been done and Device. An optocoupler is here used to guarantee to the full once the PD application power has been applied, the isolation between the cable and the application. VPORTP Rdet VDD VSUP DET PGOOD UVLO Type2PSE Rclass DC−DC Converter Powered Z_line Cline CLASS Cpd OVLO Controller GATE Application NCP1094 Rinrush INRUSH VBIAS VSS VNEG RTN AUX VPORTN nCLASS_AT To VAUX Figure 9. nClass AT indicator / possible implementation with the Powered Device As soon as the application is powered by the DC/DC and Hereafter are described several scenarios for which the after its initialization, the microprocessor will check if the NCP109x will not enable its nCLASS_AT pin during the PD interface detected a 2 event hardware classification by Powered Mode: reading its digital input (IN1 in this example). If this IN1 pin ♦ The PSE skipped the classification phase is low, the application knows that the type 2 PSE, and ♦ The PSE did a 1 event hardware classification (it therefore it can consume power till the level specified by the can be a type 1 PSE or a type 2 PSE with Layer 2 IEEE802.3at standard. Otherwise the application will have only) to perform a Layer 2 classification with the PSE. ♦ The PSE did a 2 event hardware classification but it didn’t well control the input voltage in the Mark voltage (it crossed the Reset range for example). www.onsemi.com 9

NCP1093, NCP1094 Auxiliary Supply To support application connected to non−PoE enabled In most of the cases, the auxiliary supply is connected networks and minimize the bill of materials, the NCP1094 between VPORTP and RTN with a serial diode between supports drawing power from an external supply and allows VPORTP and VAUX, as shown in Figure 10. simplified designs with PoE or auxiliary supply priorities. RJ−45 VAUX (+) VPORTP Data Rdet Pairs DB1 DET PGOOD Rclass e CLASS d To DC−DC n e p Converter Z_li Clin NCP1094 C Rinrush INRUSH RTN DB2 AUX Spare Pairs VPORTN VAUX (−) Figure 10. Auxiliary Supply Dominant PD Interface The NCP1094 offers an AUX input pin which turns off the and the application will remain supplied by the auxiliary pass switch when pulled high. This feature is useful for PD supply. The transition will happen without any power applications where the auxiliary supply has to be dominant conversion interruption since the PGOOD indicator stays over the PoE supply. When the auxiliary supply is inserted active (high impedance state). on a POE powered application, the pass switch Figure 11 depicts an other PD application where the POE disconnection will move the current path from the PSE to the supply is dominant over the VAUX supply. A diode D1 has rear auxiliary supply. Since the current delivered by the PSE been added in order to not corrupt the PD detection signature will goes below the DC MPS level (specified in IEEE when the dc−dc converter is supplied by VAUX. 802.3af/at standard), the PSE will disconnect the PoE−PD VAUX (+) RJ−45 D1 VPORTP Data Rdet Pairs DB1 DET PGOOD Rclass Z_line Cline CLASS NCP1094 Cpd TCoo nDvCe−rtDeCr Rinrush INRUSH RTN DB2 AUX Spare Pairs VPORTN VAUX (−) Figure 11. PoE Supply Dominant PD Interface www.onsemi.com 10

NCP1093, NCP1094 Thermal Shutdown Company or Product Inquiries The NCP1093/94 include a thermal shutdown which For more information about ON Semiconductor’s Power protect the device in case of high junction temperature. Once over Ethernet products visit our Web site at the thermal shutdown (TSD) threshold is exceeded, the http://www.onsemi.com. classification block, the pass switch and the PGOOD indicator are disabled. The NCP109X returns automatically to normal operation once the die temperature has fallen below the TSD low limit. www.onsemi.com 11

NCP1093, NCP1094 PACKAGE DIMENSIONS DFN10, 3x3, 0.5P CASE 485C ISSUE E D A NOTES: L L 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. B 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS L1 MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS ALTERNATE A−1 ALTERNATE A−2 THE TERMINALS. 5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG PIN ONE ÇÇÇ E ALTERDNEATTAE ITLE RAMINAL SOINDTEO E BDOGTET. OMMO LSDU RFLFAASCHEI NOGF TMEARYM NINOATL E bX.CEED 30 MICRONS REFERENCE CONSTRUCTIONS 6. FOR DEVICE OPN CONTAINING W OPTION, DETAIL A AND B ÇÇÇ ALTERNATE CONSTRUCTION ARE NOT APPLICABLE. WET- TABLE FLANK CONSTRUCTION IS DETAIL B AS SHOWN ON 2X 0.15 C ÇÇÇ SIDE VIEW OF PACKAGE. A3 EXPOSED Cu MOLD CMPD MILLIMETERS 2X 0.15 C ÉÇÉÇ ÉÉ DIM MIN MAX TOP VIEW A 0.80 1.00 ÇÇ ÇÇ A1 0.00 0.05 A1 A3 0.20 REF DETAIL B (A3) ALTERNATE B−1 ALTERNATE B−2 b 0.18 0.30 0.10 C D 3.00 BSC DETAIL B D2 2.40 2.60 A ALTERNATE E 3.00 BSC CONSTRUCTIONS E2 1.70 1.90 10X 0.08 C e 0.50 BSC SIDE VIEW A1 C SPELAATNIENG A3 K 0.19 TYP L 0.35 0.45 L1 0.00 0.03 DETAIL A D2 10XL A1 1 5 DETAIL B WETTABLE FLANK OPTION SOLDERING FOOTPRINT* CONSTRUCTION 2.64 10X E2 0.55 PACKAGE OUTLINE K 10 6 10Xb 1.90 3.30 e 0.10 C A B BOTTOM VIEW 0.05 C NOTE 3 10X 0.30 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative ◊ www.onsemi.com NCP1093/D 12

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