NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 Self-Supplied Monolithic Switcher for Low Standby- Power Offline SMPS www.onsemi.com The NCP101X series integrates a fixed−frequency current−mode controller and a 700 V MOSFET. Housed in a PDIP−7 or SOT−223 package, the NCP101X offers everything needed to build a rugged and MARKING low−cost power supply, including soft−start, frequency jittering, DIAGRAMS short−circuit protection, skip−cycle, a maximum peak current setpoint 4 and a Dynamic Self−Supply (no need for an auxiliary winding). 4 SOT−223 Unlike other monolithic solutions, the NCP101X is quiet by nature: CASE 318E AYW 101xy(cid:2) during nominal load operation, the part switches at one of the available 1 ST SUFFIX (cid:2) frequencies (65 − 100 − 130 kHz). When the current setpoint falls 1 below a given value, e.g. the output power demand diminishes, the IC automatically enters the so−called skip−cycle mode and provides excellent efficiency at light loads. Because this occurs at typically 1/4 PDIP−7 P101xAPyy of the maximum peak value, no acoustic noise takes place. As a result, CASE 626A AWL standby power is reduced to the minimum without acoustic noise 8 AP SUFFIX YYWWG generation. 1 1 Short−circuit detection takes place when the feedback signal fades away, e.g. in true short−circuit conditions or in broken Optocoupler x = Current Limit (0, 1, 2, 3, 4) cases. External disabling is easily done either simply by pulling the y = Oscillator Frequency A (65 kHz), B (100 kHz), C (130 kHz) feedback pin down or latching it to ground through an inexpensive yy = 06 (65 kHz), 10 (100 kHz), 13 (130 kHz) SCR for complete latched−off. Finally soft−start and frequency A = Assembly Location jittering further ease the designer task to quickly develop low−cost and WL = Wafer Lot YY, Y = Year robust offline power supplies. WW, W = Work Week For improved standby performance, the connection of an auxiliary (cid:2) or G = Pb−Free Package winding stops the DSS operation and helps to consume less than (Note: Microdot may be in either location) 100 mW at high line. In this mode, a built−in latched overvoltage protection prevents from lethal voltage runaways in case the ORDERING INFORMATION Optocoupler would brake. These devices are available in economical See detailed ordering and shipping information in the package 8−pin dual−in−line and 4−pin SOT−223 packages. dimensions section on page 21 of this data sheet. Features • Built−in 700 V MOSFET with Typical R of 11 (cid:2) • Auto−Recovery Internal Output Short−Circuit DSon and 22 (cid:2) Protection • • Large Creepage Distance Between High−Voltage Pins Below 100 mW Standby Power if Auxiliary Winding • Current−Mode Fixed Frequency Operation: is Used • 65 kHz – 100 kHz − 130 kHz Internal Temperature Shutdown • • Skip−Cycle Operation at Low Peak Currents Only: Direct Optocoupler Connection No Acoustic Noise! • SPICE Models Available for TRANsient Analysis • Dynamic Self−Supply, No Need for an Auxiliary • These are Pb−Free and Halide−Free Devices Winding • Internal 1.0 ms Soft−Start Typical Applications • • Latched Overvoltage Protection with Auxiliary Low Power AC/DC Adapters for Chargers • Winding Operation Auxiliary Power Supplies (USB, Appliances,TVs, etc.) • Frequency Jittering for Better EMI Signature © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: October, 2016 − Rev. 24 NCP1010/D

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 PIN CONNECTIONS SOT−223 PDIP−7 VCC 1 8 GND VCC 1 NC 2 7 GND FB 2 4 GND GND 3 DRAIN 3 FB 4 5 DRAIN (Top View) (Top View) Indicative Maximum Output Power from NCP1014 RDSon − Ip 230 Vac 100 − 250 Vac 11 (cid:2) − 450 mA DSS 14 W 6.0 W 11 (cid:2) − 450 mA Auxiliary Winding 19 W 8.0 W 1. Informative values only, with: Tamb = 50°C, Fswitching = 65 kHz, circuit mounted on minimum copper area as recommended. Vout + + 100−250 Vac 1 8 2 7 3 4 5 + NCP101X GND Figure 1. Typical Application Example Quick Selection Table NCP1010 NCP1011 NCP1012 NCP1013 NCP1014 RDSon [(cid:2)] 22 11 Ipeak [mA] 100 250 250 350 450 Freq [kHz] 65 100 130 65 100 130 65 100 130 65 100 130 65 100 www.onsemi.com 2

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 PIN FUNCTION DESCRIPTION Pin No. Pin No. (SOT−223) (PDIP−7) Pin Name Function Description 1 1 VCC Powers the Internal Circuitry This pin is connected to an external capacitor of typic- ally 10 (cid:3)F. The natural ripple superimposed on the VCC participates to the frequency jittering. For im- proved standby performance, an auxiliary VCC can be connected to Pin 1. The VCC also includes an active shunt which serves as an opto fail−safe protection. − 2 NC − − − 3 GND The IC Ground − 2 4 FB Feedback Signal Input By connecting an optocoupler to this pin, the peak current setpoint is adjusted accordingly to the output power demand. 3 5 Drain Drain Connection The internal drain MOSFET connection. − − − − − − 7 GND The IC Ground − 4 8 GND The IC Ground − VCC Startup Source Iref = 7.4 mA − VCC 1 Drain 8 GND IVCC + Vclamp* Rsense UVLO High when VCC (cid:2) 3 V S IVCC I? Management R 250 ns Q L.E.B. Reset NC 2 7 GND 4 V EMI Jittering 65, 100 or Set Flip−Flop Q 130 kHz Driver DCmax = 65% Clock Reset 18 k VCC Error flag armed? GND 3 − −+ + 0.5 V + Overload? - Startup Sequence Soft−Start Overload FB 4 Drain 5 Drain *Vclamp = VCCOFF + 200 mV (8.7 V Typical) Figure 2. Simplified Internal Circuit Architecture www.onsemi.com 3

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MAXIMUM RATINGS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating Symbol Value Unit ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Power Supply Voltage on all pins, except Pin 5 (Drain) VCC −0.3 to 10 V Drain Voltage − −0.3 to 700 V Drain Current Peak during Transformer Saturation NCP1010/11 IDS(pk) 550 mA NCP1012/13/14 1.0 A Maximum Current into Pin 1 when Activating the 8.7 V Active Clamp I_VCC 15 mA Thermal Characteristics °C/W P Suffix, Case 626A Junction−to−Lead R(cid:4)JL 9.0 Junction−to−Air, 2.0 oz (70 (cid:3)m) Printed Circuit Copper Clad R(cid:4)JA 0.36 Sq. Inch (2.32 Sq. Cm) 77 1.0 Sq. Inch (6.45 Sq. Cm) 60 ST Suffix, Plastic Package Case 318E Junction−to−Lead R(cid:4)JL 14 Junction−to−Air, 2.0 oz (70 (cid:3)m) Printed Circuit Copper Clad R(cid:4)JA 0.36 Sq. Inch (2.32 Sq. Cm) 74 1.0 Sq. Inch (6.45 Sq. Cm) 55 Maximum Junction Temperature TJmax 150 °C Storage Temperature Range − −60 to +150 °C ESD Capability, Human Body Model (All pins except HV) − 2.0 kV ESD Capability, Machine Model − 200 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 8.0 V unless otherwise noted.) Rating Pin Symbol Min Typ Max Unit SUPPLY SECTION AND VCC MANAGEMENT VCC Increasing Level at which the Current Source Turns−off 1 VCCOFF 7.9 8.5 9.1 V VCC Decreasing Level at which the Current Source Turns−on 1 VCCON 6.9 7.5 8.1 V Hysteresis between VCCOFF and VCCON 1 − − 1.0 − V VCC Decreasing Level at which the Latch−off Phase Ends 1 VCClatch 4.4 4.7 5.1 V VCC Decreasing Level at which the Internal Latch is Released 1 VCCreset − 3.0 − V Internal IC Consumption, MOSFET Switching at 65 kHz (Note 2) 1 ICC1 − 0.92 1.1 mA Internal IC Consumption, MOSFET Switching at 100 kHz (Note 2) 1 ICC1 − 0.95 1.15 mA Internal IC Consumption, MOSFET Switching at 130 kHz (Note 2) 1 ICC1 − 0.98 1.2 mA Internal IC Consumption, Latch−off Phase, VCC = 6.0 V 1 ICC2 − 290 − (cid:3)A Active Zener Voltage Positive Offset to VCCOFF 1 Vclamp 140 200 300 mV Latch−off Current 1 ILatch mA NCP1012/13/14 0°C < TJ < 125°C 6.3 7.4 9.2 −40°C < TJ < 125°C 5.8 7.4 9.2 NCP1010/11 0°C < TJ < 125°C 5.8 7.3 9.0 −40°C < TJ < 125°C 5.3 7.3 9.0 POWER SWITCH CIRCUIT Power Switch Circuit On−state Resistance 5 RDSon − (cid:2) NCP1012/13/14 (Id = 50 mA) TJ = 25°C 11 16 TJ = 125°C 19 24 NCP1010/11 (Id = 50 mA) TJ = 25°C 22 35 TJ = 125°C 38 50 2. See characterization curves for temperature evolution. 3. Adjust di/dt to reach Ipeak in 3.2 (cid:3)sec. 4. See characterization curves for temperature evolution. www.onsemi.com 4

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 8.0 V unless otherwise noted.) Rating Pin Symbol Min Typ Max Unit POWER SWITCH CIRCUIT Power Switch Circuit and Startup Breakdown Voltage 5 BVdss 700 − − V (ID(off) = 120 (cid:3)A, TJ = 25°C) Power Switch and Startup Breakdown Voltage Off−state Leakage Current IDS(OFF) (cid:3)A TJ = −40°C (Vds = 650 V) 5 − 70 120 TJ = 25°C (Vds = 700 V) 5 − 50 − TJ = 125°C (Vds = 700 V) 5 − 30 − Switching Characteristics (RL = 50 (cid:2), Vds Set for Idrain = 0.7 x Ilim) ns Turn−on Time (90%−10%) 5 ton − 20 − Turn−off Time (10%−90%) 5 toff − 10 − INTERNAL STARTUP CURRENT SOURCE High−voltage Current Source, VCC = 8.0 V 1 IC1 mA NCP1012/13/14 0°C < TJ < 125°C 5.0 8.0 10 −40°C < TJ < 125°C 5.0 8.0 11 NCP1010/11 0°C < TJ < 125°C 5.0 8.0 10.3 −40°C < TJ < 125°C 5.0 8.0 11.5 High−voltage Current Source, VCC = 0 1 IC2 − 10 − mA Minimum Start−up Drain Voltage (Istart = 0.5 mA, Vcc = Vcc(on) − 0.2 V) 5 Vstart(min) − 15 − V CURRENT COMPARATOR TJ = 25°C (Note 2) Maximum Internal Current Setpoint, NCP1010 (Note 3) 5 Ipeak (22) 90 100 110 mA Maximum Internal Current Setpoint, NCP1011 (Note 3) 5 Ipeak (22) 225 250 275 mA Maximum Internal Current Setpoint, NCP1012 (Note 3) 5 Ipeak (11) 225 250 275 mA Maximum Internal Current Setpoint, NCP1013 (Note 3) 5 Ipeak (11) 315 350 385 mA Maximum Internal Current Setpoint, NCP1014 (Note 3) 5 Ipeak (11) 405 450 495 mA Default Internal Current Setpoint for Skip−Cycle Operation, Percentage of − ILskip − 25 − % Max Ip Propagation Delay from Current Detection to Drain OFF State − TDEL − 125 − ns Leading Edge Blanking Duration − TLEB − 250 − ns INTERNAL OSCILLATOR Oscillation Frequency, 65 kHz Version, TJ = 25°C (Note 4) − fOSC 59 65 71 kHz Oscillation Frequency, 100 kHz Version, TJ = 25°C (Note 4) − fOSC 90 100 110 kHz Oscillation Frequency, 130 kHz Version, TJ = 25°C (Note 4) − fOSC 117 130 143 kHz Frequency Dithering Compared to Switching Frequency − fdither − (cid:3)3.3 − % (with active DSS) Maximum Duty−cycle − Dmax 62 67 72 % FEEDBACK SECTION Internal Pull−up Resistor 4 Rup − 18 − k(cid:2) Internal Soft−Start (Guaranteed by Design) − Tss − 1.0 − ms SKIP−CYCLE GENERATION Default Skip Mode Level on FB Pin 4 Vskip − 0.5 − V TEMPERATURE MANAGEMENT Temperature Shutdown − TSD 140 150 160 °C Hysteresis in Shutdown − − − 50 − °C 2. See characterization curves for temperature evolution. 3. Adjust di/dt to reach Ipeak in 3.2 (cid:3)sec. 4. See characterization curves for temperature evolution. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 5

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 TYPICAL CHARACTERISTICS −2 1.5 −3 1.4 −4 1.3 −5 1.2 A) −6 A) 1.1 m m IC1 ( −−87 CC1 ( 01..90 I −9 0.8 −10 0.7 −11 0.6 −12 0.5 −40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 3. IC1 @ V = 8.0 V, FB = 1.5 V Figure 4. ICC1 @ V = 8.0 V, FB = 1.5 V CC CC vs. Temperature vs. Temperature 0.40 9.0 0.38 8.9 0.36 8.8 0.34 mA) 0.32 F ( V ) 8.7 2 ( 0.30 OF 8.6 C C 0.28 C− I C 8.5 0.26 V 8.4 0.24 8.3 0.22 0.20 8.2 −40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 5. ICC2 @ V = 6.0 V, FB = Open Figure 6. V OFF, FB = 1.5 V vs. Temperature CC CC vs. Temperature 8.0 69 7.9 7.8 ON ( V) 777...567 YCLE (%) 68 C− C C 7.4 Y V UT 67 7.3 D 7.2 7.1 7.0 66 −40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. V ON, FB = 3.5 V vs. Temperature Figure 8. Duty Cycle vs. Temperature CC www.onsemi.com 6

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 TYPICAL CHARACTERISTICS 9.0 600 8.8 8.6 550 8.4 mA) 8.2 A) 500 ch ( 8.0 k (m at a _L 7.8 pe 450 NCP1014 I I 7.6 7.4 400 7.2 7.0 350 −40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 9. ILatch, FB = 1.5 V vs. Temperature Figure 10. Ipeak−RR, V = 8.0 V, FB = 3.5 V CC vs. Temperature 110 25 100 kHz 100 20 90 z) (cid:2)) 15 H (kC 80 (Son S D O R 10 f 70 65 kHz 5 60 50 0 −40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. Frequency vs. Temperature Figure 12. ON Resistance vs. Temperature, NCP1012/1013 22 V)15.25 E ( NCP1012 R G TO 21 TA15.00 S L RESI(cid:2)k)20 N VO14.75 NCP1010 P E ( AI UC R NAL PULL−RESISTAN1189 START−UP 1144..2550 NCP1014 TER 17 UM 14.00 N M I NI 16 MI13.75 −40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. R vs. Temperature Figure 14. Minimum Start−up Drain Voltage vs. up Temperature www.onsemi.com 7

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 APPLICATION INFORMATION Introduction No acoustic noise while operating: Instead of skipping The NCP101X offers a complete current−mode control cycles at high peak currents, the NCP101X waits until the solution (actually an enhanced NCP1200 controller section) peak current demand falls below a fixed 1/4 of the maximum together with a high−voltage power MOSFET in a limit. As a result, cycle skipping can take place without monolithic structure. The component integrates everything having a singing transformer … You can thus select cheap needed to build a rugged and low−cost Switch−Mode Power magnetic components free of noise problems. Supply (SMPS) featuring low standby power. The Quick SPICE model: A dedicated model to run transient Selection Table on Page 2, details the differences between cycle−by−cycle simulations is available but also an references, mainly peak current setpoints and operating averaged version to help close the loop. Ready−to−use frequency. templates can be downloaded in OrCAD’s PSpice, and No need for an auxiliary winding: ON Semiconductor INTUSOFT’s IsSpice4 from ON Semiconductor web site, Very High Voltage Integrated Circuit technology lets you NCP101X related section. supply the IC directly from the high−voltage DC rail. We call it Dynamic Self−Supply (DSS). This solution simplifies the Dynamic Self−Supply When the power supply is first powered from the mains transformer design and ensures a better control of the SMPS outlet, the internal current source (typically 8.0 mA) is in difficult output conditions, e.g. constant current biased and charges up the V capacitor from the drain pin. operations. However, for improved standby performance, CC Once the voltage on this V capacitor reaches the VCC an auxiliary winding can be connected to the V pin to CC OFF CC level (typically 8.5 V), the current source turns off and disable the DSS operation. pulses are delivered by the output stage: the circuit is awake Short−circuit protection: By permanently monitoring the and activates the power MOSFET. Figure 15 details the feedback line activity, the IC is able to detect the presence of internal circuitry. a short−circuit, immediately reducing the output power for a total system protection. Once the short has disappeared, the Vref OFF = 8.5 V controller resumes and goes back to normal operation. Drain Vref ON = 7.5 V Fail−safe optocoupler and OVP: When an auxiliary Vref Latch = 4.7 V* winding is connected to the V pin, the device stops its CC internal Dynamic Self−Supply and takes its operating power + Startup Source from the auxiliary winding. A 8.7 V active clamp is - connected between V and ground. In case the current CC injected in this clamp exceeds a level of 7.4 mA (typical), Internal Supply VCC the controller immediately latches off and stays in this position until V cycles down to 3.0 V (e.g. unplugging the CC converter from the wall). By adjusting a limiting resistor in + + series with the VCC terminal, it becomes possible to Vref VCCOFF CVCC +200 mV implement an overvoltage protection function, latching off (8.7 V Typ.) the circuit in case of broken optocoupler or feedback loop problems. *In fault condition Low standby−power: If SMPS naturally exhibits a good efficiency at nominal load, it begins to be less efficient when Figure 15. The Current Source Regulates V CC the output power demand diminishes. By skipping unneeded by Introducing a Ripple switching cycles, the NCP101X drastically reduces the power wasted during light load conditions. An auxiliary winding can further help decreasing the standby power to extremely low levels by invalidating the DSS operation. Typical measurements show results below 80 mW @ 230 Vac for a typical 7.0 W universal power supply. www.onsemi.com 8

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 8.5 V 8.00 Vcc 7.5 V 6.00 4.00 Device Internally 2.00 Pulses 0 Startup Period Figure 16. The Charge/Discharge Cycle Over a 10 (cid:2)F V Capacitor CC The protection burst duty−cycle can easily be computed for the presence of the error flag every time V crosses CC through the various timing events as portrayed by Figure 18. VCC . If the error flag is low (peak limit not active) then ON Being loaded by the circuit consumption, the voltage on the IC works normally. If the error signal is active, then the the V capacitor goes down. When the DSS controller NCP101X immediately stops the output pulses, reduces its CC detects that V has reached 7.5 V (VCC ), it activates the internal current consumption and does not allow the startup CC ON internal current source to bring V toward 8.5 V and stops source to activate: V drops toward ground until it reaches CC CC again: a cycle takes place whose low frequency depends on the so−called latch−off level, where the current source the V capacitor and the IC consumption. A 1.0 V ripple activates again to attempt a new restart. When the error is CC takes place on the V pin whose average value equals gone, the IC automatically resumes its operation. If the CC (VCC + VCC )/2. Figure 16 portrays a typical default is still there, the IC pulses during 8.5 V down to 7.5 V OFF ON operation of the DSS. and enters a new latch−off phase. The resulting burst As one can see, the V capacitor shall be dimensioned to operation guarantees a low average power dissipation and CC offer an adequate startup time, i.e. ensure regulation is lets the SMPS sustain a permanent short−circuit. Figure 17 reached before V crosses 7.5 V (otherwise the part enters shows the corresponding diagram. CC the fault condition mode). If we know that (cid:5)V = 1.0 V and ICC1 (max) is 1.1 mA (for instance we selected an 11 (cid:2) Current Sense device switching at 65 kHz), then the V capacitor can Information CC 4 V ICC1·tstartup be calculated using: C(cid:4) (eq. 1) . Let’s (cid:5)V suppose that the SMPS needs 10 ms to startup, then we will + FB calculate C to offer a 15 ms period. As a result, C should be Division − To greater than 20 (cid:3)F thus the selection of a 33 (cid:3)F/16 V Latch capacitor is appropriate. Max VCC VCCON Reset Signal Ip Short Circuit Protection The internal protection circuitry involves a patented arrangement that permanently monitors the assertion of an Flag Clamp internal error flag. This error flag is, in fact, a signal that Active? instructs the controller that the internal maximum peak current limit is reached. This naturally occurs during the startup period (Vout is not stabilized to the target value) or when the optocoupler LED is no longer biased, e.g. in a Figure 17. Simplified NCP101X Short−Circuit short−circuit condition or when the feedback network is Detection Circuitry broken. When the DSS normally operates, the logic checks www.onsemi.com 9

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 Tsw 1 V Ripple Tstart TLatch Latch−off Level Figure 18. NCP101X Facing a Fault Condition (Vin = 150 Vdc) The rising slope from the latch−off level up to 8.5 V Vds(t) (cid:5)V1·C is expressed by: Tstart(cid:5) . The time during which IC1 toff (cid:5)V2·C the IC actually pulses is given by tsw(cid:5) . Vr ICC1 Vin dt Finally, the latch−off time can be derived (cid:5)V3·C using the same formula topology: TLatch(cid:5) . ICC2 From these three definitions, the burst duty−cycle can be computed: dc(cid:5) Tsw (eq. 2) . Tstart(cid:6)Tsw(cid:6)TLatch ton t dc(cid:5)ICC1·(cid:7)(cid:5)V2(cid:5)(cid:6)V2(cid:5)V1(cid:6) (cid:5)V3(cid:8) (eq. 3) . Feeding the Tsw ICC1 IC1 ICC2 equation with values extracted from the parameter section Figure 19. A typical drain−ground waveshape gives a typical duty−cycle of 13%, precluding any lethal where leakage effects are not accounted for. thermal runaway while in a fault condition. By looking at Figure 19, the average result can easily be DSS Internal Dissipation derived by additive square area calculation: The Dynamic Self−Supplied pulls energy out from the drain pin. In Flyback−based converters, this drain level can (cid:2)Vds(t)(cid:9)(cid:5)Vin·(1(cid:10)d)(cid:6)Vr· toff (eq. 5) Tsw easily go above 600 V peak and thus increase the stress on the By developing Equation 5, we obtain: DSS startup source. However, the drain voltage evolves with time and its period is small compared to that of the DSS. As (cid:2)Vds(t)(cid:9)(cid:5)Vin(cid:10)Vin· ton (cid:6)Vr· toff (eq. 6) Tsw Tsw a result, the averaged dissipation, excluding capacitive losses, can be derived by: PDSS(cid:5)ICC1· (cid:2)Vds(t)(cid:9). (eq. 4) . toff can be expressed by: toff(cid:5)Ip· Lp (eq. 7) where ton Figure 19 portrays a typical drain−ground waveshape where Vr Lp leakage effects have been removed. can be evaluated by: ton(cid:5)Ip· (eq. 8) . Vin www.onsemi.com 10

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 Plugging Equations 7 and 8 into Equation 6 leads to Itrip is the current corresponding to the nominal operation. (cid:2)Vds(t)(cid:9)(cid:5)Vin and thus, PDSS(cid:5)Vin(cid:11)ICC1 (eq. 9) . It must be selected to avoid false tripping in overshoot The worse case occurs at high line, when Vin equals conditions. 370 Vdc. With ICC1 = 1.1 mA (65 kHz version), we can ICC1 is the controller consumption. This number slightly expect a DSS dissipation around 407 mW. If you select a decreases compared to ICC1 from the spec since the part in higher switching frequency version, the ICC1 increases and standby almost does not switch. it is likely that the DSS consumption exceeds that number. VCC is the level above which Vaux must be maintained In that case, we recommend to add an auxiliary winding in ON to keep the DSS in the OFF mode. It is good to shoot around order to offer more dissipation room to the power MOSFET. 8.0 V in order to offer an adequate design margin, e.g. to not Please read application note AND8125/D, “Evaluating reactivate the startup source (which is not a problem in itself the Power Capability of the NCP101X Members” to help in if low standby power does not matter). selecting the right part/configuration for your application. Since Rlimit shall not bother the controller in standby, e.g. keep Vaux to around 8.0 V (as selected above), we purposely Lowering the Standby Power with an Auxiliary Winding The DSS operation can bother the designer when its select a Vnom well above this value. As explained before, dissipation is too high and extremely low standby power is experience shows that a 40% decrease can be seen on a must. In both cases, one can connect an auxiliary winding auxiliary windings from nominal operation down to standby to disable the self−supply. The current source then ensures mode. Let’s select a nominal auxiliary winding of 20 V to the startup sequence only and stays in the off state as long as offer sufficient margin regarding 8.0 V when in standby V does not drop below VCC or 7.5 V. Figure 20 shows (Rlimit also drops voltage in standby…). Plugging the CC ON that the insertion of a resistor (Rlimit) between the auxiliary values in Equation 10 gives the limits within which Rlimit DC level and the V pin is mandatory to not damage the shall be selected: CC internal 8.7 V active Zener diode during an overshoot for 20(cid:10)8.7(cid:12)Rlimit(cid:12)12(cid:10)8, that is to say: instance (absolute maximum current is 15 mA) and to 6.3m 1.1m (eq. 11) implement the fail−safe optocoupler protection as offered by 1.8k(cid:2)Rlimit(cid:2)3.6k the active clamp. Please note that there cannot be bad If we design a power supply delivering 12 V, then the ratio interaction between the clamping voltage of the internal between auxiliary and power must be: 12/20 = 0.6. The OVP Zener and VCC since this clamping voltage is actually OFF latch will activate when the clamp current exceeds 6.3 mA. built on top of VCC with a fixed amount of offset OFF This will occur when Vaux increases to: 8.7 V + 1.8 k x (200 mV typical). (6.4m + 1.1m) = 22.2 V for the first boundary or 8.7 V + Self−supplying controllers in extremely low standby 3.6 k x (6.4m +1.1m) = 35.7 V for second boundary. On the applications often puzzles the designer. Actually, if a SMPS power output, it will respectively give 22.2 x 0.6 = 13.3 V operated at nominal load can deliver an auxiliary voltage of and 35.7 x 0.6 = 21.4 V. As one can see, tweaking the Rlimit an arbitrary 16 V (Vnom), this voltage can drop to below value will allow the selection of a given overvoltage output 10 V (Vstby) when entering standby. This is because the level. Theoretically predicting the auxiliary drop from recurrence of the switching pulses expands so much that the nominal to standby is an almost impossible exercise since low frequency refueling rate of the V capacitor is not CC many parameters are involved, including the converter time enough to keep a constant auxiliary voltage. Figure 21 constants. Fine tuning of Rlimit thus requires a few portrays a typical scope shot of a SMPS entering deep iterations and experiments on a breadboard to check Vaux standby (output unloaded). So care must be taken when variations but also output voltage excursion in fault. Once calculating Rlimit 1) to not trigger the V over current CC properly adjusted, the fail−safe protection will preclude any latch [by injecting 6.3 mA (min. value) into the active lethal voltage runaways in case a problem would occur in the clamp] in normal operation but 2) not to drop too much feedback loop. voltage over Rlimit when entering standby. Otherwise the When an OVP occurs, all switching pulses are DSS could reactivate and the standby performance would permanently disabled, the output voltage thus drops to zero. degrade. We are thus able to bound Rlimit between two The V cycles up and down between 8.5–4.7 V and stays CC equations: in this state until the user unplugs the power supply and Vnom(cid:10)Vclamp(cid:12)Rlimit(cid:12)Vstby(cid:10)VCCON (eq. 10) forces VCC to drop below 3.0 V (VCCreset). Below this Itrip ICC1 value, the internal OVP latch is reset and when the high Where: voltage is reapplied, a new startup sequence can take place in an attempt to restart the converter. Vnom is the auxiliary voltage at nominal load. Vstdby is the auxiliary voltage when standby is entered. www.onsemi.com 11

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 Drain VCCON = 8.5 V VCCOFF = 7.5 V - + Startup Source + VCC Rlimit D1 + − + + + Vclamp = 8.7 V typ. CVcc Caux Laux Permanent + Latch - + I > 7.4m (Typ.) Ground Figure 20. A more detailed view of the NCP101X offers better insight on how to properly wire an auxiliary winding. (cid:9)30 ms Figure 21. The burst frequency becomes so low that it is difficult to keep an adequate level on the auxiliary V . . . CC Lowering the Standby Power with Skip−Cycle which is excited by the skipping pulses. A possible Skip−cycle offers an efficient way to reduce the standby solution, successfully implemented in the NCP1200 series, power by skipping unwanted cycles at light loads. also authorizes skip−cycle but only when the power However, the recurrent frequency in skip often enters the demand has dropped below a given level. At this time, the audible range and a high peak current obviously generates peak current is reduced and no noise can be heard. acoustic noise in the transformer. The noise takes its origins Figure 22 pictures the peak current evolution of the in the resonance of the transformer mechanical structure NCP101X entering standby. www.onsemi.com 12

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 100% Peak current at nominal power Skip−cycle current limit 25% Figure 22. Low Peak Current Skip−Cycle Guarantees Noise−Free Operation Full power operation involves the nominal switching the benefit to artificially reduce the measurement noise on frequency and thus avoids any noise when running. a standard EMI receiver and pass the tests more easily. The Experiments carried on a 5.0 W universal mains board EMI sweep is implemented by routing the V ripple CC unveiled a standby power of 300 mW @ 230 Vac with the (induced by the DSS activity) to the internal oscillator. As a DSS activated and dropped to less than 100 mW when an result, the switching frequency moves up and down to the auxiliary winding is connected. DSS rhythm. Typical deviation is (cid:3)3.3% of the nominal frequency. With a 1.0 V peak−to−peak ripple, the frequency Frequency Jittering for Improved EMI Signature will equal 65 kHz in the middle of the ripple and will By sweeping the switching frequency around its nominal increase as V rises or decrease as V ramps down. CC CC value, it spreads the energy content on adjacent frequencies Figure 23 portrays the behavior we have adopted. rather than keeping it centered in one single ray. This offers VCCOFF VCC Ripple 67.15 kHz 65 kHz 62.85 kHz Internal Sawtooth VCCON Figure 23. The V ripple is used to introduce a frequency jittering on the internal oscillator sawtooth. CC Here, a 65 kHz version was selected. www.onsemi.com 13

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 Soft−Start The NCP101X features an internal 1.0 ms soft−start (OCP) sequence. Every restart attempt is followed by a activated during the power on sequence (PON). As soon as soft−start activation. Generally speaking, the soft−start will V reaches VCC , the peak current is gradually be activated when V ramps up either from zero (fresh CC OFF CC increased from nearly zero up to the maximum internal power−on sequence) or 4.7 V, the latch−off voltage clamping level (e.g. 350 mA). This situation lasts 1.0 ms occurring during OCP. Figure 24 portrays the soft−start and further to that time period, the peak current limit is behavior. The time scales are purposely shifted to offer a blocked to the maximum until the supply enters regulation. better zoom portion. The soft−start is also activated during the over current burst VCC 8.5 V 0 V (Fresh PON) or 4.7 V (Overload) Current Max Ip Sense 1.0 ms Figure 24. Soft−Start is activated during a startup sequence or an OCP condition. Non−Latching Shutdown In some cases, it might be desirable to shut off the part and ground. By pulling FB below the internal skip level temporarily and authorize its restart once the default has (Vskip), the output pulses are disabled. As soon as FB is disappeared. This option can easily be accomplished relaxed, the IC resumes its operation. Figure 25 depicts the through a single NPN bipolar transistor wired between FB application example. 1 8 2 7 3 4 5 Drain ON/OFF + CVcc Figure 25. A non−latching shutdown where pulses are stopped as long as the NPN is biased. www.onsemi.com 14

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 Full Latching Shutdown Other applications require a full latching shutdown, e.g. voltage, the NPN biases the PNP and fires the equivalent when an abnormal situation is detected (overtemperature SCR, permanently bringing down the FB pin. The or overvoltage). This feature can easily be implemented switching pulses are disabled until the user unplugs the through two external transistors wired as a discrete SCR. power supply. When the OVP level exceeds the Zener breakdown Rhold 12 k OVP 1 8 2 7 10 k BAT54 3 4 5 Drain + CVcc 10 k Figure 26. Two Bipolars Ensure a Total Latch−Off of the SMPS in Presence of an OVP Rhold ensures that the SCR stays on when fired. The bias maximum power the device can thus evacuate is: current flowing through Rhold should be small enough to let Pmax(cid:5)TJmax(cid:10)Tambmax (eq. 12) which gives around the VCC ramp up (8.5 V) and down (7.5 V) when the SCR R(cid:4)JA is fired. The NPN base can also receive a signal from a 1.0 W for an ambient of 50°C. The losses inherent to the temperature sensor. Typical bipolars can be MMBT2222 MOSFET RDSon can be evaluated using the following and MMBT2907 for the discrete latch. The MMBT3946 formula: Pmos(cid:5)1 ·Ip2·d·RDSon (eq. 13) , where Ip features two bipolars NPN+PNP in the same package and 3 is the worse case peak current (at the lowest line input), d is could also be used. the converter operating duty−cycle and R , the DSon Power Dissipation and Heatsinking MOSFET resistance for TJ = 100°C. This formula is only The NCP101X welcomes two dissipating terms, the DSS valid for Discontinuous Conduction Mode (DCM) current−source (when active) and the MOSFET. Thus, operation where the turn−on losses are null (the primary Ptot = P + P . When the PDIP−7 package is current is zero when you restart the MOSFET). Figure 27 DSS MOSFET surrounded by copper, it becomes possible to drop its gives a possible layout to help drop the thermal resistance. thermal resistance junction−to−ambient, R(cid:4)JA down When measured on a 35 (cid:3)m (1 oz) copper thickness PCB, to 75°C/W and thus dissipate more power. The we obtained a thermal resistance of 75°C/W. Figure 27. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction−to−Ambient www.onsemi.com 15

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 Design Procedure The design of an SMPS around a monolithic device does and a MOSFET. However, one needs to be aware of certain not differ from that of a standard circuit using a controller characteristics specific of monolithic devices: 350 250 150 50.0 > 0 !! −50.0 1.004M 1.011M 1.018M 1.025M 1.032M Figure 28. The Drain−Source Wave Shall Always be Positive . . . 1.In any case, the lateral MOSFET body−diode shall Ctot is the total capacitance at the drain node never be forward biased, either during startup (which is increased by the capacitor wired between (because of a large leakage inductance) or in drain and source), N the Np:Ns turn ratio, Vout the normal operation as shown by Figure 28. output voltage, Vf the secondary diode forward As a result, the Flyback voltage which is reflected on the drop and finally, Ip the maximum peak current. drain at the switch opening cannot be larger than the input Worse case occurs when the SMPS is very close to voltage. When selecting components, you thus must adopt regulation, e.g. the Vout target is almost reached a turn ratio which adheres to the following equation: and Ip is still pushed to the maximum. N·(Vout(cid:6)Vf)(cid:2)Vinmin (eq. 14) . For instance, if Taking into account all previous remarks, it becomes operating from a 120 V DC rail, with a delivery of 12 V, we possible to calculate the maximum power that can be can select a reflected voltage of 100 Vdc maximum: transferred at low line. 120–100 > 0. Therefore, the turn ratio Np:Ns must be When the switch closes, Vin is applied across the primary smaller than 100/(12 + 1) = 7.7 or Np:Ns < 7.7. We will see inductance Lp until the current reaches the level imposed by later on how it affects the calculation. the feedback loop. The duration of this event is called the ON 2.A current−mode architecture is, by definition, time and can be defined by: sensitive to subharmonic oscillations. Lp·Ip Subharmonic oscillations only occur when the ton(cid:5) (eq. 16) Vin SMPS is operating in Continuous Conduction At the switch opening, the primary energy is transferred Mode (CCM) together with a duty−cycle greater to the secondary and the flyback voltage appears across than 50%. As a result, we recommend to operate Lp, resetting the transformer core with a slope of the device in DCM only, whatever duty−cycle it N·(Vout(cid:6)Vf) implies (max = 65%). However, CCM operation . toff, the OFF time is thus: Lp with duty−cycles below 40% is possible. Lp·Ip 3.Lateral MOSFETs have a poorly dopped toff(cid:5) (eq. 17) N·(Vout(cid:6)Vf) body−diode which naturally limits their ability to sustain the avalanche. A traditional RCD clamping If one wants to keep DCM only, but still need to pass the network shall thus be installed to protect the maximum power, we will not allow a dead−time after the MOSFET. In some low power applications, core is reset, but rather immediately restart. The switching a simple capacitor can also be used since time can be expressed by: (cid:13) (cid:7) (cid:8) Vdrain max(cid:5)Vin(cid:6)N·(Vout(cid:6)Vf)(cid:6)Ip· CLtoft Tsw(cid:5)toff(cid:6)ton(cid:5)Lp·Ip· V1in(cid:6)N·(Vo1ut(cid:6)Vf) (eq. 15) , where Lf is the leakage inductance, (eq. 18) www.onsemi.com 16

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 The Flyback transfer formula dictates that: Example 1. A 12 V 7.0 W SMPS operating on a large Po(cid:6)ut(cid:5)1 ·Lp·Ip2·Fsw (eq. 19) which, by extracting mains with NCP101X: 2 Vin = 100 Vac to 250 Vac or 140 Vdc to 350 Vdc once Ip and plugging into Equation 19, leads to: (cid:13) (cid:7) (cid:8) rectified, assuming a low bulk ripple Tsw(cid:5)Lp 2·Pout · 1 (cid:6) 1 Efficiency = 80% (cid:6)·Fsw·Lp Vin N·(Vout(cid:6)Vf) Vout = 12 V, Iout = 580 mA (eq. 20) Fswitching = 65 kHz Extracting Lp from Equation 20 gives: (Vin·Vr)2·(cid:6) Ip max = 350 mA – 10% = 315 mA Lpcritical(cid:5) 2·Fsw·[Pout·(Vr2(cid:6)2·Vr·Vin(cid:6)Vin2)] Applying the above equations leads to: (eq. 21) , with Vr = N . (Vout + Vf) and (cid:6) the efficiency. Selected maximum reflected voltage = 120 V If Lp critical gives the inductance value above which with Vout = 12 V, secondary drop = 0.5 V → Np:Ns = 1:0.1 DCM operation is lost, there is another expression we can write to connect Lp, the primary peak current bounded by Lp critical = 3.2 mH the NCP101X and the maximum duty−cycle that needs to Ip = 292 mA stay below 50%: Duty−cycle worse case = 50% DCmax·Vinmin·Tsw Lpmax(cid:5) (eq. 22) where Vinmin Idrain RMS = 119 mA Ipmax corresponds to the lowest rectified bulk voltage, hence the PMOSFET = 354 mW at RDSon = 24 (cid:2) (TJ > 100°C) longest ton duration or largest duty−cycle. Ip max is the P = 1.1 mA x 350 V = 385 mW, if DSS is used DSS available peak current from the considered part, e.g. 350 mA Secondary diode voltage stress = (350 x 0.1) + 12 = 47 V typical for the NCP1013 (however, the minimum value of (e.g. a MBRS360T3, 3.0 A/60 V would fit) this parameter shall be considered for reliable evaluation). Combining Equations 21 and 22 gives the maximum Example 2. A 12 V 16 W SMPS operating on narrow theoretical power you can pass respecting the peak current European mains with NCP101X: capability of the NCP101X, the maximum duty−cycle and Vin = 230 Vac (cid:3) 15%, 276 Vdc for Vin min to 370 Vdc the discontinuous mode operation: once rectified Pmax:(cid:5)Tsw2·Vinmin2·Vr2·(cid:6)· Efficiency = 80% Fsw Vout = 12 V, Iout = 1.25 A (2·Lpmax·Vr2(cid:6)4·Lpmax·Vr·Vinmin Fswitching = 65 kHz (cid:6)2·Lpmax·Vinmin2) (eq. 23) Ip max = 350 mA – 10% = 315 mA From Equation 22 we obtain the operating duty−cycle Applying the equations leads to: Ip·Lp d(cid:5) (eq. 24) which lets us calculate the RMS Vin·Tsw Selected maximum reflected voltage = 250 V current circulating in the MOSFET: (cid:13) with Vout = 12 V, secondary drop = 0.5 V → Np:Ns = 1:0.05 IdRMS(cid:5)Ip· d (eq. 25) . From this equation, we Lp = 6.6 mH 3 obtain the average dissipation in the MOSFET: Ip = 0.305 mA Pavg(cid:5)1 ·Ip2·d·RDSon (eq. 26) to which switching Duty−cycle worse case = 0.47 3 losses shall be added. Idrain RMS = 121 mA If we stick to Equation 23, compute Lp and follow the P = 368 mW at R = 24 (cid:2) (T > 100°C) MOSFET DSon J above calculations, we will discover that a power supply P = 1.1 mA x 370 V = 407 mW, if DSS is used below an DSS built with the NCP101X and operating from a 100 Vac line ambient of 50°C. minimum will not be able to deliver more than 7.0 W Secondary diode voltage stress = (370 x 0.05) + 12 = 30.5 V continuous, regardless of the selected switching frequency (e.g. a MBRS340T3, 3.0 A/40 V) (however the transformer core size will go down as Please note that these calculations assume a flat DC rail Fswitching is increased). This number increases whereas a 10 ms ripple naturally affects the final voltage significantly when operated from a single European mains available on the transformer end. Once the Bulk capacitor has (18 W). Application note AND8125/D, “Evaluating the been selected, one should check that the resulting ripple (min Power Capability of the NCP101X Members” details how Vbulk?) is still compatible with the above calculations. As an to assess the available power budget from all the NCP101X example, to benefit from the largest operating range, a 7.0 W series. board was built with a 47 (cid:3)F bulk capacitor which ensured discontinuous operation even in the ripple minimum waves. www.onsemi.com 17

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 MOSFET Protection As in any Flyback design, it is important to limit the BV which is 700 V. Figure 29 presents possible DSS drain excursion to a safe value, e.g. below the MOSFET implementations: HV HV HV Rclamp Cclamp Dz D D 1 8 1 8 1 8 2 7 2 7 2 7 3 3 3 4 5 4 5 4 5 ++ + + CVcc CVcc CVcc NCP101X NCP101X NCP101X C A B C Figure 29. Different Options to Clamp the Leakage Spike Figure 29A: The simple capacitor limits the voltage Figure 29C: This option is probably the most expensive of according to Equation 15. This option is only valid for low all three but it offers the best protection degree. If you need power applications, e.g. below 5.0 W, otherwise chances a very precise clamping level, you must implement a Zener exist to destroy the MOSFET. After evaluating the leakage diode or a TVS. There are little technology differences inductance, you can compute C with Equation 15. Typical behind a standard Zener diode and a TVS. However, the die values are between 100 pF and up to 470 pF. Large area is far bigger for a transient suppressor than that of Zener. capacitors increase capacitive losses. A 5.0 W Zener diode like the 1N5388B will accept 180 W peak power if it lasts less than 8.3 ms. If the peak current in Figure 29B: This diagram illustrates the most standard the worse case (e.g. when the PWM circuit maximum circuitry called the RCD network. Rclamp and Cclamp are calculated using the following formulas: current limit works) multiplied by the nominal Zener voltage exceeds these 180 W, then the diode will be 2·Vclamp·(Vclamp(cid:10)(Vout(cid:6)Vfsec)·N) Rclamp(cid:5) destroyed when the supply experiences overloads. A Lleak·Ip2·Fsw transient suppressor like the P6KE200 still dissipates 5.0 W (eq. 27) of continuous power but is able to accept surges up to 600 W Cclamp(cid:5) Vclamp (eq. 28) @ 1.0 ms. Select the Zener or TVS clamping level between Vripple·Fsw·Rclamp 40 to 80 V above the reflected output voltage when the Vclamp is usually selected 50−80 V above the reflected supply is heavily loaded. value N x (Vout + Vf). The diode needs to be a fast one and a MUR160 represents a good choice. One major drawback of the RCD network lies in its dependency upon the peak current. Worse case occurs when Ip and Vin are maximum and Vout is close to reach the steady−state value. www.onsemi.com 18

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 Typical Application Examples A 6.5 W NCP1012−Based Flyback Converter Figure 30 shows a converter built with a NCP1012 feedback. This configuration was selected for cost reasons delivering 6.5 W from a universal input. The board uses the and a more precise circuitry can be used, e.g. based on a Dynamic Self−Supply and a simplified Zener−type TL431: D6 B150 1 TR1 8 7 D1 D2 E3 R2 C1 1N4007 1N4007 D5 470 (cid:3)/25 V 150 k 2.2 nF U160 6 2 4 5 1 E1 R1 10 (cid:3)/400 V IC1 ZD1 47 R NCP1012 11 V J2 1 1 5 IC2 CZM5/2 VCC HV 22 PC817 R3 2 44 GND FB 100 R E2 3 J1 D3 D4 10 (cid:3)/16 V 7 GND 8 R4 CEE7.5/2 1N4007 1N4007 GND GND 180 R C2 2n2/Y Figure 30. An NCP1012−Based Flyback Converter Delivering 6.5 W The converter built according to Figure 31 layouts, gave the following results: • Efficiency at Vin = 100 Vac and Pout = 6.5 W = 75.7% • Efficiency at Vin = 230 Vac and Pout = 6.5 W = 76.5% Figure 31. The NCP1012−Based PCB Layout . . . and its Associated Component Placement www.onsemi.com 19

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 A 7.0 W NCP1013−based Flyback Converter power since an auxiliary winding is used, the DSS is Featuring Low Standby Power disabled, and thus offering more room for the MOSFET. In Figure 32 depicts another typical application showing a this application, the feedback is made via a TLV431 whose NCP1013−65 kHz operating in a 7.0 W converter up to low bias current (100 (cid:3)A min) helps to lower the no−load 70°C of ambient temperature. We can increase the output standby power. Vbulk 1N4148 D4 R4 22 C8 R7 D2 L2 10 nF 100 k/ MBRS360T3 22 (cid:3)H 12 V @ 400 V 1 W 0.6 A T1 +C10 + + +100 (cid:3)F/16 V Aux 33 (cid:3)F/25 V C7 GND T1 C6 C8 470 (cid:3)F/16 V D3 R2 MUR160 3.3 k R3 NCP1013P06 C2 1 k + 47 (cid:3)F/ 1 VCC GND 8 R5 450 V 39 k 2 NC GND 7 3 GND 4 FB D 5 +100 (cid:3)F/10 V C4 C3 C9 1 nF IC1 100 nF SFH6156−2 IC2 R6 TLV431 4.3 k C5 2.2 nF Y1 Type Figure 32. A Typical Converter Delivering 7.0 W from a Universal Mains Measurements have been taken from a demonstration For a quick evaluation of Figure 32 application example, board implementing the diagram in Figure 32 and the the following transformers are available from Coilcraft: following results were achieved, with either the auxiliary A9619−C, Lp = 3.0 mH, Np:Ns = 1:0.1, 7.0 W winding in place or through the Dynamic Self−Supply: application on universal mains, including auxiliary winding, Vin = 230 Vac, auxiliary winding, Pout = 0, Pin = 60 mW NCP1013−65kHz. Vin = 100 Vac, auxiliary winding, Pout = 0, Pin = 42 mW A0032−A, Lp = 6.0 mH, Np:Ns = 1:0.055, 10 W application on European mains, DSS operation only, Vin = 230 Vac, Dynamic Self−Supply, Pout = 0, NCP1013−65 kHz. Pin = 300 mW Coilcraft Vin = 100 Vac, Dynamic Self−Supply, Pout = 0, 1102 Silver Lake Road Pin = 130 mW CARY IL 60013 Pout = 7.0 W, (cid:6) = 81% @ 230 Vac, with auxiliary winding Email: info@coilcraft.com Pout = 7.0 W, (cid:6) = 81.3 @ 100 Vac, with auxiliary winding Tel.: 847−639−6400 Fax.: 847−639−1469 www.onsemi.com 20

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 ORDERING INFORMATION Frequency RDSon Device Order Number (kHz) Package Type Shipping† ((cid:3)) Ipk (mA) NCP1010AP065G 65 23 100 PDIP−7 NCP1010AP100G 100 50 Units / Rail 23 100 (Pb−Free) NCP1010AP130G 130 23 100 NCP1010ST65T3G 65 23 100 SOT−223 NCP1010ST100T3G 100 4000 / Tape & Reel 23 100 (Pb−Free) NCP1010ST130T3G 130 23 100 NCP1011AP065G 65 50 Units / Rail 23 250 PDIP−7 NCP1011AP100G 100 23 250 (Pb−Free) 50 Units / Rail NCP1011AP130G 130 23 250 NCP1011ST65T3G 65 23 250 SOT−223 NCP1011ST100T3G 100 4000 / Tape & Reel 23 250 (Pb−Free) NCP1011ST130T3G 130 23 250 NCP1012AP065G 65 50 Units / Rail 11 250 PDIP−7 NCP1012AP100G 100 50 Units / Rail 11 250 (Pb−Free) NCP1012AP133G 130 50 Units / Rail 11 250 NCP1012ST65T3G 65 11 250 SOT−223 4000 / Tape & Reel NCP1012ST100T3G 100 11 250 (Pb−Free) NCP1012ST130T3G 130 4000 / Tape & Reel 11 250 NCP1013AP065G 65 11 350 PDIP−7 NCP1013AP100G 100 50 Units / Rail 11 350 (Pb−Free) NCP1013AP133G 130 11 350 NCP1013ST65T3G 65 11 350 SOT−223 NCP1013ST100T3G 100 4000 / Tape & Reel 11 350 (Pb−Free) NCP1013ST130T3G 130 11 350 NCP1014AP065G 65 50 Units / Rail 11 450 PDIP−7 NCP1014AP100G 100 (Pb−Free) 50 Units / Rail 11 450 NCP1014ST65T3G 65 11 450 SOT−223 4000 / Tape & Reel NCP1014ST100T3G 100 (Pb−Free) 11 450 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 21

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 PACKAGE DIMENSIONS PDIP−7 AP SUFFIX CASE 626A ISSUE B D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. E 2. CONTROLLING DIMENSION: INCHES. H 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK- AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 8 5 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE E1 NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR 1 4 TO DATUM C. 6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE NOTE 8 c LEADS UNCONSTRAINED. b2 B 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE END VIEW LEADS, WHERE THE LEADS EXIT THE BODY. TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). NOTE 5 INCHES MILLIMETERS A2 DIM MIN MAX MIN MAX e/2 A A −−−− 0.210 −−− 5.33 NOTE 3 A1 0.015 −−−− 0.38 −−− A2 0.115 0.195 2.92 4.95 L b 0.014 0.022 0.35 0.56 b2 0.060 TYP 1.52 TYP C 0.008 0.014 0.20 0.36 D 0.355 0.400 9.02 10.16 SEATING A1 PLANE D1 0.005 −−−− 0.13 −−− E 0.300 0.325 7.62 8.26 C M E1 0.240 0.280 6.10 7.11 D1 e 0.100 BSC 2.54 BSC e eB eB −−−− 0.430 −−− 10.92 L 0.115 0.150 2.92 3.81 8Xb END VIEW M −−−− 10° −−− 10° 0.010 M C A M B M NOTE 6 SIDE VIEW www.onsemi.com 22

NCP1010, NCP1011, NCP1012, NCP1013, NCP1014 PACKAGE DIMENSIONS SOT−223 (TO−261) CASE 318E−04 D ISSUE N b1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCH. 4 MILLIMETERS INCHES HE E DAIM 1M.5IN0 N1.O6M3 M1.A75X 0M.0I6N0 0N.O06M4 0M.0A6X8 1 2 3 A1 0.02 0.06 0.10 0.001 0.002 0.004 b 0.60 0.75 0.89 0.024 0.030 0.035 b1 2.90 3.06 3.20 0.115 0.121 0.126 c 0.24 0.29 0.35 0.009 0.012 0.014 b D 6.30 6.50 6.70 0.249 0.256 0.263 e1 E 3.30 3.50 3.70 0.130 0.138 0.145 e e 2.20 2.30 2.40 0.087 0.091 0.094 e1 0.85 0.94 1.05 0.033 0.037 0.041 L 0.20 −−− −−− 0.008 −−− −−− C L1 1.50 1.75 2.00 0.060 0.069 0.078 (cid:4) A H(cid:4)E 60.7°0 7.−00 71.03°0 0.206°4 0.2−76 01.208°7 0.08 (0003) A1 L L1 SOLDERING FOOTPRINT* 3.8 0.15 2.0 0.079 6.3 2.3 2.3 0.248 0.091 0.091 2.0 0.079 (cid:7) (cid:8) 1.5 mm SCALE 6:1 0.059 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative ◊ www.onsemi.com NCP1010/D 23