NCN5150 Wired M-BUS Slave Transceiver Description The NCN5150 is a single-chip integrated slave transceiver for use in two-wire Meter Bus (M-BUS) slave devices and repeaters. The transceiver provides all of the functions needed to satisfy the www.onsemi.com European Standards EN 13757−2 and EN 1434−3 describing the physical layer requirements for M-BUS. It includes a programmable power level of up to 2 (SOIC version) or 6 (NQFP version) unit loads, which are available for use in external circuits through a 3.3 V LDO regulator. NQFP−20 SOIC−16 The NCN5150 can provide communication up to the maximum MN SUFFIX D SUFFIX CASE 485E CASE 751B M-BUS communication speed of 38,400 baud (half-duplex). Features MARKING DIAGRAMS • Single-chip MBUS Transceiver • 20 UART Communication Speeds Up to 38,400baud • 1 Integrated 3.3 V VDD LDO Regulator with Extended Peak Current NCN Capability of 15mA 5150 • ALYW Supports Powering Slave Device from the Bus or from External (cid:2) Power Supply • NQFP−20 Adjustable I/O Levels • Adjustable Constant Current Sink up to 2 or 6 Unit Loads Depending 16 on the Package • Low Bus Voltage Operation NCN5150 • ALYYWWG Extended Current Budget for External Circuits: at least 0.88mA • 1 Polarity Independent • SOIC−16 Power-Fail Function • Fast Startup − No External Transistor Required on STC Pin A = Assembly Location • Industrial Ambient Temperature Range of −40°C to +85°C L = Wafer Lot (optional) • Y, YY = Year Available in: W, WW = Work Week ♦ 16-pin SOIC (Pin-to-Pin Compatible with TSS721A) G or (cid:2) = Pb-free Package ♦ 20-pin QFN • These are Pb-free Devices ORDERING INFORMATION See detailed ordering and shipping information in the package Typical Applications dimensions section on page 10 of this data sheet. • Multi-energy Utility Meters ♦ Water ♦ Gas ♦ Electricity ♦ Heating systems Related Standards − European Standard EN 13757−2, EN 1434−3 For more information visit www.m-bus.com © Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: September, 2017 − Rev. 4 NCN5150/D

NCN5150 D BUSL2 1 16 BUSL1 RIS RXI RX VD 20 19 18 17 16 VB 2 15 GND GND 1 15 STC 3 14 RIS BUSL1 2 14 VS RIDD 4 13 RXI NCN5150 NCN5150 BUSL2 3 13 VIO QFN20 SOIC16 PFb 5 12 RX VB 4 12 TX 5 11 TXI SC 6 11 VDD 6 7 8 9 10 TXI 7 10 VS C D b C T D F S S RI P TX 8 9 VIO Figure 1. Pin Out NCN5150 in 20-pin NQFP and 16 Pin SOIC (Top View) Table 1. NCN5150 PINOUT Pin Number Signal Name Type NCN5150 SOIC NCN5150 QFN Pin Description BUSL1 Bus 16 2 MBUS line. Connect to bus through 220 (cid:2) series resistors. Connections are polarity independent BUSL2 Bus 1 3 VB Power 2 4 Rectified bus voltage STC Output 3 6 Storage capacitor pin. Connect to bulk storage capacitor (minimum 10 (cid:3)F, maximum 330 (cid:3)F−2,700 (cid:3)F − see Table9) RIDD Input 4 7 Mark current adjustment pin. Connect to programming resistor PFb Output 5 8 Power Fail, active low SC Output 6 9 Mark bus voltage level storage capacitor pin. Connect to ceramic capacitor (typically 220 nF) TXI Output 7 11 UART Data output (inverted) TX Output 8 12 UART Data output VIO Input 9 13 I/O pins (RX, RXI, TX, TXI, PFb) high level voltage VS Output 10 14 Gate driver for PMOS switch between bus powered operation and external power supply VDD Power 11 16 Voltage regulator output. Connect to minimum 1 (cid:3)F decoupling capacitor RX Input 12 17 UART Data input RXI Input 13 18 UART Data input (inverted) RIS Input 14 20 Modulation current adjustment pin GND Ground 15 1 Ground NC NC − 5, 10, 15, 19 Not connected pins. Tie to GND EP Ground − EP Exposed Pad. Tie to GND www.onsemi.com 2

NCN5150 PFb VIO VIO_BUF Power VB_INT VIO Fail BUSL1 Buffer Detect VB CS1 BUSL2 RIDD SC VIO_BUF STC Receiver TX STC VS VS Voltage Driver Monitor TXI ECHO RXI 3.3 V STC VDD Transmitter RX LDO Clamp CS_TX Thermal POR Shutdown NCN5150 RIS GND Figure 2. NCN5150 Block Diagram Table 2. ABSOLUTE MAXIMUM RATINGS (Note 1) Symbol Parameter Min Max Unit TJ Junction Temperature −40 +150 °C TS Storage Temperature −55 +150 °C VBUS Bus Voltage (|BUSL1 − BUSL2|) −50 50 V VTX, VTXI Voltage on Pin TX, TXI −0.3 7.5 V VRX, VRXI, VIO Voltage on Pin RX, RXI, VIO −0.3 5.5 V ESDHBM ESD Rating − Human Body Model 4.0 − kV ESDMM ESD Rating − Machine Model 250 − V ESDCDM ESD Rating − Charged Device Model 750 − V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. All voltages are referenced to GND. www.onsemi.com 3

NCN5150 Table 3. THERMAL CHARACTERISTICS Rating Symbol Typical Value Unit Thermal Characteristics, SOIC−16 − Thermal Resistance, Junction-to-Air RθJA 125 °C/W Thermal Characteristics, QFN−20 − Thermal Resistance, Junction-to-Air RθJA 42 °C/W NOTE:R(cid:4)JA obtained with 1S0P (SOIC) or 2S2P (QFN) test boards according to JEDEC JESD51 standard. Table 4. RECOMMENDED OPERATING CONDITIONS (Notes 2 and 3) Symbol Parameter Min Max Unit TA Ambient Temperature −40 +85 °C VBUS Bus Voltage (|VBUSL1−VBUS2|) 1−2 Unit Loads 9.2 42 V 3−6 Unit Loads 9.7 42 V VIO VIO Pin Voltage (Note 4) 2.5 3.8 V 2. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 3. All voltages are referenced to GND. 4. VSTC must be at least 1V higher than VIO for proper operation. Table 5. ELECTRICAL CHARACTERISTICS (Note 5) Symbol Parameter Min Typ Max Unit (cid:5)VBR Voltage drop over bus rectifier (VBUS − VB) (RIDD (Note 6) = 4.02 k(cid:2)) − − 1.25 V (cid:5)VCS Voltage drop over CS1 RIDD (Note 6) ≥ 13 k(cid:2) 1.30 − − V (VB − VSTC) RIDD (Note 6) ≤ 4.02 k(cid:2) 1.70 − − IBUS Total Current Drawn from the Bus, Mark RIDD (Note 6) = 30 k(cid:2) − 1.32 1.50 mA State RIDD (Note 6) = 13 k(cid:2) − 2.71 3.00 RIDD (Note 6, 7) = 8.45 k(cid:2) − 4.10 4.50 RIDD (Note 6, 7) = 6.19 k(cid:2) − 5.50 6.00 RIDD (Note 6, 7) = 4.87 k(cid:2) − 6.80 7.50 RIDD (Note 6, 7) = 4.02 k(cid:2) − 8.22 9.00 (cid:5)IBUS Bus Current Stability (over (cid:5)VBUS = 10 V, RX/RXI = mark) − 0.2 2 % ISTC Idle Current Available for the Application RIDD (Note 6) = 30 k(cid:2) 0.88 1.05 1.20 mA tCou Drrreanwt Dfroramw nS TfrCom a nIOd VPDinDs )(Including RIDD (Note 6) = 13 k(cid:2) 2.10 2.35 2.60 RIDD (Note 6, 7) = 8.45 k(cid:2) 3.10 3.60 4.00 RIDD (Note 6, 7) = 6.19 k(cid:2) 4.20 4.80 5.40 RIDD (Note 6, 7) = 4.87 k(cid:2) 5.30 6.10 6.90 RIDD (Note 6, 7) = 4.02 k(cid:2) 6.50 7.45 8.40 (cid:5)ISTC,space Additional Current Available for the Application when Transmitting a − 200 − (cid:3)A Space ICC Internal Supply Current (RIDD (Note 6) = 13 k(cid:2), RX/RXI = mark) − 359 500 (cid:3)A IIO Current Drawn by the VIO Pin −0.5 − 0.5 (cid:3)A VSTC,clamp Clamp Voltage on Pin STC (IDD < ISTC) 6.0 6.5 7.0 V VB,PFb Threshold Voltage on VB to Trigger PFb (Note 8) VSTC + 0.3 − VSTC + 0.8 V VPFb,OH PFb Voltage High (IPFb = −100 (cid:3)A) VIO − 0.6 − VIO V VPFb,OL PFb Voltage Low (Note 9) (IPFb = 50 (cid:3)A) 0 − 0.6 V VRIDD Voltage on RIDD Pin 1.15 1.20 1.25 V VVS,OH Voltage on VS during High State VSTC − 0.4 − VSTC V (VSTC > VSTC,VDDON, IVS = −5 (cid:3)A) RVS,PD Pull-down Resistor on VS during Low State 50 100 150 k(cid:2) (VDD > 2 V, VSTC > VS) 5. All voltages are referenced to GND. 6. Resistor with 1% accuracy. 7. Only possible in NQFP variant. 8. PFb comparator has a 70mV hysteresis. 9. PFb pin is pulled down with an on-chip resistor of typically 2 M(cid:2). www.onsemi.com 4

NCN5150 Table 6. VDD REGULATOR ELECTRICAL CHARACTERISTICS (Note 10) Symbol Parameter Min Typ Max Unit VDD Voltage on VDD (Note 11 ) (IDD < 15 mA) 3.1 3.3 3.6 V IDD Peak Current that can be Supplied by VDD (Note 12) 15 − − mA IDD,OFF VBUS = 0 V, VSTC = 0 V −0.5 − 0.5 (cid:3)A VPOR,ON Power-on Reset Threshold, Release 2.65 2.85 3.15 V VPOR,OFF Power-on Reset Threshold, Reset 2.55 2.75 3.00 V VSTC,VDDON Threshold Voltage on Pin STC to Turn On VDD Regulator, Pull 5.6 6.0 6.4 V the VS Pin High and Enable the PF Function VSTC,VDDOFF Threshold Voltage on Pin STC to Turn Off VDD Regulator and 3.7 4.0 4.3 V Pull the PFb and VS Pins Low 10.All voltages are referenced to GND. 11.Including output resistance of VDD. 12.Average current draw limited by ISTC. Table 7. RECEIVER ELECTRICAL CHARACTERISTICS (Note 13) Symbol Parameter Min Typ Max Unit VT Receiver Threshold Voltage VSC − 8.2 − VSC − 5.7 V VSC Mark Level Storage Capacitor Voltage − − VB V ISC,charge Mark Level Storage Capacitor Charge Current −40 −25 −15 (cid:3)A ISC,discharge Mark Level Storage Capacitor Discharge Current 0.3 0.6 −0.033 × (cid:3)A ISC,charge CDR Charge/Discharge Current Ratio 30 40 − VTX,OH, TX/TXI High-level Voltage (ITX/ITXI = −100 (cid:3)A) (Note 14) VIO − 0.6 − VIO V VTXI,OH VTX,OL, TX/TXI Low-level Voltage (ITX/ITXI = 100 (cid:3)A) 0 − 0.35 V VTXI,OL (ITX = 1.1mA) 0 − 1.5 V ITX, ITXI VTX = 7.5 V, VSTC = 6 V 0 − 16 (cid:3)A 13.All voltages are referenced to GND. 14.VSTC must be at least 1 V higher than VIO for proper operation. Table 8. TRANSMITTER ELECTRICAL CHARACTERISTICS (Note 15) Symbol Parameter Min Typ Max Unit IMC Space Level Modulating Current (RRIS = 100 (cid:2) (Note 16)) 12.5 15.0 18.0 mA VRIS Voltage on RIS Pin 1.2 1.4 1.6 V VRX,IH, VRXI,IH RX/RXI Input High VIO − 0.8 − 5.5 V VRX,IL, VRXI,IL RX/RXI Input Low 0 − 0.8 V IRX, IRXI Current Drawn or Sourced from RX/RXI Pins (Note 17) ±6 − ±30 (cid:3)A (VIO = 3 V) 15.All voltages are referenced to GND. 16.Resistor with 1% accuracy. 17.Including internal pull-up resistor on RX and internal pull-down resistor on RXI. www.onsemi.com 5

NCN5150 APPLICATION SCHEMATICS VS VIO VDD RBUS1 CVDD BUSL2 U1 TXI NCN5150 VB TVS1 MBUS TX BUSL1 (cid:2)C RX RBUS2 RXI PFb RIS SC GND RIDD STC RIS CSC RIDD CSTC Figure 3. General Application Schematic VS VIO VDD CVDD RBUS1 BUSL2 U1 TXI NCN5150 VB TVS1 MBUS TX BUSL1 (cid:2) RX C RBUS2 RXI PFb RIS SC GND RIDD STC RIS CSC RIDD CSTC Figure 4. Application Schematic with External Power Supply (Battery) www.onsemi.com 6

NCN5150 APPLICATION SCHEMATICS Q1 VS VIO VDD RBUS1 CVDD BUSL2 U1 TXI NCN5150 VB TVS1 MBUS TX BUSL1 (cid:2) RX C RBUS2 RXI PFb RIS SC GND RIDD STC RIS CSC RIDD CSTC Figure 5. Application Schematic with Backup External Power Supply VSTC VS VIO 15 k(cid:2) 2.2 k(cid:2) VDD 15 k(cid:2) CVDD BUSL2 RBUS1 U1 TXI NCN5150 VB TVS1 MBUS U3 TX BUSL1 RX RBUS2 RXI PFb (cid:2)C 620 (cid:2) U2 RIS SC GND RIDD STC V STC RIS CSC RIDD CSTC Figure 6. Optically Isolated Application Schematic www.onsemi.com 7

NCN5150 Table 9. TYPICAL BILL OF MATERIALS Reference Designator Value (Typical) Tolerance Manufacturer Part Number U1 − − ONSemiconductor NCN5150 TVS1 40 V − ONSemiconductor 1SMA40CAT3G CVDD >1 (cid:3)F −20%, +80% RIS 100 (cid:2) 1% CSC 220 nF −20%, +80% RBUS1, RBUS2 220 (cid:2) 10% RIDD 1 UL 30 k(cid:2) 1% 2 UL 13 k(cid:2) 1% 3 UL (Note 18) 8.45 k(cid:2) 1% 4 UL (Note 18) 6.19 k(cid:2) 1% 5 UL (Note 18) 4.87 k(cid:2) 1% 6 UL (Note 18) 4.02 k(cid:2) 1% CSTC 1 UL ≤330 (cid:3)F 10% 2 UL ≤820 (cid:3)F 10% 3 UL (Note 18) ≤1,200 (cid:3)F 10% 4 UL (Note 18) ≤1,500 (cid:3)F 10% 5 UL (Note 18) ≤2,200 (cid:3)F 10% 6 UL (Note 18) ≤2,700 (cid:3)F 10% 18.3−6 UL configurations are only possible for the NQFP variant. APPLICATION INFORMATION The NCN5150 is a slave transceiver for use in the meter bit, 8 data bits, 1 even parity bit, and a stop bit. bus (M-BUS) protocol. The bus connection is fully polarity Communication speeds allowed by the M-BUS standard are independent. The transceiver will translate the bus voltage 300, 600, 2400, 4800, 9600, 19200 and 38400 baud, all of modulation from master-to-slave communication to TTL which are supported by the NCN5150. UART communication, and in the other direction translate UART voltage levels to bus current modulation. The Bus Connection and Rectification The bus should be connected to the pins BUSL1 and transceiver also integrates a voltage regulator for utilizing BUSL2 through series resistors to limit the current drawn the current drawn in this way from the bus, and an early from the bus in case of failure (according to the M-BUS power fail warning. The transceiver also supports an standard). Typically, two 220(cid:2) resistors are used for this external power supply and the I/O high level can be set to purpose. match the slave sensor circuit. A complete block diagram is Since the M-BUS connection is polarity independent, the shown in Figure 2. Each section will be explained in more NCN5150 will first rectify the bus voltage through an active detail below. diode bridge. Meter Bus Protocol M-BUS is a European standard for communication and Slave Power Supply (Bus Powered) A slave device can be powered by the M-BUS or from an powering of utility meters and other sensors. external supply. The M-BUS standard requires the slave to Communication from master to slave is achieved by draw a fixed current from the bus. This is accomplished by voltage-level signaling. The master will apply a nominal the constant current source CS1. This current is used to +36 V to the bus in idle state, or when transmitting a logical charge the external storage capacitor C . The current 1 (“mark”). When transmitting a logical 0 (“space”), the STC drawn from the bus is defined by the programming resistor master will drop the bus voltage to a nominal +24 V. R . The bus current can be chosen in increments of Communication from the slave to the master is achieved IDD 1.5 mA called unit loads. Table 5 list the different values of by current modulation. In idle mode or when transmitting a programming resistors needed for different unit loads, as logical 1 (“mark”), the slave will draw a fixed current from well as the current drawn from the bus (I ) and the current the bus. When transmitting a logical 0 (“space”), the slave BUS that can be drawn from the STC pin (I ). I is slightly will draw an extra nominal 15 mA from the bus. M-BUS STC STC less than I to account for the internal power consumption uses a half-duplex 11-bit UART frame format, with 1 start BUS www.onsemi.com 8

NCN5150 of the NCN5150. The RIDD resistor used must be at least 1% VBUS VMARK = [21V, 42V] accurate. Note that using 5 and 6 Unit Loads is not covered VT = VMARK − 6V by the M-BUS standard. When the voltage on the STC pin reaches V VSPACE = VMARK − 12V STC,VDDON t the LDO is turned on, and will regulate the voltage on the VDD pin to 3.3 V, drawing current from the storage VTX VIO capacitor. A decoupling capacitor of minimum 1 (cid:3)F is required on the VDD pin for stability of the regulator. On the t STC pin, a minimum capacitance of 10 (cid:3)F is required. Furthermore, the ratio CSTC/CVDD must be larger than 9. VTXI VIO The voltage on the STC pin is clamped to V by a STC,clamp shunt regulator, which will dissipate any excess current that t is not used by the NCN5150 or external circuits. Figure 7. Communication, Master to Slave Slave Power Supply (External) In case the external sensor circuit consumes more than the VB allowed bus current or the sensor should be kept operational when the bus is not present, an external power supply, such ICHARGE as a battery, is required. SC When the external circuitry uses different logical voltage levels, simply connect the power supply of that voltage level to VIO, so that the RX, RXI, TX, TXI and PFb pins will + IDISCHARGE respond to the correct voltage levels. The NCN5150 will still − be powered from the bus, but all communication will be translated to the voltage level of V . IO If the external power supply should be used only as a backup when the bus power supply fails, a PMOS transistor TX can be inserted between the external power supply and VDD Encoding as shown in Figure 5. The gate is connected to VS, and will Echo TXI be driven high when the voltage on STC goes above the turn-on threshold of the LDO, nl. VSTC, VDD ON. For more Figure 8. Communication, Master to Slave information see the paragraph on the power on sequence and corresponding Figure 12 on page 10. Communication, Slave to Master M-BUS communication from slave to master uses bus Communication, Master to Slave current modulation while the voltage remains constant. This M-BUS communication from master to slave is based on current modulation can be controlled from either the RX or voltage level signaling. To differentiate between master RXI pin as shown in Figure 10. When transmitting a space signaling and voltage drop caused by the signaling of (“0”), the current modulator will draw an additional current another slave over cabling resistance, etc., the mark level from the bus. This current can be set with a programming VBUS, MARK is stored, and only when the bus voltage drops resistor R . To achieve the space current required the RIS to less than VT will the NCN5150 detect communication. A M-BUS standard, R should be 100 (cid:2). A simplified RIS simplified schematic of the receiver is shown in Figure 8. schematic of the transmitter is shown in Figure 11. The received data is transmitted on the pins TX and TXI, as shown in the waveforms of Figure 7. An external capacitor must be connected to the SC pin to store the mark voltage level. This capacitor is charged to V . B Discharging of this capacitor is typically 40x slower, so that the voltage on SC drops only a little during the time the master is transmitting a space. The value of C must be SC chosen it the range of 100nF−330nF. Figure 9. Typical Relationship between RIS and Current Modulation Level www.onsemi.com 9

NCN5150 Because the M-BUS protocol is specified as half-duplex, shut down gracefully. The times ton and toff can be an echo function will cause the transmitted signal on RX or approximated by the following formulas: RXI to appear on the receiver outputs TX and TXI. Should C the master attempt to send at the same time, the bitwise t (cid:2) STCV (eq. 1) on I STC,VDDON added signal of both sources will appear on these pins, STC resulting in invalid data. C (cid:4) (cid:6) t (cid:2) STC V (cid:5)V (eq. 2) off I (cid:3)I STC,Clamp STC,VDDOFF VRX VIO CC DD Where I is the internal current consumption of the CC NCN5150 and I is the current consumed by external t DD circuits drawn from either VDD or STC. VRXI VIO These formulas can be used to dimension the value of the bulk C needed, taking into account that the M-BUS STC standard requires t to be less than 3s. t on For certain applications where the power drawn from the IBUS ISPACE = IMARK + 15mA bus is not used in external circuits, the storage capacitor value can be much lower. The NCN5150 requires a minimum STC capacitance of 10(cid:3)F to ensure that the bus IMARK = N unit loads current regulation is stable under all conditions. t Figure 10. Communication, Slave to Master VBUS VB = VSTC + 0.6 VIO_BUF VB = VB,MIN t VSTC ton VSTC,CLAMP Echo VSTC,VDD ON Decoding RX VSTC,VDD OFF VB t RXI VVS VSTC,CLAMP Enable + t − VDD 3.3V RIS t VPFb VIO Figure 11. Communication, Slave to Master toff t Figure 12. Power-on and Power-off Power On/Off Sequence The power-on and power-off sequence of the NCN5150 Thermal Shutdown is shown in Figure 12. Shown also in Figure 12 is the The NCN5150 includes a thermal shutdown function that operation of the PFb pin. This pin is used to give an early will disable the transmitter when the junction temperature of warning to the microcontroller that the bus power is the IC becomes too hot. The thermal protection is only active collapsing, allowing the microcontroller to save its data and when the slave is transmitting a space to the master. Table 10. ORDERING INFORMATION Device Package Shipping† NCN5150DG SOIC16 48 Units / Tube (Pb-free) NCN5150DR2G 3,000 / Tape & Reel NCN5150MNTWG NQFP20, 4x4 2,500 / Tape & Reel (Pb-free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 10

NCN5150 PACKAGE DIMENSIONS QFN20, 4x4, 0.5P CASE 485E ISSUE B NOTES: D A 1. DIMENSIONING AND TOLERANCING PER ASME B A3 Y14.5M, 1994. ÉÉÉ EXPOSED ÇCu ÇMOLD CMPD ÉÉ 23.. CDOIMNETNRSOIOLLNI NbG A PDPIMLIEENSS TIOON P: LMAITLELIDM TEETREMRSIN.AL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM PIN ONE ÉÉÉ ÉÉ ÉÇÉÇ FROM THE TERMINAL TIP. REFERENCE 4. COPLANARITY APPLIES TO THE EXPOSED PAD ÉÉÉ E A1 AS WELL AS THE TERMINALS. 2X MILLIMETERS DETAIL B 0.15 C DIM MIN MAX OPTIONAL CONSTRUCTIONS A 0.80 1.00 2X A1 --- 0.05 0.15 C A3 0.20 REF TOP VIEW L L b 0.20 0.30 D 4.00 BSC D2 2.60 2.90 DETAIL B (A3) A L1 E 4.00 BSC E2 2.60 2.90 0.10 C e 0.50 BSC K 0.20 REF DETAIL A L 0.35 0.45 0.08 C OPTIONAL CONSTRUCTIONS L1 0.00 0.15 SIDE VIEW A1 C SPELAATNIENG SOLDERING FOOTPRINT* 0.10 C A B 4.30 D2 20X DETAIL A 20XL 0.58 6 0.10 C A B 2.88 11 E2 1 1 2.88 4.30 K 20 20Xb e 0.10 C A B 0.05 C NOTE 3 PKG BOTTOM VIEW OUTLINE 20X 0.35 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 11

NCN5150 PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K −A− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 16 9 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. −B− P8 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION 1 8 0.25 (0.010) M B S SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX G A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F K R X 45(cid:3) F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 C K 0.10 0.25 0.004 0.009 M 0 (cid:3) 7 (cid:3) 0 (cid:3) 7 (cid:3) −T− SEATING P 5.80 6.20 0.229 0.244 PLANE M J R 0.25 0.50 0.010 0.019 D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT* 8X 6.40 16X1.12 1 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb-free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative ◊ www.onsemi.com NCN5150/D 12

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: NCN5150DG NCN5150DR2G