Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

N C 7 S Z August 2011 7 4 — T in y L NC7SZ74 o g ® i TinyLogic UHS D-Type, Flip-Flop with Preset and c ® U Clear H S D Features Description - T y  Ultra-High Speed: t 2.6ns (Typical) into 50pF at The NC7SZ74 is a single, D-type, CMOS flip-flop with p PD preset and clear from Fairchild’s ultra high-speed series e 5V VCC of TinyLogic®. The device is fabricated with advanced F  High Output Drive: ±24mA at 3V VCC CMOS technology to achieve ultra high speed with high lip output drive, while maintaining low static power -  Broad V Operating Range: 1.65V to 5.5V F CC dissipation over a very broad VCC operating range of lo  Power Down High-Impedance Inputs/Outputs 1.65V to 5.5V VCC. The inputs and outputs are high w impedance when V is 0V. Inputs tolerate voltages up  Over-Voltage Tolerance Inputs Facilitate 5V to 3V CC w Translation to 7V, independent of VCC operating voltage. it h  Proprietary Noise/EMI Reduction Circuitry The signal level applied to the D input is transferred to P the Q output during the positive-going transition of the r  Ultra-Small MicroPak™ Package CLK pulse. es e  Space-Saving US8 Surface Mount Package t a n d C Ordering Information l e a r Part Number Top Mark Package Packing Method 3000 Units on NC7SZ74K8X SZ74 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide- Tape & Reel 5000 Units on NC7SZ74L8X N9 8-Lead MicroPak, 1.6 mm Wide Tape & Reel © 2001 Fairchild Semiconductor Corporation www.fairchildsemi.com NC7SZ74 • Rev. 1.0.2

N C 7 Connection Diagrams S Z 7 IEEE/IEC 4 — T i n y L o g Figure 1. Logic Symbol i c ® Pin Configurations U H S D - T y p e F l i p - F l o p w it h Figure 2. US8 (Top View) Figure 3. MicroPak™(Top Through View) P r e s Pin Definitions e t a Pin # US8 Pin # MicroPak Name Description n d 1 7 CK Clock Pulse Input C l e 2 6 D Data Input a r 3 5 /Q Flip-Flop Output 4 4 GND Ground 5 3 Q Flip-Flop Output 6 2 /CLR Direct Clear Input 7 1 /PR Direct Preset Input 8 8 V Supply Voltage CC Function Table Inputs Output Function /CLR /PR D CK Q /Q L H X X L H Clear H L X X H L Preset L L X X H H H H L  L H H H H  H L H H X  Qn /Qn No Change H = HIGH Logic Level Qn = No change in data X = Immaterial Falling Edge  L = LOW Logic Level Z = High Impedance  = Rising Edge © 2001 Fairchild Semiconductor Corporation www.fairchildsemi.com NC7SZ74 • Rev. 1.0.2 2

N C Absolute Maximum Ratings 7 S Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be Z 7 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 4 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. — The absolute maximum ratings are stress ratings only. T i Symbol Parameter Min. Max. Unit n y L V Supply Voltage -0.5 7.0 V CC o g V DC Input Voltage -0.5 7.0 V IN ic V DC Output Voltage -0.5 7.0 V ® OUT U IIK DC Input Diode Current VIN < 0V -50 mA H S I DC Output Diode Current V < 0V -50 mA OK OUT D I DC Output Source/Sink Current ±50 mA - OUT T y I or I DC V or Ground Current ±50 mA CC GND CC p e TSTG Storage Temperature Range -65 +150 °C F TJ Junction Temperature Under Bias +150 °C lip TL Junction Lead Temperature (Soldering, 10 Seconds) +260 °C -F l P Power Dissipation at +85°C 250 mW o D p Human Body Model, JEDEC:JESD22-A114 5000 w ESD V i Charge Device Model: JEDEC:JESD22-C101 2000 th P r e s Recommended Operating Conditions e t The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended a n operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not d recommend exceeding them or designing to Absolute Maximum Ratings. C l e Symbol Parameter Conditions Min. Max. Unit a r Supply Voltage Operating 1.65 5.50 V V CC Supply Voltage Data Retention 1.50 5.50 V Input Voltage 0 5.5 V IN Active State 0 V V CC V Output Voltage OUT 3-State 0 5.5 V =1.8V, 2.5V ± 0.2V 0 20 CC t, t Input Rise and Fall Times V =3.3V ± 0.3V 0 10 ns/V r f CC V =5.0V ± 0.5V 0 5 CC T Operating Temperature -40 +85 °C A US8 250  Thermal Resistance °C/W JA MicroPak™-8 280 Note: 1. Unused inputs must be held HIGH or LOW. They may not float. © 2001 Fairchild Semiconductor Corporation www.fairchildsemi.com NC7SZ74 • Rev. 1.0.2 3

N C DC Electrical Characteristics 7 S Z T =+25°C T =-40 to +85°C A A 7 Symbol Parameter VCC Conditions Units 4 Min. Typ. Max. Min. Max. — HIGH Level Control 1.65 to 1.95 0.75VCC 0.75VCC T V V IH Input Voltage 2.30 to 5.50 0.70V 0.70V in CC CC y LOW Level Control 1.65 to 1.95 0.25VCC 0.25VCC L VIL Input Voltage 2.30 to 5.50 0.30VCC 0.30VCC V og i 1.65 1.55 1.65 1.55 c ® 2.30 V =V , 2.20 2.30 2.20 U IN IH 3.00 IOH=-100µA 2.90 3.00 2.90 HS 4.50 4.40 4.50 4.40 D HIGH Level Output - VOH Voltage 1.65 IOH=-4mA 1.29 1.52 1.29 V T y 2.30 IOH=-8mA 1.90 2.15 1.90 p e 3.00 IOH=-16mA 2.40 2.80 2.40 F 3.00 IOH=-24mA 2.30 2.68 2.30 lip 4.50 IOH=-32mA 3.80 4.20 3.80 -F l 1.65 0.10 0.10 o p 2.30 VIN=VIH, 0.10 0.10 w 3.00 IOL=100µA 0.10 0.10 it h 4.50 0.10 0.10 P VOL LOOutWpu Lt eVvoeltl aCgoen trol 1.65 IOL=4mA 0.80 0.24 0.24 V re s 2.30 IOL=8mA 0.10 0.30 0.30 e t 3.00 IOL=16mA 0.15 0.40 0.40 a n 3.00 I =24mA 0.22 0.55 0.55 OL d 4.50 I =32mA 0.22 0.55 0.55 C OL l Input Leakage e IIN Current 0 to 5.5  VIN  5.5V ±0.1 ±1.0 µA ar Power Off Leakage I 0 V or V =5.5V 1 10 µA OFF Current IN OUT Quiescent Supply I 1.65 to 5.50 V =5.5V, GND 1 10 µA CC Current IN © 2001 Fairchild Semiconductor Corporation www.fairchildsemi.com NC7SZ74 • Rev. 1.0.2 4

AC Electrical Characteristics N C 7 TA=+25°C TA=-40 to +85°C S Symbol Parameter VCC Conditions Units Figure Z Min. Typ. Max. Min. Max. 7 4 1.80 ± 0.15 75 75 — C=15pF 2.50 ± 0.20 L 150 150 3.30 ± 0.30 RD=1M 200 200 T f Maximum Clock S1=Open Figure 4 in MAX Frequency 5.00 ± 0.50 250 250 Figure 8 y L 3.30 ± 0.50 CL=50pF 175 175 o R =500, g 5.00 ± 0.50 S1D=Open 200 200 ic ® 1.80 ± 0.15 2.5 6.5 12.5 2.5 13.0 U C=15pF, 2.50 ± 0.20 L 1.5 3.8 7.5 1.5 8.0 H 3.30 ± 0.30 RD=1M 1.0 2.8 6.5 1.0 7.0 S t , t Propagation Delay S1=Open ns Figure 4 D PLH PHL CK to Q, /Q 5.00 ± 0.50 0.8 2.2 4.5 0.8 5.0 Figure 6 - T 3.30 ± 0.30 CL=50pF 1.0 3.4 7.0 1.0 7.5 y R =500, p 5.00 ± 0.50 SD=Open 1.0 2.6 5.0 1.0 5.5 e 1 F 1.80 ± 0.15 2.5 6.5 14.0 2.5 14.5 l i C=15pF, p 2.50 ± 0.20 L 1.5 3.8 9.0 1.5 9.5 t , t Propagation Delay 3.30 ± 0.30 RS1L==O1Mpen 1.0 2.8 6.5 1.0 7.0 ns Figure 4 -Flo PLH PHL /CLR, /PR to Q, /Q 5.00 ± 0.50 0.8 2.2 5.0 0.8 5.5 Figure 6 p 3.30 ± 0.30 C=50pF, 1.0 3.4 7.0 1.0 7.5 w L 5.00± 0.50 RD=500 1.0 2.6 5.0 1.0 5.5 ith S=Open 1 P 1.80 ± 0.15 6.5 6.5 r C=15pF, e 2.50 ± 0.20 L 3.5 3.5 s t Setup Time CK to D 3.30 ± 0.30 RS1L==O1Mpen 2.0 2.0 ns Figure 4 et a S 5.00 ± 0.50 1.5 1.5 Figure 7 n 3.30 ± 0.30 C=50pF, 2.0 2.0 d L R =500 C 5.00± 0.50 S1D=Open 1.5 1.5 le a 1.80 ± 0.15 0.5 0.5 r C=15pF, 2.50 ± 0.20 L 0.5 0.5 R=1M 3.30 ± 0.30 L 0.5 0.5 t Hold Time, CK to D S1=Open ns Figure 4 H 5.00 ± 0.50 0.5 0.5 Figure 7 3.30 ± 0.30 C=50pF, 0.5 0.5 L R =500 5.00± 0.50 D 0.5 0.5 S=Open 1 1.80 ± 0.15 6.0 6.0 C=15pF, 2.50 ± 0.20 L 4.0 4.0 R=1M 3.30 ± 0.30 L 3.0 3.0 t Pulse Width, CK, S1=Open ns Figure 4 W /PR, /CLR 5.00 ± 0.50 2.0 2.0 Figure 8 3.30 ± 0.30 C=50pF, 3.0 3.0 L R =500 5.00± 0.50 D 2.0 2.0 S=Open 1 1.80 ± 0.15 8.0 8.0 C=15pF, 2.50 ± 0.20 L 4.5 4.5 R=1M 3.30 ± 0.30 L 3.0 3.0 t Recover Time /CLR, S1=Open ns Figure 4 REC /PR to CK 5.00 ± 0.50 3.0 3.0 Figure 7 3.30 ± 0.30 C=50pF, 3.0 3.0 L R =500 5.00 ± 0.50 D 3.0 3.0 S=Open 1 Continued on the following page… © 2001 Fairchild Semiconductor Corporation www.fairchildsemi.com NC7SZ74 • Rev. 1.0.2 5

N AC Electrical Characteristics C 7 S T =+25°C T =-40 to +85°C A A Z Symbol Parameter V Conditions Units Figure CC 7 Min. Typ. Min. Typ. Min. 4 — C Input Capacitance 0 3 pF IN C Output Capacitance 0 4 pF T OUT i n CPD PCoawpaecr iDtainscseip(2a) tion 35..3000 1120 pF yL o Note: g i 2. C is defined as the value of the internal equivalent capacitance which is derived from dynamic operating c PD ® current consumption (ICCD) at no output loading and operating at 50% duty cycle. CPD is related to ICCD dynamic U operating current by the expression: ICCD=(CPD)(VCC)(fIN)+(ICCstatic). H S D - T y p e F l i p - F l o p w i th P Note: re 3. CL includes load and stray capacitance. Notes: se Input PRR=1.0MHz tw=500ns. 45.. CCPP iinnppuutt =PARCR W=1a0vMefHozrm; Ds utrt=yt fC=2yc.5len=s5. 0%. t a n 6. D input PRR=5MHz; Duty Cycle=50%. d Figure 4. AC Test Circuit Figure 5. I Test Circuit C CCD l e a r Figure 6. AC Waveforms Figure 7. AC Waveforms Figure 8. AC Waveforms © 2001 Fairchild Semiconductor Corporation www.fairchildsemi.com NC7SZ74 • Rev. 1.0.2 6

N C Physical Dimensions 7 S Z 7 4 0.15 12..9100 A 1.80 — 8 5 B T (8X) 0.70 i n y 3.20 L 3.00 22..4200 2.70 3.40 o g 1.55 1.00 ic ® U PIN 1 IDENT 1 4 0.2 C B A H ALL LEAD TIPS S TOP VIEW 0.50 0.30 (8X) D RECOMMENDED LAND PATTERN - T y p e 0.80 F 0.90 MAX 0.60 l 0.10 ALL LEAD TIPS ip 0.00 0.1C - A. CONFORMS TO JEDEC REGISTRATION MO-187 F l B. DIMENSIONS ARE IN MILLIMETERS. o SEATING C p PLANE C. DIMENSIONS ARE EXCLUSIVE OF BURRS, w 0.17-0.27(8X) MOLD FLASH, AND TIE BAR EXTRUSIONS. i 0.50 0.13 A B C D. DIMENSIONS AND TOLERANCES PER th ANSI Y14.5M, 1994. P SIDE VIEW E. FILE DRAWING NAME : MKT-MAB08Arev4 r e s e t a 0.4 TYP DETAIL A n d GAGE PLANE C 0.10-0.18 l e a 0°-8° 0.12 r 0.20-0.35 SEATING PLANE DETAIL A Figure 9. 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/analog/pdf/sc70-5_tr.pdf. Package Designator Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed K8X Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed © 2001 Fairchild Semiconductor Corporation www.fairchildsemi.com NC7SZ74 • Rev. 1.0.2 7

N C Physical Dimensions 7 S Z 7 2X 0.10 C 4 — A B 1.6 T i n y L 1.6 o g i c INDEX AREA ® 2X 0.10 C U H TOP VIEW S 0.55 MAX D 0.05 C - Recommended Landpattern T y p e 0.05 C 0.05 C F 0.00 l i DETAIL A 1.0 (0.20) p - 8X(0.09) 1 2 3 0.5 00..3255 Flo p 4 (0.1) w 8 4 (0.15) i t 0.35 h 0.25 P 8X00..2355 7 6 5 00..2155 8X 0.10 C A B DETAIL A re 3X(0.2) 0.05 C PSICNA #L1E :T 2EXRMINAL se t BOTTOM VIEW a n d Notes: C 1. PACKAGE CONFORMS TO JEDEC MO-255 VARIATION UAAD l 2. DIMENSIONS ARE IN MILLIMETERS e a 3. DRAWING CONFORMS TO ASME Y.14M-1994 r 4. PIN 1 FLAG, END OF PACKAGE OFFSET 5. DRAWING FILE NAME: MKT-MAC08AREV4 MAC08AREV4 Figure 10. 8-Lead, MicroPak™, 1.6mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf. Package Designator Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed L8X Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed © 2001 Fairchild Semiconductor Corporation www.fairchildsemi.com NC7SZ74 • Rev. 1.0.2 8

N C 7 S Z 7 4 — T i n y L o g i c ® U H S D - T y p e F l i p - F l o p w i t h P r e s e t a n d C l e a r © 2001 Fairchild Semiconductor Corporation www.fairchildsemi.com NC7SZ74 • Rev. 1.0.2 9

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