NBXDPA019 2.5 V / 3.3 V, 125 MHz / 250(cid:2)MHz LVDS Clock Oscillator The NBXDPA019 dual frequency crystal oscillator (XO) is designed to meet today’s requirements for 2.5 V and 3.3V LVDS http://onsemi.com clock generation applications. The device uses a high Q fundamental crystal and Phase Lock Loop (PLL) multiplier to provide selectable MARKING DIAGRAM 125 MHz or 250MHz, ultra low jitter and phase noise LVDS differential output. This device is a member of ON Semiconductor’s PureEdge(cid:2) clock NBXDPA019 family that provides accurate and precision clock solutions. 125.00/250.00 Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape 6 PIN CLCC AAWLYYWWG and reel in quantities of 1000. LN SUFFIX CASE 848AB Features • LVDS Differential Output • Uses High Q Fundamental Mode Crystal and PLL Multiplier • NBXDPA019 Ultra Low Jitter and Phase Noise − 0.5 ps (12 kHz − 20 MHz) 125.00/250.00 • Selectable Output Frequency − 125 MHz (default) / 250 MHz 6 PIN CLCC AAWLYYWWG • Hermetically Sealed Ceramic SMD Package LU SUFFIX • Operating Range: 2.5 V ±5% CASE 848AC Operating Range: 3.3 V ±10% NBXDPA019 = NBXDPA019 (±50 PPM) • Total Frequency Stability − (cid:2)50 ppm 125.00/250.00= Output Frequency (MHz) • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS AA = Assembly Location WL = Wafer Lot Compliant YY = Year WW = Work Week Applications G = Pb−Free Package • Ethernet, Gigabit Ethernet • Infiniband • ORDERING INFORMATION Base Stations Device Package Shipping† NBXDPA019LN1TAG CLCC−6 1000/ VDD CLK CLK (Pb−Free) Tape & Reel 6 5 4 NBXDPA019LNHTAG CLCC−6 100/ (Pb−Free) Tape & Reel NBXDPA019LU1TAG* CLCC−6 1000/ PLL (Pb−Free) Tape & Reel Crystal Clock Multiplier NBXDPA019LUHTAG* CLCC−6 100/ (Pb−Free) Tape & Reel †For information on tape and reel specifications, 1 2 3 including part orientation and tape sizes, please OE FSEL GND refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Figure 1. Simplified Logic Diagram *Contact factory for availability. © Semiconductor Components Industries, LLC, 2010 1 Publication Order Number: March, 2010 − Rev. 2 NBXDPA019/D

NBXDPA019 OE 1 6 VDD FSEL 2 5 CLK GND 3 4 CLK Figure 2. Pin Connections (Top View) Table 1. PIN DESCRIPTION Pin No. Symbol I/O Description ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1 OE LVTTL/LVCMOS Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁCÁÁontÁÁrol InÁÁputÁÁÁÁÁÁSeeÁÁ OE ÁÁpin dÁÁescÁÁriptioÁÁn TaÁÁble 2ÁÁ. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ2 ÁÁÁFÁSELÁÁÁLVÁTTLÁ/LVCÁMOSÁÁÁOutpÁut FÁrequÁencÁy SeÁlect ÁPin. ÁPin wÁill dÁefauÁlt to ÁlogicÁ HIGÁH wÁhenÁ left ÁopenÁ. SeÁe OuÁtputÁ Control Input Frequency Select pin description Table 3. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3 GND Power Supply Ground 0 V ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 4 CLK LVDS Output Non−Inverted Clock Output. Typically loaded with 100 (cid:2) receiver termination resistor ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ across differential pair. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 5 CLK LVDS Output Inverted Clock Output. Typically loaded with 100 (cid:2) receiver termination resistor across ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁdiffeÁÁrentiÁÁal paÁÁir. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ6 ÁÁÁÁVDDÁÁÁPÁoweÁr SuÁpplyÁÁÁPosÁitive ÁpowÁer suÁpplyÁ voltÁage.Á VolÁtageÁ shoÁuld nÁot eÁxceeÁd 2.5Á V ±Á5% Áor 3.Á3 V Á±10%Á. Á Table 2. OUTPUT ENABLE TRI−STATE FUNCTION Table 3. OUTPUT FREQUENCY SELECT OE Pin Output Pins FSEL Pin Output Frequency (MHz) Open Active Open 125 (pin will float high) HIGH Level Active HIGH Level 125 LOW Level High Z LOW Level 250 Table 4. ATTRIBUTES Characteristic Value Input Default State Resistor 170 k(cid:2) ESD Protection Human Body Model 2 kV Machine Model 200 V Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. Table 5. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Units VDD Positive Power Supply GND = 0 V 4.6 V Iout LVDS Output Current Continuous 25 mA Surge 50 TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −55 to +120 °C Tsol Wave Solder See Figure 6 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2

NBXDPA019 Table 6. DC CHARACTERISTICS (VDD = 2.5 V ± 5% or VDD = 3.3 V ± 10%, GND = 0 V, TA = −40°C to +85°C) (Note 2) Symbol Characteristic Conditions Min. Typ. Max. Units IDD Power Supply Current 78 105 mA VIH OE and FSEL Input HIGH Voltage 2000 VDD mV VIL OE and FSEL Input LOW Voltage GND − 300 800 mV IIH Input HIGH Current OE −100 +100 (cid:3)A FSEL −100 +100 IIL Input LOW Current OE −100 +100 (cid:3)A FSEL −100 +100 (cid:4)VOD Change in Magnitude of VOD for 0 1 25 mV Complementary Output States (Note 3) VOS Offset Voltage 1125 1375 mV (cid:4)VOS Change in Magnitude of VOS for 0 1 25 mV Complementary Output States (Note 3) VOH Output HIGH Voltage VDD = 2.5 V 1425 1600 mV VDD = 3.3 V VOL Output LOW Voltage VDD = 2.5 V 900 1075 mV VDD = 3.3 V VOD Differential Output Voltage 250 450 mV NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 5. 3. Parameter guaranteed by design verification not tested in production. http://onsemi.com 3

NBXDPA019 Table 7. AC CHARACTERISTICS (VDD = 2.5 V ± 5% or VDD = 3.3 V ± 10%, GND = 0 V, TA = −40°C to +85°C) (Note 4) Symbol Characteristic Conditions Min. Typ. Max. Units fCLKOUT Output Clock Frequency FSEL = HIGH 125 MHz FSEL = LOW 250 (cid:4)f Frequency Stability − NBXDPA019 (Note 5) ±50 ppm (cid:5)NOISE Phase−Noise Performance 100 Hz of Carrier −108/−103 dBc/Hz fCLKout = 125 MHz/250 MHz 1 kHz of Carrier −122/−116 dBc/Hz (See Figures 3 and 4) 10 kHz of Carrier −129/−123 dBc/Hz 100 kHz of Carrier −129/−124 dBc/Hz 1 MHz of Carrier −136/−131 dBc/Hz 10 MHz of Carrier −159/−156 dBc/Hz tjit((cid:5)) RMS Phase Jitter 12 kHz to 20 MHz 0.5 0.75 ps tjitter Cycle to Cycle, RMS 1000 Cycles 4 8 ps Cycle to Cycle, Peak−to−Peak 1000 Cycles 17 35 ps Period, RMS 10,000 Cycles 2 4 ps Period, Peak−to−Peak 10,000 Cycles 7 20 ps tOE/OD Output Enable/Disable Time 200 ns tDUTY_CYCLE Output Clock Duty Cycle 48 50 52 % (Measured at Cross Point) tR Output Rise Time (20% and 80%) 250 400 ps tF Output Fall Time (80% and 20%) 250 400 ps tstart Start−up Time 1 5 ms Aging 1st Year 3 ppm Every Year After 1st 1 ppm NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 5. 5. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration and first year aging. http://onsemi.com 4

NBXDPA019 Figure 3. Typical Phase Noise Plot at 125 MHz Figure 4. Typical Phase Noise Plot at 250 MHz http://onsemi.com 5

NBXDPA019 Table 8. RELIABILITY COMPLIANCE Parameter Standard Method ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Shock Mechanical MIL−STD−833, Method 2002, Condition B ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Solderability Mechanical MIL−STD−833, Method 2003 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Vibration Mechanical MIL−STD−833, Method 2007, Condition A ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Solvent Resistance Mechanical MIL−STD−202, Method 215 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Resistance to Soldering Heat Mechanical MIL−STD−203, Method 210, Condition I or J ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Thermal Shock Environment MIL−STD−833, Method 1001, Condition A ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Moisture Resistance Environment MIL−STD−833, Method 1004 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ NBXDPA019 CLK Zo = 50 (cid:2) D DDreivveicre 100 (cid:2) RDeecveiciever CLK Zo = 50 (cid:2) D Figure 5. Typical Termination for Output Driver and Device Evaluation temp. 260°C Temperature (°C) 20 − 40 sec. max. peak 6°C/sec. max. 260 3°C/sec. max. 217 ramp−up cooling 175 150 pre−heat reflow Time 60(cid:2)180 sec. 60(cid:2)150 sec. Figure 6. Recommended Reflow Soldering Profile http://onsemi.com 6

NBXDPA019 PACKAGE DIMENSIONS 6 PIN CLCC, 7x5, 2.54P CASE 848AB−01 ISSUE C D A NOTES: B 1. DIMENSIONING AND TOLERANCING PER D1 ASME Y14.5M, 1994. 4X 0.15 C 2. CONTROLLING DIMENSION: MILLIMETERS. MILLIMETERS DIM MIN NOM MAX A 1.70 1.80 1.90 E2 H E1 E A1 0.70 REF TERMINAL 1 INDICATOR A2 0.36 REF A3 0.08 0.10 0.12 b 1.30 1.40 1.50 D 7.00 BSC D2 D1 6.17 6.20 6.23 D2 6.66 6.81 6.96 TOP VIEW D3 5.08 BSC E 5.00 BSC A3 A2 E1 4.37 4.40 4.43 0.10 C E2 4.65 4.80 4.95 E3 3.49 BSC A e 2.54 BSC H 1.80 REF L 1.17 1.27 1.37 SIDE VIEW R 0.70 REF A1 C SEATING PLANE D3 SOLDERING FOOTPRINT* e 1 2 3 R 6X E3 1.50 5.06 0.10 C A B 6 5 4 0.05 C 6Xb 6XL BOTTOM VIEW 6X 2.54 1.50 PITCH DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7

NBXDPA019 PACKAGE DIMENSIONS 6 PIN CLCC, 5x3.2, 1.27P CASE 848AC−01 ISSUE O NOTES: D A 1. DIMENSIONING AND TOLERANCING PER B D1 ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. PIN ONE MILLIMETERS REFERENCE DIM MIN MAX E1 E A 1.05 1.35 2X 0.15 C A1 0.35 0.65 A3 0.90 REF b 0.50 0.80 2X 0.15 C D 5.00 BSC TOP VIEW D1 4.25 4.55 E 3.20 BSC E1 2.45 2.75 0.10 C E2 2.90 3.20 e 1.27 BSC A L 0.75 1.05 A1 A3 METALLIZED C SEATING SOLDERING FOOTPRINT* ZONES PLANE SIDE VIEW 6X0.74 16.X13 1 E2 3.30 6XL 6Xb e 0.10 C A B 0.05 C BOTTOM VIEW 1 PACKAGE 1.27 OUTLINE PITCH DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PureEdge is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5773−3850 Sales Representative http://onsemi.com NBXDPA019/D 8