Numonyx® NAND SLC small page 70 nm Discrete 512 Mbit, 528 Byte/264 Word page, x8/x16, 1.8 V/3 V Features – Hardware program/erase locked during power transitions  Density  Electronic signature – 512 Mbit: 4096 blocks – Manufacturer ID:  NAND Flash interface x8 device: 20h – x8 or x16 bus width x16 device: 0020h – Multiplexed address/data – Device ID: NAND512W3A2S: 76h  Memory configuration NAND512W4A2S: 0056h – Page size: NAND512R3A2S: 36h x8 device: (512 + 16 spare) Bytes NAND512R4A2S: 0046h x16 device: (256 + 8 spare) Words  Package – Block size: x8 device: (16K + 512 spare) Bytes – RoHS compliant x16 device: (8K + 256 spare) Words – TSOP48 12x20mm  Supply voltage: 1.8 V, 3V – VFBGA63 9x11mm  Read/write performance – Random access: 12µs (3V)/15µs(1.8V) Table 1. Device summary (max) Root part number list - see Table25 for details – Sequential access: 30ns (3V)/50ns (1.8V)(min) NAND512W3A2S – Page program time: 200µs (typ) NAND512W4A2S – Block erase time: 2ms (typ) NAND512R3A2S – Programming performance (typ): NAND512R4A2S x8 device: 2.3MByte/s x16 device: 2.4MByte/s  Additional features – Copy back program mode – Error correction code models – Bad blocks management and wear leveling algorithms – Hardware simulation models  Quality and reliability – 100,000 program/erase cycles (with ECC) – 10 years data retention – Operating temperature: –40 to 85°C  Security – OTP area – Serial number (unique ID) January 2018 210403 - Rev 5 1/51 www.numonyx.com 1

Contents Numonyx SLC SP 70 nm Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 Pointer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2.1 Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2.2 Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.3 Sequential row read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.4 Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.5 Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.7 Read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.7.1 Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.7.2 P/E/R controller bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.7.3 Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.7.4 SR5, SR4, SR3, SR2 and SR1 are reserved . . . . . . . . . . . . . . . . . . . . . 26 6.8 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2/51

Numonyx SLC SP 70 nm Contents 7 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2 NAND Flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5 Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.6 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.6.1 Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.6.2 IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 32 9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.1 Ready/Busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 44 10.2 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3/51

List of tables Numonyx SLC SP 70 nm List of tables Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Product description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. Valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6. Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 7. Address insertion, x8 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Address insertion, x16 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9. Address definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 10. Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11. Copy back program addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 12. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 13. Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 14. NAND Flash failure modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 15. Program, erase times and program erase endurance cycles. . . . . . . . . . . . . . . . . . . . . . . 32 Table 16. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 17. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 18. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 19. DC characteristics, 1.8V devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 20. DC characteristics, 3V devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 21. AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 22. AC characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 23. TSOP48 - 48 lead plastic thin small outline, 12x20mm, mechanical data. . . . . . . . . . . . 47 Table 24. VFBGA63 9x11x1.05mm - 6x8 +15 active ball array, 0.8mm pitch, mechanical data 48 Table 25. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 26. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4/51

Numonyx SLC SP 70 nm List of figures List of figures Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. TSOP48 connections - x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. VFBGA63 connections - x8 devices (top view through package). . . . . . . . . . . . . . . . . . . . 10 Figure 5. Memory array organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Pointer operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. Pointer operations for programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 8. Read (A,B,C) operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9. Sequential row read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 10. Sequential row read block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 11. Read block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 12. Page program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 13. Copy back operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14. Block erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 15. Bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 16. Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 17. Equivalent testing circuit for AC characteristics measurement. . . . . . . . . . . . . . . . . . . . . . 34 Figure 18. Command Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 19. Address Latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 20. Data Input Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 21. Sequential data output after read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 22. Read status register AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 23. Read electronic signature AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 24. Page read A/read B operation AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 25. Read C operation, one page AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 26. Page program AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 27. Block erase AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 28. Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 29. Program/erase enable waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 30. Program/erase disable waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 31. Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 32. Ready/Busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 33. Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 46 Figure 34. Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 35. TSOP48 - 48 lead plastic thin small outline, 12x20mm, package outline . . . . . . . . . . . . 47 Figure 36. VFBGA63 9x11x1.05mm - 6x8+15, 0.8mm pitch, package outline. . . . . . . . . . . . . . 48 5/51

Important Notes and Warnings Important Notes and Warnings Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron. Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications. Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product. Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component. Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative.

Description Numonyx SLC SP 70 nm 1 Description The NAND Flash 528Byte/264Word page is a family of non-volatile Flash memories that uses the single level cell (SLC) NAND technology. It is referred to as the small page family. The devices have a density of 512Mbits and operate with either a 1.8 or 3V voltage supply. The size of a page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width. The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or x16 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. To extend the lifetime of NAND Flash devices it is strongly recommended to implement an error correction code (ECC). The use of ECC correction allows to achieve up to 100,000 program/erase cycles for each block. A write protect pin is available to give a hardware protection against program and erase operations. The devices feature an open-drain Ready/Busy output that can be used to identify if the program/erase/read (P/E/R) controller is currently active. The use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. A Copy Back command is available to optimize the management of defective blocks. When a page program operation fails, the data can be programmed in another page without having to resend the data to be programmed. The devices are available in the TSOP48 (12x20mm) and VFBGA63 (9 x 11 x 1.05mm) packages and in two different versions: l No option (Chip Enable ‘care’, sequential row read enabled): the sequential row read feature allows to download up to all the pages in a block with one read command and addressing only the first page to read l With Chip Enable ‘don’t care’ feature. This enables the sharing of the bus between more active memories that are simultaneously active as Chip Enable transitions during latency do not stop read operations. Program and erase operations are not interrupted by Chip Enable transitions. They also come with the following security features: l OTP (one time programmable) area, which is a restricted access area where sensitive data/code can be stored permanently. The access sequence and further details about this feature are subject to an NDA (non disclosure agreement) l Serial number (unique identifier), which enables each device to be uniquely identified. It is subject to an NDA and is, therefore, not described in the datasheet. For more details about these security features, contact your nearest Numonyx sales office. For information on how to order these devices refer to Table25: Ordering information scheme. Devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ’1’. See Table2: Product description, for all the devices available in the family. 6/51

Numonyx SLC SP 70 nm Description Table 2. P roduct description Timings Root part Bus Page Block Memory Operating Density Random Sequential Page Block Package number width size size array voltage access access program erase Max Min Typ Typ 512+16 16K+512 NAND512W3A2S x8 Bytes Bytes 2.7 to 3.6V 12µs 30ns 256+8 8K+256 NAND512W4A2S x16 512 Words Words 32 pages x TSOP48 200µs 2ms Mbit 512+16 16K+512 4096 blocks VFBGA63 NAND512R3A2S x8 Bytes Bytes 1.7 to 1.95V 15µs 50ns 256+8 8K+256 NAND512R4A2S x16 Words Words Figure 1. Logic diagram VDD 8 I/O8-I/O15, x16 E I/O0-I/O7, x8/x16 R W NAND flash RB AL CL WP VSS AI07557C 7/51

Description Numonyx SLC SP 70 nm Table 3. S ignal names Signal Function Direction I/O8-15 Data input/outputs for x16 devices I/O Data input/outputs, address inputs, or command inputs for x8 and I/O0-7 I/O x16 devices AL Address Latch Enable Input CL Command Latch Enable Input E Chip Enable Input R Read Enable Input RB Ready/Busy (open-drain output) Output W Write Enable Input WP Write Protect Input V Supply voltage Power supply DD V Ground Ground SS NC Not connected internally – DU Do not use – Figure 2. Logic block diagram Address register/counter er AL d o NAND flash c CL e memory array d W Command P/E/R controller, X high voltage E interface generator logic WP R Page buffer Y decoder Command register I/O buffers & latches RB I/O0-I/O7, x8/x16 I/O8-I/O15, x16 AI07561c 8/51

Numonyx SLC SP 70 nm Description Figure 3. TSOP48 connections - x8 devices NC 1 48 NC NC NC NC NC NC NC NC I/O7 NC I/O6 RB I/O5 R I/O4 E NC NC NC NC NC NAND flash VDD 12 (x8) 37 VDD VSS 13 36 VSS NC NC NC NC CL NC AL I/O3 W I/O2 WP I/O1 NC I/O0 NC NC NC NC NC NC NC 24 25 NC AI07585C 9/51

Description Numonyx SLC SP 70 nm Figure 4. VFBGA63 connections - x8 devices (top view through package) 1 2 3 4 5 6 7 8 9 10 A DU DU DU DU B DU DU DU C WP AL VSS E W RB D NC R CL NC NC NC E NC NC NC NC NC NC F NC NC NC NC NC NC G NC NC NC NC NC NC H NC I/O0 NC NC NC VDD J NC I/O1 NC VDD I/O5 I/O7 K VSS I/O2 I/O3 I/O4 I/O6 VSS L DU DU DU DU M DU DU DU DU AI07586B 10/51

Numonyx SLC SP 70 nm Memory array organization 2 Memory array organization The memory array is made up of NAND structures where 16 cells are connected in series. The memory array is organized in blocks where each block contains 32 pages. The array is split into two areas, the main area and the spare area. The main area of the array is used to store data whereas the spare area is typically used to store error correction codes, software flags or bad block identification. In x8 devices the pages are split into a main area with two half pages of 256 Bytes each and a spare area of 16 Bytes. In the x16 devices the pages are split into a 256 Word main area and an 8Word spare area. Refer to Figure5: Memory array organization. Bad blocks The NAND Flash 528 Byte/264 Word page devices may contain bad blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional bad blocks may develop during the lifetime of the device. The bad block information is written prior to shipping (refer to Section7.1: Bad block management for more details). Table4 shows the minimum number of valid blocks in each device. The values shown include both the bad blocks that are present when the device is shipped and the bad blocks that could develop later on. These blocks need to be managed using bad blocks management, block replacement or error correction codes (refer to Section7: Software algorithms). T able 4. Valid blocks Density of device Min Max 512Mbit 4016 4096 11/51

Memory array organization Numonyx SLC SP 70 nm Figure 5. Memory array organization x8 DEVICES x16 DEVICES Block = 32 pages Block = 32 pages Page = 528 bytes (512+16) Page = 264 words (256+8) S p are are a S p are are a 1st half page 2nd half page Main area (256 bytes) (256 bytes) Block Block Page Page 8 bits 16 bits 512 Bytes 256 words 16 8 bytes words Page buffer, 512 bytes Page buffer, 264 words 512 bytes by1t6es 8 bits 256 words wo8rds 16 bits AI07587 12/51

Numonyx SLC SP 70 nm Signal descriptions 3 Signal descriptions See Figure1: Logic diagram, and Table3: Signal names, for a brief overview of the signals connected to the devices. Table5 provides the detailed descriptions of the signals. T able 5. Signal descriptions Symbol Type Description Input/Output signals Input/outputs 0 to 7 are used to input the selected address, output the data during a read operation or input a command or data during a write operation. The inputs are I/O0-I/O7 Input/Output latched on the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or the outputs are disabled. Input/outputs 8 to 15 are only available in x16 devices. They are used to output the data during a read operation or input data during a write operation. Command and address I/O8-I/O15 Input/Output inputs only require I/O0 to I/O7. The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when the device is deselected or the outputs are disabled. Control signals The Address Latch Enable activates the latching of the address inputs in the command interface. When AL is AL Input High, the inputs are latched on the rising edge of Write Enable. The Command Latch Enable activates the latching of the command inputs in the command interface. When CL is CL Input High, the inputs are latched on the rising edge of Write Enable. The Chip Enable input activates the memory control logic, input buffers, decoders and read circuitry. When Chip Enable is Low, V , the device is selected. IL If Chip Enable goes High (V ) while the device is busy IH programming or erasing, the device remains selected and does not go into standby mode. While the device is busy reading: – the Chip Enable input should be held Low during the E Input whole busy time (t ) for devices that do not feature BLBH1 the Chip Enable don’t care option. Otherwise, the read operation in progress is interrupted and the device goes into standby mode. – for devices that feature the Chip Enable don’t care option, the Chip Enable going High during the busy time (t ) will not interrupt the read operation and the BLBH1 device will not go into standby mode. 13/51

Signal descriptions Numonyx SLC SP 70 nm Table 5. Signal descriptions (continued) Symbol Type Description The Read Enable, R, controls the sequential data output during read operations. Data is valid t after the falling R Input RLQV edge of R. The falling edge of R also increments the internal column address counter by one. The Write Enable input, W, controls writing to the command interface, input address and data latches. Both addresses and data are latched on the rising edge of Write Enable. W Input During power-up and power-down a recovery time of 10µs (min) is required before the command interface is ready to accept a command. It is recommended to keep Write Enable High during the recovery time. The Write Protect pin is an input that gives a hardware protection against unwanted program or erase operations. When Write Protect is Low, V , the device does not accept WP Input IL any program or erase operations. It is recommended to keep the Write Protect pin Low, V , IL during power-up and power-down. The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R controller is currently active. When Ready/Busy is Low, V , a read, program or erase OL operation is in progress. When the operation completes Ready/Busy goes High, V . OH The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single RB Output pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. During power-up and power-down a recovery time of 10µs (min) is required before the command interface is ready to accept a command. During the recovery time the RB signal is Low, V . OL Refer to the Section10.1: Ready/Busy signal electrical characteristics for details on how to calculate the value of the pull-up resistor. Supply V provides the power supply to the internal core of the DD memory device. It is the main power supply for all operations (read, program and erase). VDD Supply voltage An internal voltage detector disables all functions whenever V is below the V threshold (see Figure34: DD LKO Data protection) to protect the device from any involuntary program/erase operations during power-transitions. Ground, V is the reference for the power supply. It must V Ground SS, SS be connected to the system ground. 14/51

Numonyx SLC SP 70 nm Bus operations 4 Bus operations There are six standard bus operations that control the memory. Each of these is described in this section, see Table6: Bus operations, for a summary. 4.1 Command input Command input bus operations are used to give commands to the memory. Command are accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input commands. See Figure18 and Table21 for details of the timings requirements. 4.2 Address input Address input bus operations are used to input the memory address. Four bus cycles are required to input the addresses for the 512Mbit devices (refer to Table7 and Table8, Address Insertion). The addresses are accepted when Chip Enable is Low, Address Latch Enable is High, Command Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses. See Figure19 and Table21 for details of the timings requirements. 4.3 Data input Data Input bus operations are used to input the data to be programmed. Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the Write Enable signal. The data is input sequentially using the Write Enable signal. See Figure20, Table21, and Table22 for details of the timings requirements. 4.4 Data output Data Output bus operations are used to read: the data in the memory array, the status register, the electronic signature and the serial number. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low, and Command Latch Enable is Low. The data is output sequentially using the Read Enable signal. See Figure21 and Table22 for details of the timings requirements. 15/51

Bus operations Numonyx SLC SP 70 nm 4.5 Write protect Write protect bus operations are used to protect the memory against program or erase operations. When the Write Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up. 4.6 Standby When Chip Enable is High the memory enters standby mode, the device is deselected, outputs are disabled and power consumption is reduced. T able 6. Bus operations Bus operation E AL CL R W WP I/O0 - I/O7 I/O8 - I/O15(1) Command input V V V V Rising X(2) Command X IL IL IH IH Address input V V V V Rising X Address X IL IH IL IH Data input V V V V Rising X Data input Data input IL IL IL IH Data output V V V Falling V X Data output Data output IL IL IL IH Write protect X X X X X V X X IL Standby V X X X X X X X IH 1. Only for x16 devices. 2. WP must be V when issuing a program or erase command. IH T able 7. Address insertion, x8 devices(1)(2) Bus I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 cycle 1st A7 A6 A5 A4 A3 A2 A1 A0 2nd A16 A15 A14 A13 A12 A11 A10 A9 3rd A24 A23 A22 A21 A20 A19 A18 A17 4th V V V V V V V A25 IL IL IL IL IL IL IL 1. A8 is set Low or High by the 00h or 01h command, see Section6.1: Pointer operations. 2. Any additional address input cycles is ignored. T able 8. Address insertion, x16 devices(1)(2) Bus I/O8- I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 cycle I/O15 1st X A7 A6 A5 A4 A3 A2 A1 A0 2nd X A16 A15 A14 A13 A12 A11 A10 A9 3rd X A24 A23 A22 A21 A20 A19 A18 A17 4th(4) X V V V V V V V A25 IL IL IL IL IL IL IL 1. A8 is don’t care in x16 devices. 2. Any additional address input cycle is ignored. 16/51

Numonyx SLC SP 70 nm Bus operations T able 9. Address definition Address Definition A0 - A7 Column address A9 - A25 Page address A9 - A13 Address in block A14 - A25 Block address A8 is set Low or High by the 00h or 01h A8 command, and is don’t care in x16 devices 17/51

Command set Numonyx SLC SP 70 nm 5 Command set All bus write operations to the device are interpreted by the command interface. The commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal is High. Device operations are selected by writing specific commands to the command register. The two-step command sequences for program and erase operations are imposed to maximize data security. The commands are summarized in Table10. T able 10. Commands Bus write operations(1)(2) Command Command accepted during 1st cycle 2nd cycle 3rd cycle busy Read A 00h – – Read B(3) 01h – – Read C 50h – – Read Electronic Signature 90h – – Read Status Register 70h – – Yes Page Program 80h 10h – Copy Back Program 00h 8Ah (10h)(4) Block Erase 60h D0h – Reset FFh – – Yes 1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown. 2. Any undefined command sequence is ignored by the device. 3. The Read B command (code 01h) is not used in x16 devices. 4. The Program Confirm command (code 10h) is no more necessary for 512Mbit, 70 nm devices. It is optional and has been maintained for backward compatibility. 18/51

Numonyx SLC SP 70 nm Device operations 6 Device operations 6.1 Pointer operations As the NAND Flash memories contain two different areas for x16 devices and three different areas for x8 devices (see Figure6) the read command codes (00h, 01h, 50h) are used to act as pointers to the different areas of the memory array (they select the most significant column address). The Read A and Read B commands act as pointers to the main memory area. Their use depends on the bus width of the device. l In x16 devices the Read A command (00h) sets the pointer to area A (the whole of the main area) that is Words 0 to 255. l In x8 devices the Read A command (00h) sets the pointer to area A (the first half of the main area) that is Bytes 0 to 255, and the Read B command (01h) sets the pointer to area B (the second half of the main area) that is Bytes 256 to 511. In both the x8 and x16 devices the Read C command (50h), acts as a pointer to area C (the spare memory area) that is Bytes 512 to 527 or Words 256 to 263. Once the Read A and Read C commands have been issued the pointer remains in the respective areas until another pointer code is issued. However, the Read B command is effective for only one operation, once an operation has been executed in area B the pointer returns automatically to area A. The pointer operations can also be used before a program operation, that is the appropriate code (00h, 01h or 50h) can be issued before the program command 80h is issued (see Figure7). Figure 6. Pointer operations x8 devices x16 devices Area A Area B Area C Area A Area C (00h) (01h) (50h) (00h) (50h) bytes words bytes 0 - 255 bytes 256 - 511 512 - 527 words 0 - 255 256 - 263 A B C Page buffer A C Page buffer Pointer Pointer (00h,01h,50h) (00h,50h) AI07592 19/51

Device operations Numonyx SLC SP 70 nm Figure 7. Pointer operations for programming AREA A I/O 00h 80h AIdndpruetsss Data Input 10h 00h 80h AIdndpruetsss Data Input 10h Areas A, B, C can be programmed depending on how much data is input. Subsequent 00h commands can be omitted. AREA B I/O 01h 80h AIdndpruetsss Data Input 10h 01h 80h AIdndpruetsss Data Input 10h Areas B, C can be programmed depending on how much data is input. The 01h command must be re-issued before each program. AREA C I/O 50h 80h AIdndpruetsss Data Input 10h 50h 80h AIdndpruetsss Data Input 10h Only Areas C can be programmed. Subsequent 50h commands can be omitted. ai07591 6.2 Read memory array Each operation to read the memory area starts with a pointer operation as shown in the Section6.1: Pointer operations. Once the area (main or spare) has been selected using the Read A, Read B or Read C commands four bus cycles are required to input the address (refer to Table7 and Table8) of the data to be read. The device defaults to read A mode after power-up or a reset operation. When reading the spare area addresses: l A0 to A3 (x8 devices) l A0 to A2 (x16 devices) are used to set the start address of the spare area while addresses: l A4 to A7 (x8 devices) l A3 to A7 (x16 devices) are ignored. Once the Read A or Read C commands have been issued they do not need to be reissued for subsequent read operations as the pointer remains in the respective area. However, the Read B command is effective for only one operation, once an operation has been executed in area B the pointer returns automatically to area A and so another Read B command is required to start another read operation in area B. Once a Read command is issued two types of operations are available: random read and page read. 6.2.1 Random read Each time the command is issued the first read is random read. 20/51

Numonyx SLC SP 70 nm Device operations 6.2.2 Page read After the random read access the page data is transferred to the page buffer in a time of t (refer to Table22 for value). Once the transfer is complete the Ready/Busy signal WHBH goes High. The data can then be read out sequentially (from selected column address to last column address) by pulsing the Read Enable signal. Figure 8. Read (A,B,C) operations CL E W AL R tBLBH1 (read) RB I/O 010h0/ h5/0h Address input Data output (sequentially) Command code Busy ai07595c 6.2.3 Sequential row read After the data in last column of the page is output, if the Read Enable signal is pulsed and Chip Enable remains Low, then the next page is automatically loaded into the page buffer and the read operation continues. A sequential row read operation can only be used to read within a block. If the block changes a new read command must be issued. Refer to Figure9: Sequential row read operations and Figure10: Sequential row read block diagrams for details about sequential row read operations. To terminate a sequential row read operation, set to High the Chip Enable signal for more than t . Sequential row read is not available EHEL when the Chip Enable don’t care option is enabled. 21/51

Device operations Numonyx SLC SP 70 nm Figure 9. Sequential row read operations tBLBH1 tBLBH1 tBLBH1 (Read Busy time) RB Busy Busy Busy I/O 010h0/ h5/0h Address Inputs Page1 sOt utput Page2 n Od utput PageN tOhu tput Command Code ai07597 Figure 10. Sequential row read block diagrams Read A Command, x8 Devices Read A Command, x16 Devices Area A Area B Area C Area A Area C (1st half Page) (2nd half Page)(Spare) (main area) (Spare) 1st page 1st page Block 2nd page Block 2nd page Nth page Nth page Read B Command, x8 Devices Read C Command, x8/x16 Devices Area A Area B Area C Area A Area A/ B Area C (1st half Page) (2nd half Page)(Spare) (Spare) 1st page 1st page Block 2nd page Block 2nd page Nth page Nth page AI07598 Figure 11. Read block diagrams Read A command, x8 devices Read A command, x16 devices Area A Area B Area C Area A Area C (1st half page) (2nd half page) (spare) (main area) (spare) A9-A26(1) A9-A26(1) A0-A7 A0-A7 Read B command, x8 devices Read C command, x8/x16 devices Area A Area B Area C Area A Area A/ B Area C (1st half page) (2nd half page) (spare) (spare) A9-A26(1) A9-A26(1) A0-A3 (x 8) A0-A7 A0-A2 (x 16) A4-A7 (x 8), A3-A7 (x 16) are don't care AI07596 1. Highest address depends on device density. 22/51

Numonyx SLC SP 70 nm Device operations 6.3 Page program The page program operation is the standard operation to program data to the memory array. The main area of the memory array is programmed by page, however partial page programming is allowed where any number of Bytes (1 to 528) or Words (1 to 264) can be programmed. The maximum number of consecutive partial page program operations allowed in the same page is three. After exceeding this a Block Erase command must be issued before any further program operations can take place in that page. Before starting a page program operation a pointer operation can be performed to point to the area to be programmed. Refer to the Section6.1: Pointer operations and Figure7 for details. Each page program operation consists of five steps (see Figure12): 1. One bus cycle is required to setup the Page Program command 2. Four bus cycles are then required to input the program address (refer to Table7 and Table8) 3. The data is then input (up to 528 Bytes/264 Words) and loaded into the page buffer 4. One bus cycle is required to issue the confirm command to start the P/E/R controller 5. The P/E/R controller then programs the data into the array. Once the program operation has started the status register can be read using the Read Status Register command. During program operations the status register only flags errors for bits set to '1' that have not been successfully programmed to '0'. During the program operation, only the Read Status Register and Reset commands are accepted, all other commands are ignored. Once the program operation has completed the P/E/R controller bit SR6 is set to ‘1’ and the Ready/Busy signal goes High. The device remains in read status register mode until another valid command is written to the command interface. Figure 12. Page program operation tBLBH2 (Program Busy time) RB Busy I/O 80h Address Inputs Data Input 10h 70h SR0 Page Program Confirm Read Status Register Setup Code Code ai07566 1. Before starting a page program operation a pointer operation can be performed. Refer to Section6.1: Pointer operations for details. 23/51

Device operations Numonyx SLC SP 70 nm 6.4 Copy back program The copy back program operation is used to copy the data stored in one page and reprogram it in another page. The copy back program operation does not require external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. The operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block. If the copy back program operation fails an error is signalled in the status register. However as the standard external ECC cannot be used with the copy back operation bit error due to charge loss cannot be detected. For this reason it is recommended to limit the number of copy back operations on the same data and or to improve the performance of the ECC. The copy back program operation requires two steps: 1. The source page must be read using the Read A command (one bus write cycle to setup the command and then 4 bus write cycles to input the source page address). This operation copies all 264 Words/ 528 Bytes from the page into the page buffer 2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is given with the 4 bus cycles to input the target page address. Refer to Table11 for the addresses that must be the same for the source and target pages 3. The Program Confirm command (code 10h) is no more necessary on 512Mbit, 70nm devices. It is optional and has been maintained for backward compatibility. After a copy back program operation, a partial-page program is not allowed in the target page until the block has been erased. See Figure13 for an example of the copy back operation. Table 11. C opy back program addresses Density Same address for source and target pages 512 Mbit A25 Figure 13. Copy back operation tBLBH1 tBLBH2 (Read Busy time) (Program Busy time) RB Busy I/O 00h AddSreosusr cIneputs 8Ah AddrTeasrsg eIntputs 10h(1) 70h SR0 Read Code Copy Back Read Status Register Code ai13187 1. The Program Confirm command (code 10h) is no more necessary on 512Mbit, 70 nm devices. It is optional and has been maintained for backward compatibility. 24/51

Numonyx SLC SP 70 nm Device operations 6.5 Block erase Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to ‘1’. All previous data in the block is lost. An erase operation consists of three steps (refer to Figure14): 1. One bus cycle is required to setup the Block Erase command 2. Only three bus cycles are required to input the block address. The first cycle (A0 to A7) is not required as only addresses A14 to A25 are valid, A9 to A13 are ignored. In the last address cycle I/O2 to I/O7 must be set to V . IL 3. One bus cycle is required to issue the Confirm command to start the P/E/R controller. Once the erase operation has completed the status register can be checked for errors. Figure 14. Block erase operation tBLBH3 (Erase Busy time) RB Busy I/O 60h BlockIn Apudtdsress D0h 70h SR0 Block Erase Confirm Read Status Register Setup Code Code ai07593 6.6 Reset The Reset command is used to reset the command interface and status register. If the Reset command is issued during any operation, the operation will be aborted. If it was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be partially programmed or erased. If the device has already been reset then the new Reset command will not be accepted. The Ready/Busy signal goes Low for t after the Reset command is issued. The value BLBH4 of t depends on the operation that the device was performing when the command was BLBH4 issued, refer to Table22 for the values. 25/51

Device operations Numonyx SLC SP 70 nm 6.7 Read status register The device contains a status register which provides information on the current or previous program or erase operation. The various bits in the status register convey information and errors on the operation. The status register is read by issuing the Read Status Register command. The status register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip Enable or Read Enable, whichever occurs last. When several memories are connected in a system, the use of Chip Enable and Read Enable signals allows the system to poll each device separately, even when the Ready/Busy pins are common-wired. It is not necessary to toggle the Chip Enable or Read Enable signals to update the contents of the status register. After the Read Status Register command has been issued, the device remains in read status register mode until another command is issued. Therefore if a Read Status Register command is issued during a random read cycle a new read command must be issued to continue with a page read. The status register bits are summarized in Table12: Status register bits. Refer to Table12 in conjunction with the following text descriptions. 6.7.1 Write protection bit (SR7) The write protection bit can be used to identify if the device is protected or not. If the write protection bit is set to ‘1’ the device is not protected and program or erase operations are allowed. If the write protection bit is set to ‘0’ the device is protected and program or erase operations are not allowed. 6.7.2 P/E/R controller bit (SR6) The program/erase/read controller bit indicates whether the P/E/R controller is active or inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R controller is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive (device is ready). 6.7.3 Error bit (SR0) The error bit is used to identify if any errors have been detected by the P/E/R controller. The error bit is set to ’1’ when a program or erase operation has failed to write the correct data to the memory. If the error bit is set to ‘0’ the operation has completed successfully. 6.7.4 SR5, SR4, SR3, SR2 and SR1 are reserved Table 12. S tatus register bits Bit Name Logic level Definition '1' Not protected SR7 Write protection '0' Protected '1' P/E/R C inactive, device ready SR6 Program/ erase/ read controller '0' P/E/R C active, device busy SR5, SR4, SR3, SR2, SR1 Reserved Don’t care 26/51

Numonyx SLC SP 70 nm Device operations Table 12. Status register bits Bit Name Logic level Definition ‘1’ Error – operation failed SR0 Generic error ‘0’ No error – operation successful 6.8 Read electronic signature The device contains a manufacturer code and device code. To read these codes two steps are required: 1. first use one bus write cycle to issue the Read Electronic Signature command (90h), followed by an address input of 00h 2. then perform two bus read operations – the first reads the manufacturer code and the second, the device code. Further bus read operations are ignored. Refer to Table13: Electronic signature, for information on the addresses. Table 13. E lectronic signature Part number I/O organization Supply voltage Manufacturer code Device code NAND512W3A2S x8 20h 76h 3 V NAND512W4A2S x16 0020h 0056h NAND512R3A2S x8 20h 36h 1.8V NAND512R4A2S x16 0020h 0046h 27/51

Software algorithms Numonyx SLC SP 70 nm 7 Software algorithms This section gives information on the software algorithms that Numonyx recommends to implement to manage the bad blocks and extend the lifetime of the NAND device. NAND Flash memories are programmed and erased by Fowler-Nordheim tunneling using a high voltage. Exposing the device to a high voltage for extended periods can cause the oxide layer to be damaged. For this reason, the number of program and erase cycles is limited (see Table15: Program, erase times and program erase endurance cycles for value) and it is recommended to implement garbage collection, a wear-leveling algorithm and an error correction code, to extend the number of program and erase cycles and increase the data retention. To help integrate a NAND memory into an application Numonyx can provide a full range of software solutions: file system, sector management, drivers, and code management. Contact the nearest Numonyx sales office or visit www.numonyx.com for more details. 7.1 Bad block management Devices with bad blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A bad block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased (FFh). The bad block information is written prior to shipping. Any block, where the 1st and 6th Bytes (x8 device)/1st Word (x16 device), in the spare area of the 1st page, does not contain FFh is a bad block. The bad block information must be read before any erase is attempted as the bad block information may be erased. For the system to be able to recognize the bad blocks based on the original information it is recommended to create a bad block table following the flowchart shown in Figure15. 7.2 NAND Flash memory failure modes Over the lifetime of the device additional bad blocks may develop. To implement a highly reliable system, all the possible failure modes must be considered: l Program/erase failure: in this case the block has to be replaced by copying the data to a valid block. These additional bad blocks can be identified as attempts to program or erase them will give errors in the status register. As the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. The Copy Back Program command can be used to copy the data to a valid block. See Section6.4: Copy back program for more details l Read failure: in this case, ECC correction must be implemented. To efficiently use the memory space, it is mandatory to recover single-bit errors, which occur during read operations, by using ECC without replacing the whole block. 28/51

Numonyx SLC SP 70 nm Software algorithms Refer to Table14 for the procedure to follow if an error occurs during an operation. T able 14. NAND Flash failure modes Operation Procedure Erase Block Replacement Program Block Replacement Read ECC Figure 15. Bad block management flowchart START Block Address = Block 0 Increment Block Address Data NO Update = FFh? Bad Block table YES Last NO block? YES END AI07588C 29/51

Software algorithms Numonyx SLC SP 70 nm 7.3 Garbage collection When a data page needs to be modified, it is faster to write to the first available page, and the previous page is marked as invalid. After several updates it is necessary to remove invalid pages to free some memory space. To free this memory space and allow further program operations it is recommended to implement a garbage collection algorithm. In a garbage collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see Figure16). Figure 16. Garbage collection Old area New area (after GC) Valid page Invalid Free page page (erased) AI07599B 7.4 Wear-leveling algorithm For write-intensive applications, it is recommended to implement a wear-leveling algorithm to monitor and spread the number of write cycles per block. In memories that do not use a wear-leveling algorithm not all blocks get used at the same rate. The wear-leveling algorithm ensures that equal use is made of all the available write cycles for each block. There are two wear-leveling levels: l First level wear-leveling, new data is programmed to the free blocks that have had the fewest write cycles l Second level wear-leveling, long-lived data is copied to another block so that the original block can be used for more frequently-changed data. The second level wear-leveling is triggered when the difference between the maximum and the minimum number of write cycles per block reaches a specific threshold. 7.5 Error correction code Users must implement an error correction code (ECC) to identify and correct errors in the data stored in the NAND Flash memories. The ECC implemented must be able to correct 1bit every 512Bytes. Sensible data stored in the spare area must be covered by ECC as well. 30/51

Numonyx SLC SP 70 nm Software algorithms 7.6 Hardware simulation models 7.6.1 Behavioral simulation models Denali software corporation models are platform independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior and timings of NAND Flash devices, and so allow software to be developed before hardware. 7.6.2 IBIS simulations models IBIS (I/O buffer information specification) models describe the behavior of the I/O buffers and electrical characteristics of Flash devices. These models provide information such as AC characteristics, rise/fall times and package mechanical data, all of which are measured or simulated at voltage and temperature ranges wider than those allowed by target specifications. IBIS models are used to simulate PCB connections and can be used to resolve compatibility issues when upgrading devices. They can be imported into SPICETOOLS. 31/51

Program and erase times and endurance cycles Numonyx SLC SP 70 nm 8 Program and erase times and endurance cycles The program and erase times and the number of program/erase cycles per block are shown in Table15. T able 15. Program, erase times and program erase endurance cycles NAND Flash Parameters Unit Min Typ Max Page program time 200 500 µs Block erase time 2 3 ms Program/erase cycles per block (with ECC) 100,000 cycles Data retention 10 years 9 Maximum ratings Stressing the device above the ratings listed in Table16: Absolute maximum ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 16. A bsolute maximum ratings Value Symbol Parameter Unit Min Max T Temperature under bias –50 125 °C BIAS T Storage temperature –65 150 °C STG T Lead temperature during soldering 260 °C LEAD 1.8 V devices –0.6 2.7 V V (1) Input or output voltage IO 3 V devices –0.6 4.6 V 1.8 V devices –0.6 2.7 V V Supply voltage DD 3 V devices –0.6 4.6 V 1. Minimum voltage may undershoot to –2V for less than 20ns during transitions on input and I/O pins. Maximum voltage may overshoot to V + 2V for less than 20ns during transitions on I/O pins. DD 32/51

Numonyx SLC SP 70 nm DC and AC parameters 10 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table17: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. T able 17. Operating and AC measurement conditions NAND Flash Parameter Units Min Max 1.8V devices 1.7 1.95 Supply voltage (V ) V DD 3V devices 2.7 3.6 Ambient temperature (T ) Grade 6 –40 85 °C A Load capacitance (C ) (1 TTL GATE 1.8V devices 30 L pF and C ) L 3V devices 50 1.8V devices 0 V DD Input pulses voltages V 3V devices 0.4 2.4 1.8V devices 0.9 Input and output timing ref. voltages V 3V devices 1.5 Input rise and fall times 5 ns Output circuit resistors, R 8.35 k ref T able 18. Capacitance(1)(2) Symbol Parameter Test conditions Typ Max Unit C Input capacitance V = 0V 10 pF IN IN Input/output C V = 0V 10 pF I/O capacitance IL 1. T = 25°C, f = 1MHz. C and C are not 100% tested. A IN I/O 2. Input/output capacitances double on stacked devices. 33/51

DC and AC parameters Numonyx SLC SP 70 nm M Figure 17. Equivalent testing circuit for AC characteristics measurement VDD 2Rref NAND flash CL 2Rref GND GND Ai11085 Table 19. D C characteristics, 1.8V devices(1) Symbol Parameter Test conditions Min Typ Max Unit I Sequential tRLRL minimum – 8 15 mA DD1 read E=V I =0mA IL, OUT Operating current I Program – – 8 15 mA DD2 I Erase – – 8 15 mA DD3 I Standby current (TTL) E=V -0.2, WP=0V/V – – 1 mA DD4 DD DD I Standby current (CMOS) E=V -0.2, WP=0/V – 10 50 µA DD5 DD DD I Input leakage current V = 0 to V max – – ±10 µA LI IN DD I Output leakage current V = 0 to V max – – ±10 µA LO OUT DD V Input high voltage – V -0.4 – V +0.3 V IH DD DD V Input low voltage – 0.3 – 0.4 V IL V Output high voltage level I = 100µA V -0.1 – – V OH OH DD V Output low voltage level I = 100µA – – 0.1 V OL OL I (RB) Output low current (RB) V = 0.1V 3 4 mA OL OL V supply voltage (erase and V DD – – – 1.1 V LKO program lockout) 1. Standby and leakage currents refer to a single die device. For a multiple die device, their value must be multiplied for the number of dice of the stacked device, while the active power consumption depends on the number of dice concurrently executing different operations. 34/51

Numonyx SLC SP 70 nm DC and AC parameters Table 20. D C characteristics, 3V devices(1) Symbol Parameter Test conditions Min Typ Max Unit I Sequential tRLRL minimum – 10 20 mA DD1 read E=V I =0mA IL, OUT Operating current I Program – – 10 20 mA DD2 I Erase – – 10 20 mA DD3 I Standby current (TTL) E=V , WP=0V/V – – 1 mA DD4 IH DD I Standby current (CMOS) E=V -0.2, WP=0/V – 10 50 µA DD5 DD DD I Input leakage current V = 0 to V max – – ±10 µA LI IN DD I Output leakage current V = 0 to V max – – ±10 µA LO OUT DD V Input high voltage – 2.0 – V +0.3 V IH DD V Input low voltage – 0.3 – 0.8 V IL V Output high voltage level I = 400µA 2.4 – – V OH OH V Output low voltage level I = 2.1mA – – 0.4 V OL OL I (RB) Output low current (RB) V = 0.4V 8 10 mA OL OL V supply voltage (erase and V DD – – – 1.5 V LKO program lockout) 1. Standby and leakage currents refer to a single die device. For a multiple die device, their value must be multiplied for the number of dice of the stacked device, while the active power consumption depends on the number of dice concurrently executing different operations. Table 21. A C characteristics for command, address, data input Alt. 1.8 V 3 V Symbol Parameter Unit symbol devices devices t Address Latch Low to Write Enable High ALLWH t AL setup time Min 25 15 ns ALS t Address Latch High to Write Enable High ALHWH t Command Latch High to Write Enable High CLHWH t CL setup time Min 25 15 ns CLS t Command Latch Low to Write Enable High CLLWH t t Data Valid to Write Enable High Data setup time Min 20 15 ns DVWH DS t t Chip Enable Low to Write Enable High E setup time Min 30 20 ns ELWH CS t Write Enable High to Address Latch High WHALH t AL hold time Min 10 5 ns ALH t Write Enable High to Address Latch Low WHALL t Write Enable High to Command Latch High WHCLH t CL hold time Min 10 5 ns CLH t Write Enable High to Command Latch Low WHCLL t t Write Enable High to Data Transition Data hold time Min 10 5 ns WHDX DH t t Write Enable High to Chip Enable High E hold time Min 10 5 ns WHEH CH W High hold t t Write Enable High to Write Enable Low Min 15 10 ns WHWL WH time t t Write Enable Low to Write Enable High W pulse width Min 25 15 ns WLWH WP t t Write Enable Low to Write Enable Low Write cycle time Min 45 30 ns WLWL WC 35/51

DC and AC parameters Numonyx SLC SP 70 nm Table 22. A C characteristics for operations Alt. 1.8 V 3 V Symbol Parameter Unit symbol devices devices tALLRL1 Address Latch Low to Read electronic signature Min 10 10 ns t t AR Read Enable Low Read cycle Min 10 10 ns ALLRL2 t t Ready/Busy High to Read Enable Low Min 20 20 ns BHRL RR t Read busy time Max 15 12 µs BLBH1 t t Program busy time Max 500 500 µs BLBH2 PROG t t Erase busy time Max 3 3 ms BLBH3 BERS Ready/Busy Low to Reset busy time, during ready Max 5 5 µs Ready/Busy High Reset busy time, during read Max 5 5 µs t t BLBH4 RST Reset busy time, during program Max 10 10 µs Reset busy time, during erase Max 500 500 µs t t Command Latch Low to Read Enable Low Min 10 10 ns CLLRL CLR t t Data Hi-Z to Read Enable Low Min 0 0 ns DZRL IR t t Chip Enable High to Output Hi-Z Max 30 30 ns EHQZ CHZ t t Chip Enable Low to Output Valid Max 45 35 ns ELQV CEA Read Enable High to t t Read Enable High hold time Min 15 10 ns RHRL REH Read Enable Low t t Read Enable High to Output Hi-Z Max 30 30 ns RHQZ RHZ t EHQX T Chip Enable High or Read Enable High to Output Hold Min 10 10 ns OH t RHQX Read Enable Low to t t Read Enable pulse width Min 25 15 ns RLRH RP Read Enable High Read Enable Low to t t Read cycle time Min 50 30 ns RLRL RC Read Enable Low Read Enable Low to Read Enable access time t t Max 30 18 ns RLQV REA Output Valid Read ES access time(1) Write Enable High to t t Read busy time Max 15 12 µs WHBH R Ready/Busy High t t Write Enable High to Ready/Busy Low Max 100 100 ns WHBL WB t t Write Enable High to Read Enable Low Min 60 60 ns WHRL WHR t VHWH t Write protection time Min 100 100 ns t (2) WW VLWH 1. ES = electronic signature. 2. During a program/erase enable operation, t is the delay from WP High to W High. During a program/erase disable VHWH operation, t is the delay from WP Low to W High. VLWH 36/51

Numonyx SLC SP 70 nm DC and AC parameters Figure 18. Command Latch AC waveforms CL tCLHWH tWHCLL (CL Setup time) (CL Hold time) tELWH tWHEH H(E Setup time) (E Hold time) E tWLWH W tALLWH tWHALH (ALSetup time) (AL Hold time) AL tDVWH tWHDX (Data Setup time) (Data Hold time) I/O Command ai13105 Figure 19. Address Latch AC waveforms tCLLWH (CL Setup time) CL tWLWL tWLWL tWLWL tWLWL tELWH (E Setup time) E tWLWH tWLWH tWLWH tWLWH tWLWH W tWHWL tWHWL tWHWL tWHWL tALHWH (AL Setup time) tWHALL tWHALL tWHALL tWHALL (AL Hold time) AL tDVWH tDVWH tDVWH tDVWH tDVWH (Data Setup time) tWHDX tWHDX tWHDX tWHDX tWHDX (Data Hold time) I/O Adrress Adrress Adrress Adrress Adrress cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 ai13106 37/51

DC and AC parameters Numonyx SLC SP 70 nm Figure 20. Data Input Latch AC waveforms tWHCLH (CL Hold time) CL tWHEH (E Hold time) E tALLWH (ALSetup time) tWLWL AL tWLWH tWLWH tWLWH W tDVWH tDVWH tDVWH (Data Setup time) tWHDX tWHDX tWHDX (Data Hold time) I/O Data In 0 Data In 1 Data In Last ai13107 Figure 21. Sequential data output after read AC waveforms tEHQX tEHQZ ai08031b 1. CL = Low, AL = Low, W = High. 38/51

Numonyx SLC SP 70 nm DC and AC parameters Figure 22. Read status register AC waveforms tCLHWH tELWH tEHQX ai08032c Figure 23. Read electronic signature AC waveforms CL E W AL tALLRL1 R tRLQV (Read ES Access time) I/O 90h 00h Man. Device code code Read Electronic 1st Cycle Manufacturer and Signature Address Device Codes Command ai08039b 1. Refer to Table13 for the values of the manufacturer and device codes. 39/51

DC and AC parameters Numonyx SLC SP 70 nm Figure 24. Page read A/read B operation AC waveforms CL E tWLWL tEHQZ W tWHBL AL tALLRL2 tWHBH tRLRL tRHQZ (Read Cycle time) R tRLRH tBLBH1 RB I/O 00h or Add.N Add.N Add.N Add.N Data Data Data Data 01h cycle 1 cycle 2 cycle 3 cycle 4 N N+1 N+2 Last Command Data Output Code Address N Input Busy from Address N to Last Byte or Word in Page tRHQX tEHQX ai08033c 40/51

Numonyx SLC SP 70 nm DC and AC parameters Figure 25. Read C operation, one page AC waveforms CL E W tWHBH tWHALL AL tALLRL2 tBHRL R I/O 50h Acydcdle. M1 Acydcdle. M2 Acydcdle. M3 Acydcdle. M4 Data M DLaatsat RB Command Data Output from M to Code Address M Input Busy Last Byte or Word in Area C ai08035b 1. A0-A7 is the address in the spare memory area, where A0-A3 are valid and A4-A7 are don’t care. 41/51

DC and AC parameters Numonyx SLC SP 70 nm Figure 26. Page program AC waveforms CL E tWLWL tWLWL tWLWL (Write Cycle time) W tWHBL tBLBH2 (Program Busy time) AL R I/O 80h cAydcdle.N 1 cAydcdle.N 2 cAydcdle.N 3 cAydcdle.N 4 N Last 10h 70h SR0 RB Page Program Confirm Setup Code Code Page Address Input Data Input Program Read Status Register ai08037 42/51

Numonyx SLC SP 70 nm DC and AC parameters Figure 27. Block erase AC waveforms CL E tWLWL (Write Cycle time) W tWHBL tBLBH3 (Erase Busy time) AL R I/O 60h Add. Add. Add. D0h 70h SR0 cycle 1 cycle 2 cycle 3 RB SeBtulopc Ck oEmramsaend Block Address Input CCoondfierm Block Erase Read Status Register ai08038b Figure 28. Reset AC waveforms W AL CL R I/O FFh tBLBH4 (Reset Busy time) RB ai08043 43/51

DC and AC parameters Numonyx SLC SP 70 nm Figure 29. Program/erase enable waveforms W tVHWH WP RB I/O 80h 10h ai12477 Figure 30. Program/erase disable waveforms W tVLWH WP High RB I/O 80h 10h ai12478 10.1 Ready/Busy signal electrical characteristics Figure31, Figure32 and Figure33 show the electrical characteristics for the Ready/Busy signal. The value required for the resistor R can be calculated using the following equation: P V –V  DDmax OLmax R min= ------------------------------------------------------------- P IOL+ IL So, 1.85V R min1.8V= --------------------------- P + 3mA I L 3.2V R min3V= --------------------------- P + 8mA I L where I is the sum of the input currents of all the devices tied to the Ready/Busy signal. R L P max is determined by the maximum value of t. r 44/51

Numonyx SLC SP 70 nm DC and AC parameters Figure 31. Ready/Busy AC waveform 1.8 V device - VOL: 0.1 V, VOH : VDD - 0.1 V 3.3 V device - VOL: 0.4 V, VOH : 2.4 V ready VDD VOH VOL busy tf tr NI3087 Figure 32. Ready/Busy load circuit ibusy VDD RP DEVICE RB Open Drain Output VSS AI07563B 45/51

DC and AC parameters Numonyx SLC SP 70 nm Figure 33. Resistor value versus waveform timings for Ready/Busy signal 1. T = 25°C. 10.2 Data protection The Numonyx NAND device is designed to guarantee data protection during power transitions. A V detection circuit disables all NAND operations, if V is below the V threshold. DD DD LKO In the V range from V to the lower limit of nominal range, the WP pin should be kept DD LKO Low (V ) to guarantee hardware protection during power transitions as shown in the figure IL below (Figure34). Figure 34. Data protection VDD Nominal Range VLKO Locked Locked WP Ai13188 46/51

Numonyx SLC SP 70 nm Package mechanical 11 Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which have a lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. RoHS compliant specifications are available at www.numonyx.com. Figure 35. TSOP48 - 48 lead plastic thin small outline, 12x20mm, package outline 1 48 e D1 B L1 24 25 A2 A E1 E DIE A1 α L C CP TSOP-G 1. Drawing is not to scale. Table 23. T SOP48 - 48 lead plastic thin small outline, 12x20mm, mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 1.20 0.047 A1 0.10 0.05 0.15 0.004 0.002 0.006 A2 1.00 0.95 1.05 0.039 0.037 0.041 B 0.22 0.17 0.27 0.009 0.007 0.011 C 0.10 0.21 0.004 0.008 CP 0.08 0.003 D1 12.00 11.90 12.10 0.472 0.468 0.476 E 20.00 19.80 20.20 0.787 0.779 0.795 E1 18.40 18.30 18.50 0.724 0.720 0.728 e 0.50 – – 0.020 – – L 0.60 0.50 0.70 0.024 0.020 0.028 L1 0.80 0.031  3° 0° 5° 3° 0° 5° 47/51

Package mechanical Numonyx SLC SP 70 nm Figure 36. VFBGA63 9x11x1.05mm - 6x8+15, 0.8mm pitch, package outline D D2 D1 FD1 FE e E E2 E1 SE b ddd BALL "A1" FE1 A e SD FD A2 A1 BGA-Z75 1. Drawing is not to scale. Table 24. V FBGA63 9x11x1.05mm - 6x8 +15 active ball array, 0.8mm pitch, mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 1.05 0.041 A1 0.25 0.010 A2 0.65 0.026 b 0.45 0.40 0.50 0.018 0.016 0.020 D 9.00 8.90 9.10 0.354 0.350 0.358 D1 4.00 0.157 D2 7.20 0.283 ddd 0.10 0.004 E 11.00 10.90 11.10 0.433 0.429 0.437 E1 5.60 0.220 E2 8.80 0.346 e 0.80 0.031 FD 2.50 0.098 FD1 0.90 0.035 FE 2.70 0.106 FE1 1.10 0.043 SD 0.40 0.016 SE 0.40 0.016 48/51

Numonyx SLC SP 70 nm Ordering information 12 Ordering information Note: Not all combinations are necessarily available. For a list of available devices or for further information on any aspect of these products, please contact your nearest Numonyx sales office. Table 25. O rdering information scheme Example: NAND512W3A 2 S ZA 6 E Device type NAND = NAND Flash memory Density 512 = 512Mbit Operating voltage R = V = 1.7 to 1.95V DD W = V = 2.7 to 3.6V DD Bus width 3 = x8 4 = x16 Family identifier A = 528Byte/264Word page Device options 0 = No option (Chip Enable ‘care’; sequential row read enabled) 2 = Chip Enable don’t care enabled Product version S = fifth version Package N = TSOP48 12 x 20mm ZA = VFBGA63 9x11x1.05mm Temperature range 6 = –40°C to 85°C X = –40°C to 85°C; included in product longevity program (PLP) Option E = RoHS compliant package, standard packing F = RoHS compliant package, tape & reel packing 49/51

Revision history Numonyx SLC SP 70 nm 13 Revision history Table 26. Document revision history Date Revision Changes 03-Feb-2010 1 Initial release. 29-Jul-2010 2 Added information about 1.8 V devices. 25-Mar-2011 3 Removed “Preliminary Data” status from document. Added option X under temperature range in ordering information 17-Oct-2012 4 table Added Important Notes and Warnings section for further 30-Jan-2018 5 clarification aligning to industry. 50/51

Numonyx SLC SP 70 nm 51/51