MTD5P06V Preferred Device Power MOSFET 5 Amps, 60 Volts P−Channel DPAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge http://onsemi.com circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage V(BR)DSS RDS(on) TYP ID MAX transients. 60 V 340 m(cid:2) 5.0 A Features • Avalanche Energy Specified P−Channel • I and V Specified at Elevated Temperature DSS DS(on) D • Pb−Free Packages are Available MAXIMUM RATINGS (TC = 25°C unless otherwise noted) G Rating Symbol Value Unit Drain−to−Source Voltage VDSS 60 Vdc S Drain−to−Gate Voltage (RGS = 1.0 M(cid:2)) VDGR 60 Vdc Gate−to−Source Voltage − Continuous VGS ±15 Vdc MARKING − Non−repetitive (tp ≤ 10 ms) VGSM ±25 Vpk DIAGRAM Drain Current − Continuous @ 25°C ID 5 Adc 4 − Continuous @ 100°C ID 4 Drain − Single Pulse (tp ≤ 10 (cid:3)s) IDM 18 Apk 4 Total Power Dissipation @ 25°C PD 40 W DPAK G DToetraal tPe oawbeorv eD i2s5s°ipCation @ TA = 25°C (Note 2) 02.2.17 WW/°C 1 2 3 CSATSYEL 3E6 92C YWW5P06V Operating and Storage Temperature Range TJ, Tstg −55 to °C 175 2 1 3 Drain Single Pulse Drain−to−Source Avalanche EAS 125 mJ Gate Source Energy − Starting TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 5 Apk, L = 10 mH, RG = 25 (cid:2)) Y = Year Thermal Resistance °C/W WW = Work Week Junction−to−Case R(cid:4)JC 3.75 5P06V = Device Code Junction−to−Ambient (Note 1) R(cid:4)JA 100 G = Pb−Free Package Junction−to−Ambient (Note 2) R(cid:4)JA 71.4 Maximum Lead Temperature for Soldering TL 260 °C Purposes, 1/8″ from Case for 10 seconds ORDERING INFORMATION Stresses exceeding Maximum Ratings may damage the device. Maximum Device Package Shipping† Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the MTD5P06V DPAK 75 Units/Rail Recommended Operating Conditions may affect device reliability. 1. When surface mounted to an FR4 board using the minimum recommended MTD5P06VT4 DPAK 2500/Tape & Reel pad size. 2. When surface mounted to an FR−4 board using the 0.5 sq in drain pad size. MTD5P06VT4G DPAK 2500/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Preferred devices are recommended choices for future use and best overall value. © Semiconductor Components Industries, LLC, 2006 1 Publication Order Number: July, 2006 − Rev. 6 MTD5P06V/D

MTD5P06V ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain−Source Breakdown Voltage V(BR)DSS Vdc (VGS = 0 Vdc, ID = 0.25 mAdc) 60 − − Temperature Coefficient (Positive) − 61.2 − mV/°C Zero Gate Voltage Drain Current IDSS (cid:3)Adc (VDS = 60 Vdc, VGS = 0 Vdc) − − 10 (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) − − 100 Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS − − 100 nAdc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage VGS(th) Vdc (VDS = VGS, ID = 250 (cid:3)Adc) 2.0 2.8 4.0 Threshold Temperature Coefficient (Negative) − 4.7 − mV/°C Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 2.5 Adc) RDS(on) − 0.34 0.45 (cid:2) Drain−Source On−Voltage VDS(on) Vdc (VGS = 10 Vdc, ID = 5 Adc) − − 2.7 (VGS = 10 Vdc, ID = 2.5 Adc, TJ = 150°C) − − 2.6 Forward Transconductance gFS Mhos (VDS = 15 Vdc, ID = 2.5 Adc) 1.5 3.6 − DYNAMIC CHARACTERISTICS Input Capacitance Ciss − 367 510 pF Output Capacitance (VDS = 2f5 = V 1d.c0, MVHGSz )= 0 Vdc, Coss − 140 200 Transfer Capacitance Crss − 29 60 SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time td(on) − 11 20 ns Rise Time (VDD = 30 Vdc, ID = 5 Adc, tr − 26 50 Turn−Off Delay Time VGS = 10 Vdc, RG = 9.1 (cid:2)) td(off) − 17 30 Fall Time tf − 19 40 Gate Charge QT − 12 20 nC (See Figure 8) Q1 − 3.0 − (VDS = 48 Vdc, ID = 5 Adc, VGS = 10 Vdc) Q2 − 5.0 − Q3 − 5.0 − SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 5( IASd =c ,5 V AGdSc =, V0G VSd =c ,0 T VJ d=c 1)50°C) VSD −− 11..7324 3−.5 Vdc Reverse Recovery Time trr − 97 − ns (IS = 5 Adc, VGS = 0 Vdc, ta − 73 − dIS/dt = 100 A/(cid:3)s) tb − 24 − Reverse Recovery Stored Charge QRR − 0.42 − (cid:3)C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance LD nH (Measured from the drain lead 0.25″ from package to center of die) − 4.5 − Internal Source Inductance LS nH (Measured from the source lead 0.25″ from package to source bond pad) − 7.5 − 3. Pulse Test: Pulse Width ≤300 (cid:3)s, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2

MTD5P06V TYPICAL ELECTRICAL CHARACTERISTICS 10 10 VGS = 10V 9 V 8 V 7 V 9 VDS ≥ 10 V TJ = −55°C 25°C MPS) 8 TJ = 25°C MPS) 8 100°C T (A T (A 7 N 6 V N E 6 E 6 R R R R U U 5 C C AIN 4 AIN 4 R R D D 3 , D 5 V , D I 2 I 2 4 V 1 0 0 0 1 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics S) S) M M H 0.6 H 0.4 CE (O 0.55 VGS = 10 V CE (O TJ = 25°C TAN TJ = 100°C TAN VGS = 10 V S 0.5 S0.35 SI SI E E E R 0.45 E R C C OUR 0.4 25°C OUR 0.3 15 V S S − − O 0.35 O T T − − N N AI 0.3 AI0.25 R R D D , n) 0.25 −55°C , n) o o S( S( D 0.2 D 0.2 R 1 2 3 4 5 6 7 8 9 10 R 1 2 3 4 5 6 7 8 9 10 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Drain Current Figure 4. On−Resistance versus Drain Current and Temperature and Gate Voltage 1.8 100 E NC VGS = 10 V VGS = 0 V TA 1.6 ID = 2.5 A S SI E 1.4 RCE RED)1.2 E (nA) UZ G −SOMALI 1 AKA 10 TJ = 125°C OR E AIN−T(NO0.8 , LSS DR 0.6 ID , n) S(o 0.4 D R 0.2 1 −50 −25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Figure 6. Drain−To−Source Leakage Temperature Current versus Voltage http://onsemi.com 3

MTD5P06V POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted The capacitance (C ) is read from the capacitance curve at iss by recognizing that the power MOSFET is charge a voltage corresponding to the off−state condition when controlled. The lengths of various switching intervals ((cid:5)t) calculating t and is read at a voltage corresponding to the d(on) are determined by how fast the FET input capacitance can on−state when calculating t . d(off) be charged by current from the generator. At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET The published capacitance data is difficult to use for source lead, inside the package and in the circuit wiring calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive charge data is used. In most cases, a satisfactory estimate of current. The voltage is determined by Ldi/dt, but since di/dt average input current (I ) can be made from a G(AV) rudimentary analysis of the drive circuit so that is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also t = Q/I G(AV) complicates the mathematics. And finally, MOSFETs have During the rise and fall time interval when switching a finite internal gate resistance which effectively adds to the resistive load, V remains virtually constant at a level resistance of the driving source, but the internal resistance GS known as the plateau voltage, V . Therefore, rise and fall is difficult to measure and, consequently, is not specified. SGP times may be approximated by the following: The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching t = Q x R /(V − V ) r 2 G GG GSP performance is affected by the parasitic circuit elements. If t = Q x R /V f 2 G GSP the parasitics were not present, the slope of the curves would where maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize V = the gate drive voltage, which varies from zero to V GG GG common inductance in the drain and gate circuit loops and R = the gate drive resistance G is believed readily achievable with board mounted and Q2 and VGSP are read from the gate charge curve. components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which During the turn−on and turn−off delay times, gate current is approximates an optimally snubbed inductive load. Power not constant. The simplest calculation uses appropriate MOSFETs may be safely operated into an inductive load; values from the capacitance curves in a standard equation for however, snubbing reduces switching losses. voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] t = R C In (V /V ) d(off) G iss GG GSP 1000 900 Ciss VDS = 0 V TJ = 25°C 800 pF) 700 E ( NC 600 Crss A T 500 CI PA 400 Ciss A C C, 300 Coss 200 100 VGS = 0 V Crss 0 10 5 0 5 10 15 20 25 VGS VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4

MTD5P06V GE (VOLTS) 1098 QT VGS 645084DS, DRAV 100 TIVDJD =D= 5=2 5A3°0C V −SOURCE VOLTA 7564 Q1 Q2 32340462IN−TO−SOURCE V t, TIME (ns) 10 VGS = 10 V td(off)tftr td(on) O O −T 3 18LT E A T G V, GAGS 021 Q3 VDS TIDJ == 52 5A°C 1602E (VOLTS 1 0 2 4 6 8 10 12 14 ) 1 10 100 Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS) Figure 8. Gate−To−Source and Drain−To−Source Figure 9. Resistive Switching Time Voltage versus Total Charge Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS 5 4.5 TJ = 25°C VGS = 0 V 4 S) P M 3.5 A T ( 3 N E RR 2.5 U C 2 E C R 1.5 U O S 1 , S I 0.5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the reliable operation, the stored energy from circuit inductance maximum simultaneous drain−to−source voltage and drain dissipated in the transistor while in avalanche must be less current that a transistor can handle safely when it is forward than the rated limit and adjusted for operating conditions biased. Curves are based upon maximum peak junction differing from those specified. Although industry practice is temperature and a case temperature (T ) of 25°C. Peak to rate in terms of energy, avalanche energy capability is not C repetitive pulsed power limits are determined by using the a constant. The energy rating decreases non−linearly with an thermal response data in conjunction with the procedures increase of peak current in avalanche and peak junction discussed in AN569, “Transient Thermal Resistance−General temperature. Data and Its Use.” Although many E−FETs can withstand the stress of Switching between the off−state and the on−state may drain−to−source avalanche at currents up to rated pulsed traverse any load line provided neither rated peak current current (I ), the energy rating is specified at rated DM (I ) nor rated voltage (V ) is exceeded and the continuous current (I ), in accordance with industry DM DSS D transition time (t,t) do not exceed 10 (cid:3)s. In addition the total custom. The energy rating must be derated for temperature r f power averaged over a complete switching cycle must not as shown in the accompanying graph (Figure 12). Maximum exceed (TJ(MAX) − TC)/(R(cid:4)JC). energy at currents below rated continuous ID can safely be A Power MOSFET designated E−FET can be safely used assumed to equal the values indicated. in switching circuits with unclamped inductive loads. For http://onsemi.com 5

MTD5P06V SAFE OPERATING AREA 100 140 VSIGNSG =L E20 P VULSE CE ID = 5 A R 120 S) TC = 25°C OU T (AMP 10 −TO−SGY (mJ) 100 N NR CURRE 100 (cid:3)s E DRAIE ENE 80 N LSCH 60 I, DRAID 1 RTHDSE(RonM) AL1ILM mLITsIMI1T0 ms dc , SINGLE PUSAVALAN 4200 PACKAGE LIMIT EA 0.1 0 0.1 1 10 100 25 50 75 100 125 150 175 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus Safe Operating Area Starting Junction Temperature 1.0 D = 0.5 E C EN TIVSTA 0.2 FFECRESI 0.1 EL ED MA 0.1 P(pk) MALIZTHER 0.05 RD (cid:4)CJCU(Rt)V =E rS(t )A RP(cid:4)PJCLY FOR POWER ORNT 0.02 PULSE TRAIN SHOWN r(t), NTRANSIE SINGLE PU0.L0S1E DUTtY1 CYt2CLE, D = t1/t2 RTJE(pAkD) − T TIMC E= APT(p tk1) R(cid:4)JC(t) 0.01 1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01 t, TIME (s) Figure 13. Thermal Response di/dt IS trr ta tb TIME tp 0.25 IS IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 6

MTD5P06V PACKAGE DIMENSIONS DPAK CASE 369C−01 ISSUE O NOTES: −T− SPELAATNIENG 1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. B C 2.CONTROLLING DIMENSION: INCH. V R E INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.235 0.245 5.97 6.22 B 0.250 0.265 6.35 6.73 4 Z C 0.086 0.094 2.19 2.38 A D 0.027 0.035 0.69 0.88 S E 0.018 0.023 0.46 0.58 1 2 3 F 0.037 0.045 0.94 1.14 U G 0.180 BSC 4.58 BSC K H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.102 0.114 2.60 2.89 F J L 0.090 BSC 2.29 BSC R 0.180 0.215 4.57 5.45 L H S 0.025 0.040 0.63 1.01 U 0.020 −−− 0.51 −−− D2 PL V 0.035 0.050 0.89 1.27 Z 0.155 −−− 3.93 −−− G 0.13 (0.005)M T STYLE 2: PIN 1.GATE 2.DRAIN 3.SOURCE 4.DRAIN SOLDERING FOOTPRINT* 6.20 3.0 0.244 0.118 2.58 0.101 5.80 1.6 6.172 0.228 0.063 0.243 (cid:2) (cid:3) mm SCALE 3:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5773−3850 Sales Representative http://onsemi.com MTD5P06V/D 7