MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • LowSupplyVoltageRange:1.8Vto3.6V • UniversalSerialInterface(USI)SupportingSPI 23 • Ultra-LowPowerConsumption andI2C – ActiveMode:220µAat1MHz,2.2V • 10-Bit200-kspsAnalog-to-Digital(A/D) ConverterWithInternalReference,Sample- – StandbyMode:0.5 µA and-Hold,andAutoscan(MSP430G2x52Only) – OffMode(RAMRetention):0.1µA • On-ChipComparatorforAnalog • FivePower-SavingModes • BrownoutDetector • Ultra-FastWake-UpFromStandbyModein • SerialOnboardProgramming, LessThan1µs NoExternalProgrammingVoltageNeeded, • 16-BitRISCArchitecture,62.5-nsInstruction ProgrammableCodeProtectionbySecurity CycleTime Fuse • BasicClockModuleConfigurations • On-ChipEmulationLogicWithSpy-Bi-Wire – InternalFrequenciesupto16MHzWith Interface FourCalibratedFrequencies • FamilyMembersareSummarizedinTable1 – InternalVery-Low-PowerLow-Frequency • PackageOptions (LF)Oscillator – TSSOP:14Pin,20Pin – 32-kHzCrystal – PDIP:20Pin – ExternalDigitalClockSource – QFN:16Pin • One16-BitTimer_AWithThree • ForCompleteModuleDescriptions,Seethe Capture/CompareRegisters MSP430x2xxFamilyUser’sGuide(SLAU144) • Upto16Capacitive-TouchEnabledI/OPins DESCRIPTION The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes,isoptimizedtoachieveextendedbatterylifeinportablemeasurementapplications.Thedevicefeaturesa powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. Thedigitallycontrolledoscillator(DCO)allowswake-upfromlow-powermodestoactivemodeinlessthan1µs. The MSP430G2x52 and MSP430G2x12 series of microcontrollers are ultra-low-power mixed signal microcontrollers with built-in 16-bit timers, and up to 16 I/O capacitive-touch enabled pins and built-in communication capability using the universal serial communication interface and have a versatile analog comparator. The MSP430G2x52 series have a 10-bit A/D converter. For configuration details see Table 1. Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, andthenprocessthedatafordisplayorfortransmissiontoahostsystem. 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. MSP430isatrademarkofTexasInstruments. 2 Allothertrademarksarethepropertyoftheirrespectiveowners. 3 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2010–2013,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Table1.AvailableOptions(1) Flash RAM Comp_A ADC10 Package Device EEM (KB) (B) Timer_A Channel Channel USI Clock I/O Type(2) MSP430G2452IN20 16 20-PDIP MSP430G2452IPW20 16 20-TSSOP 1 8 256 1xTA3 8 8 1 LF,DCO,VLO MSP430G2452IRSA16 10 16-QFN MSP430G2452IPW14 10 14-TSSOP MSP430G2352IN20 16 20-PDIP MSP430G2352IPW20 16 20-TSSOP 1 4 256 1xTA3 8 8 1 LF,DCO,VLO MSP430G2352IRSA16 10 16-QFN MSP430G2352IPW14 10 14-TSSOP MSP430G2252IN20 16 20-PDIP MSP430G2252IPW20 16 20-TSSOP 1 2 256 1xTA3 8 8 1 LF,DCO,VLO MSP430G2252IRSA16 10 16-QFN MSP430G2252IPW14 10 14-TSSOP MSP430G2152IN20 16 20-PDIP MSP430G2152IPW20 16 20-TSSOP 1 1 128 1xTA3 8 8 1 LF,DCO,VLO MSP430G2152IRSA16 10 16-QFN MSP430G2152IPW14 10 14-TSSOP MSP430G2412IN20 16 20-PDIP MSP430G2412IPW20 16 20-TSSOP 1 8 256 1xTA3 8 - 1 LF,DCO,VLO MSP430G2412IRSA16 10 16-QFN MSP430G2412IPW14 10 14-TSSOP MSP430G2312IN20 16 20-PDIP MSP430G2312IPW20 16 20-TSSOP 1 4 256 1xTA3 8 - 1 LF,DCO,VLO MSP430G2312IRSA16 10 16-QFN MSP430G2312IPW14 10 14-TSSOP MSP430G2212IN20 16 20-PDIP MSP430G2212IPW20 16 20-TSSOP 1 2 256 1xTA3 8 - 1 LF,DCO,VLO MSP430G2212IRSA16 10 16-QFN MSP430G2212IPW14 10 14-TSSOP MSP430G2112IN20 16 20-PDIP MSP430G2112IPW20 16 20-TSSOP 1 1 128 1xTA3 8 - 1 LF,DCO,VLO MSP430G2112IRSA16 10 16-QFN MSP430G2112IPW14 10 14-TSSOP (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) Packagedrawings,thermaldata,andsymbolizationareavailableatwww.ti.com/packaging. 2 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 DEVICE PINOUTS PWPACKAGE (TOPVIEW) DVCC 1 14 DVSS P1.0/TA0CLK/ACLK/A0/CA0 2 13 XIN/P2.6/TA0.1 P1.1/TA0.0/A1/CA1 3 12 XOUT/P2.7 P1.2/TA0.1/A2/CA2 4 11 TEST/SBWTCK P1.3/ADC10CLK/CAOUT/A3/VREF-/VEREF-/CA3 5 10 RST/NMI/SBWTDIO P1.4/TA0.2/SMCLK/A4/VREF+/VEREF+/CA4/TCK 6 9 P1.7/SDI/SDA/CAOUT/A7/CA7/TDO/TDI P1.5/TA0.0/SCLK/A5/CA5/TMS 7 8 P1.6/TA0.1/SDO/SCL/A6/CA6/TDI/TCLK NOTE: ADC10pinfunctionsareavailableonlyonMSP430G2x52. NOTE: ThepulldownresistorsofportpinsP2.0,P2.1,P2.2,P2.3,P2.4,andP2.5shouldbeenabledbysettingP2REN.x=1. RSAPACKAGE (TOPVIEW) CCSS CCSS VVVV DADA 16151413 P1.0/TA0CLK/ACLK/A0/CA0 1 12 XIN/P2.6/TA0.1 P1.1/TA0.0/A1/CA1 2 11 XOUT/P2.7 P1.2/TA0.1/A2/CA2 3 10 TEST/SBWTCK P1.3/ADC10CLK/CAOUT/A3/VREF-/VEREF-/CA3 4 9 RST/NMI/SBWTDIO 5 6 7 8 KSKDI LK/A4/VREF+/VEREF+/CA4/TCP1.5/TA0.0/SCLK/A5/CA5/TMA0.1/SDO/SCL/A6/CA6 TDI/TCL//TDO/TDI/SDA/CAOUT/A7/CA7 C TS M 6/7/ 4/S P1.P1. 1. P NOTE: ADC10pinfunctionsareavailableonlyonMSP430G2x52. NOTE: ThepulldownresistorsofportpinsP2.0,P2.1,P2.2,P2.3,P2.4,andP2.5shouldbeenabledbysettingP2REN.x=1. NORPWPACKAGE (TOPVIEW) DVCC 1 20 DVSS P1.0/TA0CLK/ACLK/A0/CA0 2 19 XIN/P2.6/TA0.1 P1.1/TA0.0/A1/CA1 3 18 XOUT/P2.7 P1.2/TA0.1/A2/CA2 4 17 TEST/SBWTCK P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3 5 16 RST/NMI/SBWTDIO P1.4/TA0.2/SMCLK/A4/VREF+/VEREF+/CA4/TCK 6 15 P1.7/SDI/SDA/CAOUT/A7/CA7/TDO/TDI P1.5/TA0.0/SCLK/A5/CA5/TMS 7 14 P1.6/TA0.1/SDO/SCL/A6/CA6/TDI/TCLK P2.0 8 13 P2.5 P2.1 9 12 P2.4 P2.2 10 11 P2.3 NOTE: ADC10pinfunctionsareavailableonlyonMSP430G2x52. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com FUNCTIONAL BLOCK DIAGRAMS FunctionalBlockDiagram,MSP430G2x52 XIN XOUT DVCC DVSS P1.x P2.x 8 up to 8 ACLK Clock Flash RAM ADC Port P1 Port P2 System SMCLK 8KB 256B 10-Bit 8 I/O up to 8 I/O 4KB 256B 8 Ch. Interrupt Interrupt MCLK 2KB 256B Autoscan capability capability 1KB 128B 1 ch DMA pullup/down pullup/down resistors resistors 16MHz CPU MAB incl. 16 MDB Registers Emulation USI 2BP Watchdog Timer0_A3 Comp_A+ Brownout WDT+ Universal JTAG Protection 3 CC Serial Interface 8 Channels 15-Bit Registers Interface SPI, I2C Spy-Bi Wire RST/NMI NOTE: Port P2. Two pins are available on the 14-pin and 16-pin package options. Eight pins are available on the 20-pin packageoptions. FunctionalBlockDiagram,MSP430G2x12 XIN XOUT DVCC DVSS P1.x P2.x 8 up to 8 ACLK Clock Flash Port P1 Port P2 System SMCLK 8KB RAM 8 I/O up to 8 I/O 4KB Interrupt Interrupt 2KB 256B capability capability MCLK 1KB pullup/down pullup/down resistors resistors 16MHz MAB CPU MDB incl. 16 Registers Emulation USI 2BP Watchdog Timer0_A3 Comp_A+ Brownout WDT+ Universal JTAG Protection 3 CC Serial Interface 8 Channels 15-Bit Registers Interface SPI, I2C Spy-Bi Wire RST/NMI NOTE: Port P2. Two pins are available on the 14-pin and 16-pin package options. Eight pins are available on the 20-pin packageoptions. 4 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 TERMINAL FUNCTIONS Table2.TerminalFunctions TERMINAL NO. I/O DESCRIPTION NAME 14 16 20 PW RSA N,PW P1.0/ General-purposedigitalI/Opin TA0CLK/ Timer0_A,clocksignalTACLKinput ACLK/ 2 1 2 I/O ACLKsignaloutput A0/ ADC10analoginputA0(1) CA0 Comparator_A+,CA0input P1.1/ General-purposedigitalI/Opin TA0.0/ Timer0_A,capture:CCI0Ainput,compare:Out0output 3 2 3 I/O A1/ ADC10analoginputA1(1) CA1 Comparator_A+,CA1input P1.2/ General-purposedigitalI/Opin TA0.1/ Timer0_A,capture:CCI1Ainput,compare:Out1output 4 3 4 I/O A2/ ADC10analoginputA2(1) CA2 Comparator_A+,CA2input P1.3/ General-purposedigitalI/Opin ADC10CLK/ ADC10,conversionclockoutput(1) CAOUT/ Comparator_A+,output 5 4 5 I/O A3/ ADC10analoginputA3(1) VREF-/VEREF-/ ADC10negativereferencevoltage(1) CA3 Comparator_A+,CA3input P1.4/ General-purposedigitalI/Opin SMCLK/ SMCLKsignaloutput TA0.2/ Timer0_A,capture:CCI2Ainput,compare:Out2output A4/ 6 5 6 I/O ADC10analoginputA4(1) VREF+/VEREF+/ ADC10positivereferencevoltage(1) CA4/ Comparator_A+,CA4input TCK JTAGtestclock,inputterminalfordeviceprogrammingandtest P1.5/ General-purposedigitalI/Opin TA0.0/ Timer0_A,compare:Out0output SCLK/ USI:clkinputinI2Cmode;clkin/outputinSPImode 7 6 7 I/O A5/ ADC10analoginputA5(1) CA5/ Comparator_A+,CA5input TMS JTAGtestmodeselect,inputterminalfordeviceprogrammingandtest P1.6/ General-purposedigitalI/Opin TA0.1/ Timer0_A,compare:Out1output SDO/ USI:DataoutputinSPImode SCL/ 8 7 14 I/O USI:I2CclockinI2Cmode A6/ ADC10analoginputA6(1) CA6/ Comparator_A+,CA6input TDI/TCLK JTAGtestdatainputortestclockinputduringprogrammingandtest (1) AvailableonlyonMSP430G2x52devices. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Table2.TerminalFunctions(continued) TERMINAL NO. I/O DESCRIPTION NAME 14 16 20 PW RSA N,PW P1.7/ General-purposedigitalI/Opin CAOUT/ Comparator_A+,output SDI/ USI:DatainputinSPImode SDA/ 9 8 15 I/O USI:I2CdatainI2Cmode A7/ ADC10analoginputA7(1) CA7/ Comparator_A+,CA7input TDO/TDI(2) JTAGtestdataoutputterminalortestdatainputduringprogrammingandtest P2.0 - - 8 I/O General-purposedigitalI/Opin P2.1 - - 9 I/O General-purposedigitalI/Opin P2.2 - - 10 I/O General-purposedigitalI/Opin P2.3 - - 11 I/O General-purposedigitalI/Opin P2.4 - - 12 I/O General-purposedigitalI/Opin P2.5 - - 13 I/O General-purposedigitalI/Opin XIN/ Inputterminalofcrystaloscillator P2.6/ 13 12 19 I/O General-purposedigitalI/Opin TA0.1 Timer0_A,compare:Out1output XOUT/ Outputterminalofcrystaloscillator(3) 12 11 18 I/O P2.7 General-purposedigitalI/Opin RST/ Reset NMI/ 10 9 16 I Nonmaskableinterruptinput SBWTDIO Spy-Bi-Wiretestdatainput/outputduringprogrammingandtest TEST/ SelectstestmodeforJTAGpinsonport1.Thedeviceprotectionfuseis 11 10 17 I connectedtoTEST. SBWTCK Spy-Bi-Wiretestclockinputduringprogrammingandtest DVCC 1 16 1 NA Supplyvoltage AVCC - 15 - NA Supplyvoltage DVSS 14 14 20 NA Groundreference AVSS - 13 - NA Groundreference NC - - - NA Notconnected QFNPad - Pad - NA QFNpackagepadconnectiontoV recommended. SS (2) TDOorTDIisselectedviaJTAGinstruction. (3) IfXOUT/P2.7isusedasaninput,excesscurrentflowsuntilP2SEL.7iscleared.Thisisduetotheoscillatoroutputdriverconnectionto thispadafterreset. 6 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All Program Counter PC/R0 operations, other than program-flow instructions, are performed as register operations in conjunction with Stack Pointer SP/R1 seven addressing modes for source operand and four addressingmodesfordestinationoperand. Status Register SR/CG1/R2 The CPU is integrated with 16 registers that provide Constant Generator CG2/R3 reduced instruction execution time. The register-to- register operation execution time is one cycle of the General-Purpose Register R4 CPUclock. General-Purpose Register R5 Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and General-Purpose Register R6 constant generator, respectively. The remaining registersaregeneral-purposeregisters. General-Purpose Register R7 Peripherals are connected to the CPU using data, address, and control buses, and can be handled with General-Purpose Register R8 allinstructions. General-Purpose Register R9 The instruction set consists of the original 51 instructions with three formats and seven address General-Purpose Register R10 modes and additional instructions for the expanded address range. Each instruction can operate on word General-Purpose Register R11 andbytedata. General-Purpose Register R12 Instruction Set General-Purpose Register R13 The instruction set consists of 51 instructions with three formats and seven address modes. Each General-Purpose Register R14 instruction can operate on word and byte data. Table 3 shows examples of the three types of General-Purpose Register R15 instruction formats; Table 4 shows the address modes. Table3.InstructionWordFormats FORMAT EXAMPLE OPERATION Dualoperands,source-destination ADDR4,R5 R4+R5–->R5 Singleoperands,destinationonly CALLR8 PC–>(TOS),R8–>PC Relativejump,un/conditional JNE Jump-on-equalbit=0 Table4.AddressModeDescriptions(1) ADDRESSMODE S D SYNTAX EXAMPLE OPERATION Register ✓ ✓ MOVRs,Rd MOVR10,R11 R10––>R11 Indexed ✓ ✓ MOVX(Rn),Y(Rm) MOV2(R5),6(R6) M(2+R5)––>M(6+R6) Symbolic(PCrelative) ✓ ✓ MOVEDE,TONI M(EDE)––>M(TONI) Absolute ✓ ✓ MOV&MEM,&TCDAT M(MEM)––>M(TCDAT) Indirect ✓ MOV@Rn,Y(Rm) MOV@R10,Tab(R6) M(R10)––>M(Tab+R6) M(R10)––>R11 Indirectautoincrement ✓ MOV@Rn+,Rm MOV@R10+,R11 R10+2––>R10 Immediate ✓ MOV#X,TONI MOV#45,TONI #45––>M(TONI) (1) S=source,D=destination Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Operating Modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-powermodeonreturnfromtheinterruptprogram. Thefollowingsixoperatingmodescanbeconfiguredbysoftware: • Activemode(AM) – Allclocksareactive • Low-powermode0(LPM0) – CPUisdisabled – ACLKandSMCLKremainactive,MCLKisdisabled • Low-powermode1(LPM1) – CPUisdisabled – ACLKandSMCLKremainactive,MCLKisdisabled – DCO'sdcgeneratorisdisabledifDCOnotusedinactivemode • Low-powermode2(LPM2) – CPUisdisabled – MCLKandSMCLKaredisabled – DCO'sdcgeneratorremainsenabled – ACLKremainsactive • Low-powermode3(LPM3) – CPUisdisabled – MCLKandSMCLKaredisabled – DCO'sdcgeneratorisdisabled – ACLKremainsactive • Low-powermode4(LPM4) – CPUisdisabled – ACLKisdisabled – MCLKandSMCLKaredisabled – DCO'sdcgeneratorisdisabled – Crystaloscillatorisstopped 8 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h. Thevectorcontainsthe16-bitaddressoftheappropriateinterrupthandlerinstructionsequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed) the CPUgoesintoLPM4immediatelyafterpower-up. Table5.InterruptSources,Flags,andVectors SYSTEM WORD INTERRUPTSOURCE INTERRUPTFLAG PRIORITY INTERRUPT ADDRESS Power-Up PORIFG ExternalReset RSTIFG WatchdogTimer+ WDTIFG Reset 0FFFEh 31,highest Flashkeyviolation KEYV(2) PCout-of-range(1) NMI NMIIFG (non)-maskable Oscillatorfault OFIFG (non)-maskable 0FFFCh 30 Flashmemoryaccessviolation ACCVIFG(2)(3) (non)-maskable 0FFFAh 29 0FFF8h 28 Comparator_A+ CAIFG(4) maskable 0FFF6h 27 WatchdogTimer+ WDTIFG maskable 0FFF4h 26 Timer0_A3 TACCR0CCIFG(4) maskable 0FFF2h 25 Timer0_A3 TACCR2TACCR1CCIFG.TAIFG(2)(4) maskable 0FFF0h 24 0FFEEh 23 0FFECh 22 ADC10(5) ADC10IFG(4)(5) maskable 0FFEAh 21 USI USIIFG,USISTTIFG(2)(4) maskable 0FFE8h 20 I/OPortP2(uptoeightflags) P2IFG.0toP2IFG.7(2)(4) maskable 0FFE6h 19 I/OPortP1(uptoeightflags) P1IFG.0toP1IFG.7(2)(4) maskable 0FFE4h 18 0FFE2h 17 0FFE0h 16 See (6) 0FFDEhto 15to0,lowest 0FFC0h (1) AresetisgeneratediftheCPUtriestofetchinstructionsfromwithinthemoduleregistermemoryaddressrange(0hto01FFh)orfrom withinunusedaddressranges. (2) Multiplesourceflags (3) (non)-maskable:theindividualinterrupt-enablebitcandisableaninterruptevent,butthegeneralinterruptenablecannot. (4) Interruptflagsarelocatedinthemodule. (5) MSP430G2x52only (6) Theinterruptvectorsataddresses0FFDEhto0FFC0harenotusedinthisdeviceandcanbeusedforregularprogramcodeif necessary. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Special Function Registers (SFRs) Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided withthisarrangement. Legend rw: Bitcanbereadandwritten. rw-0,1: Bitcanbereadandwritten.ItisresetorsetbyPUC. rw-(0,1): Bitcanbereadandwritten.ItisresetorsetbyPOR. SFRbitisnotpresentindevice. Table6.InterruptEnableRegister1and2 Address 7 6 5 4 3 2 1 0 00h ACCVIE NMIIE OFIE WDTIE rw-0 rw-0 rw-0 rw-0 WDTIE WatchdogTimerinterruptenable.Inactiveifwatchdogmodeisselected.ActiveifWatchdogTimerisconfiguredin intervaltimermode. OFIE Oscillatorfaultinterruptenable NMIIE (Non)maskableinterruptenable ACCVIE Flashaccessviolationinterruptenable Address 7 6 5 4 3 2 1 0 01h Table7.InterruptFlagRegister1and2 Address 7 6 5 4 3 2 1 0 02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw-0 rw-(0) rw-(1) rw-1 rw-(0) WDTIFG Setonwatchdogtimeroverflow(inwatchdogmode)orsecuritykeyviolation. ResetonV power-onoraresetconditionattheRST/NMIpininresetmode. CC OFIFG Flagsetonoscillatorfault. PORIFG Power-OnResetinterruptflag.SetonV power-up. CC RSTIFG Externalresetinterruptflag.SetonaresetconditionatRST/NMIpininresetmode.ResetonV power-up. CC NMIIFG SetviaRST/NMIpin Address 7 6 5 4 3 2 1 0 03h 10 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 Memory Organization Table8.MemoryOrganization MSP430G2112 MSP430G2212 MSP430G2312 MSP430G2412 MSP430G2152 MSP430G2252 MSP430G2352 MSP430G2452 Memory Size 1kB 2kB 4kB 8kB Main:interruptvector Flash 0xFFFFto0xFFC0 0xFFFFto0xFFC0 0xFFFFto0xFFC0 0xFFFFto0xFFC0 Main:codememory Flash 0xFFFFto0xFC00 0xFFFFto0xF800 0xFFFFto0xF000 0xFFFFto0xE000 Informationmemory Size 256Byte 256Byte 256Byte 256Byte Flash 010FFhto01000h 010FFhto01000h 010FFhto01000h 010FFhto01000h RAM Size 128B 256B 256B 256B 0x027Fto0x0200 0x02FFto0x0200 0x02FFto0x0200 0x02FFto0x0200 Peripherals 16-bit 01FFhto0100h 01FFhto0100h 01FFhto0100h 01FFhto0100h 8-bit 0FFhto010h 0FFhto010h 0FFhto010h 0FFhto010h 8-bitSFR 0Fhto00h 0Fhto00h 0Fhto00h 0Fhto00h Flash Memory The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can performsingle-byteandsingle-wordwritestotheflashmemory.Featuresoftheflashmemoryinclude: • Flash memory has n segments of main memory and four segments of information memory (A to D) of 64byteseach.Eachsegmentinmainmemoryis512bytesinsize. • Segments0tonmaybeerasedinonestep,oreachsegmentmaybeindividuallyerased. • Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also calledinformationmemory. • Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is required. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions.Forcompletemoduledescriptions,seetheMSP430x2xxFamilyUser'sGuide(SLAU144). OscillatorandSystemClock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic clockmoduleprovidesthefollowingclocksignals: • Auxiliaryclock(ACLK),sourcedeitherfroma32768-HzwatchcrystalortheinternalLFoscillator. • Mainclock(MCLK),thesystemclockusedbytheCPU. • Sub-Mainclock(SMCLK),thesub-systemclockusedbytheperipheralmodules. TheDCOsettingstocalibratetheDCOoutputfrequencyarestoredintheinformationmemorysegmentA. CalibrationDataStoredinInformationMemorySegmentA CalibrationdataisstoredforboththeDCOandforADC10organizedinatag-length-valuestructure. Table9.TagsUsedbytheADCCalibrationTags NAME ADDRESS VALUE DESCRIPTION TAG_DCO_30 0x10F6 0x01 DCOfrequencycalibrationatV =3VandT =30°Catcalibration CC A TAG_ADC10_1 0x10DA 0x10 ADC10_1calibrationtag TAG_EMPTY - 0xFE Identifierforemptymemoryareas Table10.LabelsUsedbytheADCCalibrationTags ADDRESS LABEL CONDITIONATCALIBRATION/DESCRIPTION SIZE OFFSET CAL_ADC_25T85 INCHx=0x1010,REF2_5=1,T =85°C word 0x0010 A CAL_ADC_25T30 INCHx=0x1010,REF2_5=1,T =30°C word 0x000E A CAL_ADC_25VREF_FACTOR REF2_5=1,T =30°C,I =1mA word 0x000C A (VREF+) CAL_ADC_15T85 INCHx=0x1010,REF2_5=0,T =85°C word 0x000A A CAL_ADC_15T30 INCHx=0x1010,REF2_5=0,T =30°C word 0x0008 A CAL_ADC_15VREF_FACTOR REF2_5=0,T =30°C,I =0.5mA word 0x0006 A (VREF+) CAL_ADC_OFFSET ExternalVREF=1.5V,f =5MHz word 0x0004 (ADC10CLK) CAL_ADC_GAIN_FACTOR ExternalVREF=1.5V,f =5MHz word 0x0002 (ADC10CLK) CAL_BC1_1MHz - byte 0x0009 CAL_DCO_1MHz - byte 0x00008 CAL_BC1_8MHz - byte 0x0007 CAL_DCO_8MHz - byte 0x0006 CAL_BC1_12MHz - byte 0x0005 CAL_DCO_12MHz - byte 0x0004 CAL_BC1_16MHz - byte 0x0003 CAL_DCO_16MHz - byte 0x0002 12 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 MainDCOCharacteristics • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ..., RSELx = 14 overlapsRSELx=15. • DCOcontrolbitsDCOxhaveastepsizeasdefinedbyparameterS . DCO • Modulation control bits MODx select how often f is used within the period of 32 DCOCLK DCO(RSEL,DCO+1) cycles. The frequency f is used for the remaining cycles. The frequency is an average equal to: DCO(RSEL,DCO) 32×fDCO(RSEL,DCO) ×fDCO(RSEL,DCO+1) faverage = MOD×fDCO(RSEL,DCO) +(32–MOD)×fDCO(RSEL,DCO+1) Brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and poweroff. DigitalI/O Therearetwo8-bitI/Oportsimplemented: • AllindividualI/Obitsareindependentlyprogrammable. • Anycombinationofinput,output,andinterruptcondition(portP1andportP2only)ispossible. • Edge-selectableinterruptinputcapabilityforalltheeightbitsofportP1andportP2,ifavailable. • Read/writeaccesstoport-controlregistersissupportedbyallinstructions. • EachI/Ohasanindividuallyprogrammablepullup/pulldownresistor. • Each I/O has an individually programmable pin-oscillator enable bit to enable low-cost capacitive-touch detection. WDT+WatchdogTimer The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generateinterruptsatselectedtimeintervals. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Timer0_A3 Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table11.Timer0_A3SignalConnections(1) INPUTPINNUMBER DEVICE MODULE MODULE OUTPUTPINNUMBER MODULE INPUT INPUT OUTPUT N20,PW20 PW14 RSA16 SIGNAL NAME BLOCK SIGNAL N20,PW20 PW14 RSA16 P1.0-2 P1.0-2 P1.0-1 TACLK TACLK ACLK ACLK Timer NA SMCLK SMCLK PinOsc PinOsc PinOsc INCLK P1.1-3 P1.1-3 P1.1-2 TA0.0 CCI0A P1.1-3 P1.1-3 P1.1-2 ACLK CCI0B P1.5-7 P1.5-7 P1.5-6 CCR0 TA0 V GND SS V V CC CC P1.2-4 P1.2-4 P1.2-3 TA0.1 CCI1A P1.2-4 P1.2-4 P1.2-3 CAOUT CCI1B P1.6-14 P1.6-8 P1.6-7 CCR1 TA1 V GND P2.6-19 P2.6-12 P2.6-12 SS V V CC CC P1.4-6 P1.4-6 P1.4-5 TA0.2 CCI2A P1.4-6 P1.4-6 P1.4-5 PinOsc PinOsc PinOsc TA0.2 CCI2B CCR2 TA2 V GND SS V V CC CC (1) Onlyonepin-oscillatormustbeenabledatatime. USI The universal serial interface (USI) module is used for serial data communication and provides the basic hardwareforsynchronouscommunicationprotocolslikeSPIandI2C. Comparator_A+ The primary function of the Comparator_A+module is to support precision slope analog-to-digital conversions, battery-voltagesupervision,andmonitoringofexternalanalogsignals. ADC10(MSP430G2x52only) The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion resulthandling,allowingADCsamplestobeconvertedandstoredwithoutanyCPUintervention. 14 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 PeripheralFileMap Table12.PeripheralsWithWordAccess REGISTER MODULE REGISTERDESCRIPTION OFFSET NAME ADC10(MSP430G2x52devicesonly) ADCdatatransferstartaddress ADC10SA 01BCh ADCmemory ADC10MEM 01B4h ADCcontrolregister1 ADC10CTL1 01B2h ADCcontrolregister0 ADC10CTL0 01B0h Timer0_A3 Capture/compareregister TACCR2 0176h Capture/compareregister TACCR1 0174h Capture/compareregister TACCR0 0172h Timer_Aregister TAR 0170h Capture/comparecontrol TACCTL2 0166h Capture/comparecontrol TACCTL1 0164h Capture/comparecontrol TACCTL0 0162h Timer_Acontrol TACTL 0160h Timer_Ainterruptvector TAIV 012Eh FlashMemory Flashcontrol3 FCTL3 012Ch Flashcontrol2 FCTL2 012Ah Flashcontrol1 FCTL1 0128h WatchdogTimer+ Watchdog/timercontrol WDTCTL 0120h Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Table13.PeripheralsWithByteAccess REGISTER MODULE REGISTERDESCRIPTION OFFSET NAME ADC10(MSP430G2x52devicesonly) Analogenable1 ADC10AE1 04Bh Analogenable0 ADC10AE0 04Ah ADCdatatransfercontrolregister1 ADC10DTC1 049h ADCdatatransfercontrolregister0 ADC10DTC0 048h USI USIcontrol0 USICTL0 078h USIcontrol1 USICTL1 079h USIclockcontrol USICKCTL 07Ah USIbitcounter USICNT 07Bh USIshiftregister USISR 07Ch Comparator_A+ Comparator_A+portdisable CAPD 05Bh Comparator_A+control2 CACTL2 05Ah Comparator_A+control1 CACTL1 059h BasicClockSystem+ Basicclocksystemcontrol3 BCSCTL3 053h Basicclocksystemcontrol2 BCSCTL2 058h Basicclocksystemcontrol1 BCSCTL1 057h DCOclockfrequencycontrol DCOCTL 056h PortP2 PortP2selection2 P2SEL2 042h PortP2resistorenable P2REN 02Fh PortP2selection P2SEL 02Eh PortP2interruptenable P2IE 02Dh PortP2interruptedgeselect P2IES 02Ch PortP2interruptflag P2IFG 02Bh PortP2direction P2DIR 02Ah PortP2output P2OUT 029h PortP2input P2IN 028h PortP1 PortP1selection2 P1SEL2 041h PortP1resistorenable P1REN 027h PortP1selection P1SEL 026h PortP1interruptenable P1IE 025h PortP1interruptedgeselect P1IES 024h PortP1interruptflag P1IFG 023h PortP1direction P1DIR 022h PortP1output P1OUT 021h PortP1input P1IN 020h SpecialFunction SFRinterruptflag2 IFG2 003h SFRinterruptflag1 IFG1 002h SFRinterruptenable2 IE2 001h SFRinterruptenable1 IE1 000h 16 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 Absolute Maximum Ratings(1) VoltageappliedatV toV –0.3Vto4.1V CC SS Voltageappliedtoanypin(2) –0.3VtoV +0.3V CC Diodecurrentatanydevicepin ±2mA Unprogrammeddevice –55°Cto150°C Storagetemperaturerange,T (3) stg Programmeddevice –55°Cto150°C (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesreferencedtoV .TheJTAGfuse-blowvoltage,V ,isallowedtoexceedtheabsolutemaximumrating.Thevoltageis SS FB appliedtotheTESTpinwhenblowingtheJTAGfuse. (3) HighertemperaturemaybeappliedduringboardsolderingaccordingtothecurrentJEDECJ-STD-020specificationwithpeakreflow temperaturesnothigherthanclassifiedonthedevicelabelontheshippingboxesorreels. Recommended Operating Conditions TypicalvaluesarespecifiedatV =3.3VandT =25°C(unlessotherwisenoted) CC A MIN NOM MAX UNIT Duringprogramexecution 1.8 3.6 V Supplyvoltage V CC Duringflashprogramming/erase 2.2 3.6 V Supplyvoltage 0 V SS T Operatingfree-airtemperature -40 85 °C A V =1.8V, CC dc 6 Dutycycle=50%±10% Processorfrequency(maximumMCLKfrequency V =2.7V, fSYSTEM usingtheUSARTmodule)(1)(2) DCuCtycycle=50%±10% dc 12 MHz V =3.3V, CC dc 16 Dutycycle=50%±10% (1) TheMSP430CPUisclockeddirectlywithMCLK.BoththehighandlowphaseofMCLKmustnotexceedthepulsewidthofthe specifiedmaximumfrequency. (2) Modulesmighthaveadifferentmaximuminputclockspecification.Seethespecificationoftherespectivemoduleinthisdatasheet. Legend: 16 MHz Supply voltage range, Hz during flash memory M programming y - 12 MHz c n e u Supply voltage range, q e during program execution Fr m ste 6 MHz y S 1.8 V 2.2 V 2.7 V 3.3 V 3.6 V Supply Voltage - V Note: Minimumprocessorfrequencyisdefinedbysystemclock.FlashprogramoreraseoperationsrequireaminimumV CC of2.2V. Figure1. SafeOperatingArea Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Electrical Characteristics Active Mode Supply Current Into V Excluding External Current CC overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1)(2) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC f =f =f =1MHz, 2.2V 220 DCO MCLK SMCLK f =32768Hz, ACLK Programexecutesinflash, Activemode(AM) I BCSCTL1=CALBC1_1MHZ, µA AM,1MHz current(1MHz) DCOCTL=CALDCO_1MHZ, 3V 320 400 CPUOFF=0,SCG0=0,SCG1=0, OSCOFF=0 (1) Allinputsaretiedto0VortoV .Outputsdonotsourceorsinkanycurrent. CC (2) ThecurrentsarecharacterizedwithaMicroCrystalCC4V-T1ASMDcrystalwithaloadcapacitanceof9pF.Theinternalandexternal loadcapacitanceischosentocloselymatchtherequired9pF. Typical Characteristics – Active Mode Supply Current (Into V ) CC 5.0 4.0 4.0 fDCO= 16 MHz TA= 85°C A A 3.0 m m − − TA= 25°C Active Mode Current 23..00 fDCO= 8 MfHDzCO= 12 MHz Active Mode Current 12..00 VCC= 3 V TTAA== 8255°°CC 1.0 fDCO= 1 MHz VCC= 2.2 V 0.0 0.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 4.0 8.0 12.0 16.0 VCC−Supply Voltage−V fDCO−DCO Frequency−MHz Figure2.ActiveModeCurrentvsV ,T =25°C Figure3.ActiveModeCurrentvsDCOFrequency CC A 18 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 Low-Power Mode Supply Currents (Into V ) Excluding External Current CC overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) (2) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC f =0MHz, MCLK f =f =1MHz, SMCLK DCO f =32768Hz, Low-powermode0 ACLK ILPM0,1MHz (LPM0)current(3) BCSCTL1=CALBC1_1MHZ, 25°C 2.2V 55 µA DCOCTL=CALDCO_1MHZ, CPUOFF=1,SCG0=0,SCG1=0, OSCOFF=0 f =f =0MHz, MCLK SMCLK f =1MHz, DCO f =32768Hz, Low-powermode2 ACLK ILPM2 (LPM2)current(4) BCSCTL1=CALBC1_1MHZ, 25°C 2.2V 22 µA DCOCTL=CALDCO_1MHZ, CPUOFF=1,SCG0=0,SCG1=1, OSCOFF=0 f =f =f =0MHz, DCO MCLK SMCLK Low-powermode3 f =32768Hz, ILPM3,LFXT1 (LPM3)current(4) CAPCLUKOFF=1,SCG0=1,SCG1=1, 25°C 2.2V 0.7 1.0 µA OSCOFF=0 f =f =f =0MHz, DCO MCLK SMCLK Low-powermode3 f frominternalLFoscillator(VLO), ILPM3,VLO current,(LPM3)(4) CAPCLUKOFF=1,SCG0=1,SCG1=1, 25°C 2.2V 0.5 0.7 µA OSCOFF=0 f =f =f =0MHz, 25°C 0.1 0.5 DCO MCLK SMCLK Low-powermode4 f =0Hz, ILPM4 (LPM4)current(5) CAPCLUKOFF=1,SCG0=1,SCG1=1, 85°C 2.2V 0.8 1.5 µA OSCOFF=1 (1) Allinputsaretiedto0VortoV .Outputsdonotsourceorsinkanycurrent. CC (2) ThecurrentsarecharacterizedwithaMicroCrystalCC4V-T1ASMDcrystalwithaloadcapacitanceof9pF. (3) CurrentforbrownoutandWDTclockedbySMCLKincluded. (4) CurrentforbrownoutandWDTclockedbyACLKincluded. (5) Currentforbrownoutincluded. Typical Characteristics Low-Power Mode Supply Currents overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) 2.0 1.0 1.8 A 0.9 µ A − −µ 1.6 ent 0.8 urrent 1.4 e curr 0.7 e c 1.2 VCC= 3.6 V mod 0.6 d w−power mo 01..80 VCVCCC= =2 .32 VV Low−power 00..45 VVCCCC== 3 3.6 V V o 0.6 − 0.3 V = 2.2 V L 4 CC − M 3 0.4 LP 0.2 M I P L V = 1.8 V I 0.2 CC 0.1 V = 1.8 V 0.0 0.0 CC −40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 −40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 TA−Temperature−°C TTAA−−TTeemmppeerraattuurree−− CC Figure4.LPM3(VLO)CurrentvsTemperature Figure5.LPM4CurrentvsTemperature Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Schmitt-Trigger Inputs – Ports Px(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 0.45V 0.75V CC CC V Positive-goinginputthresholdvoltage V IT+ 3V 1.35 2.25 0.25V 0.55V CC CC V Negative-goinginputthresholdvoltage V IT– 3V 0.75 1.65 V Inputvoltagehysteresis(V –V ) 3V 0.3 1 V hys IT+ IT– Forpullup:V =V R Pullup/pulldownresistor IN SS 3V 20 35 50 kΩ Pull Forpulldown:V =V IN CC C Inputcapacitance V =V orV 5 pF I IN SS CC (1) Anexternalsignalsetstheinterruptflageverytimetheminimuminterruptpulsewidtht ismet.Itmaybesetevenwithtriggersignals (int) shorterthant . (int) Leakage Current – Ports Px overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC I High-impedanceleakagecurrent (1) (2) 3V ±50 nA lkg(Px.x) (1) TheleakagecurrentismeasuredwithV orV appliedtothecorrespondingpin(s),unlessotherwisenoted. SS CC (2) Theleakageofthedigitalportpinsismeasuredindividually.Theportpinisselectedforinput,andthepullup/pulldownresistoris disabled. Outputs – Ports Px overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC V High-leveloutputvoltage I =–6mA(1) 3V V –0.3 V OH (OHmax) CC V Low-leveloutputvoltage I =6mA(1) 3V V +0.3 V OL (OLmax) SS (1) Themaximumtotalcurrent,I andI ,foralloutputscombinedshouldnotexceed±48mAtoholdthemaximumvoltagedrop (OHmax) (OLmax) specified. Output Frequency – Ports Px overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC f Portoutputfrequency(withload) Px.y,C =20pF,R =1kΩ(1) (2) 3V 12 MHz Px.y L L f Clockoutputfrequency Px.y,C =20pF(2) 3V 16 MHz Port_CLK L (1) Aresistivedividerwithtwo0.5-kΩresistors betweenV andV isusedasload.Theoutputisconnectedtothecentertapofthe CC SS divider. (2) Theoutputvoltagereachesatleast10%and90%V atthespecifiedtogglefrequency. CC 20 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 Typical Characteristics – Outputs overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) TYPICALLOW-LEVELOUTPUTCURRENT TYPICALLOW-LEVELOUTPUTCURRENT vs vs LOW-LEVELOUTPUTVOLTAGE LOW-LEVELOUTPUTVOLTAGE 30.0 50.0 VCC= 2.2 V VCC= 3 V mA P1.7 TA= 25°C mA P1.7 TA= 25°C 25.0 − − 40.0 nt nt e e Curr 20.0 TA= 85°C Curr TA= 85°C put put 30.0 ut ut O O el 15.0 el v v e e w-L w-L 20.0 Lo 10.0 Lo al al c c Typi 5.0 Typi 10.0 − − L L O O I I 0.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOL−Low-Level Output Voltage−V VOL−Low-Level Output Voltage−V Figure6. Figure7. TYPICALHIGH-LEVELOUTPUTCURRENT TYPICALHIGH-LEVELOUTPUTCURRENT vs vs HIGH-LEVELOUTPUTVOLTAGE HIGH-LEVELOUTPUTVOLTAGE 0.0 0.0 VCC= 2.2 V VCC= 3 V A P1.7 A P1.7 m m − − nt −5.0 nt −10.0 e e urr urr C C ut ut p −10.0 p −20.0 ut ut O O el el v v e e h-L −15.0 h-L −30.0 g g cal Hi TA= 85°C cal Hi TA= 85°C ypi −20.0 ypi −40.0 T T − − H H O O TA= 25°C I TA= 25°C I −25.0 −50.0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH−High-Level Output Voltage−V VOH−High-Level Output Voltage−V Figure8. Figure9. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Pin-Oscillator Frequency – Ports Px overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC P1.y,C =10pF,R =100kΩ(1)(2) 1400 L L fo Portoutputoscillationfrequency 3V kHz P1.x P1.y,C =20pF,R =100kΩ(1)(2) 900 L L P2.0toP2.5,C =10pF,R =100kΩ(1)(2) 1800 L L fo Portoutputoscillationfrequency 3V kHz P2.x P2.0toP2.5,C =20pF,R =100kΩ(1)(2) 1000 L L P2.6andP2.7,C =20pF,R =100 foP2.6/7 Portoutputoscillationfrequency kΩ(1)(2) L L 3V 700 kHz (1) Aresistivedividerwithtwo50-kΩresistors betweenV andV isusedasload.Theoutputisconnectedtothecentertapofthe CC SS divider. (2) Theoutputvoltageoscillateswithatypicalamplitudeof700mVatthespecifiedtogglefrequency. Typical Characteristics – Pin-Oscillator Frequency TYPICALOSCILLATING FREQUENCY TYPICALOSCILLATING FREQUENCY vs vs LOAD CAPACITANCE LOAD CAPACITANCE 1.50 1.50 VCC= 2.2 V VCC= 3.0 V z 1.35 z 1.35 H H M M − 1.20 − 1.20 y y c c en 1.05 en 1.05 u u q P1.y q P1.y e e Fr 0.90 Fr 0.90 n P2.0 ... P2.5 n P2.0 ... P2.5 atio 0.75 atio 0.75 scill 0.60 P2.6, P2.7 scill 0.60 P2.6, P2.7 O O cal 0.45 cal 0.45 pi pi y y T 0.30 T 0.30 − − c c os 0.15 os 0.15 f f 0.00 0.00 10 50 100 10 50 100 CLOAD−External Capacitance−pF CLOAD−External Capacitance−pF Figure10. Figure11. 22 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 POR, BOR(1)(2) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC V SeeFigure12 dV /dt≤3V/s 0.7×V V CC(start) CC (B_IT–) V SeeFigure12throughFigure14 dV /dt≤3V/s 1.40 V (B_IT–) CC V SeeFigure12 dV /dt≤3V/s 140 mV hys(B_IT–) CC t SeeFigure12 2000 µs d(BOR) PulsedurationneededatRST/NMIpinto t 2.2V 2 µs (reset) acceptedresetinternally (1) ThecurrentconsumptionofthebrownoutmoduleisalreadyincludedintheI currentconsumptiondata.ThevoltagelevelV + CC (B_IT–) V is≤1.8V. hys(B_IT–) (2) Duringpowerup,theCPUbeginscodeexecutionfollowingaperiodoft afterV =V +V .ThedefaultDCOsettings d(BOR) CC (B_IT–) hys(B_IT–) mustnotbechangeduntilV ≥V ,whereV istheminimumsupplyvoltageforthedesiredoperatingfrequency. CC CC(min) CC(min) V CC V hys(B_IT−) V (B_IT−) VCC(start) 1 0 td(BOR) Figure12. PORandBORvsSupplyVoltage Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Typical Characteristics – POR and BOR 2 VCC tpw 3 V VCC= 3 V Typical Conditions V 1.5 − p) dro 1 C( C VCC(drop) V 0.5 0 0.001 1 1000 1 ns 1 ns tpw−Pulse Width− µs tpw−Pulse Width− µs Figure13.V LevelWithaSquareVoltageDroptoGenerateaPOR/BrownoutSignal CC(drop) VCC tpw 2 3 V VCC= 3 V V 1.5 Typical Conditions − p) o dr 1 C( C VCC(drop) V 0.5 tf= tr 0 0.001 1 1000 tf tr tpw−Pulse Width− µs tpw−Pulse Width− µs Figure14.V LevelWithaTriangleVoltageDroptoGenerateaPOR/BrownoutSignal CC(drop) 24 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 DCO Frequency overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC RSELx<14 1.8 3.6 V V Supplyvoltage RSELx=14 2.2 3.6 V CC RSELx=15 3 3.6 V f DCOfrequency(0,0) RSELx=0,DCOx=0,MODx=0 3V 0.06 0.14 MHz DCO(0,0) f DCOfrequency(0,3) RSELx=0,DCOx=3,MODx=0 3V 0.07 0.17 MHz DCO(0,3) f DCOfrequency(1,3) RSELx=1,DCOx=3,MODx=0 3V 0.15 MHz DCO(1,3) f DCOfrequency(2,3) RSELx=2,DCOx=3,MODx=0 3V 0.21 MHz DCO(2,3) f DCOfrequency(3,3) RSELx=3,DCOx=3,MODx=0 3V 0.30 MHz DCO(3,3) f DCOfrequency(4,3) RSELx=4,DCOx=3,MODx=0 3V 0.41 MHz DCO(4,3) f DCOfrequency(5,3) RSELx=5,DCOx=3,MODx=0 3V 0.58 MHz DCO(5,3) f DCOfrequency(6,3) RSELx=6,DCOx=3,MODx=0 3V 0.54 1.06 MHz DCO(6,3) f DCOfrequency(7,3) RSELx=7,DCOx=3,MODx=0 3V 0.80 1.50 MHz DCO(7,3) f DCOfrequency(8,3) RSELx=8,DCOx=3,MODx=0 3V 1.6 MHz DCO(8,3) f DCOfrequency(9,3) RSELx=9,DCOx=3,MODx=0 3V 2.3 MHz DCO(9,3) f DCOfrequency(10,3) RSELx=10,DCOx=3,MODx=0 3V 3.4 MHz DCO(10,3) f DCOfrequency(11,3) RSELx=11,DCOx=3,MODx=0 3V 4.25 MHz DCO(11,3) f DCOfrequency(12,3) RSELx=12,DCOx=3,MODx=0 3V 4.30 7.30 MHz DCO(12,3) f DCOfrequency(13,3) RSELx=13,DCOx=3,MODx=0 3V 6.00 9.60 MHz DCO(13,3) f DCOfrequency(14,3) RSELx=14,DCOx=3,MODx=0 3V 8.60 13.9 MHz DCO(14,3) f DCOfrequency(15,3) RSELx=15,DCOx=3,MODx=0 3V 12.0 18.5 MHz DCO(15,3) f DCOfrequency(15,7) RSELx=15,DCOx=7,MODx=0 3V 16.0 26.0 MHz DCO(15,7) Frequencystepbetween S S =f /f 3V 1.35 ratio RSEL rangeRSELandRSEL+1 RSEL DCO(RSEL+1,DCO) DCO(RSEL,DCO) Frequencystepbetween S S =f /f 3V 1.08 ratio DCO tapDCOandDCO+1 DCO DCO(RSEL,DCO+1) DCO(RSEL,DCO) Dutycycle MeasuredatSMCLKoutput 3V 50 % Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Calibrated DCO Frequencies – Tolerance overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC BCSCTL1=CALBC1_1MHZ, 1-MHztoleranceover temperature(1) DCOCTL=CALDCO_1MHZ, 0°Cto85°C 3V -3 ±0.5 +3 % calibratedat30°Cand3V BCSCTL1=CALBC1_1MHZ, 1-MHztoleranceoverV DCOCTL=CALDCO_1MHZ, 30°C 1.8Vto3.6V -3 ±2 +3 % CC calibratedat30°Cand3V BCSCTL1=CALBC1_1MHZ, 1-MHztoleranceoverall DCOCTL=CALDCO_1MHZ, -40°Cto85°C 1.8Vto3.6V -6 ±3 +6 % calibratedat30°Cand3V BCSCTL1=CALBC1_8MHZ, 8-MHztoleranceover temperature(1) DCOCTL=CALDCO_8MHZ, 0°Cto85°C 3V -3 ±0.5 +3 % calibratedat30°Cand3V BCSCTL1=CALBC1_8MHZ, 8-MHztoleranceoverV DCOCTL=CALDCO_8MHZ, 30°C 2.2Vto3.6V -3 ±2 +3 % CC calibratedat30°Cand3V BCSCTL1=CALBC1_8MHZ, 8-MHztoleranceoverall DCOCTL=CALDCO_8MHZ, -40°Cto85°C 2.2Vto3.6V -6 ±3 +6 % calibratedat30°Cand3V BCSCTL1=CALBC1_12MHZ, 12-MHztoleranceover temperature(1) DCOCTL=CALDCO_12MHZ, 0°Cto85°C 3V -3 ±0.5 +3 % calibratedat30°Cand3V BCSCTL1=CALBC1_12MHZ, 12-MHztoleranceoverV DCOCTL=CALDCO_12MHZ, 30°C 2.7Vto3.6V -3 ±2 +3 % CC calibratedat30°Cand3V BCSCTL1=CALBC1_12MHZ, 12-MHztoleranceoverall DCOCTL=CALDCO_12MHZ, -40°Cto85°C 2.7Vto3.6V -6 ±3 +6 % calibratedat30°Cand3V BCSCTL1=CALBC1_16MHZ, 16-MHztoleranceover temperature(1) DCOCTL=CALDCO_16MHZ, 0°Cto85°C 3V -3 ±0.5 +3 % calibratedat30°Cand3V BCSCTL1=CALBC1_16MHZ, 16-MHztoleranceoverV DCOCTL=CALDCO_16MHZ, 30°C 3.3Vto3.6V -3 ±2 +3 % CC calibratedat30°Cand3V BCSCTL1=CALBC1_16MHZ, 16-MHztoleranceoverall DCOCTL=CALDCO_16MHZ, -40°Cto85°C 3.3Vto3.6V -6 ±3 +6 % calibratedat30°Cand3V (1) Thisisthefrequencychangefromthemeasuredfrequencyat30°Covertemperature. 26 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 Wake-Up From Lower-Power Modes (LPM3 or LPM4) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC DCOclockwake-uptimefromLPM3 BCSCTL1=CALBC1_1MHZ, tDCO,LPM3/4 orLPM4(1) DCOCTL=CALDCO_1MHZ 3V 1.5 µs CPUwake-uptimefromLPM3or 1/f + tCPU,LPM3/4 LPM4(2) t MCLK Clock,LPM3/4 (1) TheDCOclockwake-uptimeismeasuredfromtheedgeofanexternalwake-upsignal(forexample,aportinterrupt)tothefirstclock edgeobservableexternallyonaclockpin(MCLKorSMCLK). (2) ParameterapplicableonlyifDCOCLKisusedforMCLK. Typical Characteristics – DCO Clock Wake-Up Time From LPM3 or LPM4 10.00 s u − e m Ti e k RSELx= 0...11 a W 1.00 RSELx = 12...15 O C D 0.10 0.10 1.00 10.00 DCO Frequency−MHz Figure15.DCOWake-UpTimeFromLPM3vsDCOFrequency Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Crystal Oscillator, XT1, Low-Frequency Mode(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC LFXT1oscillatorcrystal f XTS=0,LFXT1Sx=0or1 1.8Vto3.6V 32768 Hz LFXT1,LF frequency,LFmode0,1 LFXT1oscillatorlogiclevel f squarewaveinputfrequency, XTS=0,XCAPx=0,LFXT1Sx=3 1.8Vto3.6V 10000 32768 50000 Hz LFXT1,LF,logic LFmode XTS=0,LFXT1Sx=0, 500 Oscillationallowancefor fLFXT1,LF=32768Hz,CL,eff=6pF OA kΩ LF LFcrystals XTS=0,LFXT1Sx=0, 200 f =32768Hz,C =12pF LFXT1,LF L,eff XTS=0,XCAPx=0 1 Integratedeffectiveload XTS=0,XCAPx=1 5.5 CL,eff capacitance,LFmode(2) XTS=0,XCAPx=2 8.5 pF XTS=0,XCAPx=3 11 XTS=0,MeasuredatP2.0/ACLK, Dutycycle LFmode 2.2V 30 50 70 % f =32768Hz LFXT1,LF fFault,LF OLFscmilloadtoer(3f)aultfrequency, XTS=0,XCAPx=0,LFXT1Sx=3(4) 2.2V 10 10000 Hz (1) ToimproveEMIontheXT1oscillator,thefollowingguidelinesshouldbeobserved. (a)Keepthetracebetweenthedeviceandthecrystalasshortaspossible. (b)Designagoodgroundplanearoundtheoscillatorpins. (c)PreventcrosstalkfromotherclockordatalinesintooscillatorpinsXINandXOUT. (d)AvoidrunningPCBtracesunderneathoradjacenttotheXINandXOUTpins. (e)UseassemblymaterialsandpraxistoavoidanyparasiticloadontheoscillatorXINandXOUTpins. (f)Ifconformalcoatingisused,ensurethatitdoesnotinducecapacitiveorresistiveleakagebetweentheoscillatorpins. (g)DonotroutetheXOUTlinetotheJTAGheadertosupporttheserialprogrammingadapterasshowninotherdocumentation.This signalisnolongerrequiredfortheserialprogrammingadapter. (2) Includesparasiticbondandpackagecapacitance(approximately2pFperpin). BecausethePCBaddsadditionalcapacitance,itisrecommendedtoverifythecorrectloadbymeasuringtheACLKfrequency.Fora correctsetup,theeffectiveloadcapacitanceshouldalwaysmatchthespecificationoftheusedcrystal. (3) FrequenciesbelowtheMINspecificationsetthefaultflag.FrequenciesabovetheMAXspecificationdonotsetthefaultflag. Frequenciesinbetweenmightsettheflag. (4) Measuredwithlogic-levelinputfrequencybutalsoappliestooperationwithcrystals. Internal Very-Low-Power Low-Frequency Oscillator (VLO) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER T V MIN TYP MAX UNIT A CC f VLOfrequency -40°Cto85°C 3V 4 12 20 kHz VLO df /d VLOfrequencytemperaturedrift -40°Cto85°C 3V 0.5 %/°C VLO T df /dV VLOfrequencysupplyvoltagedrift 25°C 1.8Vto3.6V 4 %/V VLO CC Timer_A overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC SMCLK f Timer_Ainputclockfrequency f MHz TA Dutycycle=50%±10% SYSTEM t Timer_Acapturetiming TA0,TA1 3V 20 ns TA,cap 28 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 USI, Universal Serial Interface overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC External:SCLK, f USImoduleclockfrequency f MHz USI Dutycycle=50%±10% SYSTEM f Serialclockfrequency,slavemode SPIslavemode 3V 6 MHz (SCLK) Low-leveloutputvoltageonSDAand USImoduleinI2Cmode, V V 3V V SS V OL,I2C SCL I =1.5mA SS +0.4 (OLmax) Typical Characteristics -- USI Low-Level Output Voltage on SDA and SCL 5.0 5.0 VCC= 2.2 V VCC= 3 V A A TA= 25°C m 4.0 m 4.0 Current− 3.0 TA= 25°C Current− 3.0 TA= 85°C Output TA= 85°C Output w-Level 2.0 w-Level 2.0 Lo Lo − 1.0 − 1.0 OL OL I I 0.0 0.0 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0 VOL−Low-Level Output Voltage−V VOL−Low-Level Output Voltage−V Figure16.USILow-LevelOutputVoltagevsOutputCurrent Figure17.USILow-LevelOutputVoltagevsOutputCurrent Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Comparator_A+ overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC I CAON=1,CARSEL=0,CAREF=0 3V 45 µA (DD) CAON=1,CARSEL=0,CAREF=1/2/3, I 3V 45 µA (Refladder/RefDiode) NoloadatCA0andCA1 V V Common-modeinputvoltage CAON=1 3V 0 CC V (IC) –1 PCA0=1,CARSEL=1,CAREF=1, V (Voltageat0.25V node)÷V 3V 0.24 (Ref025) CC CC NoloadatCA0andCA1 PCA0=1,CARSEL=1,CAREF=2, V (Voltageat0.5V node)÷V 3V 0.48 (Ref050) CC CC NoloadatCA0andCA1 PCA0=1,CARSEL=1,CAREF=3, V SeeFigure18andFigure19 3V 490 mV (RefVT) NoloadatCA0andCA1,T =85°C A V Offsetvoltage(1) 3V ±10 mV (offset) V Inputhysteresis CAON=1 3V 0.7 mV hys T =25°C,Overdrive10mV, A 120 ns Responsetime Withoutfilter:CAF=0 t 3V (response) (low-highandhigh-low) T =25°C,Overdrive10mV, A 1.5 µs Withfilter:CAF=1 (1) TheinputoffsetvoltagecanbecancelledbyusingtheCAEXbittoinverttheComparator_A+inputsonsuccessivemeasurements.The twosuccessivemeasurementsarethensummedtogether. 30 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 Typical Characteristics – Comparator_A+ 650 650 VCC= 2.2 V VCC= 3 V V 600 V 600 m m − − Volts Typical Volts Typical Reference 550500 Reference 550500 − − T) T) V V F F E E V(R 450 V(R 450 400 400 −45 −25 −5 15 35 55 75 95 115 −45 −25 −5 15 35 55 75 95 115 TA−Free-AirTemperature− °C TA−Free-AirTemperature− °C Figure18.V vsTemperature,V =2.2V Figure19.V vsTemperature,V =3V (RefVT) CC (RefVT) CC 100.00 s m VCC= 1.8 V h kO VCC= 2.2 V − ce VCC= 3.0 V n 10.00 a st si e R ort h S VCC= 3.6 V 1.00 0.0 0.2 0.4 0.6 0.8 1.0 VIN/VCC−Normalized Input Voltage−V/V Figure20.ShortResistancevsV /V IN CC Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com 10-Bit ADC, Power Supply and Input Range Conditions (MSP430G2x52 Only) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC V Analogsupplyvoltage V =0V 2.2 3.6 V CC SS V Analoginputvoltage(2) AllAxterminals,Analoginputs 3V 0 V V Ax selectedinADC10AEregister CC f =5.0MHz, ADC10CLK I ADC10supplycurrent(3) ADC10ON=1,REFON=0, 25°C 3V 0.6 mA ADC10 ADC10SHT0=1,ADC10SHT1=0, ADC10DIV=0 f =5.0MHz, ADC10CLK ADC10ON=0,REF2_5V=0, 0.25 Referencesupplycurrent, REFON=1,REFOUT=0 IREF+ referencebufferdisabled(4) f =5.0MHz, 25°C 3V mA ADC10CLK ADC10ON=0,REF2_5V=1, 0.25 REFON=1,REFOUT=0 f =5.0MHz, ADC10CLK Referencebuffersupply ADC10ON=0,REFON=1, IREFB,0 currentwithADC10SR=0(4) REF2_5V=0,REFOUT=1, 25°C 3V 1.1 mA ADC10SR=0 f =5.0MHz, ADC10CLK Referencebuffersupply ADC10ON=0,REFON=1, IREFB,1 currentwithADC10SR=1(4) REF2_5V=0,REFOUT=1, 25°C 3V 0.5 mA ADC10SR=1 OnlyoneterminalAxcanbeselected C Inputcapacitance 25°C 3V 27 pF I atonetime R InputMUXONresistance 0V≤V ≤V 25°C 3V 1000 Ω I Ax CC (1) TheleakagecurrentisdefinedintheleakagecurrenttablewithPx.x/Axparameter. (2) TheanaloginputvoltagerangemustbewithintheselectedreferencevoltagerangeV toV forvalidconversionresults. R+ R– (3) TheinternalreferencesupplycurrentisnotincludedincurrentconsumptionparameterI . ADC10 (4) TheinternalreferencecurrentissuppliedviaterminalV .ConsumptionisindependentoftheADC10ONcontrolbit,unlessa CC conversionisactive.TheREFONbitenablesthebuilt-inreferencetosettlebeforestartinganA/Dconversion. 32 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 10-Bit ADC, Built-In Voltage Reference (MSP430G2x52 Only) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC Positivebuilt-inreference IVREF+≤1mA,REF2_5V=0 2.2 V V CC,REF+ analogsupplyvoltagerange I ≤1mA,REF2_5V=1 2.9 VREF+ Positivebuilt-inreference IVREF+≤IVREF+max,REF2_5V=0 1.41 1.5 1.59 V 3V V REF+ voltage I ≤I max,REF2_5V=1 2.35 2.5 2.65 VREF+ VREF+ MaximumVREF+load I 3V ±1 mA LD,VREF+ current I =500µA±100µA, VREF+ AnaloginputvoltageV ≉0.75V, ±2 Ax REF2_5V=0 VREF+loadregulation 3V LSB I =500µA±100µA, VREF+ AnaloginputvoltageV ≉1.25V, ±2 Ax REF2_5V=1 I =100µA→900µA, VREF+ V loadregulation V ≉0.5×VREF+, REF+ Ax 3V 400 ns responsetime Errorofconversionresult≤1LSB, ADC10SR=0 Maximumcapacitanceat C I ≤±1mA,REFON=1,REFOUT=1 3V 100 pF VREF+ pinVREF+ VREF+ ppm/ TC Temperaturecoefficient I =constwith0mA≤I ≤1mA 3V ±100 REF+ VREF+ VREF+ °C Settlingtimeofinternal I =0.5mA,REF2_5V=0, t referencevoltageto99.9% VREF+ 3.6V 30 µs REFON REFON=0→1 VREF I =0.5mA, Settlingtimeofreference VREF+ t REF2_5V=1,REFON=1, 3V 2 µs REFBURST bufferto99.9%VREF REFBURST=1,ADC10SR=0 Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com 10-Bit ADC, External Reference(1) (MSP430G2x52 Only) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC VEREF+>VEREF–, 1.4 V Positiveexternalreferenceinput SREF1=1,SREF0=0 CC VEREF+ voltagerange(2) VEREF–≤VEREF+≤V –0.15V, V SREF1=1,SREF0=1C(3C) 1.4 3 Negativeexternalreferenceinput VEREF– voltagerange(4) VEREF+>VEREF– 0 1.2 V Differentialexternalreference ΔVEREF inputvoltagerange, VEREF+>VEREF– (5) 1.4 V V CC ΔVEREF=VEREF+–VEREF– 0V≤VEREF+≤V , CC ±1 SREF1=1,SREF0=0 I StaticinputcurrentintoVEREF+ 3V µA VEREF+ 0V≤VEREF+≤V –0.15V≤3V, SREF1=1,SREF0CC=1(3) 0 I StaticinputcurrentintoVEREF– 0V≤VEREF–≤V 3V ±1 µA VEREF– CC (1) Theexternalreferenceisusedduringconversiontochargeanddischargethecapacitancearray.Theinputcapacitance,C,isalsothe I dynamicloadforanexternalreferenceduringconversion.Thedynamicimpedanceofthereferencesupplyshouldfollowthe recommendationsonanalog-sourceimpedancetoallowthechargetosettlefor10-bitaccuracy. (2) Theaccuracylimitstheminimumpositiveexternalreferencevoltage.Lowerreferencevoltagelevelsmaybeappliedwithreduced accuracyrequirements. (3) Underthisconditiontheexternalreferenceisinternallybuffered.Thereferencebufferisactiveandrequiresthereferencebuffersupply currentI .ThecurrentconsumptioncanbelimitedtothesampleandconversionperiodwithREBURST=1. REFB (4) Theaccuracylimitsthemaximumnegativeexternalreferencevoltage.Higherreferencevoltagelevelsmaybeappliedwithreduced accuracyrequirements. (5) Theaccuracylimitstheminimumexternaldifferentialreferencevoltage.Lowerdifferentialreferencevoltagelevelsmaybeappliedwith reducedaccuracyrequirements. 10-Bit ADC, Timing Parameters (MSP430G2x52 Only) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC ADC10inputclock Forspecifiedperformanceof ADC10SR=0 0.45 6.3 f 3V MHz ADC10CLK frequency ADC10linearityparameters ADC10SR=1 0.45 1.5 ADC10built-inoscillator ADC10DIVx=0,ADC10SSELx=0, f 3V 3.7 6.3 MHz ADC10OSC frequency f =f ADC10CLK ADC10OSC ADC10built-inoscillator,ADC10SSELx=0, 3V 2.06 3.51 f =f ADC10CLK ADC10OSC tCONVERT Conversiontime 13× µs f fromACLK,MCLK,orSMCLK: ADC10CLK ADC10DIV× ADC10SSELx≠0 1/f ADC10CLK t Turn-onsettlingtimeof (1) 100 ns ADC10ON theADC (1) Theconditionisthattheerrorinaconversionstartedaftert islessthan±0.5LSB.Thereferenceandinputsignalarealready ADC10ON settled. 10-Bit ADC, Linearity Parameters (MSP430G2x52 Only) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC E Integrallinearityerror 3V ±1 LSB I E Differentiallinearityerror 3V ±1 LSB D E Offseterror SourceimpedanceR <100Ω 3V ±1 LSB O S E Gainerror 3V ±1.1 ±2 LSB G E Totalunadjustederror 3V ±2 ±5 LSB T 34 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 10-Bit ADC, Temperature Sensor and Built-In V (MSP430G2x52 Only) MID overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC Temperaturesensorsupply REFON=0,INCHx=0Ah, ISENSOR current(1) T =25°C 3V 60 µA A TC ADC10ON=1,INCHx=0Ah (2) 3V 3.55 mV/°C SENSOR Sampletimerequiredifchannel ADC10ON=1,INCHx=0Ah, tSensor(sample) 10isselected (3) Errorofconversionresult≤1LSB 3V 30 µs I Currentintodivideratchannel11 ADC10ON=1,INCHx=0Bh 3V (4) µA VMID ADC10ON=1,INCHx=0Bh, V V divideratchannel11 3V 1.5 V MID CC V ≉0.5×V MID CC Sampletimerequiredifchannel ADC10ON=1,INCHx=0Bh, tVMID(sample) 11isselected (5) Errorofconversionresult≤1LSB 3V 1220 ns (1) ThesensorcurrentI isconsumedif(ADC10ON=1andREFON=1)or(ADC10ON=1andINCH=0Ahandsamplesignalis SENSOR high).WhenREFON=1,I isincludedinI .WhenREFON=0,I appliesduringconversionofthetemperaturesensor SENSOR REF+ SENSOR input(INCH=0Ah). (2) Thefollowingformulacanbeusedtocalculatethetemperaturesensoroutputvoltage: V =TC (273+T[°C])+V [mV]or Sensor,typ Sensor Offset,sensor V =TC T[°C]+V (T =0°C)[mV] Sensor,typ Sensor Sensor A (3) Thetypicalequivalentimpedanceofthesensoris51kΩ.Thesampletimerequiredincludesthesensor-ontimet . SENSOR(on) (4) Noadditionalcurrentisneeded.TheV isusedduringsampling. MID (5) Theon-timet isincludedinthesamplingtimet ;noadditionalontimeisneeded. VMID(on) VMID(sample) Flash Memory overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC V Programanderasesupplyvoltage 2.2 3.6 V CC(PGM/ERASE) f Flashtiminggeneratorfrequency 257 476 kHz FTG I SupplycurrentfromV duringprogram 2.2V/3.6V 1 5 mA PGM CC I SupplycurrentfromV duringerase 2.2V/3.6V 1 7 mA ERASE CC t Cumulativeprogramtime(1) 2.2V/3.6V 10 ms CPT t Cumulativemasserasetime 2.2V/3.6V 20 ms CMErase Program/eraseendurance 104 105 cycles t Dataretentionduration T =25°C 100 years Retention J t Wordorbyteprogramtime (2) 30 t Word FTG t Blockprogramtimeforfirstbyteorword (2) 25 t Block,0 FTG t Blockprogramtimeforeachadditional (2) 18 t Block,1-63 byteorword FTG t Blockprogramend-sequencewaittime (2) 6 t Block,End FTG t Masserasetime (2) 10593 t MassErase FTG t Segmenterasetime (2) 4819 t SegErase FTG (1) Thecumulativeprogramtimemustnotbeexceededwhenwritingtoa64-byteflashblock.Thisparameterappliestoallprogramming methods:individualword/bytewriteandblockwritemodes. (2) ThesevaluesarehardwiredintotheFlashController'sstatemachine(t =1/f ). FTG FTG Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com RAM overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT V RAMretentionsupplyvoltage (1) CPUhalted 1.6 V (RAMh) (1) ThisparameterdefinestheminimumsupplyvoltageV whenthedatainRAMremainsunchanged.Noprogramexecutionshould CC happenduringthissupplyvoltagecondition. JTAG and Spy-Bi-Wire Interface overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC f Spy-Bi-Wireinputfrequency 2.2V 0 20 MHz SBW t Spy-Bi-Wirelowclockpulselength 2.2V 0.025 15 µs SBW,Low Spy-Bi-Wireenabletime tSBW,En (TESThightoacceptanceoffirstclockedge(1)) 2.2V 1 µs t Spy-Bi-Wirereturntonormaloperationtime 2.2V 15 100 µs SBW,Ret f TCKinputfrequency(2) 2.2V 0 5 MHz TCK R InternalpulldownresistanceonTEST 2.2V 25 60 90 kΩ Internal (1) ToolsaccessingtheSpy-Bi-Wireinterfaceneedtowaitforthemaximumt timeafterpullingtheTEST/SBWCLKpinhighbefore SBW,En applyingthefirstSBWCLKclockedge. (2) f mayberestrictedtomeetthetimingrequirementsofthemoduleselected. TCK JTAG Fuse(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT V Supplyvoltageduringfuse-blowcondition T =25°C 2.5 V CC(FB) A V VoltagelevelonTESTforfuseblow 6 7 V FB I SupplycurrentintoTESTduringfuseblow 100 mA FB t Timetoblowfuse 1 ms FB (1) Oncethefuseisblown,nofurtheraccesstotheJTAG/Test,Spy-Bi-Wire,andemulationfeatureispossible,andJTAGisswitchedto bypassmode. 36 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 PIN SCHEMATICS Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger To Comparator from Comparator ToADC10* INCHx = y* CAPD.y orADC10AE0.y * PxSEL2.y PxSEL.y PxDIR.y 0 1 Direction 0 2 0: Input 1: Output 3 PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 PxSEL2.y PxSEL.y 1 DVSS 0 DV 1 1 CC PxOUT.y 0 From Module 1 2 0 3 KeBeupser P1.0/TA0CLK/ACLK/CA0/A0* EN P1.1/TA0.0/CA1/A1* P1.2/TA0.1/CA2/A2* TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y EN Q Set PxIFG.y PxSEL.y Interrupt Edge PxIES.y Select * Note: MSP430G2x32 devices only. MSP430G2x22 devices have noADC10. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Table14.PortP1(P1.0toP1.2)PinFunctions CONTROLBITS/SIGNALS(1) PINNAME (P1.x) x FUNCTION P1DIR.x P1SEL.x P1SEL2.x Comfrpoamrator (AINDCCH1.0yA=1E).(x2) P1.0/ P1.x(I/O) I:0;O:1 0 0 0 0 TA0CLK/ TA0.TACLK 0 1 0 0 0 ACLK/ ACLK 1 1 0 0 0 0 A0(2)/ A0 X X X 0 1(y=0) CA0/ CA0 X X X 1 0 PinOsc Capacitivesensing X 0 1 0 0 P1.1/ P1.x(I/O) I:0;O:1 0 0 0 0 TA0.0/ TA0.0 1 1 0 0 0 TA0.CCI0A 0 1 0 0 0 1 A1(2)/ A1 X X X 0 1(y=1) CA1/ CA1 X X X 1 0 PinOsc Capacitivesensing X 0 1 0 0 P1.2/ P1.x(I/O) I:0;O:1 0 0 0 0 TA0.1/ TA0.1 1 1 0 0 0 TA0.CCI1A 0 1 0 0 0 2 A2(2)/ A2 X X X 0 1(y=2) CA2/ CA2 X X X 1 0 PinOsc Capacitivesensing X 0 1 0 0 (1) X=don'tcare (2) MSP430G2x52devicesonly 38 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger SREF2 * 0 VSS ToADC10 VREF- * 1 To Comparator from Comparator ToADC10 * INCHx = y * CAPD.y orADC10AE0.y * PxSEL2.yPxSEL.y PxDIR.y 0,2,3 Direction 1 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 PxSEL2.y 1 PxSEL.y DVSS 0 DV 1 1 CC PxOUT.y 0 From ADC10 * 1 2 Bus 3 P1.3/ADC10CLK*/CAOUT/A3*/ From Comparator Keeper VREF-*/VEREF-*/CA3 EN TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y EN Q Set PxIFG.y PxSEL.y Interrupt Edge PxIES.y Select * Note: MSP430G2x52 devices only. MSP430G2x12 devices have noADC10. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Table15.PortP1(P1.3)PinFunctions CONTROLBITS/SIGNALS(1) PINNAME (P1.x) x FUNCTION P1DIR.x P1SEL.x P1SEL2.x Comfrpoamrator (AINDCCH1.0xA=1E).(x2) P1.3/ P1.x(I/O) I:0;O:1 0 0 0 0 ADC10CLK(2)/ ADC10CLK 1 1 0 0 0 CAOUT/ CAOUT 1 1 1 0 0 A3(2)/ A3 X X X 0 1(y=3) 3 VREF-(2)/ VREF- X X X 0 1 VEREF-(2)/ VEREF- X X X 0 1 CA3/ CA3 X X X 1 0 PinOsc Capacitivesensing X 0 1 0 0 (1) X=don'tcare (2) MSP430G2x52devicesonly 40 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 Port P1 Pin Schematic: P1.4, Input/Output With Schmitt Trigger From/ToADC10 Ref+ * To Comparator from Comparator ToADC10 * INCHx = y * CAPD.y orADC10AE0.y * PxSEL.y PxDIR.y 0 Direction 1 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 PxSEL2.y PxSEL.y 1 DVSS 0 DV 1 1 PxOUT.y CC 0 SMCLK 1 2 from Timer 3 KeBeupser P1.4/SMCLK/TA0.2/A4*/ EN VREF+*/VEREF+*/ CA4/TCK TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y EN Q Set PxIFG.y PxSEL.y Interrupt Edge PxIES.y Select From JTAG To JTAG * Note: MSP430G2x52 devices only. MSP430G2x12 devices have noADC10. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Table16.PortP1(P1.4)PinFunctions CONTROLBITS/SIGNALS(1) PINNAME (P1.x) x FUNCTION P1DIR.x P1SEL.x P1SEL2.x (AINDCCH1.0xA=1E).(x2) JTAGMode CAPD.y P1.4/ P1.x(I/O) I:0;O:1 0 0 0 0 0 SMCLK/ SMCLK 1 1 0 0 0 0 TA0.2/ TA0.2 1 1 1 0 0 0 TA0.CCI2A 0 1 1 0 0 0 VREF+(2)/ VREF+ X X X 1 0 0 4 VEREF+(2)/ VEREF+ X X X 1 0 0 A4(2)/ A4 X X X 1(y=4) 0 0 CA4/ CA4 X X X 0 0 1(y=4) TCK/ TCK X X X 0 1 0 PinOsc Capacitivesensing X 0 1 0 0 0 (1) X=don'tcare (2) MSP430G2x52devicesonly 42 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 Port P1 Pin Schematic: P1.5 to P1.7, Input/Output With Schmitt Trigger To Comparator from Comparator ToADC10 * INCHx = y * CAPD.y ADC10AE0.y * PxSEL2.y PxSEL.y PxDIR.y 0 From Module 1 Direction 2 0: Input 1: Output 3 PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 PxSEL2.y PxSEL.y 1 DVSS 0 DV 1 1 PxOUT.y 0 CC From Module 1 2 0 3 Bus P1.5/TA0.0/SCLK/A5*/CA5/TMS Keeper EN P1.6/TA0.1/SDO/SCL/A6*/CA6/TDI/TCLK P1.7/CAOUT/SDI/SDA/A7*/CA7/TDO/TDI TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y EN Q Set PxIFG.y PxSEL.y Interrupt Edge PxIES.y Select From JTAG To JTAG * Note: MSP430G2x52 devices only. MSP430G2x12 devices have noADC10. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 43

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Table17.PortP1(P1.5toP1.7)PinFunctions CONTROLBITS/SIGNALS(1) PINNAME (P1.x) x FUNCTION P1DIR.x P1SEL.x P1SEL2.x USIP.x JTAGMode CAPD.y (AINDCCH1.0xA=1E).(x2) P1.5/ P1.x(I/O) I:0;O:1 0 0 0 0 0 0 TA0.0/ TA0.0 1 1 0 0 0 0 0 SCLK/ SPImode fromUSI 1 0 1 0 0 0 A5(2)/ 5 A5 X X X X 0 0 1(y=5) CA5/ CA5 X X X X 0 1 0 TMS/ TMS X X X X 1 X X PinOsc Capacitivesensing X 0 1 X 0 0 0 P1.6/ P1.x(I/O) I:0;O:1 0 0 0 0 0 0 TA0.1/ TA0.1 1 1 0 0 0 0 0 SDO/ SPImode fromUSI 1 0 1 0 0 0 SCL/ I2Cmode fromUSI 1 0 1 0 0 0 6 A6(2)/ A6 X X X X 0 0 1(y=6) CA6/ CA6 X X X X 0 1 0 TDI/TCLK/ TDI/TCLK X X X X 1 X X PinOsc Capacitivesensing X 0 1 X 0 0 0 P1.7/ P1.x(I/O) I:0;O:1 0 0 0 0 0 0 CAOUT/ CAOUT 1 1 0 0 0 0 0 SDI/ SPImode fromUSI 1 0 1 0 0 0 SDA/ I2Cmode fromUSI 1 0 1 0 0 0 7 A7(2)/ A7 X X X X 0 0 1(y=7) CA7/ CA7 X X X X 0 1 0 TDO/TDI/ TDO/TDI X X X X 1 X X PinOsc Capacitivesensing X 0 1 X 0 0 0 (1) X=don'tcare (2) MSP430G2x52devicesonly 44 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger PxSEL.y PxDIR.y 0 Direction 1 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 PxSEL2.y 1 PxSEL.y DVSS 0 DV 1 1 CC PxOUT.y 0 0 1 2 0 3 P2.0 P2.1 P2.2 P2.3 TAx.y P2.4 TAxCLK P2.5 PxIN.y EN To Module D PxIE.y PxIRQ.y EN Q Set PxIFG.y PxSEL.y Interrupt Edge PxIES.y Select Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 45

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Table18.PortP2(P2.0toP2.5)PinFunctions PINNAME CONTROLBITS/SIGNALS(1) x FUNCTION (P2.x) P2DIR.x P2SEL.x P2SEL2.x P2.0/ P2.x(I/O) I:0;O:1 0 0 0 PinOsc Capacitivesensing X 0 1 P2.1/ P2.x(I/O) I:0;O:1 0 0 1 PinOsc Capacitivesensing X 0 1 P2.2/ P2.x(I/O) I:0;O:1 0 0 2 PinOsc Capacitivesensing X 0 1 P2.3/ P2.x(I/O) I:0;O:1 0 0 3 PinOsc Capacitivesensing X 0 1 P2.4/ P2.x(I/O) I:0;O:1 0 0 4 PinOsc Capacitivesensing X 0 1 P2.5/ P2.x(I/O) I:0;O:1 0 0 5 PinOsc Capacitivesensing X 0 1 (1) X=don'tcare 46 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger XOUT/P2.7 LF off PxSEL.6 & PxSEL.7 PxSEL2.6 | PxSEL.7 BCSCTL3.LFXT1Sx = 11 0 LFXT1CLK 1 PxSEL.y PxDIR.y 0 Direction 1 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 PxSEL2.y PxSEL.y 1 DVSS 0 DV 1 1 PxOUT.y CC 0 From Module 1 2 3 XIN/P2.6/TA0.1 TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y EN Q Set PxIFG.y PxSEL.y Interrupt Edge PxIES.y Select Table19.PortP2(P2.6)PinFunctions CONTROLBITS/SIGNALS(1) PINNAME (P2.x) x FUNCTION P2DIR.x P2SEL.6 P2SEL2.6 P2SEL.7 P2SEL2.7 1 0 XIN/ XIN X 1 0 0 0 P2.6/ P2.x(I/O) I:0;O:1 X 0 6 1 0 TA0.1/ Timer0_A3.TA1 1 0 0 0 1 PinOsc Capacitivesensing X X X (1) X=don'tcare Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 47

MSP430G2x52 MSP430G2x12 SLAS722G–DECEMBER2010–REVISEDMAY2013 www.ti.com Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger XIN LF off PxSEL.6 & PxSEL.7 PxSEL2.6 | PxSEL.7 BCSCTL3.LFXT1Sx = 11 0 LFXT1CLK 1 from P2.6 PxSEL.y PxDIR.y 0 Direction 1 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 PxSEL2.y 1 PxSEL.y DVSS 0 DV 1 1 PxOUT.y 0 CC From Module 1 2 3 XOUT/P2.7 TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y EN Q Set PxIFG.y PxSEL.y Interrupt Edge PxIES.y Select Table20.PortP2(P2.7)PinFunctions CONTROLBITS/SIGNALS(1) PINNAME (P2.x) x FUNCTION P2DIR.x P2SEL.6 P2SEL2.6 P2SEL.7 P2SEL2.7 1 0 XOUT/ XOUT X 1 0 0 0 P2.7/ 7 P2.x(I/O) I:0;O:1 X 0 0 1 PinOsc Capacitivesensing X X X (1) X=don'tcare 48 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated

MSP430G2x52 MSP430G2x12 www.ti.com SLAS722G–DECEMBER2010–REVISEDMAY2013 REVISION HISTORY REVISION DESCRIPTION SLAS722 Initialrelease Page1,Changed"InternalFrequenciesupto16MHzWithOneCalibratedFrequency"to"InternalFrequenciesupto16 SLAS722A MHzWithFourCalibratedFrequencies" AddednoteconcerningpulldownresistortoPW14andRSA16pinoutdrawings. Added"N20,PW20"toInputPinNumberandOutputPinNumbercolumnsinTable11. SLAS722B CorrectedpinnumbersforP1.0toP1.3forPW14packageinTable2. CorrectedN20,PW20OutputPinNumberforTA0.0inTable11.(June2011) ChangedStoragetemperaturerangelimitinAbsoluteMaximumRatings. SLAS722C CorrectedSDApinnameinTable17. ChangedTAG_ADC10_1valueto0x10inTable9. SLAS722D ChangedT ,Programmeddevice,to-55°Cto150°CinAbsoluteMaximumRatings. stg SLAS722E Changedallportschematics(addedbufferafterPxOUT.ymux)inPinSchematics Table2,CorrectedtypoonVEREF-(P1.3)signalname. RecommendedOperatingConditions,Addedtestconditionsfortypicalvalues. SLAS722F Pin-OscillatorFrequency–PortsPx,Correctedresistorvalueinnote(1). POR,BOR,Addednote(2). SLAS722G Throughout,Changedallvariationsoftouchsense(1)tocapacitivetouch. (1) TouchSenseisatrademarkofImmersionCorporation. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 49

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MSP430G2112IN20 ACTIVE PDIP N 20 20 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 85 M430G2112 (RoHS) MSP430G2112IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 G2112 & no Sb/Br) MSP430G2112IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 G2112 & no Sb/Br) MSP430G2112IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 430G2112 & no Sb/Br) MSP430G2112IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430 & no Sb/Br) G2112 MSP430G2152IN20 ACTIVE PDIP N 20 20 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 85 M430G2152 (RoHS) MSP430G2152IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 G2152 & no Sb/Br) MSP430G2152IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 G2152 & no Sb/Br) MSP430G2152IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 430G2152 & no Sb/Br) MSP430G2152IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 430G2152 & no Sb/Br) MSP430G2152IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430 & no Sb/Br) G2152 MSP430G2152IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430 & no Sb/Br) G2152 MSP430G2212IN20 ACTIVE PDIP N 20 20 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 85 M430G2212 (RoHS) MSP430G2212IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 G2212 & no Sb/Br) MSP430G2212IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 G2212 & no Sb/Br) MSP430G2212IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 430G2212 & no Sb/Br) MSP430G2212IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 430G2212 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MSP430G2212IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430 & no Sb/Br) G2212 MSP430G2212IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430 & no Sb/Br) G2212 MSP430G2252IN20 ACTIVE PDIP N 20 20 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 85 M430G2252 (RoHS) MSP430G2252IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 G2252 & no Sb/Br) MSP430G2252IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 G2252 & no Sb/Br) MSP430G2252IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 430G2252 & no Sb/Br) MSP430G2252IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 430G2252 & no Sb/Br) MSP430G2252IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430 & no Sb/Br) G2252 MSP430G2252IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430 & no Sb/Br) G2252 MSP430G2312IN20 ACTIVE PDIP N 20 20 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 85 M430G2312 (RoHS) MSP430G2312IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 G2312 & no Sb/Br) MSP430G2312IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 G2312 & no Sb/Br) MSP430G2312IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 430G2312 & no Sb/Br) MSP430G2312IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 430G2312 & no Sb/Br) MSP430G2312IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430 & no Sb/Br) G2312 MSP430G2312IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430 & no Sb/Br) G2312 MSP430G2352IN20 ACTIVE PDIP N 20 20 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 85 M430G2352 (RoHS) MSP430G2352IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 G2352 & no Sb/Br) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MSP430G2352IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 G2352 & no Sb/Br) MSP430G2352IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 430G2352 & no Sb/Br) MSP430G2352IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 430G2352 & no Sb/Br) MSP430G2352IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430 & no Sb/Br) G2352 MSP430G2352IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430 & no Sb/Br) G2352 MSP430G2412IN20 ACTIVE PDIP N 20 20 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 85 M430G2412 (RoHS) MSP430G2412IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 G2412 & no Sb/Br) MSP430G2412IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 G2412 & no Sb/Br) MSP430G2412IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 430G2412 & no Sb/Br) MSP430G2412IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 430G2412 & no Sb/Br) MSP430G2412IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430 & no Sb/Br) G2412 MSP430G2452IN20 ACTIVE PDIP N 20 20 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 85 M430G2452 (RoHS) MSP430G2452IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 G2452 & no Sb/Br) MSP430G2452IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 G2452 & no Sb/Br) MSP430G2452IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 430G2452 & no Sb/Br) MSP430G2452IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 430G2452 & no Sb/Br) MSP430G2452IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430 & no Sb/Br) G2452 MSP430G2452IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430 & no Sb/Br) G2452 Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 11-Jun-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) MSP430G2112IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430G2112IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2152IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430G2152IPW20R TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 MSP430G2152IRSA16R QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2152IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2212IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430G2212IPW20R TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 MSP430G2212IRSA16R QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2212IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2252IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430G2252IPW20R TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 MSP430G2252IRSA16R QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2252IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2312IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430G2312IPW20R TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 MSP430G2312IRSA16R QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2312IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Jun-2020 Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) MSP430G2352IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430G2352IPW20R TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 MSP430G2352IRSA16R QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2352IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2412IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430G2412IPW20R TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 MSP430G2412IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2452IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430G2452IPW20R TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 MSP430G2452IRSA16R QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2452IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) MSP430G2112IPW14R TSSOP PW 14 2000 367.0 367.0 35.0 MSP430G2112IRSA16T QFN RSA 16 250 210.0 185.0 35.0 MSP430G2152IPW14R TSSOP PW 14 2000 367.0 367.0 35.0 MSP430G2152IPW20R TSSOP PW 20 2000 350.0 350.0 43.0 MSP430G2152IRSA16R QFN RSA 16 3000 367.0 367.0 35.0 MSP430G2152IRSA16T QFN RSA 16 250 210.0 185.0 35.0 PackMaterials-Page2

PACKAGE MATERIALS INFORMATION www.ti.com 11-Jun-2020 Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) MSP430G2212IPW14R TSSOP PW 14 2000 367.0 367.0 35.0 MSP430G2212IPW20R TSSOP PW 20 2000 350.0 350.0 43.0 MSP430G2212IRSA16R QFN RSA 16 3000 367.0 367.0 35.0 MSP430G2212IRSA16T QFN RSA 16 250 210.0 185.0 35.0 MSP430G2252IPW14R TSSOP PW 14 2000 367.0 367.0 35.0 MSP430G2252IPW20R TSSOP PW 20 2000 350.0 350.0 43.0 MSP430G2252IRSA16R QFN RSA 16 3000 367.0 367.0 35.0 MSP430G2252IRSA16T QFN RSA 16 250 210.0 185.0 35.0 MSP430G2312IPW14R TSSOP PW 14 2000 367.0 367.0 35.0 MSP430G2312IPW20R TSSOP PW 20 2000 350.0 350.0 43.0 MSP430G2312IRSA16R QFN RSA 16 3000 367.0 367.0 35.0 MSP430G2312IRSA16T QFN RSA 16 250 210.0 185.0 35.0 MSP430G2352IPW14R TSSOP PW 14 2000 367.0 367.0 35.0 MSP430G2352IPW20R TSSOP PW 20 2000 350.0 350.0 43.0 MSP430G2352IRSA16R QFN RSA 16 3000 367.0 367.0 35.0 MSP430G2352IRSA16T QFN RSA 16 250 210.0 185.0 35.0 MSP430G2412IPW14R TSSOP PW 14 2000 367.0 367.0 35.0 MSP430G2412IPW20R TSSOP PW 20 2000 350.0 350.0 43.0 MSP430G2412IRSA16T QFN RSA 16 250 210.0 185.0 35.0 MSP430G2452IPW14R TSSOP PW 14 2000 350.0 350.0 43.0 MSP430G2452IPW20R TSSOP PW 20 2000 350.0 350.0 43.0 MSP430G2452IRSA16R QFN RSA 16 3000 367.0 367.0 35.0 MSP430G2452IRSA16T QFN RSA 16 250 210.0 185.0 35.0 PackMaterials-Page3

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