Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 MSP430FG461x, MSP430CG461x Mixed-Signal Microcontrollers 1 Device Overview 1.1 Features 1 • Lowsupply-voltagerange:1.8Vto3.6V • Universalserialcommunicationinterface • Ultra-lowpowerconsumption – EnhancedUARTsupportsautomaticbaud-rate – Activemode:400 µAat1MHz,2.2V detection – Standbymode:1.3 µA – IrDAencoderanddecoder – Offmode(RAMretention):0.22 µA – SynchronousSPI • Fivepower-savingmodes – I2C • Wakeupfromstandbymodeinlessthan6µs • Serialonboardprogramming,programmablecode protectionbysecurityfuse • 16-bitRISCarchitecture,extendedmemory, 125‑nsinstructioncycletime • Brownoutdetector • Three-channelinternalDMA • Basictimerwithreal-timeclock(RTC)feature • 12-bitanalog-to-digitalconverter(ADC)with • IntegratedLCDdriverupto160segmentswith internalreference,sample-and-holdandautoscan regulatedchargepump feature • DeviceComparisonsummarizestheavailable • Threeconfigurableoperationalamplifiers familymembers • Dual12-bitdigital-to-analogconverters(DACs) – MSP430FG4616,MSP430FG4616, withsynchronization 92KB+256BofflashorROM, 4KBofRAM • 16-bitTimer_Awiththreecapture/compare registers – MSP430FG4617,MSP430CG4617, 92KB+256BofflashorROM, • 16-bitTimer_Bwithsevencapture/compare-with- 8KBofRAM shadowregisters – MSP430FG4618,MSP430CG4618, • On-chipcomparator 116KB+256BofflashorROM, • Supplyvoltagesupervisorandmonitorwith 8KBofRAM programmableleveldetection – MSP430FG4619,MSP430CG4619, • Serialcommunicationinterface(USART1),select 120KB+256BofflashorROM, asynchronousUARTorsynchronousSPIby 4KBofRAM software 1.2 Applications • Portablemedicalapplications • E-meterapplications 1.3 Description The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low- powermodestoactivemodeinlessthan6µs. The MSP430xG461x series are microcontroller configurations with two 16-bit timers, a high-performance 12-bit ADC, dual 12-bit DACs, three configurable operational amplifiers, one universal serial communication interface (USCI), one universal synchronous/asynchronous communication interface (USART), DMA, 80 I/O pins, and a segment liquid crystal display (LCD) driver with regulated charge pump. Forcompletemoduledescriptions,seethe MSP430x4xxFamilyUser’sGuide. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(2) MSP430FG4619IPZ LQFP(100) 14mm×14mm MSP430FG4619IZCA nFBGA(113) 7mm×7mm MSP430FG4619IZQW(3) MicroStarJunior™BGA(113) 7mm×7mm (1) Forthemostcurrentpart,package,andorderinginformationforallavailabledevices,seethePackage OptionAddenduminSection8,orseetheTIwebsiteatwww.ti.com. (2) Thesizesshownhereareapproximations.Forthepackagedimensionswithtolerances,seethe MechanicalDatainSection8. (3) AllorderablepartnumbersintheZQW(MicroStarJuniorBGA)packagehavebeenchangedtoa statusofLastTimeBuy.VisittheProductlifecyclepagefordetailsonthisstatus. 1.4 Functional Block Diagram Figure1-1showsthefunctionalblockdiagram. XIN/ XOUT/ P3.x/P4.x P7.x/P8.x DVCC1/2 DVSS1/2 AVCC AVSS P1.x/P2.x XT2IN XT2OUT P5.x/P6.x P9.x/P10.x 2 2 2x8 4x8 4x8/2x16 Oscillators ACLK FRlOasMh ((CFGG)) RAM ADC12 DAC12 OA0,OA1, PP1o/rPts2 PP3o/rPts4 PP7o/rPts8 12-Bit 12-Bit P5/P6 P9/P10 FLL+ SMCLK 11912260KKKBBB 488KKKBBB 12 2Channels 3OOpAA2mps Com_pAarator I2nxte8r rIu/Opt 4x8 I/O 4x8, 2x16 I/O MCLK 92KB 4KB Channels Voltage out capability MAB 8MHz DMA CPUX Controller incl.16 Registers MDB 3Channels Enhanced Emulation Hardware Timer_B7 (FG only) Brownout Multiplier Watchdog Timer_A3 BasicTimer LCD_A USUCAIR_TA,0: USART1 JTAG Protection MPY, WDT+ 3CC Re7gisCtCers, Reaaln-Tdime 160 IrDA,SPI UART,SPI Interface SVS/SVM MPYS, 15/16-Bit Registers Shadow Clock Segments USCI_B0: MAC, Reg 1,2,3,4Mux SPI,I2C MACS RST/NMI Figure1-1.FunctionalBlockDiagram 2 DeviceOverview Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 Table of Contents 1 DeviceOverview......................................... 1 5.30 12-BitADC,TimingParameters .................... 37 .............................................. ................... 1.1 Features 1 5.31 12-BitADC,LinearityParameters 37 1.2 Applications........................................... 1 5.32 12-BitADC,TemperatureSensorandBuilt-InVMID ...................................................... ............................................ 38 1.3 Description 1 .................. ............................ 5.33 12-BitDAC,SupplySpecifications 38 1.4 FunctionalBlockDiagram 2 ................ 2 Revision History......................................... 4 5.34 12-BitDAC,LinearitySpecifications 39 .................. 3 Device Comparison..................................... 5 5.35 12-BitDAC,OutputSpecifications 41 ........ 4 TerminalConfigurationandFunctions.............. 6 5.36 12-BitDAC,ReferenceInputSpecifications 41 ................ ......................................... 5.37 12-BitDAC,DynamicSpecifications 42 4.1 PinDiagrams 6 .... ................................... 5.38 12-BitDAC,DynamicSpecificationsContinued 43 4.2 SignalDescriptions 8 ... 5 Specifications........................................... 14 5.39 OperationalAmplifierOA,SupplySpecifications 44 ........................ 5.40 OperationalAmplifierOA,Input/Output 5.1 AbsoluteMaximumRatings 14 ........................................ Specifications 44 ........................................ 5.2 ESDRatings 14 . 5.41 OperationalAmplifierOA,DynamicSpecifications 45 ............... 5.3 RecommendedOperatingConditions 14 .. 5.42 OperationalAmplifierOA,TypicalCharacteristics 45 5.4 SupplyCurrentIntoAV +DV Excluding ......C..C.......C.C.................... 5.43 OperationalAmplifierOAFeedbackNetwork, ExternalCurrent 16 .......... NoninvertingAmplifierMode(OAFCx=4) 46 ............................. 5.5 Thermal Characteristics 17 5.44 OperationalAmplifierOAFeedbackNetwork, 5.6 Schmitt-TriggerInputs–PortsP1toP10,RST/NMI, .............. InvertingAmplifierMode(OAFCx=6) 46 ............ JTAG(TCK,TMS,TDI/TCLK,TDO/TDI) 18 ............. 5.45 FlashMemory(FG461xDevicesOnly) 47 ............................... 5.7 InputsPx.x,TAx,TBX 18 ...................................... 5.46 JTAGInterface 47 ................ 5.8 LeakageCurrent–PortsP1toP10 18 ......................................... 5.47 JTAGFuse 47 .......................... 5.9 Outputs–PortsP1toP10 18 6 DetailedDescription................................... 48 ................................... 5.10 OutputFrequency 19 ................................................. 6.1 CPU 48 ................... 5.11 TypicalCharacteristics–Outputs 20 ....................................... 6.2 InstructionSet 49 ....................... 5.12 Wake-upTimingFromLPM3 21 .................................... 6.3 OperatingModes 50 ................................................. 5.13 RAM 21 .......................... 6.4 InterruptVectorAddresses 51 ............................................... 5.14 LCD_A 21 ................. 6.5 SpecialFunctionRegisters(SFRs) 52 ...................................... 5.15 Comparator_A 22 ............................... 6.6 Memory Organization 54 ............ 5.16 TypicalCharacteristics–Comparator_A 23 ............................. 6.7 BootstrapLoader(BSL) 55 .......................................... 5.17 POR,BOR 24 ....................................... 6.8 FlashMemory 55 ..... 5.18 SVS(SupplyVoltageSupervisorandMonitor) 25 .......................................... 6.9 Peripherals 55 ................................................. 5.19 DCO 27 ............................ 6.10 Input/OutputSchematics 65 ................ 5.20 CrystalOscillator,LFXT1Oscillator 29 7 DeviceandDocumentationSupport.............. 100 ................... 5.21 CrystalOscillator,XT2Oscillator 29 ..................................... 7.1 DeviceSupport 100 ................................. 5.22 USCI(UARTMode) 29 ............................ 7.2 DocumentationSupport 103 ............................ 5.23 USCI(SPIMasterMode) 30 ...................................... 7.3 RelatedLinks 103 ............................. 5.24 USCI(SPISlaveMode) 30 ............................. 7.4 CommunityResources 104 5.25 USCI(I2CMode).................................... 33 ........................................ 7.5 Trademarks 104 ............................................. 5.26 USART1 33 ................... 7.6 ElectrostaticDischargeCaution 104 5.27 12-BitADC,PowerSupplyandInputRange .............................. .......................................... 7.7 ExportControlNotice 104 Conditions 34 ............................................ ................... 7.8 Glossary 104 5.28 12-BitADC,ExternalReference 34 ...................... 8 Mechanical,Packaging,andOrderable 5.29 12-BitADC,Built-InReference 35 Information............................................. 105 Copyright©2006–2020,TexasInstrumentsIncorporated TableofContents 3 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 2 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromJune20,2015toMay4,2020 Page • Throughoutthedocument,addedtheZCApackage............................................................................ 1 • ChangedthestatusofallorderablepartnumbersintheZQWpackage ..................................................... 2 4 RevisionHistory Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 3 Device Comparison Table3-1summarizestheavailablefamilymembers. Table3-1.DeviceComparison(1)(2) FLASH ROM RAM ADC12 DAC12 COMP_A DEVICE EEM Timer_A Timer_B OPAMP USART USCI I/O PACKAGE (KB) (KB) (KB) (Channels) (Channels) (Channels) PZ100 MSP430FG4619 120 – 4 1 TA3 TB7 12 3 2 2 1 A0,B0 80 ZCA113 ZQW113 PZ100 MSP430FG4618 116 – 8 1 TA3 TB7 12 3 2 2 1 A0,B0 80 ZCA113 ZQW113 PZ100 MSP430FG4617 92 – 8 1 TA3 TB7 12 3 2 2 1 A0,B0 80 ZCA113 ZQW113 PZ100 MSP430FG4616 92 – 4 1 TA3 TB7 12 3 2 2 1 A0,B0 80 ZCA113 ZQW113 PZ100 MSP430CG4619 – 120 4 – TA3 TB7 12 3 2 2 1 A0,B0 80 ZQW113(3) PZ100 MSP430CG4618 – 116 8 – TA3 TB7 12 3 2 2 1 A0,B0 80 ZQW113(3) PZ100 MSP430CG4617 – 92 8 – TA3 TB7 12 3 2 2 1 A0,B0 80 ZQW113(3) PZ100 MSP430CG4616 – 92 4 – TA3 TB7 12 3 2 2 1 A0,B0 80 ZQW113(3) (1) Forthemostcurrentdevice,package,andorderinginformationforallavailabledevices,seethePackageOptionAddenduminSection8,orseetheTIwebsiteatwww.ti.com. (2) Packagedrawings,thermaldata,andsymbolizationareavailableatwww.ti.com/packaging. (3) AllorderablepartnumbersintheZQW(MicroStarJuniorBGA)packagehavebeenchangedtoastatusofLastTimeBuy.VisittheProductlifecyclepagefordetailsonthisstatus. Copyright©2006–2020,TexasInstrumentsIncorporated DeviceComparison 5 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 4 Terminal Configuration and Functions 4.1 Pin Diagrams Figure4-1showsthepinoutforthe100-pinPZpackage. T U O K VCCVSS1VSS6.2/A2/OA0I1 6.1/A1/OA0O 6.0/A0/OA0I0 ST/NMI CK MS DI/TCLK DO/TDI T2IN T2OUT 1.0/TA0 1.1/TA0/MCLK 1.2/TA1 1.3/TBOUTH/SVS 1.4/TBCLK/SMCL 1.5/TACLK/ACLK 1.6/CA0 1.7/CA1 2.0/TA2 2.1/TB0 2.2/TB1 2.3/TB2 A D A P P P R T T T T X X P P P P P P P P P P P P 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 0 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 8 7 7 7 7 1 DVCC1 1 75 P2.4/UCA0TXD P6.3/A3/OA1O 2 74 P2.5/UCA0RXD P6.4/A4/OA1I0 3 73 P2.6/CAOUT P6.5/A5/OA2O 4 72 P2.7/ADC12CLK/DMAE0 P6.6/A6/DAC0/OA2I0 5 71 P3.0/UCB0STE P6.7/A7/DAC1/SVSIN 6 70 P3.1/UCB0SIMO/UCB0SDA VREF+ 7 69 P3.2/UCB0SOMI/UCB0SCL XIN 8 68 P3.3/UCB0CLK XOUT 9 67 P3.4/TB3 VeREF+/DAC0 10 66 P3.5/TB4 VREF-/VeREF- 11 65 P3.6/TB5 P5.1/S0/A12/DAC1 12 64 P3.7/TB6 P5.0/S1/A13/OA1I1 13 63 P4.0/UTXD1 P10.7/S2/A14/OA2I1 14 62 P4.1/URXD1 P10.6/S3/A15 15 61 DVSS2 P10.5/S4 16 60 DVCC2 P10.4/S5 17 59 LCDCAP/R33 P10.3/S6 18 58 P5.7/R23 P10.2/S7 19 57 P5.6/LCDREF/R13 P10.1/S8 20 56 P5.5/R03 P10.0/S9 21 55 P5.4/COM3 P9.7/S10 22 54 P5.3/COM2 P9.6/S11 23 53 P5.2/COM1 P9.5/S12 24 52 COM0 P9.4/S13 25 51 P4.2/STE1/S39 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 S S S S S S S S S S S S S S S S S S S S S S S S S P9.3/ P9,2/ P9.1/ P9.0/ P8.7/ P8.6/ P8.5/ P8.4/ P8.3/ P8.2/ P8.1/ P8.0/ P7.7/ P7.6/ P7.5/ P7.4/ A0CLK/ 0SOMI/ 0SIMO/ A0STE/ A0RXD/ A0TXD/ UCLK1/ SOMI1/ SIMO1/ P7.3/UC 7.2/UCA 7.1/UCA P7.0/UC P4.7/UC P4.6/UC P4.5/ P4.4/ P4.3/ P P Figure4-1.100-PinPZPackage(TopView) 6 TerminalConfigurationandFunctions Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 Figure 4-2 shows the pinout for the 113-pin ZCA and ZQW packages. This figure shows only the default pinassignments;forallpinassignments,seeTable4-1. DV AV AV P6.0 TCK TDO P1.0 P1.3 P1.6 P2.0 P2.3 N/A CC1 CC SS A P6.3 P6.4 DV P6.2 RST XT2INXT2OUT P1.4 P1.5 P1.7 N/A P2.4 SS1 B P6.6 P6.5 P6.7 P2.5 P2.6 C XIN V N/A P6.1 TDI P1.2 P2.1 N/A P3.0 P3.1 REF+ D XOUT Ve V P10.7 TMS P1.1 P2.2 P2.7 P3.3 P3.4 REF+ REF– E P5.1 P5.0 P10.4 P10.1 N/A P3.2 P3.6 P3.7 F P10.6 P10.5 P9.6 P8.4 N/A P3.5 P4.1 DV SS2 G P10.3 P10.2 P8.7 P8.1 P7.3 P4.4 N/A P4.0 LCDCAP DV CC2 H P10.0 P9.7 N/A P8.0 P7.5 P4.7 P5.3 N/A P5.7 P5.6 J P9.5 P9.2 P5.5 P5.4 K P9.4 N/A P9.1 P8.6 P8.3 P7.6 P7.2 P7.0 P4.5 COM0 N/A P5.2 L N/A P9.3 P9.0 P8.5 P8.2 P7.7 P7.4 P7.1 P4.6 P4.3 P4.2 N/A M 1 2 3 4 5 6 7 8 9 10 11 12 N/A=NotAssigned.AllunassignedballlocationsontheZCAorZQWpackageshouldbeelectricallytiedtothe groundsupply.TheshortestgroundreturnpathtothedeviceshouldbeestablishedtoballlocationB3,DV . SS1 Figure4-2.113-PinZCAandZQWPackages(TopView) Copyright©2006–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 7 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 4.2 Signal Descriptions Table4-1describesthesignalsforalldevicevariantsandpackageoptions. Table4-1.SignalDescriptions PINNO. SIGNALNAME ZCA, I/O DESCRIPTION PZ ZQW DV 1 A1 Digitalsupplyvoltage,positiveterminal CC1 P6.3 General-purposedigitalI/O A3 2 B1 I/O AnaloginputA3for12-bitADC OA1O OA1output P6.4 General-purposedigitalI/O A4 3 B2 I/O AnaloginputA4for12-bitADC OA1I0 OA1inputmultiplexeron+terminaland–terminal P6.5 General-purposedigitalI/O A5 4 C2 I/O AnaloginputA5for12-bitADC OA2O OA2output P6.6 General-purposedigitalI/O A6 AnaloginputA6for12-bitADC 5 C1 I/O DAC0 DAC12.0output OA2I0 OA2inputmultiplexeron+terminaland–terminal P6.7 General-purposedigitalI/O A7 AnaloginputA7for12-bitADC 6 C3 I/O DAC1 DAC12.1output SVSIN Analoginputtobrownout,supplyvoltagesupervisor V 7 D2 O OutputofpositiveterminalofthereferencevoltageintheADC REF+ XIN 8 D1 I InputportforcrystaloscillatorXT1.Standardorwatchcrystalscanbeconnected. XOUT 9 E1 O OutputterminalofcrystaloscillatorXT1 Ve InputforanexternalreferencevoltagetotheADC REF+ 10 E2 I/O DAC0 DAC12.0output V Internalreferencevoltage,negativeterminalfortheADCreferencevoltage REF 11 E4 I Ve Externalappliedreferencevoltage,negativeterminalfortheADCreferencevoltage REF– P5.1 General-purposedigitalI/O S0(1) LCDsegmentoutput0 12 F1 I/O A12 AnaloginputA12for12-bitADC DAC1 DAC12.1output P5.0 General-purposedigitalI/O S1(1) LCDsegmentoutput1 13 F2 I/O A13 AnaloginputA13for12-bitADC OA1I1 OA1inputmultiplexeron+terminaland–terminal P10.7 General-purposedigitalI/O S2(1) LCDsegmentoutput2 14 E5 I/O A14 AnaloginputA14for12-bitADC OA2I1 OA2inputmultiplexeron+terminaland–terminal P10.6 General-purposedigitalI/O S3(1) 15 G1 I/O LCDsegmentoutput3 A15 AnaloginputA15to12-bitADC (1) SegmentsS0throughS3aredisabledwhentheLCDchargepumpfeatureisenabled(LCDCPEN=1)and,therefore,cannotbeused togetherwiththeLCDchargepump.OntheMSP430xG461xdevicesonly,S0throughS3arealsodisabledifVLCDEXT=1.This settingistypicallyusedtoapplyanexternalLCDvoltagesupplytotheLCDCAPterminal.Forthesedevices,setLCDCPEN=0, VLCDEXT=0,andVLCDx>0toenableanexternalLCDvoltagesupplytobeappliedtotheLCDCAPterminal. 8 TerminalConfigurationandFunctions Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 Table4-1.SignalDescriptions(continued) PINNO. SIGNALNAME ZCA, I/O DESCRIPTION PZ ZQW P10.5 General-purposedigitalI/O 16 G2 I/O S4 LCDsegmentoutput4 P10.4 General-purposedigitalI/O 17 F4 I/O S5 LCDsegmentoutput5 P10.3 General-purposedigitalI/O 18 H1 I/O S6 LCDsegmentoutput6 P10.2 General-purposedigitalI/O 19 H2 I/O S7 LCDsegmentoutput7 P10.1 General-purposedigitalI/O 20 F5 I/O S8 LCDsegmentoutput8 P10.0 General-purposedigitalI/O 21 J1 I/O S9 LCDsegmentoutput9 P9.7 General-purposedigitalI/O 22 J2 I/O S10 LCDsegmentoutput10 P9.6 General-purposedigitalI/O 23 G4 I/O S11 LCDsegmentoutput11 P9.5 General-purposedigitalI/O 24 K1 I/O S12 LCDsegmentoutput12 P9.4 General-purposedigitalI/O 25 L1 I/O S13 LCDsegmentoutput13 P9.3 General-purposedigitalI/O 26 M2 I/O S14 LCDsegmentoutput14 P9.2 General-purposedigitalI/O 27 K2 I/O S15 LCDsegmentoutput15 P9.1 General-purposedigitalI/O 28 L3 I/O S16 LCDsegmentoutput16 P9.0 General-purposedigitalI/O 29 M3 I/O S17 LCDsegmentoutput17 P8.7 General-purposedigitalI/O 30 H4 I/O S18 LCDsegmentoutput18 P8.6 General-purposedigitalI/O 31 L4 I/O S19 LCDsegmentoutput19 P8.5 General-purposedigitalI/O 32 M4 I/O S20 LCDsegmentoutput20 P8.4 General-purposedigitalI/O 33 G5 I/O S21 LCDsegmentoutput21 P8.3 General-purposedigitalI/O 34 L5 I/O S22 LCDsegmentoutput22 P8.2 General-purposedigitalI/O 35 M5 I/O S23 LCDsegmentoutput23 P8.1 General-purposedigitalI/O 36 H5 I/O S24 LCDsegmentoutput24 P8.0 General-purposedigitalI/O 37 J5 I/O S25 LCDsegmentoutput25 P7.7 General-purposedigitalI/O 38 M6 I/O S26 LCDsegmentoutput26 Copyright©2006–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 9 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com Table4-1.SignalDescriptions(continued) PINNO. SIGNALNAME ZCA, I/O DESCRIPTION PZ ZQW P7.6 General-purposedigitalI/O 39 L6 I/O S27 LCDsegmentoutput27 P7.5 General-purposedigitalI/O 40 J6 I/O S28 LCDsegmentoutput28 P7.4 General-purposedigitalI/O 41 M7 I/O S29 LCDsegmentoutput29 P7.3 General-purposedigitalI/O UCA0CLK Externalclockinput–USCI_A0inUARTorSPImode, 42 H6 I/O Clockoutput–USCI_A0inSPImode S30 LCDsegment30 P7.2 General-purposedigitalI/O UCA0SOMI 43 L7 I/O Slaveout/masterinofUSCI_A0inSPImode S31 LCDsegmentoutput31 P7.1 General-purposedigitalI/O UCA0SIMO 44 M8 I/O Slavein/masteroutofUSCI_A0inSPImode S32 LCDsegmentoutput32 P7.0 General-purposedigitalI/O UCA0STE 45 L8 I/O Slavetransmitenable–USCI_A0inSPImode S33 LCDsegmentoutput33 P4.7 General-purposedigitalI/O UCA0RXD 46 J7 I/O Receivedatain–USCI_A0inUARTorIrDAmode S34 LCDsegmentoutput34 P4.6 General-purposedigitalI/O UCA0TXD 47 M9 I/O Transmitdataout–USCI_A0inUARTorIrDAmode S35 LCDsegmentoutput35 P4.5 General-purposedigitalI/O UCLK1 Externalclockinput–USART1inUARTorSPImode, 48 L9 I/O Clockoutput–USART1inSPIMODE S36 LCDsegmentoutput36 P4.4 General-purposedigitalI/O SOMI1 49 H7 I/O Slaveout/masterinofUSART1inSPImode S37 LCDsegmentoutput37 P4.3 General-purposedigitalI/O SIMO1 50 M10 I/O Slavein/masteroutofUSART1inSPImode S38 LCDsegmentoutput38 P4.2 General-purposedigitalI/O STE1 51 M11 I/O Slavetransmitenable–USART1inSPImode S39 LCDsegmentoutput39 COM0 52 L10 O Commonoutput,COM0forLCDbackplanes P5.2 General-purposedigitalI/O 53 L12 I/O COM1 Commonoutput,COM1forLCDbackplanes P5.3 General-purposedigitalI/O 54 J8 I/O COM2 Commonoutput,COM2forLCDbackplanes P5.4 General-purposedigitalI/O 55 K12 I/O COM3 Commonoutput,COM3forLCDbackplanes 10 TerminalConfigurationandFunctions Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 Table4-1.SignalDescriptions(continued) PINNO. SIGNALNAME ZCA, I/O DESCRIPTION PZ ZQW P5.5 General-purposedigitalI/O 56 K11 I/O R03 InputportoflowestanalogLCDlevel(V5) P5.6 General-purposedigitalI/O LCDREF 57 J12 I/O ExternalreferencevoltageinputforregulatedLCDvoltage R13 InputportofthirdmostpositiveanalogLCDlevel(V4orV3) P5.7 General-purposedigitalI/O 58 J11 I/O R23 InputportofsecondmostpositiveanalogLCDlevel(V2) LCDCAP LCDcapacitorconnection 59 H11 I R33 Input/outputportofmostpositiveanalogLCDlevel(V1) DV 60 H12 Digitalsupplyvoltage,positiveterminal CC2 DV 61 G12 Digitalsupplyvoltage,negativeterminal SS2 P4.1 General-purposedigitalI/O 62 G11 I/O URXD1 Receivedatain–USART1inUARTmode P4.0 General-purposedigitalI/O 63 H9 I/O UTXD1 Transmitdataout–USART1inUARTmode P3.7 General-purposedigitalI/O 64 F12 I/O TB6 Timer_B7CCR6.Capture:CCI6A/CCI6Binput,compare:Out6output P3.6 General-purposedigitalI/O 65 F11 I/O TB5 Timer_B7CCR5.Capture:CCI5A/CCI5Binput,compare:Out5output P3.5 General-purposedigitalI/O 66 G9 I/O TB4 Timer_B7CCR4.Capture:CCI4A/CCI4Binput,compare:Out4output P3.4 General-purposedigitalI/O 67 E12 I/O TB3 Timer_B7CCR3.Capture:CCI3A/CCI3Binput,compare:Out3output P3.3 General-purposedigitalI/O UCB0CLK 68 E11 I/O Externalclockinput–USCI_B0inUARTorSPImode, Clockoutput–USCI_B0inSPImode P3.2 General-purposedigitalI/O UCB0SOMI 69 F9 I/O Slaveout/masterinofUSCI_B0inSPImode UCB0SCL I2Cclock–USCI_B0inI2Cmode P3.1 General-purposedigitalI/O UCB0SIMO 70 D12 I/O Slavein/masteroutofUSCI_B0inSPImode UCB0SDA I2Cdata–USCI_B0inI2Cmode P3.0 General-purposedigitalI/O 71 D11 I/O UCB0STE Slavetransmitenable–USCI_B0inSPImode P2.7 General-purposedigitalI/O ADC12CLK 72 E9 I/O Conversionclockfor12-bitADC DMAE0 DMAchannel0externaltrigger P2.6 General-purposedigitalI/O 73 C12 I/O CAOUT Comparator_Aoutput P2.5 General-purposedigitalI/O 74 C11 I/O UCA0RXD Receivedatain–USCI_A0inUARTorIrDAmode P2.4 General-purposedigitalI/O 75 B12 I/O UCA0TXD Transmitdataout–USCI_A0inUARTorIrDAmode P2.3 General-purposedigitalI/O 76 A11 I/O TB2 Timer_B7CCR2.Capture:CCI2A/CCI2Binput,compare:Out2output Copyright©2006–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 11 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com Table4-1.SignalDescriptions(continued) PINNO. SIGNALNAME ZCA, I/O DESCRIPTION PZ ZQW P2.2 General-purposedigitalI/O 77 E8 I/O TB1 Timer_B7CCR1.Capture:CCI1A/CCI1Binput,compare:Out1output P2.1 General-purposedigitalI/O 78 D8 I/O TB0 Timer_B7CCR0.Capture:CCI0A/CCI0Binput,compare:Out0output P2.0 General-purposedigitalI/O 79 A10 I/O TA2 Timer_ACapture:CCI2Ainput,compare:Out2output P1.7 General-purposedigitalI/O 80 B10 I/O CA1 Comparator_Ainput P1.6 General-purposedigitalI/O 81 A9 I/O CA0 Comparator_Ainput P1.5 General-purposedigitalI/O TACLK 82 B9 I/O Timer_A,clocksignalTACLKinput ACLK ACLKoutput(dividedby1,2,4,or8) P1.4 General-purposedigitalI/O TBCLK 83 B8 I/O InputclockTBCLK–Timer_B7 SMCLK SubmainsystemclockSMCLKoutput P1.3 General-purposedigitalI/O TBOUTH 84 A8 I/O SwitchallPWMdigitaloutputportstohighimpedance–Timer_B7TB0toTB6 SVSOUT SVS:outputofSVScomparator P1.2 General-purposedigitalI/O 85 D7 I/O TA1 Timer_A,Capture:CCI1Ainput,compare:Out1output P1.1 General-purposedigitalI/O TA0 86 E7 I/O Timer_A.Capture:CCI0Binput.Note:TA0isonlyaninputonthispin.BSLreceive. MCLK MCLKoutput P1.0 General-purposedigitalI/O 87 A7 I/O TA0 Timer_A.Capture:CCI0Ainput,compare:Out0output.BSLtransmit. XT2OUT 88 B7 O OutputterminalofcrystaloscillatorXT2 XT2IN 89 B6 I InputportforcrystaloscillatorXT2.Onlystandardcrystalscanbeconnected. TDO Testdataoutputport.TDO/TDIdataoutput. 90 A6 I/O TDI Programmingdatainputterminal TDI Testdatainput 91 D6 I TCLK Testclockinput.ThedeviceprotectionfuseisconnectedtoTDI/TCLK. TMS 92 E6 I Testmodeselect.TMSisusedasaninputportfordeviceprogrammingandtest. TCK 93 A5 I Testclock.TCKistheclockinputportfordeviceprogrammingandtest. RST Resetinput 94 B5 I NMI Nonmaskableinterruptinputport P6.0 General-purposedigitalI/O A0 95 A4 I/O AnaloginputA0for12-bitADC OA0I0 OA0inputmultiplexeron+terminaland–terminal P6.1 General-purposedigitalI/O A1 96 D5 I/O AnaloginputA1for12-bitADC OA0O OA0output P6.2 General-purposedigitalI/O A2 97 B4 I/O AnaloginputA2for12-bitADC OA0I1 OA0inputmultiplexeron+terminaland–terminal 12 TerminalConfigurationandFunctions Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 Table4-1.SignalDescriptions(continued) PINNO. SIGNALNAME ZCA, I/O DESCRIPTION PZ ZQW Analogsupplyvoltage,negativeterminal.SuppliesSVS,brownout,oscillator, AVSS 98 A3 Comparator_A,port1 DV 99 B3 Digitalsupplyvoltage,negativeterminal SS1 Analogsupplyvoltage,positiveterminal.SuppliesSVS,brownout,oscillator, AV 100 A2 CC Comparator_A,port1.DonotpowerupbeforepoweringDV andDV . CC1 CC2 A12, B11,D4, D9,F8, AllunassignedballlocationsontheZCAandZQWpackagesshouldbeelectricallytiedto NotAssigned – G8,H8, – thegroundsupply.Theshortestgroundreturnpathtothedeviceshouldbeestablishedto J4,J9, balllocationB3,DV . SS1 L2,L11, M1,M12 Copyright©2006–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 13 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 5 Specifications 5.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT VoltageappliedatV toV –0.3 4.1 V CC SS Voltageappliedtoanypin(2) –0.3 V +0.3 V CC Diodecurrentatanydeviceterminal ±2 mA Unprogrammeddevice –55 105 Storagetemperature,T °C stg Programmeddevice –40 85 (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesarereferencedtoV .TheJTAGfuse-blowvoltage,V ,isallowedtoexceedtheabsolutemaximumrating.Thevoltageis SS FB appliedtotheTDI/TCLKpinwhenblowingtheJTAGfuse. 5.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±1000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±250 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.Pinslistedas ±1000Vmayactuallyhavehigherperformance. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.Pinslistedas±250V mayactuallyhavehigherperformance. 5.3 Recommended Operating Conditions TypicalvaluesarespecifiedatV =3.3VandT =25°C(unlessotherwisenoted) CC A MIN NOM MAX UNIT Duringprogramexecution(1) 1.8 3.6 (AV =DV =V ) CC CC1/2 CC Duringflashmemoryprogramming(FG461x) VCC Supplyvoltage (AV =DV =V )(1) 2.7 3.6 V CC CC1/2 CC Duringprogramexecution,SVSenabledandPORON=1(1) (AV =DV =V )(2) 2 3.6 CC CC1/2 CC V Supplyvoltage(AV =DV =V ) 0 0 V SS SS SS1/2 SS T Operatingfree-airtemperaturerange –40 85 °C A LFselected,XTS_FLL=0(3) Watchcrystal 32.768 f Crystalfrequency(3) XT1selected,XTS_FLL=1 Ceramicresonator 450 8000 kHz (LFXT1) XT1selected,XTS_FLL=1 Crystal 1000 8000 Ceramicresonator 450 8000 f Crystalfrequency kHz (XT2) Crystal 1000 8000 V =1.8V DC 3 CC f Processorfrequency(signalMCLK) V =2.0V DC 4.6 MHz (System) CC V =3.6V DC 8 CC (1) TIrecommendspoweringAV andDV fromthesamesource.Amaximumdifferenceof0.3VbetweenAV andDV canbe CC CC CC CC toleratedduringpowerupandoperation. (2) TheminimumoperatingsupplyvoltageisdefinedaccordingtothetrippointwherePORisgoingactivebydecreasingthesupply voltage.PORisgoinginactivewhenthesupplyvoltageisraisedabovetheminimumsupplyvoltageplusthehysteresisoftheSVS circuitry. (3) InLFmode,theLFXT1oscillatorrequiresawatchcrystal.InXT1mode,LFXT1acceptsaceramicresonatororacrystal. 14 Specifications Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 f (MHz) System 8.0 MHz Supply voltage range, MSP430xG461x, during Supply voltage range, MSP430FG461x, program execution during flash memory programming 4.6 MHz 3.0 MHz 1.8 2.0 2.7 3 3.6 Supply Voltage (V) Figure5-1.FrequencyvsSupplyVoltage Copyright©2006–2020,TexasInstrumentsIncorporated Specifications 15 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 5.4 Supply Current Into AV + DV Excluding External Current CC CC overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITION MIN TYP MAX UNIT Activemode(1)(2) VCC=2.2V 280 370 CG461x T =–40°Cto85°C f(MCLK)=f(SMCLK)=1MHz, A VCC=3V 470 580 I f =32768Hz, µA (AM) (ACLK) XTS=0,SELM=(0,1), VCC=2.2V 400 480 FG461x T =–40°Cto85°C (FG461x:programexecutesfromflash) A V =3V 600 740 CC V =2.2V 45 70 I Lowpowermode(LPM0)(1) (2) T =–40°Cto85°C CC µA (LPM0) A V =3V 75 110 CC Low-powermode(LPM2), V =2.2V 11 20 CC I f =f =0MHz, T =–40°Cto85°C µA (LPM2) (MCLK) (SMCLK) A f(ACLK)=32768Hz,SCG0=0(3) (2) VCC=3V 17 24 T =–40°C 1.3 4.0 A T =25°C 1.3 4.0 A V =2.2V Low-powermode(LPM3), T =60°C CC 2.22 6.5 A f =f =0MHz, (MCLK) (SMCLK) I f(ACLK)=32768Hz,SCG0=1, TA=85°C 6.5 15.0 µA (LPM3) BasicTimer1enabled,ACLKselected, T =–40°C 1.9 5.0 A LCD_Aenabled,LCDCPEN=0, (staticmode,fLCD=f(ACLK)/32)(3) (4) (2) TA=25°C V =3V 1.9 5.0 CC T =60°C 2.5 7.5 A T =85°C 7.5 18.0 A T =–40°C 1.5 5.5 A T =25°C 1.5 5.5 A V =2.2V Low-powermode(LPM3), T =60°C CC 2.8 7.0 A f =f =0MHz, (MCLK) (SMCLK) I f(ACLK)=32768Hz,SCG0=1, TA=85°C 7.2 17.0 µA (LPM3) BasicTimer1enabled,ACLKselected, T =–40°C 2.5 6.5 A LCD_Aenabled,LCDCPEN=0, (4-muxmode;fLCD=f(ACLK)/32)(3) (4) (2) TA=25°C V =3V 2.5 6.5 CC T =60°C 3.2 8.0 A T =85°C 8.5 20.0 A T =–40°C 0.13 1.0 A T =25°C 0.22 1.0 A V =2.2V CC T =60°C 0.9 2.5 A Low-powermode(LPM4), T =85°C 4.3 12.5 A I f =0MHz,f =0MHz, µA (LPM4) (MCLK) (SMCLK) f(ACLK)=0Hz,SCG0=1(3) (2) TA=–40°C 0.13 1.6 T =25°C 0.3 1.6 A V =3V CC T =60°C 1.1 3.0 A T =85°C 5.0 15.0 A (1) Timer_Bisclockedbyf =f =1MHz.Allinputsaretiedto0VortoV .Outputsdonotsourceorsinkanycurrent. (DCOCLK) (DCO) CC (2) Currentforbrownoutincluded. (3) Allinputsaretiedto0VortoV .Outputsdonotsourceorsinkanycurrent. CC (4) TheLPM3currentsarecharacterizedwithaMicroCrystalCC4V-T1A(9pF)crystalandOSCCAPx=1h. Currentconsumptionofactivemodeversussystemfrequency,FGversion: I =I ×f [MHz] (AM) (AM)[1MHz] (System) Currentconsumptionofactivemodeversussupplyvoltage,FGversion: I =I +200µA/V×(V –3V) (AM) (AM)[3V] CC 16 Specifications Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 5.5 Thermal Characteristics PARAMETER PACKAGE VALUE UNIT θ Junction-to-ambientthermalresistance,stillair(1) 42 °C/W JA θ Junction-to-case(top)thermalresistance(2) 10 °C/W JC,TOP θ Junction-to-boardthermalresistance(3) ZQW(BGA) 12 °C/W JB Ψ Junction-to-boardthermalcharacterizationparameter 12 °C/W JB Ψ Junction-to-topthermalcharacterizationparameter 0.3 °C/W JT θ Junction-to-ambientthermalresistance,stillair(1) 43.5 °C/W JA θ Junction-to-case(top)thermalresistance(2) 6.2 °C/W JC,TOP θ Junction-to-boardthermalresistance(3) PZ(PQFP-100) 21.8 °C/W JB Ψ Junction-to-boardthermalcharacterizationparameter 21.2 °C/W JB Ψ Junction-to-topthermalcharacterizationparameter 0.2 °C/W JT (1) Thejunction-to-ambientthermalresistanceundernaturalconvectionisobtainedinasimulationonaJEDEC-standard,High-Kboard,as specifiedinJESD51-7,inanenvironmentdescribedinJESD51-2a. (2) Thejunction-to-case(top)thermalresistanceisobtainedbysimulatingacoldplatetestonthepackagetop.NospecificJEDEC standardtestexists,butaclosedescriptioncanbefoundintheANSISEMIstandardG30-88. (3) Thejunction-to-boardthermalresistanceisobtainedbysimulatinginanenvironmentwitharingcoldplatefixturetocontrolthePCB temperature,asdescribedinJESD51-8. Copyright©2006–2020,TexasInstrumentsIncorporated Specifications 17 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 5.6 Schmitt-Trigger Inputs – Ports P1 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK,TDO/TDI) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT V =2.2V 1.1 1.55 CC V Positive-goinginputthresholdvoltage V IT+ V =3V 1.5 1.98 CC V =2.2V 0.4 0.9 CC V Negative-goinginputthresholdvoltage V IT– V =3V 0.9 1.3 CC V =2.2V 0.3 1.1 CC V Inputvoltagehysteresis(V –V ) V hys IT+ IT– V =3V 0.5 1 CC 5.7 Inputs Px.x, TAx, TBX overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC PortP1,P2:P1.xtoP2.x,externaltriggersignal 2.2V 62 t(int) Externalinterrupttiming fortheinterruptflag(1) 3V 50 ns TA0,TA1,TA2 2.2V 62 t Timer_A,Timer_Bcapturetiming ns (cap) TB0,TB1,TB2,TB3,TB4,TB5,TB6 3V 50 f(TAext) Timer_AorTimer_Bclockfrequency TACLK,TBCLK 2.2V 8 MHz f(TBext) externallyappliedtopin INCLKt(H)=t(L) 3V 10 f 2.2V 8 (TAint) TimerAorTimerBclockfrequency SMCLKorACLKsignalselected MHz f 3V 10 (TBint) (1) Theexternalsignalsetstheinterruptflageverytimetheminimumt parametersaremet.Itmaybesetevenwithtriggersignals (int) shorterthant . (int) 5.8 Leakage Current – Ports P1 to P10(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT V(Px.y)(2) I Leakagecurrent,PortPx V =2.2V,3V ±50 nA lkg(Px.y) (1≤×≤10,0≤y≤7) CC (1) TheleakagecurrentismeasuredwithV orV appliedtothecorrespondingpins,unlessotherwisenoted. SS CC (2) Theportpinmustbeselectedasinput. 5.9 Outputs – Ports P1 to P10 overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT I =–1.5mA,V =2.2V(1) V –0.25 V OH(max) CC CC CC I =–6mA,V =2.2V(2) V –0.6 V OH(max) CC CC CC V High-leveloutputvoltage V OH I =–1.5mA,V =3V(1) V –0.25 V OH(max) CC CC CC I =–6mA,V =3V(2) V –0.6 V OH(max) CC CC CC I =1.5mA,V =2.2V(1) V V +0.25 OL(max) CC SS SS I =6mA,V =2.2V(2) V V +0.6 OL(max) CC SS SS V Low-leveloutputvoltage V OL I =1.5mA,V =3V(1) V V +0.25 OL(max) CC SS SS I =6mA,V =3V(2) V V +0.6 OL(max) CC SS SS (1) Themaximumtotalcurrent,I andI ,foralloutputscombined,shouldnotexceed±12mAtosatisfythemaximumspecified OH(max) OL(max) voltagedrop. (2) Themaximumtotalcurrent,I andI ,foralloutputscombined,shouldnotexceed±48mAtosatisfythemaximumspecified OH(max) OL(max) voltagedrop. 18 Specifications Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 5.10 Output Frequency overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V =2.2V DC 10 CC f (1≤×≤10,0≤y≤7) C =20F,I =±1.5mA MHz (Px.y) L L V =3V DC 12 CC f P1.1/TA0/MCLK (MCLK) V =2.2V 10 f(SMCLK) P1.4/TBCLK/SMCLK CL=20pF CC MHz f P1.5/TACLK/ACLK V =3V DC 12 (ACLK) CC f =f =f 40% 60% (ACLK) (LFXT1) (XT1) P1.5/TACLK/ACLK, f =f =f 30% 70% C =20pF,V =2.2V,3V (ACLK) (LFXT1) (LF) L CC f =f 50% (ACLK) (LFXT1) f =f 40% 60% t Dutycycleofoutput P1.1/TA0/MCLK, (MCLK) (XT1) (Xdc) frequency CL=20pF,VCC=2.2V,3V f(MCLK)=f(DCOCLK) 5105%n–s 50% 5105%n+s f =f 40% 60% (SMCLK) (XT2) P1.4/TBCLK/SMCLK, CL=20pF,VCC=2.2V,3V f(SMCLK)=f(DCOCLK) 5105%n–s 50% 5105%n+s Copyright©2006–2020,TexasInstrumentsIncorporated Specifications 19 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 5.11 Typical Characteristics – Outputs overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) 25.0 50.0 mA VP2CC.0= 2.2 V TA= 25°C mA VP2CC.0= 3 V TA= 25°C urrent - 20.0 TA= 85°C -urrent 40.0 C C T = 85°C ut ut A p 15.0 p 30.0 ut ut O O w-Level 10.0 w-Level 20.0 o o L L pical 5.0 pical 10.0 Ty Ty - - L L O O I I 0.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 V –Low-Level Output Voltage–V V -Low-Level Output Voltage-V OL OL Figure5-2.TypicalLow-LevelOutputCurrentvsTypicalLow- Figure5-3.TypicalLow-LevelOutputCurrentvsTypicalLow- LevelOutputCurrent LevelOutputCurrent 0.0 0.0 mA VCC= 2.2 V mA VCC= 3 V P2.0 P2.0 Output Current - -1-05..00 -Output Curren --1200..00 - typical High-Level --1250..00 TA= 85°C -Typical High-Level --3400..00 TA= 85°C H H O O I -25.0 TA= 25°C! I -50.0 TA= 25°C 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 V -High-Level Output Voltage-V V -High-Level Output Voltage-V OH OH Figure5-4.TypicalHigh-LevelOutputCurrentvsTypicalHigh- Figure5-5.TypicalHigh-LevelOutputCurrentvsTypicalHigh- LevelOutputCurrent LevelOutputCurrent 20 Specifications Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 5.12 Wake-up Timing From LPM3 overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT f=1MHz 6 t Delaytime f=2MHz V =2.2V,3V 6 µs d(LPM3) CC f=3MHz 6 5.13 RAM overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT VRAMh CPUhalted(1) 1.6 V (1) ThisparameterdefinestheminimumsupplyvoltagewhenthedatainprogrammemoryRAMremainunchanged.Noprogramexecution shouldtakeplaceduringthissupplyvoltagecondition. 5.14 LCD_A overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC V Supplyvoltage(1) Chargepumpenabled 2.2 3.6 V CC(LCD) (LCDCPEN=1,VLCDx>0000) V =3V,LCDCPEN=1, LCD(typ) I Supplycurrent(1) VLCDx=1000,allsegmentson,f =f /32, 2.2V 3 µA CC(LCD) LCD ACLK noLCDconnected(2),T =25°C A C CapacitoronLCDCAP(3) (4) Chargepumpenabled 4.7 µF LCD (LCDCPEN=1,VLCDx>0000) f LCDfrequency 1.1 kHz LCD VLCDx=0000 V CC VLCDx=0001 2.60 VLCDx=0010 2.66 VLCDx=0011 2.72 VLCDx=0100 2.78 VLCDx=0101 2.84 VLCDx=0110 2.90 VLCDx=0111 2.96 V LCDvoltage(4) V LCD VLCDx=1000 3.02 VLCDx=1001 3.08 VLCDx=1010 3.14 VLCDx=1011 3.20 VLCDx=1100 3.26 VLCDx=1101 3.32 VLCDx=1110 3.38 VLCDx=1111 3.44 3.60 R V =3V,CPEN=1, LCD LCDdriveroutputimpedance LCD 2.2V 10 kΩ VLCDx=1000,I =±10µΑ LOAD (1) RefertothesupplycurrentspecificationsI foradditionalcurrentspecificationswiththeLCD_Amoduleactive. (LPM3) (2) ConnectinganactualdisplayincreasesthecurrentconsumptiondependingonthesizeoftheLCD. (3) Enablingtheinternalchargepumpwithanexternalcapacitorsmallerthantheminimumspecifiedmightdamagethedevice. (4) SegmentsS0throughS3aredisabledwhentheLCDchargepumpfeatureisenabled(LCDCPEN=1)and,therefore,cannotbeused togetherwiththeLCDchargepump.OntheMSP430xG461xdevicesonly,S0throughS3arealsodisabledifVLCDEXT=1.This settingistypicallyusedtoapplyanexternalLCDvoltagesupplytotheLCDCAPterminal.Forthesedevices,setLCDCPEN=0, VLCDEXT=0,andVLCDx>0toenableanexternalLCDvoltagesupplytobeappliedtotheLCDCAPterminal. Copyright©2006–2020,TexasInstrumentsIncorporated Specifications 21 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 5.15 Comparator_A(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 2.2V 25 40 I CAON=1,CARSEL=0,CAREF=0 µA (CC) 3V 45 60 CAON=1,CARSEL=0,CAREF=(1,2,3), 2.2V 30 50 I µA (Refladder/RefDiode) NoloadatP1.6/CA0andP1.7/CA1 3V 45 71 Voltage @ 0.25 V node PCA0=1,CARSEL=1,CAREF=1, V CC 2.2V,3V 0.23 0.24 0.25 (Ref025) VCC NoloadatP1.6/CA0andP1.7/CA1 Voltage @ 0.5 V node PCA0=1,CARSEL=1,CAREF=2, V CC 2.2V,3V 0.47 0.48 0.5 (Ref050) VCC NoloadatP1.6/CA0andP1.7/CA1 PCA0=1,CARSEL=1,CAREF=3, 2.2V 390 480 540 V NoloadatP1.6/CA0andP1.7/CA1, mV (RefVT) T =85°C 3V 400 490 550 A Common-modeinput V CAON=1 2.2V,3V 0 V –1 V IC voltagerange CC V –V Offsetvoltage(2) 2.2V,3V –30 30 mV p S V Inputhysteresis CAON=1 2.2V,3V 0 0.7 1.4 mV hys T =25°C, 2.2V 160 210 300 A ns Overdrive10mV,withoutfilter:CAF=0 3V 80 150 240 t (responseLH) T =25°C, 2.2V 1.4 1.9 3.4 A µs Overdrive10mV,withoutfilter:CAF=1 3V 0.9 1.5 2.6 t(responseHL) TA=25°C, 2.2V 130 210 300 ns Overdrive10mV,withoutfilter:CAF=0 3V 80 150 240 T =25°C, 2.2V 1.4 1.9 3.4 A µs Overdrive10mV,withoutfilter:CAF=1 3V 0.9 1.5 2.6 (1) TheleakagecurrentfortheComparator_AterminalsisidenticaltoI specification. lkg(Px.x) (2) TheinputoffsetvoltagecanbecancelledbyusingtheCAEXbittoinverttheComparator_Ainputsonsuccessivemeasurements.The twosuccessivemeasurementsarethensummedtogether. 22 Specifications Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 5.16 Typical Characteristics – Comparator_A 650 650 V = 2.2 V V = 3 V CC CC mV 600 mV 600 - - Reference Voltage 555000 Typical Reference Voltage 555000 Typical - - VREF VREF 450 450 400 400 -45 -25 -5 15 35 55 75 95 -45 -25 -5 15 35 55 75 95 T -Free-Air Temperature-°C T -Free-Air Temperature-°C A A Figure5-6.ReferenceVoltagevsFree-AirTemperature Figure5-7.ReferenceVoltagevsFree-AirTemperature 0 V VCC 0 1 CAF CAON Low-Pass Filter To Internal Modules 0 0 V+ + _ V- 1 1 CAOUT Set CAIFG Flag t»2 µs Figure5-8.BlockDiagramofComparator_AModule Overdrive VCAOUT V- 400 mV V+ t(response) Figure5-9.OverdriveDefinition Copyright©2006–2020,TexasInstrumentsIncorporated Specifications 23 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 5.17 POR, BOR overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t 2000 µs d(BOR) 0.7× V dV /dt≤3V/s(seeFigure5-10) V CC(start) CC V (B_IT–) V Brownout(2)(3) dVCC/dt≤3V/s(seeFigure5-10throughFigure5- 1.79 V (B_IT–) 12) V dV /dt≤3V/s(seeFigure5-10) 70 130 210 mV hys(B_IT–) CC PulsedurationneededatRST/NMIpintoaccepted t 2 µs (reset) resetinternally,V =2.2V,3V CC (1) ThecurrentconsumptionofthebrownoutmoduleisalreadyincludedintheI currentconsumptiondata. CC (2) ThevoltagelevelV +V ≤1.89V. (B_IT–) hys(B_IT–) (3) Duringpowerup,theCPUbeginscodeexecutionfollowingaperiodoft afterV =V +V .ThedefaultFLL+settings d(BOR) CC (B_IT–) hys(B_IT–) mustnotbechangeduntilV ≥V ,whereV istheminimumsupplyvoltageforthedesiredoperatingfrequency.Seethe CC CC(min) CC(min) MSP430x4xxFamilyUser’sGuide(SLAU056)formoreinformationonthebrownoutandSVScircuit. V CC V hys(B_IT-) V (B_IT-) V CC(start) 1 0 t d(BOR) Figure5-10.POR,BORvsSupplyVoltage 2 VCC tpw 3 V V = 3 V CC Typical Conditions 1.5 V - op) 1 dr C( VC VCC(drop) 0.5 0 0.001 1 1000 1 ns 1 ns t - Pulse Width -ms t - Pulse Width -ms pw pw Figure5-11.V LevelwithaSquareVoltageDroptoGenerateaPORorBORSignal CC(drop) 24 Specifications Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 VCC tpw 2 3 V V = 3 V CC 1.5 Typical Conditions V -p) o 1 r d C( VCC(drop) C V 0.5 t = t f r 0 0.001 1 1000 t t f r tpw - Pulse Width -ms tpw - Pulse Width -ms Figure5-12.V LevelWithaTriangleVoltageDroptoGenerateaPORorBORSignal CC(drop) 5.18 SVS (Supply Voltage Supervisor and Monitor) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT dV /dt>30V/ms(seeFigure5-13) 5 150 CC t µs (SVSR) dV /dt≤30V/ms 2000 CC t SVSon,switchfromVLD=0toVLD≠0,V =3V 150 300 µs d(SVSon) CC t VLD≠0(1) 12 µs settle V VLD≠0,V /dt≤3V/s(seeFigure5-13) 1.55 1.7 V (SVSstart) CC VLD=1 70 120 155 mV VCC/dt≤3V/s(seeFigure5-13) VLD=2to14 V(SVS_IT–) V(SVS_IT–) V ×0.001 ×0.016 hys(SVS_IT–) V /dt≤3V/s(seeFigure5-13),externalvoltage CC VLD=15 4.4 20 mV appliedonA7 VLD=1 1.8 1.9 2.05 VLD=2 1.94 2.1 2.23 VLD=3 2.05 2.2 2.35 VLD=4 2.14 2.3 2.46 VLD=5 2.24 2.4 2.58 VLD=6 2.33 2.5 2.69 VLD=7 2.46 2.65 2.84 V /dt≤3V/s(seeFigure5-13) CC VLD=8 2.58 2.8 2.97 V V (SVS_IT–) VLD=9 2.69 2.9 3.10 VLD=10 2.83 3.05 3.26 VLD=11 2.94 3.2 3.39 VLD=12 3.11 3.35 3.58(2) VLD=13 3.24 3.5 3.73(2) VLD=14 3.43 3.7(2) 3.96(2) V /dt≤3V/s(seeFigure5-13),externalvoltage CC VLD=15 1.1 1.2 1.3 appliedonA7 I (3) VLD≠0,V =2.2V,3V 10 15 µA CC(SVS) CC (1) t isthesettlingtimethatthecomparatoroutputneedstohaveastablelevelafterVLDisswitchedfromVLD≠0toadifferentVLD settle valuefrom2to15.Theoverdriveisassumedtobe>50mV. (2) Therecommendedoperatingvoltagerangeislimitedto3.6V. (3) ThecurrentconsumptionoftheSVSmoduleisnotincludedintheI currentconsumptiondata. CC Copyright©2006–2020,TexasInstrumentsIncorporated Specifications 25 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com Software Sets VLD>0: VCC SVS isActive Vhys(SVS_IT-) V (SVS_IT-) V (SVSstart) Vhys(B_IT-) V(B_IT-) VCC(start) Brown Brownout Out Region Brownout Region 1 0 SVSOut td(BOR) td(BOR) SVS Circuit isActive From VLD > to VCC < V(B_IT-) 1 0 td(SVSon) td(SVSR) Set POR 1 undefined 0 Figure5-13.SVSReset(SVSR)vsSupplyVoltage V CC t pw 3 V 2 Rectangular Drop V CC(drop) 1.5 Triangular Drop V -p) ro 1 d ( C 1 ns 1 ns C V 0.5 V CC t pw 3 V 0 1 10 100 1000 tpw - Pulse Width -ms V CC(drop) t = t f r t t f r t - Pulse Width -ms Figure5-14.V withaSquareVoltageDropandaTriangleVoltageDroptoGenerateanSVSSignal CC(drop) 26 Specifications Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 5.19 DCO overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC N =01Eh,FN_8=FN_4=FN_3=FN_2=0,D=2, f (DCO) 2.2V,3V 1 MHz (DCOCLK) DCOPLUS=0 2.2V 0.3 0.65 1.25 f FN_8=FN_4=FN_3=FN_2=0,DCOPLUS=1 MHz (DCO=2) 3V 0.3 0.7 1.3 2.2V 2.5 5.6 10.5 f FN_8=FN_4=FN_3=FN_2=0,DCOPLUS=1 MHz (DCO=27) 3V 2.7 6.1 11.3 2.2V 0.7 1.3 2.3 f FN_8=FN_4=FN_3=FN_2=1,DCOPLUS=1 MHz (DCO=2) 3V 0.8 1.5 2.5 2.2V 5.7 10.8 18 f FN_8=FN_4=FN_3=FN_2=1,DCOPLUS=1 MHz (DCO=27) 3V 6.5 12.1 20 2.2V 1.2 2 3 f FN_8=FN_4=0,FN_3=1,FN_2=x,DCOPLUS=1 MHz (DCO=2) 3V 1.3 2.2 3.5 2.2V 9 15.5 25 f FN_8=FN_4=0,FN_3=1,FN_2=x,DCOPLUS=1 MHz (DCO=27) 3V 10.3 17.9 28.5 2.2V 1.8 2.8 4.2 f FN_8=0,FN_4=1,FN_3=FN_2=x,DCOPLUS=1 MHz (DCO=2) 3V 2.1 3.4 5.2 2.2V 13.5 21.5 33 f FN_8=0,FN_4=1,FN_3=FN_2=x,DCOPLUS=1 MHz (DCO=27) 3V 16 26.6 41 2.2V 2.8 4.2 6.2 f FN_8=1,FN_4=1=FN_3=FN_2=x,DCOPLUS=1 MHz (DCO=2) 3V 4.2 6.3 9.2 2.2V 21 32 46 f FN_8=1,FN_4=1=FN_3=FN_2=x,DCOPLUS=1 MHz (DCO=27) 3V 30 46 70 StepsizebetweenadjacentDCOtaps: 1<TAP≤20 1.06 1.11 S n Sn=fDCO(Tapn+1)/fDCO(Tapn)(seeFigure5-16fortaps21to27) TAP=27 1.07 1.17 Temperaturedrift,N =01Eh, 2.2V –0.2 –0.3 –0.4 D (DCO) %/°C t FN_8=FN_4=FN_3=FN_2=0,D=2,DCOPLUS=0 3V –0.2 –0.3 –0.4 DriftwithV variation,N =01Eh, D CC (DCO) 0 5 15 %/V V FN_8=FN_4=FN_3=FN_2=0,D=2,DCOPLUS=0 f f (DCO) (DCO) f(DCO3V) f(DCO20°C) 1.0 1.0 0 1.8 2.4 3.0 3.6 -40 -20 0 20 40 60 85 V - V T - °C CC A Figure5-15.DCOFrequencyvsSupplyVoltageV andvsAmbientTemperature CC Copyright©2006–2020,TexasInstrumentsIncorporated Specifications 27 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com s p a T 1.17 O C D n e e w et b o Rati 1.11 Max e z si p e t S n- 1.07 S 1.06 Min 1 20 27 DCO Tap Figure5-16.DCOTapStepSize Legend Tolerance at Tap 27 O) C D f( DCO Frequency Adjusted by Bits 9 5 2 to 2 in SCFI1 {N } {DCO} Tolerance at Tap 2 Overlapping DCO Ranges: Uninterrupted Frequency Range FN_2=0 FN_2=1 FN_2=x FN_2=x FN_2=x FN_3=0 FN_3=0 FN_3=1 FN_3=x FN_3=x FN_4=0 FN_4=0 FN_4=0 FN_4=1 FN_4=x FN_8=0 FN_8=0 FN_8=0 FN_8=0 FN_8=1 Figure5-17.FiveOverlappingDCORangesControlledbyFN_xBits 28 Specifications Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 5.20 Crystal Oscillator, LFXT1 Oscillator overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) (2) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT OSCCAPx=0h,V =2.2V,3V 0 CC OSCCAPx=1h,V =2.2V,3V 10 C Integratedinputcapacitance(3) CC pF XIN OSCCAPx=2h,V =2.2V,3V 14 CC OSCCAPx=3h,V =2.2V,3V 18 CC OSCCAPx=0h,V =2.2V,3V 0 CC OSCCAPx=1h,V =2.2V,3V 10 C Integratedoutputcapacitance(3) CC pF XOUT OSCCAPx=2h,V =2.2V,3V 14 CC OSCCAPx=3h,V =2.2V,3V 18 CC V Low-levelinputvoltageatXIN V =2.2V,3V(4) V 0.2×V V IL CC SS CC V High-levelinputvoltageatXIN V =2.2V,3V(4) 0.8×V V V IH CC CC CC (1) Theparasiticcapacitancefromthepackageandboardmaybeestimatedtobe2pF.Theeffectiveloadcapacitorforthecrystalis (C ×C )/(C +C ).ThisisindependentofXTS_FLL. XIN XOUT XIN XOUT (2) ToimproveEMIonthelow-powerLFXT1oscillator,particularlyintheLFmode(32kHz),thefollowingguidelinesshouldbeobserved. • KeepthetracebetweentheMCUandthecrystalasshortaspossible. • Designagoodgroundplanearoundtheoscillatorpins. • PreventcrosstalkfromotherclockordatalinesintooscillatorpinsXINandXOUT. • AvoidrunningPCBtracesunderneathoradjacenttotheXINandXOUTpins. • UseassemblymaterialsandprocessesthatavoidanyparasiticloadontheoscillatorXINandXOUTpins. • Ifconformalcoatingisused,ensurethatitdoesnotinducecapacitiveorresistiveleakagebetweentheoscillatorpins. • DonotroutetheXOUTlinetotheJTAGheadertosupporttheserialprogrammingadapterasshowninotherdocumentation.This signalisnolongerrequiredfortheserialprogrammingadapter. (3) TIrecommendsexternalcapacitanceforprecisionreal-timeclockapplications;OSCCAPx=0h. (4) Appliesonlywhenusinganexternallogic-levelclocksource.XTS_FLLmustbeset.Notapplicablewhenusingacrystalorresonator. 5.21 Crystal Oscillator, XT2 Oscillator overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT C Integratedinputcapacitance V =2.2V,3V 2 pF XT2IN CC C Integratedoutputcapacitance V =2.2V,3V 2 pF XT2OUT CC V V 0.2×V V IL SS CC InputlevelsatXT2IN V V =2.2V,3V(2) 0.8×V V V IH CC CC CC (1) Theoscillatorneedscapacitorsatbothterminals,withvaluesspecifiedbythecrystalmanufacturer. (2) Appliesonlywhenusinganexternallogic-levelclocksource.Notapplicablewhenusingacrystalorresonator. 5.22 USCI (UART Mode) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC Internal:SMCLK,ACLK f USCIinputclockfrequency External:UCLK f MHz USCI SYSTEM Dutycycle=50%±10% BITCLKclockfrequency f 2.2V,3V 1 MHz BITCLK (equalsbaudrateinMBaud) 2.2V 50 150 600 t UARTreceivedeglitchtimeUART(1) ns τ 3V 50 100 600 (1) PulsesontheUARTreceiveinput(UCxRX)shorterthantheUARTreceivedeglitchtimearesuppressed.Toensurethatpulsesare correctlyrecognized,theirdurationshouldexceedthemaximumspecificationofthedeglitchtime. Copyright©2006–2020,TexasInstrumentsIncorporated Specifications 29 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 5.23 USCI (SPI Master Mode) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(seeFigure5-18 andFigure5-19) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC SMCLK,ACLK f USCIinputclockfrequency f MHz USCI Dutycycle=50%±10% SYSTEM 2.2V 110 t SOMIinputdatasetuptime ns SU,MI 3V 75 2.2V 0 t iSOMIinputdataholdtime ns HD,MI 3V 0 2.2V 30 t SIMOoutputdatavalidtime UCLKedgetoSIMOvalid,C =20pF ns VALID,MO L 3V 20 5.24 USCI (SPI Slave Mode) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(seeFigure5-20 andFigure5-21) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC STEleadtime t 2.2V,3V 50 ns STE,LEAD STElowtoclock STElagtime t 2.2V,3V 10 ns STE,LAG LastclocktoSTEhigh STEaccesstime t 2.2V,3V 50 ns STE,ACC STElowtoSOMIdataout STEdisabletime t 2.2V,3V 50 ns STE,DIS STEhightoSOMIhighimpedance 2.2V 20 t SIMOinputdatasetuptime ns SU,SI 3V 15 2.2V 10 t SIMOinputdataholdtime ns HD,SI 3V 10 2.2V 75 110 t SOMIoutputdatavalidtime UCLKedgetoSOMIvalid,C =20pF ns VALID,SO L 3V 50 75 30 Specifications Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 1/f UCxCLK CKPL =0 UCLK CKPL =1 t t t LOW/HIGH LOW/HIGH SU,MI t HD,MI SOMI t VALID,MO SIMO Figure5-18.SPIMasterMode,CKPH=0 1/f UCxCLK CKPL =0 UCLK CKPL =1 t t LOW/HIGH LOW/HIGH t HD,MI t SU,MI SOMI t VALID,MO SIMO Figure5-19.SPIMasterMode,CKPH=1 Copyright©2006–2020,TexasInstrumentsIncorporated Specifications 31 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com t t STE,LEAD STE,LAG STE 1/f UCxCLK CKPL =0 UCLK CKPL =1 t t t LOW/HIGH LOW/HIGH SU,SIMO t HD,SIMO SIMO t t t ACC VALID,SOMI DIS SOMI Figure5-20.SPISlaveMode,CKPH=0 t t STE,LEAD STE,LAG STE 1/f UCxCLK CKPL=0 UCLK CKPL=1 t t LOW/HIGH LOW/HIGH t HD,SI t SU,SI SIMO t t t ACC VALID,SO DIS SOMI Figure5-21.SPISlaveMode,CKPH=1 32 Specifications Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 5.25 USCI (I2C Mode) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(seeFigure5-22) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC Internal:SMCLK,ACLK f USCIinputclockfrequency External:UCLK f MHz USCI SYSTEM DutyCycle=50%±10% f SCLclockfrequency 2.2V,3V 0 400 kHz SCL f ≤100kHz 2.2V,3V 4 SCL t Holdtime(repeated)START µs HD,STA f >100kHz 2.2V,3V 0.6 SCL f ≤100kHz 2.2V,3V 4.7 SCL t SetuptimeforarepeatedSTART µs SU,STA f >100kHz 2.2V,3V 0.6 SCL t Dataholdtime 2.2V,3V 0 ns HD,DAT t Datasetuptime 2.2V,3V 250 ns SU,DAT t SetuptimeforSTOP 2.2V,3V 4 µs SU,STO Pulsedurationofspikessuppressedby 2.2V 50 150 600 t ns SP inputfilter 3V 50 100 600 t t t t HD,STA SU,STA HD,STA BUF SDA t t t LOW HIGH SP SCL t t SU,DAT SU,STO t HD,DAT Figure5-22.I2CModeTiming 5.26 USART1 overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V =2.2V,SYNC=0,UARTmode 200 430 800 CC t USART1deglitchtime ns (τ) V =3V,SYNC=0,UARTmode 150 280 500 CC (1) ThesignalappliedtotheUSART1receivesignal(terminal)(URXD1)mustmeetthetimingrequirementsoft toensurethattheURXS (τ) flip-flopisset.TheURXSflip-flopissetwithnegativepulsesthatmeettheminimum-timingconditionoft .Theoperatingconditionsto (τ) settheflagmustbemetindependentlyfromthistimingconstraint.Thedeglitchcircuitryisactiveonlyonnegativetransitionsonthe URXD1line. Copyright©2006–2020,TexasInstrumentsIncorporated Specifications 33 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 5.27 12-Bit ADC, Power Supply and Input Range Conditions overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT AV andDV areconnectedtogether, CC CC AV Analogsupplyvoltage AV andDV areconnectedtogether, 2.2 3.6 V CC SS SS V =V =0V (AVSS) (DVSS) AllexternalAxterminals,Analoginputsselectedin V Analoginputvoltagerange(2) ADC12MCTLxregister,P6Sel.x=1, 0 V V (P6.x/Ax) AVCC V ≤V ≤V (AVSS) Ax (AVCC) f =5.0MHz, V =2.2V 0.65 1.3 Operatingsupplycurrentinto ADC12CLK CC IADC12 AVCCterminal(3) ASDHCT012=O0N,S=H1T,1R=EF0O,AND=C01,2DIV=0 VCC=3V 0.8 1.6 mA f =5.0MHz, ADC12CLK V =3V 0.5 0.8 ADC12ON=0,REFON=1,REF2_5V=1 CC Operatingsupplycurrentinto IREF+ AVCCterminal(4) fADC12CLK=5.0MHz, VCC=2.2V 0.5 0.8 mA ADC12ON=0,REFON=1,REF2_5V=0 V =3V 0.5 0.8 CC Onlyoneterminalcanbeselectedatone C Inputcapacitance V =2.2V 40 pF I time,Ax CC R InputMUXONresistance 0V≤V ≤V V =3V 2000 Ω I Ax AVCC CC (1) TheleakagecurrentisdefinedintheleakagecurrenttablewithAxparameter. (2) TheanaloginputvoltagerangemustbewithintheselectedreferencevoltagerangeV toV forvalidconversionresults. R+ R– (3) TheinternalreferencesupplycurrentisnotincludedincurrentconsumptionparameterI . ADC12 (4) TheinternalreferencecurrentissuppliedfromterminalAV .ConsumptionisindependentoftheADC12ONcontrolbit,unlessa CC conversionisactive.TheREFONbitenablestosettlethebuilt-inreferencebeforestartinganA/Dconversion. 5.28 12-Bit ADC, External Reference overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Ve Positiveexternalreference Ve >V /Ve (2) 1.4 V V REF+ voltageinput REF+ REF– REF– AVCC V /Ve Negativeexternalreference Ve >V /Ve (3) 0 1.2 V REF– REF– voltageinput REF+ REF– REF– (VeREF+– Differentialexternalreference Ve >V /Ve (4) 1.4 V V V /Ve ) voltageinput REF+ REF– REF– AVCC REF– REF– I Inputleakagecurrent 0V≤Ve ≤V V =2.2V,3V ±1 µA VeREF+ REF+ AVCC CC I Inputleakagecurrent 0V≤Ve ≤V V =2.2V,3V ±1 µA VREF–/VeREF– REF– AVCC CC (1) Theexternalreferenceisusedduringconversiontochargeanddischargethecapacitancearray.Theinputcapacitance,C,isalsothe I dynamicloadforanexternalreferenceduringconversion.Thedynamicimpedanceofthereferencesupplyshouldfollowthe recommendationsonanalog-sourceimpedancetoallowthechargetosettlefor12-bitaccuracy. (2) Theaccuracylimitstheminimumpositiveexternalreferencevoltage.Lowerreferencevoltagelevelsmaybeappliedwithreduced accuracyrequirements. (3) Theaccuracylimitsthemaximumnegativeexternalreferencevoltage.Higherreferencevoltagelevelsmaybeappliedwithreduced accuracyrequirements. (4) Theaccuracylimitsminimumexternaldifferentialreferencevoltage.Lowerdifferentialreferencevoltagelevelsmaybeappliedwith reducedaccuracyrequirements. 34 Specifications Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 5.29 12-Bit ADC, Built-In Reference overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT REF2_5V=1for2.5V, V =3V 2.4 2.5 2.6 Positivebuiltinreferencevoltage IVREF+max≤IVREF+≤IVREF+min CC V V REF+ output REF2_5V=0for1.5V, V =2.2V,3V 1.44 1.5 1.56 I max≤I ≤I min CC VREF+ VREF+ VREF+ REF2_5V=0,I max≤I ≤I min 2.2 VREF+ VREF+ VREF+ AV minimumvoltage,Positive AV CC REF2_5V=1,I min≥I ≥–0.5mA 2.8 V CC(min) builtinreferenceactive VREF+ VREF+ REF2_5V=1,I min≥I ≥–1mA 2.9 VREF+ VREF+ I LoadcurrentoutofVREF+ VCC=2.2V 0.01 –0.5 mA VREF+ terminal V =3V 0.01 –1 CC I =500µA±100µA, V =2.2V ±2 VREF+ CC Analoginputvoltage≈0.75V, Load-currentregulation,V REF2_5V=0 VCC=3V ±2 I REF+ LSB L(VREF+) terminal I =500µA±100µA, VREF+ Analoginputvoltage≈1.25V, V =3V ±2 CC REF2_5V=1 I =100µA→900µA, Loadcurrentregulation,VREF+ VREF+ I C =5µF,Ax≈0.5×V , V =3V 20 ns DL(VREF+) terminal VREF+ REF+ CC Errorofconversionresult≤1LSB C CapacitanceatpinV (1) REFON=1, V =2.2V,3V 5 10 µF VREF+ REF+ 0mA≤I ≤I max CC VREF+ VREF+ Temperaturecoefficientofbuilt- I isaconstantintherangeof T VREF+ V =2.2V,3V ±100 ppm/°C REF+ inreference 0mA≤I ≤1mA CC VREF+ Settlingtimeofinternalreference I =0.5mA,C =10µF, tREFON voltage(seeFigure5-23) (2) VVREF+=1.5V,V VRE=F+2.2V 17 ms REF+ AVCC (1) Theinternalbufferoperationalamplifierandtheaccuracyspecificationsrequireanexternalcapacitor.AllINLandDNLtestsusestwo capacitorsbetweenpinsV andAV andV /Ve andAV :10-µFtantalumand100-nFceramic. REF+ SS REF-– REF– SS (2) Theconditionisthattheerrorinaconversionstartedaftert islessthan±0.5LSB.Thesettlingtimedependsontheexternal REFON capacitiveload. C VREF+ 100 mF t ».66 x C [ms] with C inmF 10mF REFON VREF+ VREF+ 1mF 0 1 ms 10 ms 100 ms t REFON Figure5-23.TypicalSettlingTimeofInternalReferencet vsExternalCapacitoronV REFON REF+ Copyright©2006–2020,TexasInstrumentsIncorporated Specifications 35 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com From DV CC1/2 Power + Supply - DV SS1/2 10mF 100nF AV + CC MSP430FG461x - AV SS 10 mF 100nF Apply External Reference [V ] eREF+ or Use Internal Reference [VREF+] + VREF+or VeREF+ - 10 mF 100nF Apply External + VREF-/VeREF- Reference - 10 mF 100nF Figure5-24.SupplyVoltageandReferenceVoltageDesignV /Ve ExternalSupply REF– REF– From DV CC1/2 Power + Supply - DV SS1/2 10 mF 100nF AV + CC MSP430FG461x - AV SS 10 mF 100 nF Apply External Reference [V ] eREF+ or Use Internal Reference [VREF+] + VREF+or VeREF+ - 10 mF 100nF Reference Is Internally V /V REF- eREF- Switched toAV SS Figure5-25.SupplyVoltageandReferenceVoltageDesignV /Ve =AV ,InternallyConnected REF– REF– SS 36 Specifications Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 5.30 12-Bit ADC, Timing Parameters overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC ForspecifiedperformanceofADC12 f 2.2V,3V 0.45 5 6.3 MHz ADC12CLK linearityparameters InternalADC12 ADC12DIV=0, f 2.2V,3V 3.7 5 6.3 MHz ADC12OSC oscillator f =f ADC12CLK ADC12OSC C ≥5µF,Internaloscillator, VREF+ 2.2V,3V 2.06 3.51 f =3.7MHzto6.3MHz ADC12OSC tCONVERT Conversiontime ExternalfADC12CLKfromACLK,MCLK,or 13×ADC12DIV µs SMCLK, ×1/f ADC12SSEL≠0 ADC12CLK t Turnonsettlingtime (1) 100 ns ADC12ON oftheADC R =400Ω,R =1000Ω, 3V 1220 tSample Samplingtime CSI=30pF,τ=I[RS+RI]×CI (2) 2.2V 1400 ns (1) Theconditionisthattheerrorinaconversionstartedaftert islessthan±0.5LSB.Thereferenceandinputsignalarealready ADC12ON settled. (2) ApproximatelytenTau(τ)areneededtogetanerroroflessthan±0.5LSB: t =ln(2n+1)×(R +R)xC+800nswheren=ADCresolution=12,R =externalsourceresistance. Sample S I I S 5.31 12-Bit ADC, Linearity Parameters overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC Integrallinearity 1.4V≤(VeREF+–VREF–/VeREF–)min≤1.6V ±2 E 2.2V,3V LSB I error 1.6V<(Ve –V /Ve )min≤[V ] ±1.7 REF+ REF– REF– AVCC Differentiallinearity (Ve –V /Ve )min≤(Ve –V /Ve ), E REF+ REF– REF– REF+ REF– REF– 2.2V,3V ±1 LSB D error C =10µF(tantalum)and100nF(ceramic) VREF+ (Ve –V /Ve )min≤(Ve –V /Ve ), REF+ REF– REF– REF+ REF– REF– E Offseterror InternalimpedanceofsourceRS<100Ω, 2.2V,3V ±2 ±4 LSB O C =10µF(tantalum)and100nF(ceramic) VREF+ (Ve –V /Ve )min≤(Ve –V /Ve ), E Gainerror REF+ REF– REF– REF+ REF– REF– 2.2V,3V ±1.1 ±2 LSB G C =10µF(tantalum)and100nF(ceramic) VREF+ Totalunadjusted (Ve -–V /Ve )min≤(Ve –V /Ve ), E REF+ REF– REF– REF+ REF– REF– 2.2V,3V ±2 ±5 LSB T error CVREF+=10µF(tantalum)and100nF(ceramic) Copyright©2006–2020,TexasInstrumentsIncorporated Specifications 37 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 5.32 12-Bit ADC, Temperature Sensor and Built-In V MID overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC Operatingsupplycurrent REFON=0,INCH=0Ah, 2.2V 40 120 ISENSOR intoAVCCterminal(1) ADC12ON=N/A,TA=25°C 3V 60 160 µA V (2) ADC12ON=1,INCH=0Ah, 2.2V,3V 986 mV SENSOR T =0°C A TC ADC12ON=1,INCH=0Ah 2.2V,3V 3.55±3% mV/°C SENSOR Sampletimerequiredif ADC12ON=1,INCH=0Ah, 2.2V 30 tSENSOR(sample) channel10isselected(3) Errorofconversionresult≤1LSB 3V 30 µs Currentintodividerat 2.2V N/A(4) IVMID channel11(4) ADC12ON=1,INCH=0Bh 3V N/A(4) µA ADC12ON=1,INCH=0Bh, 2.2V 1.1 1.1±0.04 V AV divideratchannel11 V MID CC VMID≈0.5×VAVCC 3V 1.5 1.50±0.04 Sampletimerequiredif ADC12ON=1,INCH=0Bh, 2.2V 1400 tVMID(sample) channel11isselected(5) Errorofconversionresult≤1LSB 3V 1220 ns (1) ThesensorcurrentI isconsumedif(ADC12ON=1andREFON=1),or(ADC12ON=1ANDINCH=0Ahandsamplesignalis SENSOR high).WhenREFON=1,I isalreadyincludedinI . SENSOR REF+ (2) Thetemperaturesensoroffsetcanbeasmuchas±20°C.TIrecommendsasingle-pointcalibrationtominimizetheoffseterrorofthe built-intemperaturesensor. (3) Thetypicalequivalentimpedanceofthesensoris51kΩ.Thesampletimerequiredincludesthesensor-ontimet SENSOR(on) (4) Noadditionalcurrentisneeded.TheV isusedduringsampling. MID (5) Theon-timet isincludedinthesamplingtimet ;noadditionalontimeisneeded. VMID(on) VMID(sample) 5.33 12-Bit DAC, Supply Specifications overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC AV Analogsupplyvoltage AV =DV ,AV =DV =0V 2.20 3.60 V CC CC CC SS SS DAC12AMPx=2,DAC12IR=0, 50 110 DAC12_xDAT=0800h DAC12AMPx=2,DAC12IR=1, DAC12_xDAT=0800h, 50 110 Ve =V =AV REF+ REF+ CC Supplycurrent,singleDAC IDD channel(1) (2) DAC12AMPx=5,DAC12IR=1, 2.2V,3V µA DAC12_xDAT=0800h, 200 440 Ve =V =AV REF+ REF+ CC DAC12AMPx=7,DAC12IR=1, DAC12_xDAT=0800h, 700 1500 Ve =V =AV REF+ REF+ CC DAC12_xDAT=800h,V =1.5V, REF 2.2V Power-supplyrejection ΔAVCC=100mV PSRR ratio(3)(4) DAC12_×DAT=800h,V =1.5Vor2.5V, 70 dB REF 3V ΔAV =100mV CC (1) Noloadattheoutputpin,DAC12_0orDAC12_1,assumingthatthecontrolbitsforthesharedpinsaresetproperly. (2) Currentintoreferenceterminalsnotincluded.IfDAC12IR=1currentflowsthroughtheinputdivider;seeReferenceInputspecifications. (3) PSRR=20×log{ΔAV /ΔV }. CC DAC12_xOUT (4) V isappliedexternally.Theinternalreferenceisnotused. REF 38 Specifications Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 5.34 12-Bit DAC, Linearity Specifications overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(seeFigure5-26) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC Resolution 12-bitmonotonic 12 bits V =1.5V, ref 2.2V DAC12AMPx=7,DAC12IR=1 INL Integralnonlinearity(1) ±2.0 ±8.0 LSB V =2.5V, ref 3V DAC12AMPx=7,DAC12IR=1 V =1.5V, ref 2.2V DAC12AMPx=7,DAC12IR=1 DNL Differentialnonlinearity(1) ±0.4 ±1.0 LSB V =2.5V, ref 3V DAC12AMPx=7,DAC12IR=1 V =1.5V, ref 2.2V DAC12AMPx=7,DAC12IR=1 Offsetvoltagewithoutcalibration(1) (2) ±21 V =2.5V, ref 3V DAC12AMPx=7,DAC12IR=1 E mV O V =1.5V, ref 2.2V DAC12AMPx=7,DAC12IR=1 Offsetvoltagewithcalibration(1) (2) ±2.5 V =2.5V, ref 3V DAC12AMPx=7,DAC12IR=1 d /d Offseterrortemperaturecoefficient(1) 2.2V,3V ±30 µV/°C E(O) T V =1.5V 2.2V E Gainerror(1) REF ±3.5 %FSR G V =2.5V 3V REF d /d Gaintemperaturecoefficient(1) 2.2V,3V 10 ppmof E(G) T FSR/°C DAC12AMPx=2 100 t Timeforoffsetcalibration(3) DAC12AMPx=3,5 2.2V,3V 32 ms Offset_Cal DAC12AMPx=4,6,7 6 (1) Parameterscalculatedfromthebest-fitcurvefrom0x0Ato0xFFF.Thebest-fitcurvemethodisusedtodelivercoefficients“a”and“b”of thefirstorderequation:y=a+b×x.V =E +(1+E )×(Ve /4095)×DAC12_xDAT,DAC12IR=1. DAC12_xOUT O G REF+ (2) Theoffsetcalibrationworksontheoutputoperationalamplifier.OffsetcalibrationistriggeredbysettingbitDAC12CALON. (3) TheoffsetcalibrationcanbedoneifDAC12AMPx={2,3,4,5,6,7}.TheoutputoperationalamplifierisswitchedoffwithDAC12AMPx= {0,1}.TIrecommendsthattheDAC12modulebeconfiguredbeforeinitiatingcalibration.Portactivityduringcalibrationmayeffect accuracyandisnotrecommended. DAC VOUT DAC Output RLoad = VR+ Ideal transfer AVCC function 2 Offset Error Gain Error CLoad = 100pF Positive Negative DAC Code Figure5-26.LinearityTestLoadConditionsandGainandOffsetDefinition Copyright©2006–2020,TexasInstrumentsIncorporated Specifications 39 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 4 V = 2.2 V, V = 1.5 V CC REF B 3 DAC12AMPx = 7 S DAC12IR = 1 L – r 2 o r r E y 1 rit a e n 0 nli o N al -1 r g e nt -2 I – L N -3 I -4 0 512 1024 1536 2048 2560 3072 3584 4095 DAC12_xDAT–Digital Code Figure5-27.TypicalINLErrorvsDigitalInputData 2.0 V = 2.2 V, V = 1/.5 V B CC REF S 1.5 DAC12AMPx = 7 L r - DAC12IR = 1 o 1.0 r r E y rit 0.5 a e n nli 0.0 o N ntial -0.5 e r e Diff -1.0 - L N -1.5 D -2.0 0 512 1024 1536 2048 2560 3072 3584 4095 DAC12_xDAT - Digital Code Figure5-28.TypicalDNLErrorvsDigitalInputData 40 Specifications Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 5.35 12-Bit DAC, Output Specifications overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC Noload,Ve =AV , REF+ CC DAC12_xDAT=0h,DAC12IR=1, 0 0.005 DAC12AMPx=7 Noload,Ve =AV , REF+ CC AV – DAC12_xDAT=0FFFh,DAC12IR=1, CC AV 0.05 CC Outputvoltagerange(see DAC12AMPx=7 VO Figure5-29)(1) R =3kΩ,Ve =AV , 2.2V,3V V Load REF+ CC DAC12_xDAT=0h,DAC12IR=1, 0 0.1 DAC12AMPx=7 R =3kΩ,Ve =AV , Load REF+ CC AV – DAC12_xDAT=0FFFh,DAC12IR=1, CC AV 0.13 CC DAC12AMPx=7 MaxDAC12load C 2.2V,3V 100 pF L(DAC12) capacitance 2.2V –0.5 +0.5 I MaxDAC12loadcurrent mA L(DAC12) 3V –1.0 +1.0 R =3kΩ,V <0.3V, Load O/P(DAC12) 150 250 DAC12AMPx=2,DAC12_xDAT=0h R =3kΩ, Outputresistance(see Load R V >AV –0.3V, 2.2V,3V 150 250 Ω O/P(DAC12) Figure5-29) O/P(DAC12) CC DAC12_xDAT=0FFFh R =3kΩ, Load 1 4 0.3V≤V ≤AV –0.3V O/P(DAC12) CC (1) Dataisvalidaftertheoffsetcalibrationoftheoutputamplifier. RO/P(DAC12_x) Max ILoad RLoad AVCC DAC12 2 O/P(DAC12_x) CLoad= 100pF Min 0.3 AVCC-0.3V VOUT AVCC Figure5-29.DAC12_xOutputResistanceTests 5.36 12-Bit DAC, Reference Input Specifications overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC Referenceinputvoltage DAC12IR=0(1) (2) AVCC/3 AVCC+0.2 Ve 2.2V,3V V REF+ range DAC12IR=1(3) (4) AV AV +0.2 CC CC DAC12_0IR=DAC12_1IR=0 20 MΩ DAC12_0IR=1,DAC12_1IR=0 40 48 56 Ri(VREF+), Referenceinputresistance DAC12_0IR=0,DAC12_1IR=1 2.2V,3V (Ri(VeREF+) kΩ DAC12_0IR=DAC12_1IR=1, DAC12_0SREFx=DAC12_1 20 24 28 SREFx(5) (1) Forafull-scaleoutput,thereferenceinputvoltagecanbeashighas1/3ofthemaximumoutputvoltageswing(AV ). CC (2) ThemaximumvoltageappliedatreferenceinputvoltageterminalVe =[AV –V ]/[3×(1+E )]. REF+ CC E(O) G (3) Forafull-scaleoutput,thereferenceinputvoltagecanbeashighasthemaximumoutputvoltageswing(AV ). CC (4) ThemaximumvoltageappliedatreferenceinputvoltageterminalVe =[AV –V ]/(1+E ). REF+ CC E(O) G (5) WhenDAC12IR=1andDAC12SREFx=0or1forbothchannels,thereferenceinputresistivedividersforeachDACareinparallel reducingthereferenceinputresistance. Copyright©2006–2020,TexasInstrumentsIncorporated Specifications 41 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 5.37 12-Bit DAC, Dynamic Specifications V =V ,DAC12IR=1,overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwise ref CC noted)(seeFigure5-30andFigure5-31) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC DAC12AMPx=0→{2,3,4} 60 120 DAC12_xDAT=800h, t DAC12ontime Error <±0.5LSB(1) DAC12AMPx=0→{5,6} 2.2V,3V 15 30 µs ON V(O) (seeFigure5-30) DAC12AMPx=0→7 6 12 DAC12AMPx=2 100 200 DAC12_xDAT= t Settlingtime,fullscale DAC12AMPx=3,5 2.2V,3V 40 80 µs S(FS) 80h→F7Fh→80h DAC12AMPx=4,6,7 15 30 DAC12AMPx=2 5 DAC12_xDAT= t Settlingtime,codetocode 3F8h→408h→3F8h DAC12AMPx=3,5 2.2V,3V 2 µs S(C–C) BF8h→C08h→BF8h DAC12AMPx=4,6,7 1 DAC12AMPx=2 0.05 0.12 DAC12_xDAT= SR Slewrate 80h→F7Fh→80h(2) DAC12AMPx=3,5 2.2V,3V 0.35 0.7 V/µs DAC12AMPx=4,6,7 1.5 2.7 DAC12AMPx=2 600 DAC12_xDAT= Glitchenergy,full-scale DAC12AMPx=3,5 2.2V,3V 150 nV-s 80h→F7Fh→80h DAC12AMPx=4,6,7 30 (1) R andC connectedtoAV (notAV /2)inFigure5-30. Load Load SS CC (2) Slewrateappliestooutputvoltagesteps≥200mV. Conversion 1 Conversion 2 Conversion 3 DAC Output VOUT Glitch +/- 1/2 LSB RLoad= 3 kW Energy ILoad AVCC 2 +/- 1/2 LSB CLoad = 100pF RO/P(DAC12.x) tsettleLH tsettleHL Figure5-30.SettlingTimeandGlitchEnergyTesting Conversion 1 Conversion 2 Conversion 3 VOUT 90% 90% 10% 10% tSRLH tSRHL Figure5-31.SlewRateTesting 42 Specifications Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 5.38 12-Bit DAC, Dynamic Specifications Continued T =25°C(unlessotherwisenoted) A PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC DAC12AMPx={2,3,4},DAC12SREFx=2, 40 DAC12IR=1,DAC12_xDAT=800h 3-dBbandwidth, DAC12AMPx={5,6},DAC12SREFx=2, BW V =1.5V,V =0.1VPP 2.2V,3V 180 kHz –3dB DC AC DAC12IR=1,DAC12_xDAT=800h (seeFigure5-32) DAC12AMPx=7,DAC12SREFx=2, 550 DAC12IR=1,DAC12_xDAT=800h DAC12_0DAT=800h,NoLoad, DAC12_1DAT=80h↔F7Fh,R =3kΩ –80 Load Channel-to-channel f =10kHzat50/50dutycycle DAC12_1OUT crosstalk 2.2V,3V dB (seeFigure5-33)(1) DAC12_0DAT=80h↔F7Fh,RLoad=3kΩ, DAC12_1DAT=800h,NoLoad, –80 f =10kHzat50/50dutycycle DAC12_0OUT (1) R =3kΩ,C =100pF LOAD LOAD RLoad= 3 kW ILoad Ve REF+ AV DAC12_x CC DACx 2 AC CLoad= 100pF DC Figure5-32.TestConditionsfor3-dBBandwidthSpecification RLoad ILoad DAC12_0 AVCC DAC12_xDAT 080h F7Fh 080h F7Fh 080h DAC0 2 VOUT CLoad= 100 pF VREF+ VDAC12_yOUT RLoad ILoad DAC12_1 AVCC VDAC12_xOUT 2 1/f DAC1 Toggle CLoad= 100 pF Figure5-33.CrosstalkTestConditions Copyright©2006–2020,TexasInstrumentsIncorporated Specifications 43 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 5.39 Operational Amplifier OA, Supply Specifications overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC V Supplyvoltage 2.2 3.6 V CC FastMode,OARRIP=1(rail-to-railmodeoff) 180 290 MediumMode,OARRIP=1(rail-to-railmodeoff) 110 190 SlowMode,OARRIP=1(rail-to-railmodeoff) 50 80 I Supplycurrent(1) 2.2V,3V µA CC FastMode,OARRIP=0(rail-to-railmodeon) 300 490 MediumMode,OARRIP=0(rail-to-railmodeon) 190 350 SlowMode,OARRIP=0(rail-to-railmodeon) 90 190 PSRR Powersupplyrejectionratio Noninverting 2.2V,3V 70 dB (1) P6SEL.x=1foreachcorrespondingpinwhenusedinOAinputorOAoutputmode. 5.40 Operational Amplifier OA, Input/Output Specifications overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC OARRIP=1(rail-to-railmodeoff) –0.1 V –1.2 CC V Voltagesupply,I/P V I/P OARRIP=0(rail-to-railmodeon) –0.1 V +0.1 CC T =–40to+55°C –5 ±0.5 5 I Inputleakagecurrent,I/P(1) (2) A nA Ikg T =+55to+85°C –20 ±5 20 A FastMode 50 MediumMode f =1kHz 80 V(I/P) SlowMode 140 V Voltagenoisedensity,I/P nV/√HZ n FastMode 30 MediumMode f =10kHz 50 V(I/P) SlowMode 65 V Offsetvoltage,I/P 2.2V,3V ±10 mV IO Offsettemperaturedrift,I/P (3) 2.2V,3V ±10 µV/°C Offsetvoltagedriftwithsupply, 0.3V≤V ≤V –0.3V IN CC 2.2V,3V ±1.5 mV/V I/P ΔV ≤±10%,T =25°C CC A FastMode,I ≤–500µA 2.2V V –0.2 V SOURCE CC CC V High-leveloutputvoltage,O/P V OH SlowMode,I ≤–150µA 3V V –0.1 V SOURCE CC CC FastMode,I ≤+500µA 2.2V V 0.2 SOURCE SS V Low-leveloutputvoltage,O/P V OL SlowMode,I ≤+150µA 3V V 0.1 SOURCE SS R =3kΩ,C =50pF, Load Load OARRIP=0(rail-to-railmodeon), 150 250 V <0.2V O/P(OAx) R =3kΩ,C =50pF, Outputresistance(see Load Load RO/P(OAx) Figure5-34)(4) OARRIP=0(rail-to-railmodeon), 2.2V,3V 150 250 Ω V >AV –0.2V O/P(OAx) CC R =3kΩ,C =50pF, Load Load OARRIP=0(rail-to-railmodeon), 0.1 4 0.2V≤V ≤AV –0.2V O/P(OAx) CC CMRR Common-moderejectionratio Noninverting 2.2V,3V 70 dB (1) ESDdamagecandegradeinputcurrentleakage. (2) Theinputbiascurrentisoverriddenbytheinputleakagecurrent. (3) Calculatedusingtheboxmethod. (4) Specificationvalidforvoltage-followerOAxconfiguration. 44 Specifications Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 RO/P(OAx) Max ILoad RLoad AVCC OAx 2 O/P(OAx) CLoad Min 0.2V AVCC-0.2V AVCC VOUT Figure5-34.OAxOutputResistanceTests 5.41 Operational Amplifier OA, Dynamic Specifications overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC FastMode 1.2 SR Slewrate MediumMode 0.8 V/µs SlowMode 0.3 Open-loopvoltagegain 100 dB φm Phasemargin C =50pF 60 deg L Gainmargin C =50pF 20 dB L Noninverting,FastMode,R =47kΩ,C =50pF 2.2 Gain-bandwidthproduct L L GBW (seeFigure5-35and Noninverting,MediumMode,R =300kΩ,C =50pF 2.2V,3V 1.4 MHz L L Figure5-36) Noninverting,SlowMode,R =300kΩ,C =50pF 0.5 L L t Enabletimeon t ,Noninverting,Gain=1 2.2V,3V 10 20 µs en(on) on t Enabletimeoff 2.2V,3V 1 µs en(off) 5.42 Operational Amplifier OA, Typical Characteristics 140 0 120 Fast Mode 100 -50 80 Medium Mode Fast Mode 60 es B re -100 = d 40 deg ain 20 e - Medium Mode G s a -150 0 Slow Mode Ph Slow Mode -20 -40 -200 -60 -80 0.001 0.01 0.1 1 10 100 1000 10000 -250 1 10 100 1000 10000 Input Frequency - kHz Input Frequency - kHz Figure5-35.TypicalOpen-LoopGainvsFrequency Figure5-36.TypicalPhasevsFrequency Copyright©2006–2020,TexasInstrumentsIncorporated Specifications 45 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 5.43 Operational Amplifier OA Feedback Network, Noninverting Amplifier Mode (OAFCx = 4) overrecommendedoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC OAFBRx=0 0.996 1.00 1.002 OAFBRx=1 1.329 1.334 1.340 OAFBRx=2 1.987 2.001 2.016 OAFBRx=3 2.64 2.667 2.70 G Gain 2.2V,3V OAFBRx=4 3.93 4.00 4.06 OAFBRx=5 5.22 5.33 5.43 OAFBRx=6 7.76 7.97 8.18 OAFBRx=7 15.0 15.8 16.6 2.2V –60 THD Totalharmonicdistortionandnonlinearity Allgains dB 3V –70 t Settlingtime(1) Allpowermodes 2.2V,3V 7 12 µs Settle (1) ThesettlingtimespecifiesthetimeuntilanADCresultisstable.ThisincludestheminimumrequiredsamplingtimeoftheADC.The settlingtimeoftheamplifieritselfmightbefaster. 5.44 Operational Amplifier OA Feedback Network, Inverting Amplifier Mode (OAFCx = 6)(1) overrecommendedoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC OAFBRx=1 –0.371 –0.335 –0.298 OAFBRx=2 –1.031 –1.002 –0.972 OAFBRx=3 –1.727 –1.668 –1.609 G Gain OAFBRx=4 2.2V,3V –3.142 –3.00 –2.856 OAFBRx=5 –4.581 –4.33 –4.073 OAFBRx=6 –7.529 –6.97 –6.379 OAFBRx=7 –17.040 –14.8 –12.279 2.2V –60 THD Totalharmonicdistortionandnonlinearity Allgains dB 3V –70 t Settlingtime(2) Allpowermodes 2.2V,3V 7 12 µs Settle (1) ThisincludesthetwoOAconfiguration"invertingamplifierwithinputbuffer".BothOAsneedtobesettothesamepowermode,OAPMx. (2) ThesettlingtimespecifiesthetimeuntilanADCresultisstable.ThisincludestheminimumrequiredsamplingtimeoftheADC.The settlingtimeoftheamplifieritselfmightbefaster. 46 Specifications Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 5.45 Flash Memory (FG461x Devices Only) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) TEST PARAMETER V MIN TYP MAX UNIT CONDITIONS CC V Programanderasesupplyvoltage 2.7 3.6 V CC(PGM/ERASE) f Flashtiminggeneratorfrequency 257 476 kHz FTG I SupplycurrentfromDVCCduringprogram 2.7V,3.6V 3 5 mA PGM I SupplycurrentfromDVCCduringerase (1) 2.7V,3.6V 3 7 mA ERASE I SupplycurrentfromDVCCduringglobalmasserase (2) 2.7V,3.6V 6 14 mA GMERASE t Cumulativeprogramtime (3) 2.7V,3.6V 10 ms CPT t Cumulativemasserasetime 2.7V,3.6V 20 ms CMErase Programanderaseendurance 104 105 cycles t Dataretentionduration T =25°C 100 years Retention J t Wordorbyteprogramtime 30 Word t Blockprogramtimefor1stbyteorword 25 Block,0 t Blockprogramtimeforeachadditionalbyteorword 18 Block,1-63 t Blockprogramend-sequencewaittime (4) 6 t Block,End FTG t Masserasetime 10593 MassErase t Globalmasserasetime 10593 GlobalMassErase t Segmenterasetime 4819 SegErase (1) Lower64KBorupper64KBflashmemoryerased. (2) Allflashmemoryerased. (3) Thecumulativeprogramtimemustnotbeexceededduringablock-writeoperation.Thisparameterisonlyrelevantiftheblockwrite featureisused. (4) Thesevaluesarehardwiredintotheflashcontrollerstatemachine(t =1/f ). FTG FTG 5.46 JTAG Interface overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 2.2V 0 5 f TCKinputfrequency (1) MHz TCK 3V 0 10 R InternalpullupresistanceonTMS,TCK,TDI/TCLK (2) 2.2V,3V 25 60 90 kΩ Internal (1) f mayberestrictedtomeetthetimingrequirementsofthemoduleselected. TCK (2) TMS,TDI/TCLK,andTCKpullupresistorsareimplementedinallversions. 5.47 JTAG Fuse(1) overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT V Supplyvoltageduringfuse-blowcondition T =25°C 2.5 V CC(FB) A V VoltagelevelonTDI/TCLKforfuse-blow(FG461x) 6 7 V FB I SupplycurrentintoTDI/TCLKduringfuseblow 100 mA FB t Timetoblowfuse 1 ms FB (1) Afterthefuseisblown,nofurtheraccesstotheMSP430JTAG/Testandemulationfeaturesispossible.TheJTAGblockisswitchedto bypassmode. Copyright©2006–2020,TexasInstrumentsIncorporated Specifications 47 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6 Detailed Description 6.1 CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with sevenaddressingmodesforsourceoperandandfouraddressingmodesfordestinationoperand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to- registeroperationexecutiontimeisonecycleoftheCPUclock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constantgenerator,respectively.Theremainingregistersaregeneral-purposeregisters. PeripheralsareconnectedtotheCPUusingdata,address,andcontrolbuses,and can be handled with all instructions. The MSP430xG461x device family uses the MSP430X CPU and is completely backwards compatible with the MSP430 CPU. For a complete description of the MSP430X CPU, refer to the MSP430x4xx Family User’sGuide(SLAU056). Program Counter PC/R0 Stack Pointer SP/R1 Status Register SR/CG1/R2 Constant Generator CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 48 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.2 Instruction Set The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Table 6-1 shows examples of the three types of instruction formats; the address modes are listedinTable6-2. Table6-1.InstructionWordFormats FORMAT EXAMPLE OPERATION Dualoperands,source-destination ADDR4,R5 R4+R5→R5 Singleoperands,destinationonly CALLR8 PC→(TOS),R8→PC Relativejump,un/conditional JNE Jump-on-equalbit=0 Table6-2.AddressModeDescriptions ADDRESSMODE S(1) D(1) SYNTAX EXAMPLE OPERATION Register • • MOVRs,Rd MOVR10,R11 R10→R11 Indexed • • MOVX(Rn),Y(Rm) MOV2(R5),6(R6) M(2+R5)→M(6+R6) Symbolic(PCrelative) • • MOVEDE,TONI M(EDE)→M(TONI) Absolute • • MOV&MEM,&TCDAT M(MEM)→M(TCDAT) Indirect • MOV@Rn,Y(Rm) MOV@R10,Tab(R6) M(R10)→M(Tab+R6) M(R10)→R11 Indirectautoincrement • MOV@Rn+,Rm MOV@R10+,R11 R10+2→R10 Immediate • MOV#X,TONI MOV#45,TONI #45→M(TONI) (1) NOTE:S=sourceD=destination Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 49 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.3 Operating Modes These devices have one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restorebacktothelow-powermodeonreturnfromtheinterruptprogram. Thefollowingsixoperatingmodescanbeconfiguredbysoftware: • Activemode(AM) – Allclocksareactive • Low-powermode0(LPM0) – CPUisdisabled – ACLKandSMCLKremainactive.MCLKisdisabled – FLL+loopcontrolremainsactive • Low-powermode1(LPM1) – CPUisdisabled – FLL+loopcontrolisdisabled – ACLKandSMCLKremainactive.MCLKisdisabled • Low-powermode2(LPM2) – CPUisdisabled – MCLK,FLL+loopcontrolandDCOCLKaredisabled – DCODCgeneratorremainsenabled – ACLKremainsactive • Low-powermode3(LPM3) – CPUisdisabled – MCLK,FLL+loopcontrol,andDCOCLKaredisabled – DCODCgeneratorisdisabled – ACLKremainsactive • Low-powermode4(LPM4) – CPUisdisabled – ACLKisdisabled – MCLK,FLL+loopcontrol,andDCOCLKaredisabled – DCODCgeneratorisdisabled – Crystaloscillatorisstopped 50 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.4 Interrupt Vector Addresses The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FFC0h. The vectorcontainsthe16-bitaddressoftheappropriateinterrupt-handlerinstructionsequence. Table6-3.InterruptSources,Flags,andVectors SYSTEM WORD INTERRUPTSOURCE INTERRUPTFLAG PRIORITY INTERRUPT ADDRESS Power-Up ExternalReset WDTIFG Watchdog KEYV (1) (2) Reset 0FFFEh 31,highest FlashMemory NMI NMIIFG (1) (3) (Non)maskable OscillatorFault OFIFG(1) (3) (Non)maskable 0FFFCh 30 FlashMemoryAccessViolation ACCVIFG(1) (4)(2) (Non)maskable Timer_B7 TBCCR0CCIFG0(4) Maskable 0FFFAh 29 TBCCR1CCIFG1toTBCCR6CCIFG6, Timer_B7 TBIFG(1)(4) Maskable 0FFF8h 28 Comparator_A CAIFG Maskable 0FFF6h 27 WatchdogTimer+ WDTIFG Maskable 0FFF4h 26 USCI_A0,USCI_B0Receive UCA0RXIFG,UCB0RXIFG(1) Maskable 0FFF2h 25 USCI_A0,USCI_B0Transmit UCA0TXIFG,UCB0TXIFG (1) Maskable 0FFF0h 24 ADC12 ADC12IFG (1) (4) Maskable 0FFEEh 23 Timer_A3 TACCR0CCIFG0(4) Maskable 0FFECh 22 TACCR1CCIFG1andTACCR2CCIFG2, Timer_A3 TAIFG(1) (4) Maskable 0FFEAh 21 I/OPortP1(EightFlags) P1IFG.0toP1IFG.7(1) (4) Maskable 0FFE8h 20 USART1Receive URXIFG1 Maskable 0FFE6h 19 USART1Transmit UTXIFG1 Maskable 0FFE4h 18 I/OPortP2(EightFlags) P2IFG.0toP2IFG.7 (1) (4) Maskable 0FFE2h 17 BasicTimer1,RTC BTIFG Maskable 0FFE0h 16 DMA DMA0IFG,DMA1IFG,DMA2IFG(1) (4) Maskable 0FFDEh 15 DAC12 DAC12.0IFG,DAC12.1IFG(1) (4) Maskable 0FFDCh 14 0FFDAh 13 Reserved Reserved(5) ⋮ ⋮ 0FFC0h 0,lowest (1) Multiplesourceflags (2) Accessandkeyviolations,KEYVandACCVIFG,onlyapplicabletoFGdevices. (3) AresetisgeneratediftheCPUtriestofetchinstructionsfromwithinthemoduleregistermemoryaddressrange(0hto01FFh). (Non)maskable:theindividualinterrupt-enablebitcandisableaninterruptevent,butthegeneral-interruptenablecannotdisableit. (4) Interruptflagsarelocatedinthemodule. (5) Theinterruptvectorsataddresses0FFDAhto0FFC0harenotusedinthisdeviceandcanbeusedforregularprogramcodeif necessary. Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 51 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.5 Special Function Registers (SFRs) The MSP430 SFRs are in the lowest address space and are organized as byte mode registers. SFRs shouldbeaccessedwithbyteinstructions. Legend rw Bitcanbereadandwritten. rw-0,rw-1 Bitcanbereadandwritten.ItisResetorSetbyPUC. rw-(0),rw-(1) Bitcanbereadandwritten.ItisResetorSetbyPOR. SFRbitisnotpresentindevice 6.5.1 Interrupt Enable 1 and 2 Address 7 6 5 4 3 2 1 0 0h ACCVIE NMIIE OFIE WDTIE rw*0 rw*0 rw*0 rw*0 WDTIE Watchdogtimerinterruptenable.Inactiveifwatchdogmodeisselected. Activeifwatchdogtimerisconfiguredasageneral-purposetimer. OFIE Oscillatorfault-interruptenable NMIIE Nonmaskableinterruptenable ACCVIE Flashaccessviolationinterruptenable Address 7 6 5 4 3 2 1 0 01h BTIE UTXIE1 URXIE1 UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw*0 rw*0 rw*0 rw*0 rw*0 rw*0 rw*0 UCA0RXIE USCI_A0receive-interruptenable UCA0TXIE USCI_A0transmit-interruptenable UCB0RXIE USCI_B0receive-interruptenable UCB0TXIE USCI_B0transmit-interruptenable URXIE1 USART1UARTandSPIreceive-interruptenable UTXIE1 USART1UARTandSPItransmit-interruptenable BTIE Basictimerinterruptenable 52 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.5.2 Interrupt Flag Register 1 and 2 Address 7 6 5 4 3 2 1 0 02h NMIIFG OFIFG WDTIFG rw*0 rw*1 rw*(0) WDTIFG Setonwatchdogtimeroverflow(inwatchdogmode)orsecuritykeyviolation ResetonV power-onoraresetconditionatthe RST/NMIpininresetmode CC OFIFG Flagsetonoscillatorfault NMIIFG SetbytheRST/NMIpin Address 7 6 5 4 3 2 1 0 03h BTIFG UTXIFG1 URXIFG1 UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG rw*0 rw*1 rw*0 rw*0 rw*0 rw*0 rw*0 UCA0RXIFG USCI_A0receive-interruptflag UCA0TXIFG USCI_A0transmit-interruptflag UCB0RXIFG USCI_B0receive-interruptflag UCB0TXIFG USCI_B0transmit-interruptflag URXIFG0 USART1:UARTandSPIreceiveflag UTXIFG0 USART1:UARTandSPItransmitflag BTIFG Basictimerflag 6.5.3 Module Enable Registers 1 and 2 Address 7 6 5 4 3 2 1 0 04h URXE1 USART1:UARTmodereceiveenable UTXE1 USART1:UARTmodetransmitenable USPIE1 USART1:SPImodetransmitandreceiveenable Address 7 6 5 4 3 2 1 0 UTXE1 URXE1 05h USPIE1 rw*0 rw*0 URXE1 USART1:UARTmodereceiveenable UTXE1 USART1:UARTmodetransmitenable USPIE1 USART1:SPImodetransmitandreceiveenable Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 53 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.6 Memory Organization Table 6-4 summarizes the memory organization for the FG461x devices, and Table 6-5 summarizes the memoryorganizationfortheCG461xdevices. Table6-4.MSP430FG461xMemoryOrganization MSP430FG4616 MSP430FG4617 MSP430FG4618 MSP430FG4619 Memory Size 92KB 92KB 116KB 120KB Main:interruptvector Flash 0FFFFh-0FFC0h 0FFFFh-0FFC0h 0FFFFh-0FFC0h 0FFFFh-0FFC0h Main:codememory Flash 018FFFh-002100h 019FFFh-003100h 01FFFFh-003100h 01FFFFh-002100h RAM Total Size 4KB 8KB 8KB 4KB 020FFh-01100h 030FFh-01100h 030FFh-01100h 020FFh-01100h Extended Size 2KB 6KB 6KB 2KB 020FFh-01900h 030FFh-01900h 030FFh-01900h 020FFh-01900h Mirrored Size 2KB 2KB 2KB 2KB 018FFh-01100h 018FFh-01100h 018FFh-01100h 018FFh-01100h Informationmemory Size 256Byte 256Byte 256Byte 256Byte Flash 010FFh-01000h 010FFh-01000h 010FFh-01000h 010FFh-01000h Bootmemory Size 1KB 1KB 1KB 1KB ROM 0FFFh-0C00h 0FFFh-0C00h 0FFFh-0C00h 0FFFh-0C00h RAM Size 2KB 2KB 2KB 2KB (Mirroredat018FFh- 09FFh-0200h 09FFh-0200h 09FFh-0200h 09FFh-0200h 01100h) Peripherals 16bit 01FFh-0100h 01FFh-0100h 01FFh-0100h 01FFh-0100h 8bit 0FFh-010h 0FFh-010h 0FFh-010h 0FFh-010h 8-bitSFR 0Fh-00h 0Fh-00h 0Fh-00h 0Fh-00h Table6-5.MSP430CG461xMemoryOrganization MSP430CG4616 MSP430CG4617 MSP430CG4618 MSP430CG4619 Memory Size 92KB 92KB 116KB 120KB Main:interruptvector ROM 0FFFFh-0FFC0h 0FFFFh-0FFC0h 0FFFFh-0FFC0h 0FFFFh-0FFC0h Main:codememory ROM 018FFFh-002100h 019FFFh-003100h 01FFFFh-003100h 01FFFFh-002100h RAM Total Size 4KB 8KB 8KB 4KB 020FFh-01100h 030FFh-01100h 030FFh-01100h 020FFh-01100h Extended Size 2KB 6KB 6KB 2KB 020FFh-01900h 030FFh-01900h 030FFh-01900h 020FFh-01900h Mirrored Size 2KB 2KB 2KB 2KB 018FFh-01100h 018FFh-01100h 018FFh-01100h 018FFh-01100h Informationmemory Size 256Byte 256Byte 256Byte 256Byte ROM 010FFh-01000h 010FFh-01000h 010FFh-01000h 010FFh-01000h Bootmemory Size 1KB 1KB 1KB 1KB (OptionalonCG) ROM 0FFFh-0C00h 0FFFh-0C00h 0FFFh-0C00h 0FFFh-0C00h RAM Size 2KB 2KB 2KB 2KB (Mirroredat018FFh- 09FFh-0200h 09FFh-0200h 09FFh-0200h 09FFh-0200h 01100h) Peripherals 16bit 01FFh-0100h 01FFh-0100h 01FFh-0100h 01FFh-0100h 8bit 0FFh-010h 0FFh-010h 0FFh-010h 0FFh-010h 8-bitSFR 0Fh-00h 0Fh-00h 0Fh-00h 0Fh-00h 54 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.7 Bootstrap Loader (BSL) The BSL lets users program the flash memory or RAM using a UART serial interface. Access to the MCU memory through the BSL is protected by user-defined password. A bootstrap loader security key is provided at address 0FFBEh to disable the BSL completely or to disable the erasure of the flash if an invalid password is supplied. The BSL is optional for ROM-based devices. For complete description of the features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader(SLAA089). BSLKEY DESCRIPTION Erasureofflashdisabledifaninvalidpassword 00000h issupplied 0AA55h BSLdisabled anyothervalue BSLenabled BSLFUNCTION PZ,ZCA,ZQWPACKAGEPINS DataTransmit 87/A7–P1.0 DataReceiver 86/E7–P1.1 6.8 Flash Memory The flash memory can be programmed by the JTAG port, the bootstrap loader, or in system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memoryinclude: • Flash memory has n segments of main memory and two segments of information memory (A and B) of 128byteseach.Eachsegmentinmainmemoryis512bytesinsize. • Segments0tonmaybeerasedinonestep,oreachsegmentmaybeindividuallyerased. • Segments A and B can be erased individually, or as a group with segments 0-n. Segments A and B arealsocalledinformationmemory. • New devices may have some bytes programmed in the information memory (needed for test during manufacturing).Theusershouldperformaneraseoftheinformationmemorybeforethefirstuse. 6.9 Peripherals Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be handled using all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide. 6.9.1 DMA Controller The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without havingtoawakentomovedatatoorfromaperipheral. Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 55 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.9.2 Oscillator and System Clock The clock system in the MSP430xG461x family of devices is supported by the FLL+ module, which includes support for a 32768-Hz watch crystal oscillator, an internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turnon clock source and stabilizesinlessthan6 µs.TheFLL+moduleprovidesthefollowingclocksignals: • Auxiliaryclock(ACLK),sourcedfroma32768-Hzwatchcrystalorahigh-frequencycrystal • Mainclock(MCLK),thesystemclockusedbytheCPU • Submainclock(SMCLK),thesubsystemclockusedbytheperipheralmodules • ACLK/n,thebufferedoutputofACLK,ACLK/2,ACLK/4,orACLK/8 6.9.3 Brownout, Supply Voltage Supervisor (SVS) Thebrownoutcircuitprovidestheproper internal reset signal to the device during power-on and power-off. The SVS circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is notautomaticallyreset). The CPU begins code execution after the brownout circuit releases the device reset. However, V may CC not have ramped to V at that time. The user must make sure the default FLL+ settings are not CC(min) changed until V reaches V . If desired, the SVS circuit can be used to determine when V CC CC(min) CC reachesV . CC(min) 6.9.4 Digital I/O Thereareten8-bitI/Oportsimplemented—portsP1throughP10: • AllindividualI/Obitsareindependentlyprogrammable. • Anycombinationofinput,output,andinterruptconditionsispossible. • Edge-selectableinterruptinputcapabilityforalltheeightbitsofportsP1andP2. • Readandwriteaccesstoport-controlregistersissupportedbyallinstructions • PortsP7/P8andP9/P10canbeaccessedword-wiseasportsPAandPB,respectively. 6.9.5 Basic Timer1 and Real-Time Clock The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Basic Timer1 is extended to provide an integrated real- time clock (RTC). An internal calendar compensates for months with less than 31 days and includes leap- yearcorrection. 6.9.6 LCD_A Drive With Regulated Charge Pump The LCD_A driver generates the segment and common signals required to drive a segment LCD display. The LCD_A controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral. The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. Furthermore it is possible to control the level of the LCD voltage and, thus,contrastbysoftware. 6.9.7 Watchdog Timer (WDT+) The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interruptsatselectedtimeintervals. 56 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.9.8 Universal Serial Communication Interface (USCI) The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols like SPI (3-pin or 4-pin), I2C, and asynchronous communication protocols like UART,enhancedUARTwithautomaticbaudratedetection,andIrDA. TheUSCI_A0moduleprovidessupportforSPI(3-pinor4-pin),UART,enhancedUARTandIrDA. TheUSCI_B0moduleprovidessupportforSPI(3-pinor4-pin)andI2C. 6.9.9 USART1 The hardware universal synchronous/asynchronous receive transmit (USART) peripheral module is used for serial data communication. The USART supports synchronous SPI (3-pin or 4-pin) and asynchronous UARTcommunicationprotocols,usingdouble-bufferedtransmitandreceivechannels. 6.9.10 Hardware Multiplier The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16, 16×8, 8×16, and 8×8 bit operations. The module supports signed and unsigned multiplication as well as signed and unsigned multiply-and-accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles arerequired. 6.9.11 Timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compareregisters. Table6-6.Timer_A3SignalConnections OUTPUTPIN INPUTPINNUMBER DEVICEINPUT MODULEINPUT MODULEBLOCK MODULEOUT NUMBER SIGNAL NAME SIGNAL PZ,ZCA,ZQW PZ,ZCA,ZQW 82/B9-P1.5 TACLK TACLK ACLK ACLK Timer NA SMCLK SMCLK 82/B9-P1.5 TACLK INCLK 87/A7-P1.0 TA0 CCI0A 87/A7-P1.0 86/E7-P1.1 TA0 CCI0B CCR0 TA0 DV GND SS DV V CC CC 85/D7-P1.2 TA1 CCI1A 85/D7-P1.2 CAOUT(internal) CCI1B ADC12(internal) CCR1 TA1 DV GND SS DV V CC CC 79/A10-P2.0 TA2 CCI2A 79/A10-P2.0 ACLK(internal) CCI2B CCR2 TA2 DV GND SS DV V CC CC Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 57 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.9.12 Timer_B7 Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compareregisters. Table6-7.Timer_B7SignalConnections OUTPUTPIN INPUTPINNUMBER DEVICEINPUT MODULEINPUT MODULEBLOCK MODULEOUT NUMBER SIGNAL NAME SIGNAL PZ,ZCA,ZQW PZ,ZCA,ZQW 83/B8-P1.4 TBCLK TBCLK ACLK ACLK Timer NA SMCLK SMCLK 83/B8-P1.4 TBCLK INCLK 78/D8-P2.1 TB0 CCI0A 78/D8-P2.1 78/D8-P2.1 TB0 CCI0B ADC12(internal) CCR0CCR0 TB0TB0 DV GND SS DV V CC CC 77/E8-P2.2 TB1 CCI1A 77/E8-P2.2 77/E8-P2.2 TB1 CCI1B ADC12(internal) CCR1 TB1 DV GND SS DV V CC CC 76/A11-P2.3 TB2 CCI2A 76/A11-P2.3 76/A11-P2.3 TB2 CCI2B CCR2 TB2 DV GND SS DV V CC CC 67/E12-P3.4 TB3 CCI3A 67/E12-P3.4 67/E12-P3.4 TB3 CCI3B CCR3 TB3 DV GND SS DV V CC CC 66/G9-P3.5 TB4 CCI4A 66/G9-P3.5 66/G9-P3.5 TB4 CCI4B CCR4 TB4 DV GND SS DV V CC CC 65/F11-P3.6 TB5 CCI5A 65/F11-P3.6 65/F11-P3.6 TB5 CCI5B CCR5 TB5 DV GND SS DV V CC CC 64/F12-P3.7 TB6 CCI6A 64/F12-P3.7 ACLK(internal) CCI6B CCR6 TB6 DV GND SS DV V CC CC 58 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.9.13 Comparator_A The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,battery-voltagesupervision,andmonitoringofexternalanalogsignals. 6.9.14 ADC12 The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored withoutanyCPUintervention. 6.9.15 DAC12 The DAC12 module is a 12-bit R-ladder voltage-output DAC. The DAC12 can be used in 8-bit or 12-bit mode and can be used in conjunction with the DMA controller. When multiple DAC12 modules are present,theymaybegroupedtogetherforsynchronousoperation. 6.9.16 OA The MSP430xG461x has three configurable low-current general-purpose operational amplifiers. Each OA input and output terminal is software-selectable and offer a flexible choice of connections for various applications. The OA op amps primarily support front-end analog signal conditioning before analog-to- digitalconversion. Table6-8.OASignalConnections INPUTPIN OUTPUTPIN NUMBER DEVICEINPUT MODULEINPUT MODULEBLOCK MODULE DEVICEOUTPUT NUMBER SIGNAL NAME OUTPUTSIGNAL SIGNAL PZ PZ 95-P6.0 OA0I0 OA0I0 OA0O 96-P6.1 97-P6.2 OA0I1 OA0I1 OA0O ADC12(internal) DAC12_0OUT DAC12_0OUT OA0 OA0OUT (internal) DAC12_1OUT DAC12_1OUT (internal) 3-P6.4 OA1I0 OA1I0 OA1O 2-P6.3 13-P5.0 OA1I1 OA1I1 OA1O 13-P5.0 DAC12_0OUT DAC12_0OUT OA1 OA1OUT OA1O ADC12(internal) (internal) DAC12_1OUT DAC12_1OUT (internal) 5-P6.6 OA2I0 OA2I0 OA2O 4-P6.5 14-P10.7 OA2I1 OA2I1 OA2O 14-P10.7 DAC12_0OUT DAC12_0OUT OA2 OA2OUT OA2O ADC12(internal) (internal) DAC12_1OUT DAC12_1OUT (internal) Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 59 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.9.17 Peripheral File Map Table 6-9 lists the registers and addresses for peripherals with word access. Table 6-10 lists the registers andaddressesforperipheralswithbyteaccess. Table6-9.PeripheralsWithWordAccess MODULE REGISTERNAME ACRONYM ADDRESS Watchdog+ Watchdogtimercontrol WDTCTL 0120h Timer_B7 Capture/compareregister6 TBCCR6 019Eh Capture/compareregister5 TBCCR5 019Ch Capture/compareregister4 TBCCR4 019Ah Capture/compareregister3 TBCCR3 0198h Capture/compareregister2 TBCCR2 0196h Capture/compareregister1 TBCCR1 0194h Capture/compareregister0 TBCCR0 0192h Timer_Bregister TBR 0190h Capture/comparecontrol6 TBCCTL6 018Eh Capture/comparecontrol5 TBCCTL5 018Ch Capture/comparecontrol4 TBCCTL4 018Ah Capture/comparecontrol3 TBCCTL3 0188h Capture/comparecontrol2 TBCCTL2 0186h Capture/comparecontrol1 TBCCTL1 0184h Capture/comparecontrol0 TBCCTL0 0182h Timer_Bcontrol TBCTL 0180h Timer_Binterruptvector TBIV 011Eh Timer_A3 Capture/compareregister2 TACCR2 0176h Capture/compareregister1 TACCR1 0174h Capture/compareregister0 TACCR0 0172h Timer_Aregister TAR 0170h Capture/comparecontrol2 TACCTL2 0166h Capture/comparecontrol1 TACCTL1 0164h Capture/comparecontrol0 TACCTL0 0162h Timer_Acontrol TACTL 0160h Timer_Ainterruptvector TAIV 012Eh HardwareMultiplier Sumextend SUMEXT 013Eh Resulthighword RESHI 013Ch Resultlowword RESLO 013Ah Secondoperand OP2 0138h Multiplysigned+accumulate/operand1 MACS 0136h Multiply+accumulate/operand1 MAC 0134h Multiplysigned/operand1 MPYS 0132h Multiplyunsigned/operand1 MPY 0130h Flash Flashcontrol3 FCTL3 012Ch (FGdevicesonly) Flashcontrol2 FCTL2 012Ah Flashcontrol1 FCTL1 0128h DMA DMAmodulecontrol0 DMACTL0 0122h DMAmodulecontrol1 DMACTL1 0124h DMAinterruptvector DMAIV 0126h DMAChannel0 DMAchannel0control DMA0CTL 01D0h DMAchannel0sourceaddress DMA0SA 01D2h DMAchannel0destinationaddress DMA0DA 01D6h DMAchannel0transfersize DMA0SZ 01DAh DMAChannel1 DMAchannel1control DMA1CTL 01DCh DMAchannel1sourceaddress DMA1SA 01DEh DMAchannel1destinationaddress DMA1DA 01E2h DMAchannel1transfersize DMA1SZ 01E6h DMAChannel2 DMAchannel2control DMA2CTL 01E8h DMAchannel2sourceaddress DMA2SA 01EAh DMAchannel2destinationaddress DMA2DA 01EEh DMAchannel2transfersize DMA2SZ 01F2h 60 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 Table6-9.PeripheralsWithWordAccess(continued) MODULE REGISTERNAME ACRONYM ADDRESS ADC12 Conversionmemory15 ADC12MEM15 015Eh SeealsoTable6-10 Conversionmemory14 ADC12MEM14 015Ch Conversionmemory13 ADC12MEM13 015Ah Conversionmemory12 ADC12MEM12 0158h Conversionmemory11 ADC12MEM11 0156h Conversionmemory10 ADC12MEM10 0154h Conversionmemory9 ADC12MEM9 0152h Conversionmemory8 ADC12MEM8 0150h Conversionmemory7 ADC12MEM7 014Eh Conversionmemory6 ADC12MEM6 014Ch Conversionmemory5 ADC12MEM5 014Ah Conversionmemory4 ADC12MEM4 0148h Conversionmemory3 ADC12MEM3 0146h Conversionmemory2 ADC12MEM2 0144h Conversionmemory1 ADC12MEM1 0142h Conversionmemory0 ADC12MEM0 0140h Interrupt-vector-wordregister ADC12IV 01A8h Inerrupt-enableregister ADC12IE 01A6h Inerrupt-flagregister ADC12IFG 01A4h Controlregister1 ADC12CTL1 01A2h Controlregister0 ADC12CTL0 01A0h DAC12 DAC12_1data DAC12_1DAT 01CAh DAC12_1control DAC12_1CTL 01C2h DAC12_0data DAC12_0DAT 01C8h DAC12_0control DAC12_0CTL 01C0h PortPA PortPAselection PASEL 03Eh PortPAdirection PADIR 03Ch PortPAoutput PAOUT 03Ah PortPAinput PAIN 038h PortPB PortPBselection PBSEL 00Eh PortPBdirection PBDIR 00Ch PortPBoutput PBOUT 00Ah PortPBinput PBIN 008h Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 61 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com Table6-10.PeripheralsWithByteAccess MODULE REGISTERNAME ACRONYM ADDRESS OA2 OperationalAmplifier2controlregister1 OA2CTL1 0C5h OperationalAmplifier2controlregister0 OA2CTL0 0C4h OA1 OperationalAmplifier1controlregister1 OA1CTL1 0C3h OperationalAmplifier1controlregister0 OA1CTL0 0C2h OA0 OperationalAmplifier0controlregister1 OA0CTL1 0C1h OperationalAmplifier0controlregister0 OA0CTL0 0C0h LCD_A LCDVoltageControl1 LCDAVCTL1 0AFh LCDVoltageControl0 LCDAVCTL0 0AEh LCDVoltagePortControl1 LCDAPCTL1 0ADh LCDVoltagePortControl0 LCDAPCTL0 0ACh LCDmemory20 LCDM20 0A4h : : : LCDmemory16 LCDM16 0A0h LCDmemory15 LCDM15 09Fh : : : LCDmemory1 LCDM1 091h LCDcontrolandmode LCDCTL 090h ADC12 ADCmemory-controlregister15 ADC12MCTL15 08Fh (Memorycontrolregisters ADCmemory-controlregister14 ADC12MCTL14 08Eh requirebyteaccess) ADCmemory-controlregister13 ADC12MCTL13 08Dh ADCmemory-controlregister12 ADC12MCTL12 08Ch ADCmemory-controlregister11 ADC12MCTL11 08Bh ADCmemory-controlregister10 ADC12MCTL10 08Ah ADCmemory-controlregister9 ADC12MCTL9 089h ADCmemory-controlregister8 ADC12MCTL8 088h ADCmemory-controlregister7 ADC12MCTL7 087h ADCmemory-controlregister6 ADC12MCTL6 086h ADCmemory-controlregister5 ADC12MCTL5 085h ADCmemory-controlregister4 ADC12MCTL4 084h ADCmemory-controlregister3 ADC12MCTL3 083h ADCmemory-controlregister2 ADC12MCTL2 082h ADCmemory-controlregister1 ADC12MCTL1 081h ADCmemory-controlregister0 ADC12MCTL0 080h USART1 Transmitbuffer U1TXBUF 07Fh Receivebuffer U1RXBUF 07Eh Baudrate U1BR1 07Dh Baudrate U1BR0 07Ch Modulationcontrol U1MCTL 07Bh Receivecontrol U1RCTL 07Ah Transmitcontrol U1TCTL 079h USARTcontrol U1CTL 078h USCI USCII2CSlaveAddress UCBI2CSA 011Ah USCII2COwnAddress UCBI2COA 0118h USCISynchronousTransmitBuffer UCBTXBUF 06Fh USCISynchronousReceiveBuffer UCBRXBUF 06Eh USCISynchronousStatus UCBSTAT 06Dh USCII2CInterruptEnable UCBI2CIE 06Ch USCISynchronousBitRate1 UCBBR1 06Bh USCISynchronousBitRate0 UCBBR0 06Ah USCISynchronousControl1 UCBCTL1 069h USCISynchronousControl0 UCBCTL0 068h USCITransmitBuffer UCATXBUF 067h USCIReceiveBuffer UCARXBUF 066h USCIStatus UCASTAT 065h USCIModulationControl UCAMCTL 064h USCIBaudRate1 UCABR1 063h USCIBaudRate0 UCABR0 062h USCIControl1 UCACTL1 061h USCIControl0 UCACTL0 060h USCIIrDAReceiveControl UCAIRRCTL 05Fh USCIIrDATransmitControl UCAIRTCTL 05Eh USCILINControl UCAABCTL 05Dh Comparator_A Comparator_Aportdisable CAPD 05Bh Comparator_Acontrol2 CACTL2 05Ah Comparator_Acontrol1 CACTL1 059h 62 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 Table6-10.PeripheralsWithByteAccess(continued) MODULE REGISTERNAME ACRONYM ADDRESS BrownOUT,SVS SVScontrolregister(Resetbybrownoutsignal) SVSCTL 056h FLL+Clock FLL+Control1 FLL_CTL1 054h FLL+Control0 FLL_CTL0 053h Systemclockfrequencycontrol SCFQCTL 052h Systemclockfrequencyintegrator SCFI1 051h Systemclockfrequencyintegrator SCFI0 050h RTC RealTimeClockYearHighByte RTCYEARH 04Fh (BasicTimer1) RealTimeClockYearLowByte RTCYEARL 04Eh RealTimeClockMonth RTCMON 04Dh RealTimeClockDayofMonth RTCDAY 04Ch BasicTimer1Counter2 BTCNT2 047h BasicTimer1Counter1 BTCNT1 046h RealTimeCounter4 RTCNT4 045h (RealTimeClockDayofWeek) (RTCDOW) 044h RealTimeCounter3 RTCNT3 043h (RealTimeClockHour) (RTCHOUR) 042h RealTimeCounter2 RTCNT2 041h (RealTimeClockMinute) (RTCMIN) 040h RealTimeCounter1 RTCNT1 (RealTimeClockSecond) (RTCSEC) RealTimeClockControl RTCCTL BasicTimer1Control BTCTL PortP10 PortP10selection P10SEL 00Fh PortP10direction P10DIR 00Dh PortP10output P10OUT 00Bh PortP10input P10IN 009h PortP9 PortP9selection P9SEL 00Eh PortP9direction P9DIR 00Ch PortP9output P9OUT 00Ah PortP9input P9IN 008h PortP8 PortP8selection P8SEL 03Fh PortP8direction P8DIR 03Dh PortP8output P8OUT 03Bh PortP8input P8IN 039h PortP7 PortP7selection P7SEL 03Eh PortP7direction P7DIR 03Ch PortP7output P7OUT 03Ah PortP7input P7IN 038h PortP6 PortP6selection P6SEL 037h PortP6direction P6DIR 036h PortP6output P6OUT 035h PortP6input P6IN 034h PortP5 PortP5selection P5SEL 033h PortP5direction P5DIR 032h PortP5output P5OUT 031h PortP5input P5IN 030h PortP4 PortP4selection P4SEL 01Fh PortP4direction P4DIR 01Eh PortP4output P4OUT 01Dh PortP4input P4IN 01Ch PortP3 PortP3selection P3SEL 01Bh PortP3direction P3DIR 01Ah PortP3output P3OUT 019h PortP3input P3IN 018h PortP2 PortP2selection P2SEL 02Eh PortP2interruptenable P2IE 02Dh PortP2interrupt-edgeselect P2IES 02Ch PortP2interruptflag P2IFG 02Bh PortP2direction P2DIR 02Ah PortP2output P2OUT 029h PortP2input P2IN 028h Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 63 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com Table6-10.PeripheralsWithByteAccess(continued) MODULE REGISTERNAME ACRONYM ADDRESS PortP1 PortP1selection P1SEL 026h PortP1interruptenable P1IE 025h PortP1interrupt-edgeselect P1IES 024h PortP1interruptflag P1IFG 023h PortP1direction P1DIR 022h PortP1output P1OUT 021h PortP1input P1IN 020h Specialfunctions SFRmoduleenable2 ME2 005h SFRmoduleenable1 ME1 004h SFRinterruptflag2 IFG2 003h SFRinterruptflag1 IFG1 002h SFRinterruptenable2 IE2 001h SFRinterruptenable1 IE1 000h 64 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.10 Input/Output Schematics 6.10.1 Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger Pad Logic DVSS DVSS DVSS P1DIR.x 0 Direction 1 0:Input 1:Output P1OUT.x 0 Module X OUT 1 P1.0/TA0 P1.1/TA0/MCLK P1SEL.x Bus P1.2/TA1 Keeper P1.3/TBOUTH/SVSOUT EN P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK P1IN.x EN Module X IN D P1IE.x EN P1IRQ.x Q Set P1IFG.x Interrupt P1SEL.x Edge P1IES.x Select Note:x=0,1,2,3,4,5 Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 65 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com Table6-11.PortP1(P1.0toP1.5)PinFunctions CONTROLBITSORSIGNALS PINNAME(P1.x) x FUNCTION P1DIR.x P1SEL.x P1.0/TA0 0 P1.0(I/O) I:0;O:1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 P1.1/TA0/MCLK 1 P1.1(I/O) I:0;O:1 0 Timer_A3.CCI0B 0 1 MCLK 1 1 P1.2/TA1 2 P1.2(I/O) I:0;O:1 0 Timer_A3.CCI1A 0 1 Timer_A3.TA1 1 1 P1.3/TBOUTH/SVSOUT 3 P1.3(I/O) I:0;O:1 0 Timer_B7.TBOUTH 0 1 SVSOUT 1 1 P1.4/TBCLK/SMCLK 4 P1.4(I/O) I:0;O:1 0 Timer_B7.TBCLK 0 1 SMCLK 1 1 P1.5/TACLK/ACLK 5 P1.5(I/O) I:0;O:1 0 Timer_A3.TACLK 0 1 ACLK 1 1 66 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.10.2 Port P1, P1.6, P1.7, Input/Output With Schmitt Trigger Pad Logic DVSS DVSS CAPD.x P1DIR.x 0 Direction 1 0:Input 1:Output P1OUT.x 0 Module X OUT 1 P1.6/CA0 P1SEL.x Bus P1.7/CA1 Keeper EN P1IN.x EN Module X IN D P2CA0 P1IE.x EN P1IRQ.x Comp_A Q 0 Set 1 CA0 P1IFG.x + Interrupt - P1SEL.x 0 Edge CA1 P1IES.x Select 1 Note:x=6,7 P2CA1 Table6-12.PortP1(P1.6andP1.7)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P1.x) x FUNCTION CAPD.x P1DIR.x P1SEL.x P1.6/CA0 6 P1.6(I/O) 0 I:0;O:1 0 CA0 1 X X P1.7/CA1 7 P1.7(I/O) 0 I:0;O:1 0 CA1 1 X X (1) X=don'tcare Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 67 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.10.3 Port P2, P2.0 to P2.3, P2.6 to P2.7, Input/Output With Schmitt Trigger Pad Logic DVSS DVSS TBOUTH P2DIR.x 0 Direction 1 0:Input 1:Output P2OUT.x 0 Module X OUT 1 P2.0/TA2 P2.1/TB0 P2SEL.x Bus P2.2/TB1 Keeper P2.3/TB2 EN P2.6/CAOUT P2.7/ADC12CLK/DMAE0 P2IN.x EN Module X IN D P2IE.x EN P2IRQ.x Q Set P2IFG.x Interrupt P2SEL.x Edge P2IES.x Select Note:x=0,1,2,3,6,7 68 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 Table6-13.PortP2(P2.0,P2.1,P2.2,P2.3,P2.6andP2.7)PinFunctions CONTROLBITSORSIGNALS PINNAME(P2.x) x FUNCTION P2DIR.x P2SEL.x P2.0/TA2 0 P2.0(I/O) I:0;O:1 0 Timer_A3.CCI2A 0 1 Timer_A3.TA2 1 1 P2.1/TB0 1 P2.1(I/O) I:0;O:1 0 Timer_B7.CCI0AandTimer_B7.CCI0B 0 1 Timer_B7.TB0(1) 1 1 P2.2/TB1 2 P2.2(I/O) I:0;O:1 0 Timer_B7.CCI1AandTimer_B7.CCI1B 0 1 Timer_B7.TB1(1) 1 1 P2.3/TB3 3 P2.3(I/O) I:0;O:1 0 Timer_B7.CCI2AandTimer_B7.CCI2B 0 1 Timer_B7.TB3(1) 1 1 P2.6/CAOUT 6 P2.6(I/O) I:0;O:1 0 CAOUT 1 1 P2.7/ADC12CLK/DMAE0 7 P2.7(I/O) I:0;O:1 0 ADC12CLK 1 1 DMAE0 0 1 (1) SettingTBOUTHcausesallTimer_Boutputstobesettohighimpedance. Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 69 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.10.4 Port P2, P2.4 to P2.5, Input/Output With Schmitt Trigger Pad Logic DVSS DVSS DVSS P2DIR.x 0 Direction Direction control 1 0:Input from Module X 1:Output P2OUT.x 0 Module X OUT 1 P2.4/UCA0TXD P2.5/UCA0RXD P2SEL.x Bus Keeper EN P2IN.x EN Module X IN D P2IE.x EN P2IRQ.x Q Set P2IFG.x Interrupt P2SEL.x Edge P2IES.x Select Note:x =4,5 Table6-14.PortP2(P2.4andP2.5)PinFunctions CONTROLBITSOR PINNAME(P2.x) x FUNCTION SIGNALS(1) P2DIR.x P2SEL.x P2.4(I/O) I:0;O:1 0 P2.4/UCA0TXD 4 USCI_A0.UCA0TXD (2) X 1 P2.5(I/O) I:0;O:1 0 P2.5/UCA0RXD 5 USCI_A0.UCA0RXD (2) X 1 (1) X=don'tcare (2) WheninUSCImode,P2.4issettooutput,P2.5issettoinput. 70 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.10.5 Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger Pad Logic DVSS DVSS DVSS P3DIR.x 0 Direction 1 0:Input 1:Output P3OUT.x 0 Module X OUT 1 P3.0/UCB0STE P3.1/UCB0SIMO/UCB0SDA P3SEL.x Bus P3.2/UCB0SOMI/UCB0SCL Keeper P3.3/UCB0CLK EN P3IN.x EN Module X IN D Note:x= 0,1,2,3 Table6-15.PortP3(P3.0toP3.3)PinFunctions CONTROLBITSOR PINNAME(P3.x) x FUNCTION SIGNALS(1) P3DIR.x P3SEL.x P3.0/UCB0STE 0 P3.0(I/O) I:0;O:1 0 UCB0STE (2) X 1 P3.1/UCB0SIMO/UCB0SDA 1 P3.1(I/O) I:0;O:1 0 UCB0SIMO/UCB0SDA (2) (3) X 1 P3.2/UCB0SOMI/UCB0SCL 2 P3.2(I/O) I:0;O:1 0 UCB0SOMI/UCB0SCL (2) (3) X 1 P3.3/UCB0CLK 3 P3.3(I/O) I:0;O:1 0 UCB0CLK (2) X 1 (1) X=don'tcare (2) ThepindirectioniscontrolledbytheUSCImodule. (3) IftheI2Cfunctionalityisselectedtheoutputdrivesonlythelogical0toV level. SS Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 71 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.10.6 Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger Pad Logic DVSS DVSS TBOUTH P3DIR.x 0 Direction 1 0:Input 1:Output P3OUT.x 0 Module X OUT 1 P3.4/TB3 P3.5/TB4 P3SEL.x Bus P3.6/TB5 Keeper P3.7/TB6 EN P3IN.x EN Module X IN D Note:x=4,5,6,7 Table6-16.PortP3(P3.4toP3.7)PinFunctions CONTROLBITSORSIGNALS PINNAME(P3.x) x FUNCTION P3DIR.x P3SEL.x P3.4/TB3 4 P3.4(I/O) I:0;O:1 0 Timer_B7.CCI3AandTimer_B7.CCI3B 0 1 Timer_B7.TB3(1) 1 1 P3.5/TB4 5 P3.5(I/O) I:0;O:1 0 Timer_B7.CCI4AandTimer_B7.CCI4B 0 1 Timer_B7.TB4 (1) 1 1 P3.6/TB5 6 P3.6(I/O) I:0;O:1 0 Timer_B7.CCI5AandTimer_B7.CCI5B 0 1 Timer_B7.TB5(1) 1 1 P3.7/TB6 7 P3.7(I/O) I:0;O:1 0 Timer_B7.CCI6AandTimer_B7.CCI6B 0 1 Timer_B7.TB6(1) 1 1 (1) SettingTBOUTHcausesallTimer_Boutputstobesettohighimpedance. 72 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.10.7 Port P4, P4.0 to P4.1, Input/Output With Schmitt Trigger Pad Logic DVSS DVSS DVSS P4DIR.x 0 Direction Direction control 1 0:Input from Module X 1:Output P4OUT.x 0 Module X OUT 1 P4.1/URXD1 P4.0/UTXD1 P4SEL.x Bus Keeper EN P4IN.x EN Module X IN D Note:x=0,1 Table6-17.PortP4(P4.0toP4.1)PinFunctions CONTROLBITSOR PINNAME(P4.x) x FUNCTION SIGNALS(1) P4DIR.x P4SEL.x P4.0/UTXD1 0 P4.0(I/O) I:0;O:1 0 USART1.UTXD1 (2) X 1 P4.1/URXD1 1 P4.1(I/O) I:0;O:1 0 USART1.URXD1 (2) X 1 (1) X=don'tcare (2) WheninUSART1mode,P4.0issettooutput,P4.1issettoinput. Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 73 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.10.8 Port P4, P4.2 to P4.7, Input/Output With Schmitt Trigger Pad Logic LCDS32/36 Segment Sy DVSS P4DIR.x 0 Direction Direction control 1 0:Input from Module X 1:Output P4OUT.x 0 Module X OUT 1 P4.7/UCA0RXD/S34 P4.6/UCA0TXD/S35 P4SEL.x Bus P4.5/UCLK1/S36 Keeper P4.4/SOMI1/S37 EN P4.3/SIMO1/S38 P4.2/STE1/S39 P4IN.x EN Module X IN D Note :x =2,3,4,5,6,7 y =34,35,36,37,38,39 Table6-18.PortP4(P4.2toP4.5)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P4.x) x FUNCTION P4DIR.x P4SEL.x LCDS36 P4.2(I/O) I:0;O:1 0 0 P4.2/STE1/S39 2 USART1.STE1 X 1 0 S39 X X 1 P4.3(I/O) I:0;O:1 0 0 P4.3/SIMO/S38 3 USART1.SIMO1 (2) X 1 0 S38 X X 1 P4.4(I/O) I:0;O:1 0 0 P4.4/SOMI/S37 4 USART1.SOMI1 (2) X 1 0 S37 X X 1 P4.5(I/O) I:0;O:1 0 0 P4.5/SOMI/S36 5 USART1.UCLK1 (2) X 1 0 S36 X X 1 (1) X=don'tcare (2) ThepindirectioniscontrolledbytheUSART1module. 74 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 Table6-19.PortP4(P4.6andP4.7)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P4.x) x FUNCTION P4DIR.x P4SEL.x LCDS32 P4.6(I/O) I:0;O:1 0 0 P4.6/UCA0TXD/S35 6 USCI_A0.UCA0TXD (2) X 1 0 S35 X X 1 P4.7(I/O) I:0;O:1 0 0 P4.7/UCA0RXD/S34 7 USCI_A0.UCA0RXD (2) X 1 0 S34 X X 1 (1) X=don'tcare (2) WheninUSCImode,P4.6issettooutput,P4.7issettoinput. Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 75 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.10.9 Port P5, P5.0, Input/Output With Schmitt Trigger # INCH=13 Pad Logic # A13 LCDS0 Segment Sy P5DIR.x 0 Direction 1 0:Input 1:Output P5OUT.x 0 DVSS 1 P5SEL.x Bus P5.0/S1/A13/OA1I1 Keeper EN P5IN.x Note: x = 0 y = 1 + OA1 - Table6-20.PortP5(P5.0)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P5.x) x FUNCTION OAPx(OA1) P5DIR.x P5SEL.x INCHx LCDS0 OANx(OA1) P5.0/S1/A13/OA1I1 0 P5.0(I/O) I:0;O:1 0 X X 0 OAI11 0 X X 1 0 A13 (2) X 1 13 X X S1enabled X 0 X X 1 S1disabled X 1 X X 1 (1) X=don'tcare (2) SettingtheP5SEL.xbitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplyinganalog signals. 76 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.10.10 Port P5, P5.1, Input/Output With Schmitt Trigger # INCH=12 Pad Logic # A12 LCDS0 Segment Sy DAC12.1OPS P5DIR.x 0 Direction 1 0:Input 1:Output P5OUT.x 0 DVSS 1 P5SEL.x Bus P5.1/S0/A12/DAC1 Keeper EN P5IN.x Note: x = 1 y = 0 0 DVSS 1 DAC1 2 0if DAC12.1AMPx =0and DAC12.1OPS =1 1if DAC12.1AMPx =1and DAC12.1OPS =1 2if DAC12.1AMPx >1and DAC12.1OPS =1 Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 77 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com Table6-21.PortP5(P5.1)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P5.x) x FUNCTION P5DIR.x P5SEL.x INCHx DAC12.1OPS DAC12.1AMPx LCDS0 P5.1/S0/A12/DAC1 1 P5.1(I/O) I:0;O:1 0 X 0 X 0 DAC1highimpedance X X X 1 0 X DVSS X X X 1 1 X DAC1output X X X 1 >1 X A12(2) X 1 12 0 X 0 S0enabled X 0 X 0 X 1 S0disabled X 1 X 0 X 1 (1) X=don'tcare (2) SettingtheP5SEL.xbitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplyinganalog signals. 78 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.10.11 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger Pad Logic LCD Signal DVSS P5DIR.x 0 Direction 1 0:Input 1:Output P5OUT.x 0 DVSS 1 P5.2/COM1 P5SEL.x Bus P5.3/COM2 Keeper P5.4/COM3 EN P5IN.x Note:x =2,3,4 Table6-22.PortP5(P5.2toP5.4)PinFunctions CONTROLBITSOR PINNAME(P5.x) x FUNCTION SIGNALS(1) P5DIR.x P5SEL.x P5.2/COM1 2 P5.2(I/O) I:0;O:1 0 COM1 X 1 P5.3/COM2 3 P5.3(I/O) I:0;O:1 0 COM2 X 1 P5.4/COM3 4 P5.4(I/O) I:0;O:1 0 COM3 X 1 (1) X=don'tcare Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 79 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.10.12 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger Pad Logic LCD Signal DVSS P5DIR.x 0 Direction 1 0:Input 1:Output P5OUT.x 0 DVSS 1 P5.5/R03 P5SEL.x Bus P5.6/LCDREF/R13 Keeper P5.7/R03 EN P5IN.x Note:x =5,6,7 Table6-23.PortP5(P5.5toP5.7)PinFunctions CONTROLBITSOR PINNAME(P5.x) x FUNCTION SIGNALS(1) P5DIR.x P5SEL.x P5.5/R03 5 P5.5(I/O) I:0;O:1 0 R03 X 1 P5.6/LCDREF/R13 6 P5.6(I/O) I:0;O:1 0 R13orLCDREF (2) X 1 P5.7/R03 7 P5.7(I/O) I:0;O:1 0 R03 X 1 (1) X=don'tcare (2) ExternalreferencefortheLCD_AchargepumpisappliedwhenVLCDREFx=01.OtherwiseR13isselected. 80 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.10.13 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger # INCH=0/2/4 Pad Logic # Ay P6DIR.x 0 Direction 1 0:Input P6.0/A0/OA0I0 1:Output P6.2/A2/OA0I1 P6.4/A4/OA1I0 P6OUT.x 0 DVSS 1 P6SEL.x Bus Keeper EN P6IN.x Note: x = 0, 2, 4 y = 0, 1 # = Signal from or toADC12 + OA0/1 - Table6-24.PortP6(P6.0,P6.2,andP6.4)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P6.x) x FUNCTION OAPx(OA0) OAPx(OA1) P6DIR.x P6SEL.x INCHx OANx(OA0) OANx(OA1) P6.0/A0/OA0I0 0 P6.0(I/O) I:0;O:1 0 X X X OA0I0 0 X 0 X X A0 (2) X 1 X X 0 P6.2/A2/OA0I1 2 P6.2(I/O) I:0;O:1 0 X X X OA0I1 0 X 1 X X A2 (2) X 1 X X 2 P6.4/A4/OA1I0 4 P6.4(I/O) I:0;O:1 0 X X X OA1I0 0 X X 0 X A4 (2) X 1 X X 4 (1) X=don'tcare (2) SettingtheP6SEL.xbitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplyinganalog signals. Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 81 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.10.14 Port P6, P6.1, P6.3, and P6.5 Input/Output With Schmitt Trigger # INCH=1/3/5 Pad Logic # Ay P6DIR.x 0 Direction 1 0:Input P6.1/A1/OA0O 1:Output P6.3/A3/OA1O P6.5/A5/OA2O P6OUT.x 0 DVSS 1 P6SEL.x Bus Keeper EN P6IN.x OAPMx > 0 OAADC1 + OAy Note: x = 1, 3, 5 - y = 0, 1, 2 # = Signal from or toADC12 Table6-25.PortP6(P6.1,P6.3,andP6.5)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P6.x) x FUNCTION P6DIR.x P6SEL.x OAADC1 OAPMx INCHx P6.1/A1/OA0O 1 P6.1(I/O) I:0;O:1 0 X 0 X OA0O (2) X X 1 >0 X A1 (3) X 1 X 0 1 P6.3/A3/OA1O 3 P6.3(I/O) I:0;O:1 0 X 0 X OA1O (2) X X 1 >0 X A3 (3) X 1 X 0 3 P6.5/A5/OA2O 5 P6.5(I/O) I:0;O:1 0 X 0 X OA2O (2) X X 1 >0 X A5 (3) X 1 X 0 5 (1) X=don'tcare (2) SettingtheOAADC1bitorsettingOAFCx=00willcausetheoperationalamplifiertobepresentatthepinaswellasinternally connectedtothecorrespondingADC12input. (3) SettingtheP6SEL.xbitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplyinganalog signals. 82 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.10.15 Port P6, P6.6, Input/Output With Schmitt Trigger # INCH=6 Pad Logic # A6 P6DIR.x 0 Direction 1 0:Input 1:Output P6.6/A6/DAC0/OA2I0 P6OUT.x 0 DVSS 1 P6SEL.x Bus Keeper DAC12.0AMP >0 EN DAC12.0OPS P6IN.x Note: x = 6 # = Signal from or toADC12 + OA2 - 0 DVSS 1 DAC0 2 0if DAC12.0AMPx =0and DAC12.0OPS =0 1if DAC12.0AMPx =1and DAC12.0OPS =0 2if DAC12.0AMPx >1and DAC12.0OPS =0 Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 83 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com Table6-26.PortP6(P6.6)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P6.x) x FUNCTION OAPx(OA2) P6DIR.x P6SEL.x INCHx DAC12.0OPS DAC12.0AMPx OANx(OA2) P6.6/A6/DAC0/OA2I0 6 P6.6(I/O) I:0;O:1 0 X 1 X X DAC0highimpedance X X X 0 0 X DVSS X X X 0 1 X DAC0output X X X 0 >1 X A6(2) X 1 6 X X X OA2I0 0 X 0 X X 0 (1) X=don'tcare (2) SettingtheP6SEL.xbitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplyinganalog signals. 84 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.10.16 Port P6, P6.7, Input/Output With Schmitt Trigger To SVS Mux # INCH=7 Pad Logic # A7 P6DIR.x 0 Direction 1 0:Input 1:Output P6OUT.x 0 DVSS 1 P6.7/A7/DAC1/SVSIN P6SEL.x Bus Keeper VLD =15 EN DAC12.1AMP >0 DAC12.1OPS P6IN.x Note: x = 7 # = Signal from or toADC12 0 DVSS 1 DAC1 2 0if DAC12.1AMPx =0and DAC12.1OPS= 0 1if DAC12.1AMPx =1and DAC12.1OPS= 0 2if DAC12.1AMPx >1and DAC12.1OPS= 0 Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 85 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com Table6-27.PortP6(P6.7)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P6.x) x FUNCTION P6DIR.x P6SEL.x INCHx DAC12.1OPS DAC12.1AMPx P6.7/A7/DAC1/SVSIN 7 P6.7(I/O) I:0;O:1 0 X 1 X DAC1highimpedance X X X 0 0 DVSS X X X 0 1 DAC1output X X X 0 >1 A7(2) X 1 7 X X SVSIN(2) 0 1 0 1 X (1) X=don'tcare (2) SettingtheP6SEL.xbitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplyinganalog signals. 86 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.10.17 Port P7, P7.0 to P7.3, Input/Output With Schmitt Trigger Pad Logic LCDS28/32 Segment Sy DVSS P7DIR.x 0 Direction Direction control 1 0:Input from Module X 1:Output P7OUT.x 0 Module X OUT 1 P7.3/UCA0CLK/S30 P7.2/UCA0SOMI/S31 P7SEL.x Bus P7.1/UCA0SIMO/S32 Keeper P7.0/UCA0STE/S33 EN P7IN.x EN Module X IN D Note: x = 0, 1, 2, 3 y = 30, 31, 32, 33 Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 87 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com Table6-28.PortP7(P7.0andP7.1)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P7.x) x FUNCTION P7DIR.x P7SEL.x LCDS32 P7.0/UCA0STE/S33 0 P7.0(I/O) I:0;O:1 0 0 USCI_A0.UCA0STE (2) X 1 0 S33(1) X X 1 P7.1/UCA0SIMO/S32 1 P7.1(I/O) I:0;O:1 0 0 USCI_A0.UCA0SIMO (2) X 1 0 S32 X X 1 (1) X=don'tcare (2) ThepindirectioniscontrolledbytheUSCImodule. Table6-29.PortP7(P7.2andP7.3)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P7.x) x FUNCTION P7DIR.x P7SEL.x LCDS28 P7.2/UCA0SOMI/S31 2 P7.2(I/O) I:0;O:1 0 0 USCI_A0.UCA0SOMI (2) X 1 0 S31 X X 1 P7.3/UCA0CLK/S30 3 P7.3(I/O) I:0;O:1 0 0 USCI_A0.UCA0CLK (2) X 1 0 S30 X X 1 (1) X=don'tcare (2) ThepindirectioniscontrolledbytheUSCImodule. 88 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.10.18 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger Pad Logic LCDS24/28 Segment Sy DVSS P7DIR.x 0 Direction 1 0:Input 1:Output P7OUT.x 0 DVSS 1 P7.7/S26 P7SEL.x Bus P7.6/S27 Keeper P7.5/S28 EN P7.4/S29 P7IN.x Note: x = 4, 5, 6, 7 y = 26, 27, 28, 29 Table6-30.PortP7(P7.4andP7.5)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P7.x) x FUNCTION P7DIR.x P7SEL.x LCDS28 P7.4/S29 4 P7.4(I/O) I:0;O:1 0 0 S29 X X 1 P7.5/S28 5 P7.5(I/O) I:0;O:1 0 0 S28 X X 1 (1) X=don'tcare Table6-31.PortP7(P7.6andP7.7)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P7.x) x FUNCTION P7DIR.x P7SEL.x LCDS24 P7.6/S27 6 P7.6(I/O) I:0;O:1 0 0 S27 X X 1 P7.7/S26 7 P7.7(I/O) I:0;O:1 0 0 S26 X X 1 (1) X=don'tcare Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 89 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.10.19 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger Pad Logic LCDS16/20/24 Segment Sy DVSS P8DIR.x 0 Direction 1 0:Input 1:Output P8OUT.x 0 DVSS 1 P8.7/S18 P8SEL.x Bus P8.6/S19 Keeper P8.5/S20 EN P8.4/S21 P8.3/S22 P8.2/S23 P8IN.x P8.1/S24 P8.0/S25 Note:x=0,1,2,3,4,5,6,7 y =25,24,23,22,21,20,19,18 Table6-32.PortP8(P8.0andP8.1)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P8.x) x FUNCTION P8DIR.x P8SEL.x LCDS16 P8.0/S18 0 P8.0(I/O) I:0;O:1 0 0 S18 X X 1 P8.1/S19 0 P8.0(I/O) I:0;O:1 0 0 S19 X X 1 (1) X=don'tcare Table6-33.PortP8(P8.2toP8.5)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P8.x) x FUNCTION P8DIR.x P8SEL.x LCDS20 P8.2/S20 2 P8.2(I/O) I:0;O:1 0 0 S20 X X 1 P8.3/S21 3 P8.3(I/O) I:0;O:1 0 0 S21 X X 1 P8.4/S22 4 P8.4(I/O) I:0;O:1 0 0 S22 X X 1 P8.5/S23 5 P8.5(I/O) I:0;O:1 0 0 S23 X X 1 (1) X=don'tcare 90 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 Table6-34.PortP8(P8.6andP8.7)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P8.x) X FUNCTION P8DIR.x P8SEL.x LCDS24 P8.6/S24 6 P8.6(I/O) I:0;O:1 0 0 S24 X X 1 P8.7/S25 7 P8.7(I/O) I:0;O:1 0 0 S25 X X 1 (1) X=don'tcare Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 91 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.10.20 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger Pad Logic LCDS8/12/16 Segment Sy DVSS P9DIR.x 0 Direction 1 0:Input 1:Output P9OUT.x 0 DVSS 1 P9.7/S10 P9SEL.x Bus P9.6/S11 Keeper P9.5/S12 EN P9.4/S13 P9.3/S14 P9.2/S15 P9IN.x P9.1/S16 P9.0/S17 Note:x =0,1,2,3,4,5,6,7 y =17,16,15,14,13,12,11,10 Table6-35.PortP9(P9.0andP9.1)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P9.x) x FUNCTION P9DIR.x P9SEL.x LCDS16 P9.0/S17 0 P9.0(I/O) I:0;O:1 0 0 S17 X X 1 P9.1/S16 1 P9.1(I/O) I:0;O:1 0 0 S16 X X 1 (1) X=don'tcare Table6-36.PortP9(P9.2toP9.5)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P9.x) x FUNCTION P9DIR.x P9SEL.x LCDS12 P9.2/S15 2 P9.2(I/O) I:0;O:1 0 0 S15 X X 1 P9.3/S14 3 P9.3(I/O) I:0;O:1 0 0 S14 X X 1 P9.4/S13 4 P9.4(I/O) I:0;O:1 0 0 S13 X X 1 P9.5/S12 5 P9.5(I/O) I:0;O:1 0 0 S12 X X 1 (1) X=don'tcare 92 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 Table6-37.PortP9(P9.6andP9.7)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P9.x x FUNCTION P9DIR.x P9SEL.x LCDS8 P9.6/S11 6 P9.6(I/O) I:0;O:1 0 0 S11 X X 1 P9.7/S10 7 P9.7(I/O) I:0;O:1 0 0 S10 X X 1 (1) X=don'tcare Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 93 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.10.21 Port P10, P10.0 to P10.5, Input/Output With Schmitt Trigger Pad Logic LCDS4/8 Segment Sy DVSS P10DIR.x 0 Direction 1 0:Input 1:Output P10OUT.x 0 DVSS 1 P10.5/S4 P10SEL.x Bus P10.4/S5 Keeper P10.3/S6 EN P10.2/S7 P10.1/S8 P10.0/S9 P10IN.x Note:x =0,1,2,3,4,5 y =9,8,7,6,5,4 Table6-38.PortP10(P10.0andP10.1)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P10.x) x FUNCTION P10DIR.x P10SEL.x LCDS8 P10.0/S9 0 P10.0(I/O) I:0;O:1 0 0 S9 X X 1 P10.1/S8 1 P10.1(I/O) I:0;O:1 0 0 S8 X X 1 (1) X=don'tcare Table6-39.PortP10(P10.2toP10.5)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P10.x) x FUNCTION P10DIR.x P10SEL.x LCDS4 P10.2/S7 2 P10.2(I/O) I:0;O:1 0 0 S7 X X 1 P10.3/S6 3 P10.3(I/O) I:0;O:1 0 0 S6 X X 1 P10.4/S5 4 P10.4(I/O) I:0;O:1 0 0 S5 X X 1 P10.5/S4 5 P10.5(I/O) I:0;O:1 0 0 S4 X X 1 (1) X=don'tcare 94 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.10.22 Port P10, P10.6, Input/Output With Schmitt Trigger # INCH=15 Pad Logic # A15 LCDS0 Segment Sy P10DIR.x 0 Direction 1 0:Input 1:Output P10OUT.x 0 DVSS 1 P10.6/S3/A15 P10SEL.x Bus Keeper EN P10IN.x Note:x=6 y =3 Table6-40.PortP10(P10.6)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P10.x) x FUNCTION P10DIR.x P10SEL.x INCHx LCDS0 P10.6/S3/A15 P5.0(I/O) I:0;O:1 0 X 0 A15 (2) X 1 15 0 6 S3enabled X 0 X 1 S3disabled X 1 X 1 (1) X=don'tcare (2) SettingtheP10SEL.xbitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplying analogsignals. Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 95 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.10.23 Port P10, P10.7, Input/Output With Schmitt Trigger # INCH=14 Pad Logic # A14 LCDS0 Segment Sy P10DIR.x 0 Direction 1 0:Input 1:Output P10OUT.x 0 DVSS 1 P10SEL.x Bus P10.7/S2/A14/OA2I1 Keeper EN P10IN.x Note:x=7 y =2 + OA2 - Table6-41.PortP10(P10.7)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P10.x) x FUNCTION OAPx(OA1) P10DIR.x P10SEL.x INCHx LCDS0 OANx(OA1) P10.7/S2/A14/OA2I1 7 P10.7(I/O) I:0;O:1 0 X X 0 A14 (2) X 1 14 X 0 OA2I1 (2) 0 X X 1 0 S2enabled X 0 X X 1 S2disabled X 1 X X 1 (1) X=don'tcare (2) SettingtheP10SEL.xbitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplying analogsignals. 96 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.10.24 Ve /DAC0 REF+ DAC12.0OPS 0 DAC0_2_OA P6.6/A6/DAC0/OA2I0 1 Reference Voltage to DAC1 Reference Voltage toADC12 Reference Voltage to DAC0 # VeREF+/DAC0 '0', if DAC12CALON = 0 DAC12AMPx>1AND DAC12OPS=1 + 1 - 0 '1', if DAC12AMPx>1 '1', if DAC12AMPx=1 DAC12OPS # If the reference of DAC0 is taken from pin Ve /DAC0, unpredictable voltage levels will be on pin. REF+ In this situation, the DAC0 output is fed back to its own reference input. Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 97 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 6.10.25 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output TDO Controlled by JTAG Controlled by JTAG TDO/TDI JTAG Controlled DV by JTAG CC TDI Burn and Test Fuse TDI/TCLK Test DV and CC Emulation TMS Module TMS DV CC TCK TCK RST/NMI Tau ~ 50 ns D Brownout G U S D TCK U G S 98 DetailedDescription Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 6.10.26 JTAG Fuse Check Mode Devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current (I ) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. (TF) Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system powerconsumption. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. AftereachPORthefusecheckmodehasthepotentialtobeactivated. The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see Figure 6-1). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). The JTAG pins are terminated internally and therefore do not require external termination. Time TMS Goes LowAfter POR TMS I(TF) ITDI/TCLK Figure6-1.FuseCheckModeCurrent Copyright©2006–2020,TexasInstrumentsIncorporated DetailedDescription 99 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 7 Device and Documentation Support 7.1 Device Support 7.1.1 Getting Started and Next Steps For more information on the MSP430F4x family of devices and the tools and libraries that are available to helpwithyourdevelopment,visittheGettingStarted page. 7.1.2 Development Tools Support All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools.ToolsareavailablefromTIandvariousthirdparties.Seethemallat www.ti.com/msp430tools. 7.1.2.1 HardwareFeatures SeetheComposerStudioforMSP430User'sGuide(SLAU157)fordetailsontheavailablefeatures. Break- Range LPMx.5 MSP430 4-Wire 2-Wire Clock State Trace points Break- Debugging Architecture JTAG JTAG Control Sequencer Buffer (N) points Support MSP430 Yes No 2 No Yes No No No 7.1.2.2 RecommendedHardwareOptions 7.1.2.2.1 TargetSocketBoards The target socket boards allow easy programming and debugging of the device using JTAG. They also feature header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the JTAG programmer and debugger included. The following table shows the compatible target boards and thesupportedpackages. Package TargetBoardandProgrammerBundle TargetBoardOnly 100-pinLQFP(PZ) MSP-FET430U100 MSP-TS430PZ100 7.1.2.2.2 ExperimenterBoards Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature additional hardware components and connectivity for full system evaluation and prototyping. See www.ti.com/msp430toolsfordetails. 7.1.2.2.3 DebuggingandProgrammingTools Hardware programming and debugging tools are available from TI and from its third party suppliers. See thefulllistofavailabletoolsatwww.ti.com/msp430tools. 7.1.2.2.4 ProductionProgrammers The production programmers expedite loading firmware to devices by programming several devices simultaneously. PartNumber PCPort Features Provider MSP-GANG SerialandUSB Programuptoeightdevicesatatime.WorkswithPCorstandalone. TexasInstruments 7.1.2.3 RecommendedSoftwareOptions 7.1.2.3.1 IntegratedDevelopmentEnvironments Software development tools are available from TI or from third parties. Open source solutions are also available. ThisdeviceissupportedbyCodeComposerStudio™IDE(CCS). 100 DeviceandDocumentationSupport Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 7.1.2.3.2 MSP430Ware MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing MSP430 design resources, MSP430Ware also includes a high-level API called MSP430 Driver Library. This library makes it easy to program MSP430 hardware. MSP430Ware is available as a component of CCSorasastandalonepackage. 7.1.2.3.3 Command-LineProgrammer MSP430 Flasher is an open-source shell-based interface for programming MSP430 microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher can be used to download binary files (.txt or .hex) files directly to the MSP430 microcontroller without the needforanIDE. 7.1.3 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These prefixes represent evolutionary stages of product development from engineering prototypes (XMS) throughfullyqualifiedproductiondevices(MSP). XMS – Experimental device that is not necessarily representative of the final device's electrical specifications MSP–Fullyqualifiedproductiondevice XMSdevicesareshippedagainstthefollowingdisclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." MSP devices have been characterized fully, and the quality and reliability of the device have been demonstratedfully.TI'sstandardwarrantyapplies. Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-usefailureratestillisundefined.Onlyqualifiedproductiondevicesaretobeused. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature range, package type, and distribution format. Figure 7-1 provides a legend for reading the completedevicename. Copyright©2006–2020,TexasInstrumentsIncorporated DeviceandDocumentationSupport 101 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com MSP 430 F 5 438 A I PM T -EP Processor Family Optional:Additional Features MCU Platform Optional:Tape and Reel DeviceType Packaging Series Optional:Temperature Range Feature Set Optional: Revision Processor Family CC = Embedded RF Radio MSP= Mixed-Signal Processor XMS = Experimental Silicon PMS = Prototype Device MCU Platform 430 = MSP430 low-power microcontroller platform Device Type Memory Type SpecializedApplication C = ROM AFE =Analog front end F = Flash BQ = Contactless power FR = FRAM CG = ROM medical G = Flash FE = Flash energy meter L= No nonvolatile memory FG = Flash medical FW = Flash electronic flow meter Series 1 = Up to 8 MHz 5 = Up to 25 MHz 2 = Up to 16 MHz 6 = Up to 25 MHz with LCD driver 3 = Legacy 0 = Low-voltage series 4 = Up to 16 MHz with LCD driver Feature Set Various levels of integration within a series Optional: Revision Updated version of the base part number Optional: Temperature Range S = 0°C to 50°C C = 0°C to 70°C I =–40°C to 85°C T=–40°C to 105°C Packaging http://www.ti.com/packaging Optional: Tape and Reel T= Small reel R = Large reel No markings =Tube or tray Optional:Additional Features -EP= Enhanced product (–40°C to 105°C) -HT= Extreme temperature parts (–55°C to 150°C) -Q1 =Automotive Q100 qualified Figure7-1.DeviceNomenclature 102 DeviceandDocumentationSupport Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 7.2 Documentation Support The following documents describe the MSP430FG461x and MSP430CG461x devices. Copies of these documentsareavailableontheInternetatwww.ti.com. SLAU056 MSP430F4xx Family User's Guide. Detailed information on the modules and peripherals availableinthisdevicefamily. SLAZ369 MSP430FG4619 Device Erratasheet. Describes the known exceptions to the functional specificationsforallsiliconrevisionsofthedevice. SLAZ368 MSP430FG4618 Device Erratasheet. Describes the known exceptions to the functional specificationsforallsiliconrevisionsofthedevice. SLAZ367 MSP430FG4617 Device Erratasheet. Describes the known exceptions to the functional specificationsforallsiliconrevisionsofthedevice. SLAZ366 MSP430FG4616 Device Erratasheet. Describes the known exceptions to the functional specificationsforallsiliconrevisionsofthedevice. SLAZ123 MSP430CG4619 Device Erratasheet. Describes the known exceptions to the functional specificationsforallsiliconrevisionsofthedevice. SLAZ122 MSP430CG4618 Device Erratasheet. Describes the known exceptions to the functional specificationsforallsiliconrevisionsofthedevice. SLAZ121 MSP430CG4617 Device Erratasheet. Describes the known exceptions to the functional specificationsforallsiliconrevisionsofthedevice. SLAZ120 MSP430CG4616 Device Erratasheet. Describes the known exceptions to the functional specificationsforallsiliconrevisionsofthedevice. 7.3 Related Links Table 7-1 lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table7-1.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY MSP430FG4619 Clickhere Clickhere Clickhere Clickhere Clickhere MSP430FG4618 Clickhere Clickhere Clickhere Clickhere Clickhere MSP430FG4617 Clickhere Clickhere Clickhere Clickhere Clickhere MSP430FG4616 Clickhere Clickhere Clickhere Clickhere Clickhere MSP430CG4619 Clickhere Clickhere Clickhere Clickhere Clickhere MSP430CG4618 Clickhere Clickhere Clickhere Clickhere Clickhere MSP430CG4617 Clickhere Clickhere Clickhere Clickhere Clickhere MSP430CG4616 Clickhere Clickhere Clickhere Clickhere Clickhere Copyright©2006–2020,TexasInstrumentsIncorporated DeviceandDocumentationSupport 103 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 SLAS508K–APRIL2006–REVISEDMAY2020 www.ti.com 7.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; seeTI's TermsofUse. TIE2E™Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. TIEmbeddedProcessorsWiki TexasInstruments Embedded Processors Wiki. Established to help developers get started with embedded processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardwareandsoftwaresurroundingthesedevices. 7.5 Trademarks MSP430,MicroStarJunior,CodeComposerStudio,E2EaretrademarksofTexasInstruments. 7.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 7.7 Export Control Notice Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extentrequiredbythoselaws. 7.8 Glossary TIGlossary Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 104 DeviceandDocumentationSupport Copyright©2006–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619,MSP430CG4618,MSP430CG4617,MSP430CG4616 www.ti.com SLAS508K–APRIL2006–REVISEDMAY2020 8 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revisionofthisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2006–2020,TexasInstrumentsIncorporated Mechanical,Packaging,andOrderableInformation 105 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616

PACKAGE OPTION ADDENDUM www.ti.com 1-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) MSP430FG4616IPZ ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430FG4616 & no Sb/Br) MSP430FG4616IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430FG4616 & no Sb/Br) MSP430FG4616IZCA ACTIVE NFBGA ZCA 113 260 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 FG4616 & no Sb/Br) MSP430FG4616IZCAR ACTIVE NFBGA ZCA 113 2500 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 FG4616 & no Sb/Br) MSP430FG4617IPZ ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430FG4617 & no Sb/Br) MSP430FG4617IZCAR ACTIVE NFBGA ZCA 113 2500 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 FG4617 & no Sb/Br) MSP430FG4617IZQWR LIFEBUY BGA ZQW 113 2500 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 M430FG4617 MICROSTAR & no Sb/Br) JUNIOR MSP430FG4618IPZ ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430FG4618 & no Sb/Br) MSP430FG4618IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430FG4618 & no Sb/Br) MSP430FG4618IZCA ACTIVE NFBGA ZCA 113 260 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 FG4618 & no Sb/Br) MSP430FG4618IZCAR ACTIVE NFBGA ZCA 113 2500 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 FG4618 & no Sb/Br) MSP430FG4618IZCAT ACTIVE NFBGA ZCA 113 250 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 FG4618 & no Sb/Br) MSP430FG4619IPZ ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430FG4619 & no Sb/Br) REV # MSP430FG4619IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430FG4619 & no Sb/Br) MSP430FG4619IZCAR ACTIVE NFBGA ZCA 113 2500 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 FG4619 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 1-Jul-2020 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 3-Sep-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) MSP430FG4616IPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2 MSP430FG4616IZCAR NFBGA ZCA 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 MSP430FG4617IZCAR NFBGA ZCA 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 MSP430FG4617IZQWR BGAMI ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 CROSTA RJUNI OR MSP430FG4618IPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2 MSP430FG4618IZCAR NFBGA ZCA 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 MSP430FG4618IZCAT NFBGA ZCA 113 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 MSP430FG4619IPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2 MSP430FG4619IZCAR NFBGA ZCA 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 3-Sep-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) MSP430FG4616IPZR LQFP PZ 100 1000 367.0 367.0 45.0 MSP430FG4616IZCAR NFBGA ZCA 113 2500 341.0 336.6 31.8 MSP430FG4617IZCAR NFBGA ZCA 113 2500 341.0 336.6 31.8 MSP430FG4617IZQWR BGAMICROSTAR ZQW 113 2500 350.0 350.0 43.0 JUNIOR MSP430FG4618IPZR LQFP PZ 100 1000 367.0 367.0 45.0 MSP430FG4618IZCAR NFBGA ZCA 113 2500 341.0 336.6 31.8 MSP430FG4618IZCAT NFBGA ZCA 113 250 341.0 336.6 31.8 MSP430FG4619IPZR LQFP PZ 100 1000 367.0 367.0 45.0 MSP430FG4619IZCAR NFBGA ZCA 113 2500 341.0 336.6 31.8 PackMaterials-Page2

MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 M 0,17 75 51 76 50 100 26 0,13 NOM 1 25 12,00 TYP Gage Plane 14,20 SQ 13,80 0,25 16,20 SQ 0,05 MIN 0°–7° 15,80 1,45 0,75 1,35 0,45 Seating Plane 1,60 MAX 0,08 4040149/B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

None

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PACKAGE OUTLINE ZCA0113A NFBGA - 1 mm max height PLASTIC BALL GRID ARRAY A 7.1 B 6.9 BALL A1 CORNER 7.1 6.9 1 MAX C SEATING PLANE 0.25 0.08 C 0.15 BALL TYP 5.5 (0.75) TYP TYP SYMM M L (0.75) TYP K J H SYMM 5.5 G TYP F E D C 113X Ø0.35 0.25 B 0.15 C A B A 0.05 C 0.5 TYP 1 2 3 4 5 6 7 8 9 10 1112 0.5 TYP 4225149/A 08/2019 NOTES: NanoFree is a trademark of Texas Instruments. 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT ZCA0113A NFBGA - 1 mm max height PLASTIC BALL GRID ARRAY (0.5) TYP (0.5) TYP 1 2 3 4 5 6 7 8 9 10 11 12 A B C D E 113X (Ø0.25) F SYMM G H J K L M SYMM LAND PATTERN EXAMPLE SCALE: 10X 0.05 MAX 0.05 MIN METAL UNDER ALL AROUND EXPOSED ALL AROUND SOLDER MASK METAL (Ø 0.25) METAL EXPOSED (Ø 0.25) SOLDER MASK METAL SOLDER MASK OPENING OPENING NON- SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4225149/A 08/2019 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments Literature number SNVA009 (www.ti.com/lit/snva009). www.ti.com

EXAMPLE STENCIL DESIGN ZCA0113A NFBGA - 1 mm max height PLASTIC BALL GRID ARRAY (0.5) TYP (0.5) TYP 1 2 3 4 5 6 7 8 9 10 11 12 A B C D (R0.05) E F SYMM G H J METAL TYP K L M 113X ( 0.25) SYMM SOLDER PASTE EXAMPLE BASED ON 0.100 mm THICK STENCIL SCALE: 10X 4225149/A 08/2019 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

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