MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 MSP430FG43x Mixed-Signal Microcontrollers 1 Device Overview 1.1 Features 1 • LowSupply-VoltageRange,1.8Vto3.6V • On-ChipComparator • Ultra-LowPowerConsumption • SerialCommunicationInterface(USART), – ActiveMode:300 µAat1MHz,2.2V SelectAsynchronousUARTorSynchronousSPI bySoftware – StandbyMode:1.1 µA • BrownoutDetector – OffMode(RAMRetention):0.1 µA • Supply-VoltageSupervisorandMonitorWith • FivePower-SavingModes ProgrammableLevelDetection • WakeupFromStandbyModeinLessThan6µs • BootstrapLoader(BSL) • 16-BitRISCArchitecture,125-nsInstructionCycle • SerialOnboardProgramming,NoExternal Time ProgrammingVoltageNeeded,Programmable • Single-ChannelInternalDMA CodeProtectionbySecurityFuse • 12-BitAnalog-to-DigitalConverter(ADC)With • IntegratedLiquidCrystalDisplay(LCD)Driverfor InternalReference,Sample-and-Holdand upto128Segments AutoscanFeature • Availablein113-BallBGA(ZCA)and80-PinQFP • ThreeConfigurableOperationalAmplifiers (PN)Packages • Dual12-BitDigital-to-AnalogConverters(DACs) • Section3 SummarizestheAvailableFamily WithSynchronization Members • 16-BitTimer_AWithThreeCapture/Compare • ForCompleteModuleDescriptions,Seethe Registers MSP430x4xxFamilyUser'sGuide(SLAU056) • 16-BitTimer_BWithThreeCapture/Compare- With-ShadowRegisters 1.2 Applications • AnalogandDigitalSensorSystems • Thermostats • DigitalMotorControl • DigitalTimers • RemoteControls • Hand-HeldMeters 1.3 Description The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-powermodestoactivemodeinlessthan6 µs. The MSP430FG43x devices are microcontrollers with two 16-bit timers, a high-performance 12-bit ADC, dual 12-bit DACs, three configurable operational amplifiers, one universal synchronous/asynchronous communicationinterface,DMA,48I/Opins,andanLCDdriver. Table1-1.DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(2) MSP430FG439PN LQFP(80) 12mmx12mm MSP430FG439ZCA BGA(113) 7mmx7mm (1) Forthemostcurrentdevice,package,andorderinginformation,seethePackageOptionAddenduminSection8,orseetheTIwebsite atwww.ti.com. (2) Thesizesshownhereareapproximations.Forthepackagedimensionswithtolerances,seetheMechanicalDatainSection8. 1 AnIMPORTANTNOTICEattheendofthisdatasheetaddressesavailability,warranty,changes,useinsafety-criticalapplications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 1.4 Functional Block Diagram Figure1-1showsthefunctionalblockdiagram. XIN XOUT DVCC1/2 DVSS1/2 AVCC AVSS P1 P2 P3 P4 P5 P6 8 8 8 8 8 8 ACLK XT2IN Oscillator Flash ADC12 DAC12 Port 1 Port2 XT2OUT FLL+ SMCLK RAM Port 3 Port 4 Port 5 Port 6 60KB 12-Biit 12-Bit 8 I/O 8 I/O 2KB MCLK 48KB 1KB 12Channels 2Channels Interrupt Interrupt 8 I/O 8 I/O 8 I/O 8 I/O 32KB <10µsConv. Voltage Out Capability Capability 8MHz MAB CPU incl.16 Registers MDB Emulation Module POR/ DMA WaTticmhedrog Timer_B3 Timer_A3 TBimaesirc 1 LCD USART0 OA0, OA1 SVS/ Controller WDT 3CCReg Comparator_ 128 OA2 Brownout Shadow 3CCReg A 1 Interrupt Segments UARTMode 1Channel 1,2,3,4 MUX SPIMode 3 Op Amps JTAG 15/16-Bit Reg Vector Interface fLCD RST/NMI Figure1-1.FunctionalBlockDiagram 2 DeviceOverview Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 Table of Contents 1 DeviceOverview......................................... 1 5.24 12-BitADC,Built-InReference...................... 28 .............................................. .................... 1.1 Features 1 5.25 12-BitADC,TimingParameters 30 ........................................... ................... 1.2 Applications 1 5.26 12-BitADC,LinearityParameters 30 ............................................ 1.3 Description 1 5.27 12-BitADC,TemperatureSensorandBuilt-InV 31 MID ............................ .................. 1.4 FunctionalBlockDiagram 2 5.28 12-BitDAC,SupplySpecifications 31 2 Revision History......................................... 4 5.29 12-BitDAC,LinearitySpecifications................ 32 3 Device Comparison..................................... 5 5.30 12-BitDAC,OutputSpecifications.................. 34 4 TerminalConfigurationandFunctions.............. 6 5.31 12-BitDAC,ReferenceInputSpecifications........ 35 ......................................... ................ 4.1 PinDiagrams 6 5.32 12-BitDAC,DynamicSpecifications 35 ................................... ... 4.2 SignalDescriptions 8 5.33 12-BitDAC,DynamicSpecifications(Continued) 36 5 Specifications........................................... 12 5.34 OperationalAmplifier(OA),SupplySpecifications.. 37 5.1 AbsoluteMaximumRatings ........................ 12 5.35 OperationalAmplifier(OA),Input/Output ........................................ .................................... Specifications 37 5.2 Handling Ratings 12 ............... 5.36 OperationalAmplifier(OA),DynamicSpecifications 38 5.3 RecommendedOperatingConditions 12 5.4 SupplyCurrentIntoAV +DV Excluding 5.37 OADynamicSpecificationsTypicalCharacteristics 38 CC CC .................................... ....................................... ExternalCurrent 14 5.38 FlashMemory 39 5.5 Schmitt-TriggerInputs–PortsP1toP6,RST/NMI, 5.39 JTAGInterface...................................... 39 ........... JTAG(TCK,TMS,TDI/TCLK,TDO/TDI) 15 ......................................... 5.40 JTAGFuse 39 ............................... 5.6 InputsPx.y,TAx,TBx 15 6 DetailedDescription................................... 40 ................. 5.7 LeakageCurrent–PortsP1toP6 15 ................................................. 6.1 CPU 40 ........................... 5.8 Outputs–PortsP1toP6 16 ....................................... 6.2 InstructionSet 41 ................................... 5.9 OutputFrequency 16 .................................... 6.3 OperatingModes 42 ................... 5.10 TypicalCharacteristics–Outputs 17 .......................... 6.4 InterruptVectorAddresses 43 ............................... 5.11 Wake-UpFromLPM3 18 ................. 6.5 SpecialFunctionRegisters(SFRs) 44 ................................................. 5.12 RAM 18 ............................... 6.6 Memory Organization 46 .................................................. 5.13 LCD 18 ............................. 6.7 BootstrapLoader(BSL) 47 ...................................... 5.14 Comparator_A 19 ....................................... 6.8 FlashMemory 47 .............. 5.15 Comparator_ATypicalCharacteristics 19 .......................................... 6.9 Peripherals 48 5.16 Power-OnReset(POR)andBrownoutReset(BOR) ............................ ...................................................... 6.10 Input/OutputSchematics 55 21 7 DeviceandDocumentationSupport............... 78 5.17 SupplyVoltageSupervisor(SVS)andSupply VoltageMonitor(SVM) ............................. 22 7.1 DeviceSupport...................................... 78 5.18 DCO................................................. 24 7.2 DocumentationSupport............................. 80 5.19 CrystalOscillator,XT1Oscillator ................... 26 7.3 Trademarks.......................................... 80 5.20 CrystalOscillator,XT2Oscillator ................... 26 7.4 ElectrostaticDischargeCaution..................... 80 5.21 USART0 ............................................ 26 7.5 Glossary............................................. 80 5.22 12-BitADC,PowerSupplyandInputRange 8 MechanicalPackagingandOrderable Conditions .......................................... 27 Information.............................................. 81 5.23 12-BitADC,ExternalReference ................... 27 8.1 PackagingInformation .............................. 81 Copyright©2004–2014,TexasInstrumentsIncorporated TableofContents 3 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 2 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(March2011)toRevisionD Page • Documentformatandorganizationchangesthroughout,includingadditionofsectionnumbering........................ 1 • AddedSection1.2 ................................................................................................................... 1 • AddedDeviceInformationtable .................................................................................................... 1 • AddedSection3...................................................................................................................... 5 • AddedZCApackagepinout......................................................................................................... 7 • AddedZCApackagetoTable4-1.................................................................................................. 8 • AddedSection5andmovedallelectricalspecificationstoit ................................................................. 12 • AddedSection5.2andmovedT toit.......................................................................................... 12 stg • AddedZCApackagetoBSLtable................................................................................................ 47 • AddedZCApackagetoTimer_A3table.......................................................................................... 49 • AddedZCApackagetoTimer_B3table ......................................................................................... 50 • MovedSection6.10................................................................................................................. 55 • ChangedthevaluesinthePort/LCDcolumn ................................................................................... 59 • Changedtheinputsignals(LCDPx[0:2])inthetopleftofthefigure......................................................... 60 • Changedtheinputsignal(LCDPx[2])inthetopleftofthefigure............................................................. 61 • ChangedthevaluesintheDEVICE,PORTFUNCTION,andLCDSEGMENTFUNCTIONcolumns................... 62 • Changedtheinput"1,IfLCDPx≥01h"nearthetopleftofthefigure ....................................................... 63 • ChangedthevaluesintheDEVICE,PORTFUNCTION,andLCDSEGMENTFUNCTIONcolumns................... 63 • Changedtheinput"1,IfLCDPx≥01h"nearthetopleftofthefigure ....................................................... 64 • ChangedthevaluesintheDEVICE,PORTFUNCTION,andLCDSEGMENTFUNCTIONcolumns................... 64 • Changedtheinput"1,IfLCDPx≥01h"nearthetopleftofthefigure ....................................................... 65 • ChangedthevaluesintheDEVICE,PORTFUNCTION,andLCDSEGMENTFUNCTIONcolumns................... 65 • Changedtheinput"1,IfLCDPx≥01h"nearthetopleftofthefigure ....................................................... 66 • ChangedtheLCDPxcolumnheadingandvalues.............................................................................. 66 • ChangedthevalueinthePort/LCDcolumn..................................................................................... 66 • AddedSection7..................................................................................................................... 78 • AddedSection8 .................................................................................................................... 81 4 RevisionHistory Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 3 Device Comparison Thefollowingtablesummarizestheavailablefamilymembers. Table3-1.DeviceComparison(1)(2) Device FLASH SRAM ADC12 DAC12 Comp_A Timer_A(3) Timer_B(4) USART LCD I/Os Package (KB) (KB) Type 12 16 80PN MSP430FG439 60 2 2channels 3 3 Yes Yes 48 channels channels 113ZCA 12 16 80PN MSP430FG438 48 2 2channels 3 3 Yes Yes 48 channels channels 113ZCA 12 16 80PN MSP430FG437 32 1 2channels 3 3 Yes Yes 48 channels channels 113ZCA (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddenduminSection8,orseetheTIwebsiteat www.ti.com. (2) Packagedrawings,standardpackingquantities,thermaldata,symbolization,andPCBdesignguidelinesareavailableat www.ti.com/packaging. (3) EachnumberinthesequencerepresentsaninstantiationofTimer_Awithitsassociatednumberofcapture/compareregistersandPWM outputgeneratorsavailable.Forexample,anumbersequenceof3,5wouldrepresenttwoinstantiationsofTimer_A,thefirst instantiationhaving3capture/compareregistersandPWMoutputgeneratorsandthesecondinstantiationhaving5capture/compare registersandPWMoutputgenerators,respectively. (4) EachnumberinthesequencerepresentsaninstantiationofTimer_Bwithitsassociatednumberofcapture/compareregistersandPWM outputgeneratorsavailable.Forexample,anumbersequenceof3,5wouldrepresenttwoinstantiationsofTimer_B,thefirst instantiationhaving3capture/compareregistersandPWMoutputgeneratorsandthesecondinstantiationhaving5capture/compare registersandPWMoutputgenerators,respectively. Copyright©2004–2014,TexasInstrumentsIncorporated DeviceComparison 5 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 4 Terminal Configuration and Functions 4.1 Pin Diagrams Figure4-1showsthepinassignmentsforthe80-pinPNpackage. T U O K VS CL K K S M CL VCCVSS1VSS6.2/A2/OA0I16.1/A1/OA0O 6.0/A0/OA0I0 ST/NMI CK MSDI/TCLK DO/TDI T2IN T2OUT 1.0/TA0 1.1/TA0/MCL1.2/TA11.3/TBOUTH/ 1.4/TBCLK/S 1.5/TACLK/A1.6/CA0 A D A PP P R T TT T X X P PPP P PP 80 7978 77 76 7574 73 7271 70 69 68 67 6665 64 63 62 61 DVCC1 1 60 P1.7/CA1 P6.3/A3/OA1I1/OA1O 2 59 P2.0/TA2 P6.4/A4/OA1I0 3 58 P2.1/TB0 P6.5/A5/OA2I1/OA2O 4 57 P2.2/TB1 P6.6/A6/DAC0/OA2I0 5 56 P2.3/TB2 P6.7/A7/DAC1/SVSIN 6 55 P2.4/UTXD0 VREF+ 7 54 P2.5/URXD0 XIN 8 53 DVSS2 XOUT 9 52 DVCC2 VeREF+/DAC0 10 51 P5.7/R33 VREF-/VeREF- 11 50 P5.6/R23 P5.1/S0/A12/DAC1 12 49 P5.5/R13 P5.0/S1/A13 13 48 R03 P4.7/S2/A14 14 47 P5.4/COM3 P4.6/S3/A15 15 46 P5.3/COM2 P4.5/S4 16 45 P5.2/COM1 P4.4/S5 17 44 COM0 P4.3/S6 18 43 P3.0/STE0/S31 P4.2/S7 19 42 P3.1/SIMO0/S30 P4.1/S8 20 41 P3.2/SOMI0/S29 21 22 23 24 25 26 2728 29 30 31 32 33 3435 36 37 38 39 40 90 1 2 3 45 6 78 9 0 1 2 3 4 0 67 8 S1 1 1 1 11 1 11 1 2 2 2 2 2 E 22 2 P4.0/S S S S SS S SLK/S UT/S S S S S 3.7/S DMA 3.5/S3.4/S K0/S DC12C 6/CAO P 6/S25/ PP 3/UCL A 2. 3. 3. 7/ P P P 2. P Figure4-1.80-PinPNPackage(TopView) 6 TerminalConfigurationandFunctions Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 Figure4-2showsthepinassignmentsforthe113-pinZCApackage. ZCAPACKAGE (TOPVIEW) DVSS AVSS AVCC P6.1 P6.0 RST XT2INXT2OUTDVSS P1.3 P1.6 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 DVCC DVSS AVCC P6.2 P6.3 DVSS DVSS DVSS P1.2 P1.5 P1.7 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 VREF+ DVCC DVSS P2.0 P2.4/TX C1 C2 C3 C11 C12 AVSS P6.7 P6.5 P6.4 TMS TDO P1.0 P1.1 P2.1 P2.5/RX D1 D2 D4 D5 D6 D7 D8 D9 D11 D12 XIN AVSS P6.6 TCK TDI P1.4 P2.2 DVSS2 E1 E2 E4 E5 E6 E7 E8 E9 E11 E12 XOUT AVSS P5.1 P2.3 DVCC2 F1 F2 F4 F5 F8 F9 F11 F12 AVSS AVSS P5.0 COM3 R33 G1 G2 G4 G5 G8 G9 G11 G12 VeREF+ AVSS P4.7 COM2 R23 H1 H2 H4 H5 H6 H7 H8 H9 H11 H12 VREF- AVSS P4.6 S13 S16 S21 S22 S23 COM1 R13 J1 J2 J4 J5 J6 J7 J8 J9 J11 J12 P4.5 P4.4 COM0 R03 K1 K2 K11 K12 P4.1 P4.2 P4.3 S11 S14 S17 S20 P3.6/S25P3.5/S26P3.4/S27 P3.0/S31 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 P4.0 S10 S12 S15 P2.7/S18P2.6/S19P3.7/S24P3.3/S28P3.2/S29P3.1/S30 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 Figure4-2.113-PinZCAPackage(TopView) Copyright©2004–2014,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 7 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 4.2 Signal Descriptions Table4-1describesthesignalsforalldevicevariantsandpackageoptions. Table4-1.SignalDescriptions TERMINAL NO. I/O DESCRIPTION NAME PN ZCA DVCC1 1 B1,C2 Digitalsupplyvoltage,positiveterminal. P6.3/A3/OA1I1/OA1O General-purposedigitalI/O 2 B5 I/O Analoginputa3—12-bitADC OA1outputand/orinputmultiplexeron+terminaland−terminal P6.4/A4/OA1I0 General-purposedigitalI/O 3 D5 I/O Analoginputa4—12-bitADC OA1inputmultiplexeron+terminaland−terminal P6.5/A5/OA2I1/OA2O General-purposedigitalI/O 4 D4 I/O Analoginputa5—12-bitADC OA2outputand/orinputmultiplexeron+terminaland−terminal P6.6/A6/DAC0/OA2I0 General-purposedigitalI/O Analoginputa6—12-bitADC 5 E4 I/O DAC12.0output OA2inputmultiplexeron+terminaland−terminal P6.7/A7/DAC1/SVSIN General-purposedigitalI/O 6 D2 I/O Analoginputa7—12-bitADC DAC12.1output/analoginputtosupplyvoltagesupervisor VREF+ 7 C1 O PositiveoutputterminalofthereferencevoltageintheADC XIN 8 E1 I InputterminalofcrystaloscillatorXT1 XOUT 9 F1 O OutputterminalofcrystaloscillatorXT1 VeREF+/DAC0 Positiveinputterminalforanexternalreferencevoltagetothe12-bit 10 H1 I/O ADC/DAC12.0output VREF−/VeREF− Negativeterminalforthe12-bitADC'sreferencevoltageforbothsources,the 11 J1 I internalreferencevoltageoranexternalappliedreferencevoltagetothe12-bit ADC. P5.1/S0/A12/DAC1 General-purposedigitalI/O LCDsegmentoutput0 12 F4 I/O Analoginputa12—12-bitADC DAC12.1output P5.0/S1/A13 General-purposedigitalI/O 13 G4 I/O LCDsegmentoutput1 Analoginputa13—12-bitADC P4.7/S2/A14 General-purposedigitalI/O 14 H4 I/O LCDsegmentoutput2 Analoginputa14—12-bitADC P4.6/S3/A15 General-purposedigitalI/O 15 J4 I/O LCDsegmentoutput3 Analoginputa15—12-bitADC P4.5/S4 General-purposedigitalI/O 16 K1 I/O LCDsegmentoutput4 P4.4/S5 General-purposedigitalI/O 17 K2 I/O LCDsegmentoutput5 P4.3/S6 General-purposedigitalI/O 18 L3 I/O LCDsegmentoutput6 P4.2/S7 General-purposedigitalI/O 19 L2 I/O LCDsegmentoutput7 P4.1/S8 General-purposedigitalI/O 20 L1 I/O LCDsegmentoutput8 P4.0/S9 General-purposedigitalI/O 21 M2 I/O LCDsegmentoutput9 S10 22 M3 O LCDsegmentoutput10 8 TerminalConfigurationandFunctions Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 Table4-1.SignalDescriptions(continued) TERMINAL NO. I/O DESCRIPTION NAME PN ZCA S11 23 L4 O LCDsegmentoutput11 S12 24 M4 O LCDsegmentoutput12 S13 25 J5 O LCDsegmentoutput13 S14 26 L5 O LCDsegmentoutput14 S15 27 M5 O LCDsegmentoutput15 S16 28 J6 O LCDsegmentoutput16 S17 29 L6 O LCDsegmentoutput17 P2.7/ADC12CLK/S18 General-purposedigitalI/O 30 M6 I/O Conversionclock—12-bitADC LCDsegmentoutput18 P2.6/CAOUT/S19 General-purposedigitalI/O 31 M7 I/O Comparator_Aoutput/LCDsegmentoutput19 S20 32 L7 O LCDsegmentoutput20 S21 33 J7 O LCDsegmentoutput21 S22 34 J8 O LCDsegmentoutput22 S23 35 J9 O LCDsegmentoutput23 P3.7/S24 General-purposedigitalI/O 36 M8 I/O LCDsegmentoutput24 P3.6/S25/DMAE0 General-purposedigitalI/O 37 L8 I/O LCDsegmentoutput25/DMAChannel0externaltrigger P3.5/S26 General-purposedigitalI/O 38 L9 I/O LCDsegmentoutput26 P3.4/S27 General-purposedigitalI/O 39 L10 I/O LCDsegmentoutput27 P3.3/UCLK0/S28 General-purposedigitalI/O Externalclockinput—USART0/UARTorSPImode,clockoutput—USART0/SPI 40 M9 I/O mode LCDsegmentoutput28 P3.2/SOMI0/S29 General-purposedigitalI/O 41 M10 I/O Slaveout/masterinofUSART0/SPImode LCDsegmentoutput29 P3.1/SIMO0/S30 General-purposedigitalI/O 42 M11 I/O Slavein/masteroutofUSART0/SPImode LCDsegmentoutput30 P3.0/STE0/S31 General-purposedigitalI/O 43 L12 I/O Slavetransmitenable-USART0/SPImode LCDsegmentoutput31 COM0 44 K11 O Commonoutput,COM0−3areusedforLCDbackplanes. P5.2/COM1 General-purposedigitalI/O 45 J11 I/O Commonoutput,COM0−3areusedforLCDbackplanes. P5.3/COM2 General-purposedigitalI/O 46 H11 I/O Commonoutput,COM0−3areusedforLCDbackplanes. P5.4/COM3 General-purposedigitalI/O 47 G11 I/O Commonoutput,COM0−3areusedforLCDbackplanes. R03 48 K12 I Inputportoffourthpositive(lowest)analogLCDlevel(V5) P5.5/R13 General-purposedigitalI/O 49 J12 I/O inputportofthirdmostpositiveanalogLCDlevel(V4orV3) P5.6/R23 General-purposedigitalI/O 50 H12 I/O InputportofsecondmostpositiveanalogLCDlevel(V2) P5.7/R33 General-purposedigitalI/O 51 G12 I/O OutputportofmostpositiveanalogLCDlevel(V1) DVCC2 52 F12 Digitalsupplyvoltage,positiveterminal Copyright©2004–2014,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 9 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com Table4-1.SignalDescriptions(continued) TERMINAL NO. I/O DESCRIPTION NAME PN ZCA DVSS2 53 E12 Digitalsupplyvoltage,negativeterminal P2.5/URXD0 General-purposedigitalI/O 54 D12 I/O Receivedatain—USART0/UARTmode P2.4/UTXD0 General-purposedigitalI/O 55 C12 I/O Transmitdataout—USART0/UARTmode P2.3/TB2 General-purposedigitalI/O 56 F11 I/O Timer_B3CCR2.Capture:CCI2A/CCI2Binput,compare:Out2output P2.2/TB1 General-purposedigitalI/O 57 E11 I/O Timer_B3CCR1.Capture:CCI1A/CCI1Binput,compare:Out1output P2.1/TB0 General-purposedigitalI/O 58 D11 I/O Timer_B3CCR0.Capture:CCI0A/CCI0Binput,compare:Out0output P2.0/TA2 General-purposedigitalI/O 59 C11 I/O Timer_ACapture:CCI2Ainput,compare:Out2output P1.7/CA1 General-purposedigitalI/O 60 B12 I/O Comparator_Ainput P1.6/CA0 General-purposedigitalI/O 61 A11 I/O Comparator_Ainput P1.5/TACLK/ACLK General-purposedigitalI/O 62 B10 I/O Timer_A,clocksignalTACLKinput ACLKoutput(dividedby1,2,4,or8) P1.4/TBCLK/SMCLK General-purposedigitalI/O 63 E9 I/O InputclockTBCLK—Timer_B3 SubmainsystemclockSMCLKoutput P1.3/TBOUTH/SVSOUT General-purposedigitalI/O 64 A10 I/O SwitchallPWMdigitaloutputportstohighimpedance—Timer_B3TB0toTB2 SVS:outputofSVScomparator P1.2/TA1 General-purposedigitalI/O 65 B9 I/O Timer_A,Capture:CCI1A,compare:Out1output P1.1/TA0/MCLK General-purposedigitalI/O 66 D9 I/O Timer_A.Capture:CCI0B/MCLKoutput.Note:TA0isonlyaninputonthispin BSLreceive P1.0/TA0 General-purposedigitalI/O 67 D8 I/O Timer_A.Capture:CCI0Ainput,compare:Out0output BSLtransmit XT2OUT 68 A8 O OutputterminalofcrystaloscillatorXT2 XT2IN 69 A7 I InputportforcrystaloscillatorXT2.Onlystandardcrystalscanbeconnected. TDO/TDI 70 D7 I/O Testdataoutputport.TDO/TDIdataoutputorprogrammingdatainputterminal TDI/TCLK Testdatainputortestclockinput.Thedeviceprotectionfuseisconnectedto 71 E7 I TDI/TCLK. TMS 72 D6 I Testmodeselect.TMSisusedasaninputportfordeviceprogrammingandtest. TCK 73 E6 I Testclock.TCKistheclockinputportfordeviceprogrammingandtest. RST/NMI 74 A6 I Resetornonmaskableinterruptinput P6.0/A0/OA0I0 General-purposedigitalI/O 75 A5 I/O Analoginputa0−12-bitADC OA0inputmultiplexeron+terminaland−terminal P6.1/A1/OA0O General-purposedigitalI/O 76 A4 I/O Analoginputa1−12-bitADC OA0output P6.2/A2/OA0I1 General-purposedigitalI/O 77 B4 I/O Analoginputa2−12-bitADC OA0inputmultiplexeron+terminaland−terminal 10 TerminalConfigurationandFunctions Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 Table4-1.SignalDescriptions(continued) TERMINAL NO. I/O DESCRIPTION NAME PN ZCA AVSS A2,D1, Analogsupplyvoltage,negativeterminal.SuppliesSVS,brownout,oscillator, E2,F2, comparator_A,port1,andLCDresistivedividercircuitry. 78 G2,G1, H2,J2 DVSS1 A1,B2, Digitalsupplyvoltage,negativeterminal C3,B6, 79 B7,B8, A9 AVCC Analogsupplyvoltage,positiveterminal.SuppliesSVS,brownout,oscillator, 80 A3,B3 comparator_A,port1,andLCDresistivedividercircuitry;mustnotpowerupprior toDVCC1/DVCC2. Reserved (1) Reserved (1) A12,B11,E5,E8,F5,F8,F9,G5,G8,G9,H5,H6,H7,H8,H9,L11,M1,M12arereservedandshouldbeconnectedtoground. Copyright©2004–2014,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 11 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 5 Specifications 5.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT VoltageappliedatV toV –0.3 4.1 V CC SS Voltageappliedtoanypin(2) –0.3 V +0.3 V CC Diodecurrentatanydeviceterminal ±2 mA (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesreferencedtoV .TheJTAGfuse-blowvoltage,V ,isallowedtoexceedtheabsolutemaximumrating.Thevoltageis SS FB appliedtotheTDI/TCLKpinwhenblowingtheJTAGfuse. 5.2 Handling Ratings MIN MAX UNIT Unprogrammeddevice -55 150 T Storagetemperaturerange °C stg Programmeddevice -40 85 5.3 Recommended Operating Conditions MIN NOM MAX UNIT Duringprogramexecution 1.8 3.6 Supplyvoltage(1) Duringprogramexecution, VCC (AVCC=DVCC1=DVCC2=V ) SVSenabledandPORON=1(2) 2 3.6 V CC Duringflashmemoryprogramming 2.7 3.6 Supplyvoltage(1) V 0 0 V SS (AVSS=DVSS1=DVSS2=V ) SS T Operatingfree-airtemperaturerange –40 85 °C A LFselected,XTS_FLL=0 Watchcrystal 32.768 f XT1crystalfrequency(3) XT1selected,XTS_FLL=1 Ceramicresonator 450 8000 kHz (LFXT1) XT1selected,XTS_FLL=1 Crystal 1000 8000 Ceramicresonator 450 8000 f XT2crystalfrequency kHz (XT2) Crystal 1000 8000 V =1.8V dc 4.15 CC f Processorfrequency(signalMCLK) MHz (System) V =3.6V dc 8 CC (1) ItisrecommendedtopowerAV andDV fromthesamesource.Amaximumdifferenceof0.3VbetweenAV andDV canbe CC CC CC CC toleratedduringpowerupandoperation. (2) TheminimumoperatingsupplyvoltageisdefinedaccordingtothetrippointwherePORisgoingactivebydecreasingthesupply voltage.PORisgoinginactivewhenthesupplyvoltageisraisedabovetheminimumsupplyvoltageplusthehysteresisoftheSVS circuitry. (3) InLFmode,theLFXT1oscillatorrequiresawatchcrystal.InXT1mode,LFXT1acceptsaceramicresonatororacrystal. 12 Specifications Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 8 Supply voltage range, Supply voltage range,MSP430FG43x, MSP430FG43x,during z during flash memory programming H program execution M – m) Syste 4.15 f( 1.8 2.7 3 3.6 SupplyVoltage- V Figure5-1.FrequencyvsSupplyVoltage,TypicalCharacteristic Copyright©2004–2014,TexasInstrumentsIncorporated Specifications 13 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 5.4 Supply Current Into AV + DV Excluding External Current CC CC overrecommendedoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER T V MIN TYP MAX UNIT A CC Activemode(1) 2.2V 300 370 f =f =1MHz, I (MCLK) (SMCLK) –40°Cto85°C µA (AM) f(ACLK)=32768Hz, 3V 470 570 XTS_FLL=0,SELM=(0,1) 2.2V 55 70 I Low-powermode(LPM0)(1) (2) –40°Cto85°C µA (LPM0) 3V 95 110 Low-powermode(LPM2), 2.2V 11 14 I f =f =0MHz, –40°Cto85°C µA (LPM2) (MCLK) (SMCLK) f =32768Hz,SCG0=0(3) (2) 3V 17 22 (ACLK) –40°C 1 2 25°C 1.1 2 2.2V 60°C 2 3 Low-powermode(LPM3) 85°C 3.5 6 I f =f =0MHz, µA (LPM3) (MCLK) (SMCLK) f =32768Hz,SCG0=1(3) (4) (2) –40°C 1.8 2.8 (ACLK) 25°C 1.6 2.7 3V 60°C 2.5 3.5 85°C 4.2 7.5 –40°C 0.1 0.5 25°C 0.1 0.5 2.2V 60°C 0.7 1.1 Low-powermode(LPM4) 85°C 1.7 3 I f =f =0MHz, µA (LPM4) (MCLK) (SMCLK) f =0Hz,SCG0=1(3) (2) –40°C 0.1 0.8 (ACLK) 25°C 0.1 0.8 3V 60°C 0.8 1.2 85°C 1.9 3.5 (1) Timer_Bisclockedbyf =f =1MHz.Allinputsaretiedto0VortoV .Outputsdonotsourceorsinkanycurrent. (DCOCLK) (DCO) CC (2) Currentforbrownoutincluded. (3) Allinputsaretiedto0VortoV .Outputsdonotsourceorsinkanycurrent. CC (4) ThecurrentconsumptioninLPM3ismeasuredwithactiveBasicTimer1andLCD(ACLKselected).Thecurrentconsumptionofthe Comparator_AandtheSVSmodulearespecifiedintherespectivesections.TheLPM3currentsarecharacterizedwithaKDS DaishinkuDT−38(6pF)crystalandOSCCAPx=01h. Currentconsumptionofactivemodeversussystemfrequency: I =I [1MHz]× f [MHz] (AM) (AM) (System) Currentconsumptionofactivemodeversussupplyvoltage: I =I +175µA/V×(V –3V) (AM) (AM)[3V] CC 14 Specifications Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 5.5 Schmitt-Trigger Inputs – Ports P1 to P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI) overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER V MIN MAX UNIT CC 2.2V 1.1 1.55 V Positive-goinginputthresholdvoltage V IT+ 3V 1.5 1.98 2.2V 0.4 0.9 V Negative-goinginputthresholdvoltage V IT– 3V 0.9 1.3 2.2V 0.3 1.1 V Inputvoltagehysteresis(V –V ) V hys IT+ IT– 3V 0.5 1 5.6 Inputs Px.y, TAx, TBx overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC PortP1,P2:P1.xtoP2.x,externaltriggersignal 2.2V 62 t(int) Externalinterrupttiming fortheinterruptflag(1) 3V 50 ns TA0,TA1,TA2 2.2V 62 t Timer_AorTimer_Bcapturetiming ns (cap) TB0,TB1,TB2 3V 50 f(TAext) Timer_AorTimer_Bclock 2.2V 8 TACLK,TBCLK,INCLK:t =t MHz f frequencyexternallyappliedtopin (H) (L) 3V 10 (TBext) f(TAint) Timer_AorTimer_Bclock 2.2V 8 SMCLKorACLKsignalselected MHz f frequency 3V 10 (TBint) (1) Theexternalsignalsetstheinterruptflageverytimetheminimumt parametersaremet.Itmightbesetwithtriggersignalsshorter (int) thant . (int) 5.7 Leakage Current – Ports P1 to P6(1) overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT I Leakagecurrent,PortPx V(Px.y)(2) V =2.2V,3V ±50 nA lkg(Px.y) CC (1) TheleakagecurrentismeasuredwithV orV appliedtothecorrespondingpins,unlessotherwisenoted. SS CC (2) Theportpinmustbeselectedasinput. Copyright©2004–2014,TexasInstrumentsIncorporated Specifications 15 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 5.8 Outputs – Ports P1 to P6 overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT I =–1.5mA,V =2.2V(1) V –0.25 V OH(max) CC CC CC I =–6mA,V =2.2V(2) V –0.6 V OH(max) CC CC CC V High-leveloutputvoltage V OH I =–1.5mA,V =3V(1) V –0.25 V OH(max) CC CC CC I =–6mA,V =3V(2) V –0.6 V OH(max) CC CC CC I =1.5mA,V =2.2V(1) V V +0.25 OL(max) CC SS SS I =6mA,V =2.2V(2) V V +0.6 OL(max) CC SS SS V Low-leveloutputvoltage V OL I =1.5mA,V =3V(1) V V +0.25 OL(max) CC SS SS I =6mA,V =3V(2) V V +0.6 OL(max) CC SS SS (1) Themaximumtotalcurrent,I andI ,foralloutputscombined,shouldnotexceed±12mAtosatisfythemaximumspecified OH(max) OL(max) voltagedrop. (2) Themaximumtotalcurrent,I andI ,foralloutputscombined,shouldnotexceed±48mAtosatisfythemaximumspecified OH(max) OL(max) voltagedrop. 5.9 Output Frequency overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT C =20F, f (1≤×≤6,0≤y≤7) L V =2.2V,3V dc f MHz (Px.y) I =±1.5mA CC (System) L f P1.1/TA0/MCLK (MCLK) f P1.4/TBCLK/SMCLK C =20pF f MHz (SMCLK) L (System) f P1.5/TACLK/ACLK (ACLK) f =f =f 40% 60% P1.5/TACLK/ACLK, (ACLK) (LFXT1) (XT1) C =20pF, f =f =f 30% 70% L (ACLK) (LFXT1) (LF) V =2.2V,3V CC f =f 50% (ACLK) (LFXT1) P1.1/TA0/MCLK, f(MCLK)=f(XT1) 40% 60% t(Xdc) Dutycycleofoutputfrequency CL=20pF, 50%– 50%+ VCC=2.2V,3V f(MCLK)=f(DCOCLK) 15ns 50% 15ns P1.4/TBCLK/SMCLK, f(SMCLK)=f(XT2) 40% 60% CL=20pF, 50%– 50%+ VCC=2.2V,3V f(SMCLK)=f(DCOCLK) 15ns 50% 15ns 16 Specifications Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 5.10 Typical Characteristics – Outputs overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) 16 25 A VCC= 2.2V TA= 25°C VCC= 3V m 14 P2.7 mA P2.7 TA= 25°C Current - 12 TA= 85°C urrent - 20 TA= 85°C put 10 ut C 15 Out utp vel 8 el O e v ow-l 6 w-le 10 L o cal 4 al L ypi pic 5 T y T - 2 L - O L O I 0 I 0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOL- Low-Level OutputVoltage - V VOL- Low-Level OutputVoltage - V Figure5-2. TypicalLow-LevelOutputCurrentvsTypicalLow- Figure5-3. TypicalLow-LevelOutputCurrentvsTypicalLow- LevelOutputCurrent LevelOutputCurrent 0 0 VCC= 2.2V VCC= 3V A P2.7 A P2.7 m -2 m nt - nt - -5 urre -4 urre C C -10 ut ut utp -6 utp pical High-level O -1-80 TA= 85°C pical High-level O --2105 TA= 85°C -TyL -12 -TyL -25 TA= 25°C O TA= 25°C O I -14 I -30 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH- High-Level OutputVoltage - V VOH- High-LevelOutputVoltage- V Figure5-4. TypicalHigh-LevelOutputCurrentvsTypicalHigh- Figure5-5. TypicalHigh-LevelOutputCurrentvsTypicalHigh- LevelOutputCurrent LevelOutputCurrent Copyright©2004–2014,TexasInstrumentsIncorporated Specifications 17 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 5.11 Wake-Up From LPM3 overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT f=1MHz 6 t Delaytime f=2MHz V =2.2V,3V 6 µs d(LPM3) CC f=3MHz 6 5.12 RAM overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT V CPUhalted(1) 1.6 V RAMh (1) ThisparameterdefinestheminimumsupplyvoltagewhenthedatainprogrammemoryRAMremainunchanged.Noprogramexecution shouldtakeplaceduringthissupplyvoltagecondition. 5.13 LCD overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V VoltageatP5.7/R33 2.5 V +0.2 (33) CC V VoltageatP5.6/R23 [V −V ]×2/3+V (23) (33) (03) (03) Analogvoltage V =3V V CC V VoltageatP5.5/R13 [V −V ]×1/3+V (13) (33) (03) (03) V -V VoltageatR33toR03 2.5 V +0.2 (33) (03) CC I R03=V Noloadatall ±20 (R03) SS segmentand I(R13) Inputleakage P5.5/R13=VCC/3 commonlines, ±20 nA I(R23) P5.6/R23=2×VCC/3 VCC=3V ±20 V V V -1 (Sxx0) (03) (03) V(Sxx1) Segmentline V(13) V(13)-1 I =−3µA,V =3V V V voltage (Sxx) CC V V -1 (Sxx2) (23) (23) V V V -1 (Sxx3) (33) (33) 18 Specifications Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 5.14 Comparator_A(1) overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 2.2V 25 40 I CAON=1,CARSEL=0,CAREF=0 µA (CC) 3V 45 60 CAON=1,CARSEL=0,CAREF=(1,2,3), 2.2V 30 50 I µA (Refladder/RefDiode) NoloadatP1.6/CA0andP1.7/CA1 3V 45 71 (Voltageat0.25V node)/ PCA0=1,CARSEL=1,CAREF=1, V CC 2.2V,3V 0.23 0.24 0.25 (Ref025) V NoloadatP1.6/CA0andP1.7/CA1 CC (Voltageat0.55V node)/ PCA0=1,CARSEL=1,CAREF=2, V CC 2.2V,3V 0.47 0.48 0.5 (Ref050) V NoloadatP1.6/CA0andP1.7/CA1 CC PCA0=1,CARSEL=1,CAREF=3, 2.2V 390 480 540 V SeeFigure5-6andFigure5-7 NoloadatP1.6/CA0andP1.7/CA1, mV (RefVT) T =85°C 3V 400 490 550 A Common-modeinput V V CAON=1 2.2V,3V 0 CC V IC voltagerange –1 V –V Offsetvoltage See (2) 2.2V,3V –30 30 mV p S V Inputhysteresis CAON=1 2.2V,3V 0 0.7 1.4 mV hys T =25°C, 2.2V 160 210 300 A ns Overdrive10mV,withoutfilter:CAF=0 3V 80 150 240 t (responseLH) T =25°C, 2.2V 1.4 1.9 3.4 A µs Overdrive10mV,withfilter:CAF=1 3V 0.9 1.5 2.6 t(responseHL) TA=25°C, 2.2V 130 210 300 ns Overdrive10mV,withoutfilter:CAF=0 3V 80 150 240 T =25°C, 2.2V 1.4 1.9 3.4 A µs Overdrive10mV,withfilter:CAF=1 3V 0.9 1.5 2.6 (1) TheleakagecurrentfortheComparator_AterminalsisidenticaltoI specification. lkg(Px.y) (2) TheinputoffsetvoltagecanbecancelledbyusingtheCAEXbittoinverttheComparator_Ainputsonsuccessivemeasurements.The twosuccessivemeasurementsarethensummedtogether. 5.15 Comparator_A Typical Characteristics 650 650 V = 2.2 V V = 3 V CC CC mV 600 mV 600 - - Reference Voltage 555000 Typical Reference Voltage 555000 Typical - - VREF VREF 450 450 400 400 -45 -25 -5 15 35 55 75 95 -45 -25 -5 15 35 55 75 95 T -Free-Air Temperature-°C T -Free-Air Temperature-°C A A Figure5-6. ReferenceVoltagevsFree-AirTemperature Figure5-7. ReferenceVoltagevsFree-AirTemperature Copyright©2004–2014,TexasInstrumentsIncorporated Specifications 19 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 0 V VCC 0 1 CAF CAON Low-Pass Filter To Internal Modules 0 0 V+ + _ V- 1 1 CAOUT Set CAIFG Flag t»2 µs Figure5-8.BlockDiagramofComparator_AModule Overdrive VCAOUT V- 400 mV V+ t(response) Figure5-9.OverdriveDefinition 20 Specifications Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 5.16 Power-On Reset (POR) and Brownout Reset (BOR)(1) overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t 2000 µs d(BOR) V dV /dt≤3V/s(seeFigure5-10) 0.7×V V CC(start) CC (B_IT–) dV /dt≤3V/s(seeFigure5-10through V(B_IT–) Brownout(2) FigCuCre5-12) 1.71 V V dV /dt≤3V/s(seeFigure5-10) 70 130 210 mV hys(B_IT–) CC PulselengthneededatRST/NMIpintoaccepted t 2 µs (reset) resetinternally,V =2.2V,3V CC (1) ThecurrentconsumptionofthebrownoutmoduleisalreadyincludedintheI currentconsumptiondata.ThevoltagelevelV + CC (B_IT–) V is≤1.8V. hys(B_IT–) (2) Duringpowerup,theCPUbeginscodeexecutionfollowingaperiodoft afterV =V +V .ThedefaultFLL+settings d(BOR) CC (B_IT–) hys(B_IT–) mustnotbechangeduntilV ≥V ,whereV istheminimumsupplyvoltageforthedesiredoperatingfrequency.Seethe CC CC(min) CC(min) MSP430x4xxFamilyUser'sGuide(SLAU056)formoreinformationonthebrownout/SVScircuit. V CC V hys(B_IT-) V (B_IT-) V CC(start) 1 0 t d(BOR) Figure5-10.PORandBORvsSupplyVoltage 2 VCC tpw 3 V V = 3 V CC Typical Conditions 1.5 V - op) 1 dr C( VC VCC(drop) 0.5 0 0.001 1 1000 1 ns 1 ns t - Pulse Width -ms t - Pulse Width -ms pw pw Figure5-11.V LevelwithaSquareVoltageDroptoGenerateaPORorBORSignal CC(drop) Copyright©2004–2014,TexasInstrumentsIncorporated Specifications 21 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com VCC tpw 2 3 V V = 3 V CC 1.5 Typical Conditions V -p) o 1 r d C( VCC(drop) C V 0.5 t = t f r 0 0.001 1 1000 t t f r tpw - Pulse Width -ms tpw - Pulse Width -ms Figure5-12.V LevelWithaTriangleVoltageDroptoGenerateaPORorBORSignal CC(drop) 5.17 Supply Voltage Supervisor (SVS) and Supply Voltage Monitor (SVM) overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT dV /dt>30V/ms(seeFigure5-13) 5 150 CC t µs (SVSR) dV /dt≤30V/ms 2000 CC t SVSon,switchfromVLD=0toVLD≠0,V =3V 150 300 µs d(SVSon) CC t VLD≠0(1) 12 µs settle V VLD≠0,V /dt≤3V/s(seeFigure5-13) 1.55 1.7 V (SVSstart) CC VLD=1 70 120 155 mV VCC/dt≤3V/s(seeFigure5-13) VLD=2to14 V(SVS_IT–) V(SVS_IT–) V ×0.001 ×0.016 hys(SVS_IT–) V /dt≤3V/s(seeFigure5-13), CC VLD=15 4.4 20 mV externalvoltageappliedonA7 VLD=1 1.8 1.9 2.05 VLD=2 1.94 2.1 2.23 VLD=3 2.05 2.2 2.35 VLD=4 2.14 2.3 2.46 VLD=5 2.24 2.4 2.58 VLD=6 2.33 2.5 2.69 VLD=7 2.46 2.65 2.84 V /dt≤3V/s(seeFigure5-13) CC VLD=8 2.58 2.8 2.97 V V (SVS_IT–) VLD=9 2.69 2.9 3.10 VLD=10 2.83 3.05 3.26 VLD=11 2.94 3.2 3.39 VLD=12 3.11 3.35 3.58(2) VLD=13 3.24 3.5 3.73(2) VLD=14 3.43 3.7(2) 3.96(2) V /dt≤3V/s(seeFigure5-13), CC VLD=15 1.1 1.2 1.3 externalvoltageappliedonA7 I (3) VLD≠0,V =2.2V,3V 10 15 µA CC(SVS) CC (1) t isthesettlingtimethatthecomparatoroutputneedstohaveastablelevelafterVLDisswitchedfromVLD≠0toadifferentVLD settle valuesomewherebetween2and15.Theoverdriveisassumedtobe>50mV. (2) Therecommendedoperatingvoltagerangeislimitedto3.6V. (3) ThecurrentconsumptionoftheSVSmoduleisnotincludedintheI currentconsumptiondata. CC 22 Specifications Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 Software Sets VLD>0: VCC SVS isActive Vhys(SVS_IT-) V (SVS_IT-) V (SVSstart) Vhys(B_IT-) V(B_IT-) VCC(start) Brown Brownout Out Region Brownout Region 1 0 SVSOut td(BOR) td(BOR) SVS Circuit isActive From VLD > to VCC < V(B_IT-) 1 0 td(SVSon) td(SVSR) Set POR 1 undefined 0 Figure5-13.SVSReset(SVSR)vsSupplyVoltage V CC t pw 3 V 2 Rectangular Drop V CC(drop) 1.5 Triangular Drop V -p) ro 1 d ( C 1 ns 1 ns C V 0.5 V CC t pw 3 V 0 1 10 100 1000 tpw - Pulse Width -ms V CC(drop) t = t f r t t f r t - Pulse Width -ms Figure5-14.V WithaSquareVoltageDropandaTriangleVoltageDroptoGenerateanSVSSignal CC(drop) Copyright©2004–2014,TexasInstrumentsIncorporated Specifications 23 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 5.18 DCO overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC N =01Eh,FN_8=FN_4=FN_3=FN_2=0,D=2, f (DCO) 2.2V,3V 1 MHz (DCOCLK) DCOPLUS=0,f =32.738kHz Crystal 2.2V 0.3 0.65 1.25 f FN_8=FN_4=FN_3=FN_2=0,DCOPLUS=1 MHz (DCO=2) 3V 0.3 0.7 1.3 2.2V 2.5 5.6 10.5 f FN_8=FN_4=FN_3=FN_2=0,DCOPLUS=1 MHz (DCO=27) 3V 2.7 6.1 11.3 2.2V 0.7 1.3 2.3 f FN_8=FN_4=FN_3=FN_2=1,DCOPLUS=1 MHz (DCO=2) 3V 0.8 1.5 2.5 2.2V 5.7 10.8 18 f FN_8=FN_4=FN_3=FN_2=1,DCOPLUS=1 MHz (DCO=27) 3V 6.5 12.1 20 2.2V 1.2 2 3 f FN_8=FN_4=0,FN_3=1,FN_2=x,DCOPLUS=1 MHz (DCO=2) 3V 1.3 2.2 3.5 2.2V 9 15.5 25 f FN_8=FN_4=0,FN_3=1,FN_2=x,DCOPLUS=1 MHz (DCO=27) 3V 10.3 17.9 28.5 2.2V 1.8 2.8 4.2 f FN_8=0,FN_4=1,FN_3=FN_2=x,DCOPLUS=1 MHz (DCO=2) 3V 2.1 3.4 5.2 2.2V 13.5 21.5 33 f FN_8=0,FN_4=1,FN_3=FN_2=x,DCOPLUS=1 MHz (DCO=27) 3V 16 26.6 41 2.2V 2.8 4.2 6.2 f FN_8=1,FN_4=FN_3=FN_2=x,DCOPLUS=1 MHz (DCO=2) 3V 4.2 6.3 9.2 2.2V 21 32 46 f FN_8=1,FN_4=FN_3=FN_2=x,DCOPLUS=1 MHz (DCO=27) 3V 30 46 70 StepsizebetweenadjacentDCOtaps: 1<TAP≤20 1.06 1.11 S S =f /f (seeFigure5-16fortaps21to n n DCO(Tapn+1) DCO(Tapn) 27) TAP=27 1.07 1.17 Temperaturedrift,N =01Eh, 2.2V –0.2 –0.3 –0.4 D (DCO) %/°C t FN_8=FN_4=FN_3=FN_2=0,D=2,DCOPLUS=0 3V –0.2 –0.3 –0.4 DriftwithV variation,N =01Eh, D CC (DCO) 2.2V,3V 0 5 15 %/V V FN_8=FN_4=FN_3=FN_2=0,D=2,DCOPLUS=0 f f (DCO) (DCO) f(DCO3V) f(DCO20°C) 1.0 1.0 0 1.8 2.4 3.0 3.6 -40 -20 0 20 40 60 85 V - V T - °C CC A Figure5-15.DCOFrequencyvsSupplyVoltageV andvsAmbientTemperature CC 24 Specifications Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 s p a T 1.17 O C D n e e w et b o Rati 1.11 Max e z si p e t S n- 1.07 S 1.06 Min 1 20 27 DCO Tap Figure5-16.DCOTapStepSize Legend Tolerance at Tap 27 O) C D f( DCO Frequency Adjusted by Bits 9 5 2 to 2 in SCFI1 {N } {DCO} Tolerance at Tap 2 Overlapping DCO Ranges: Uninterrupted Frequency Range FN_2=0 FN_2=1 FN_2=x FN_2=x FN_2=x FN_3=0 FN_3=0 FN_3=1 FN_3=x FN_3=x FN_4=0 FN_4=0 FN_4=0 FN_4=1 FN_4=x FN_8=0 FN_8=0 FN_8=0 FN_8=0 FN_8=1 Figure5-17.FiveOverlappingDCORangesControlledbyFN_xBits Copyright©2004–2014,TexasInstrumentsIncorporated Specifications 25 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 5.19 Crystal Oscillator, XT1 Oscillator(1) (2) overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT OSCCAPx=0h,V =2.2V,3V 0 CC OSCCAPx=1h,V =2.2V,3V 10 C Integratedinputcapacitance(3) CC pF XIN OSCCAPx=2h,V =2.2V,3V 14 CC OSCCAPx=3h,V =2.2V,3V 18 CC OSCCAPx=0h,V =2.2V,3V 0 CC OSCCAPx=1h,V =2.2V,3V 10 C Integratedoutputcapacitance(3) CC pF XOUT OSCCAPx=2h,V =2.2V,3V 14 CC OSCCAPx=3h,V =2.2V,3V 18 CC V V 0.2×V IL InputlevelsatXIN V =2.2V,3V(4) SS CC V CC V 0.8×V V IH CC CC (1) Theparasiticcapacitancefromthepackageandboardmaybeestimatedtobe2pF.Theeffectiveloadcapacitorforthecrystalis(C XIN ×C )/(C +C ).ThisisindependentofXTS_FLL. XOUT XIN XOUT (2) ToimproveEMIonthelow-powerLFXT1oscillator,particularlyintheLFmode(32kHz),thefollowingguidelinesshouldbeobserved. • Keepthetracebetweenthedeviceandthecrystalasshortaspossible. • Designagoodgroundplanearoundtheoscillatorpins. • PreventcrosstalkfromotherclockordatalinesintooscillatorpinsXINandXOUT. • AvoidrunningPCBtracesunderneathoradjacenttotheXINandXOUTpins. • UseassemblymaterialsandprocessesthatavoidanyparasiticloadontheoscillatorXINandXOUTpins. • Ifconformalcoatingisused,makesurethatitdoesnotinducecapacitiveorresistiveleakagebetweentheoscillatorpins. • DonotroutetheXOUTlinetotheJTAGheadertosupporttheserialprogrammingadapterasshowninotherdocumentation.This signalisnolongerrequiredfortheserialprogrammingadapter. (3) Externalcapacitanceisrecommendedforprecisionreal-timeclockapplications,OSCCAPx=0h. (4) Appliesonlywhenusinganexternallogic-levelclocksource.XTS_FLLmustbeset.Notapplicablewhenusingacrystalorresonator. 5.20 Crystal Oscillator, XT2 Oscillator(1) overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT C Integratedinputcapacitance V =2.2V,3V 2 pF XT2IN CC C Integratedoutputcapacitance V =2.2V,3V 2 pF XT2OUT CC V V 0.2×V V IL InputlevelsatXT2IN V =2.2V,3V(2) SS CC CC V 0.8×V V V IH CC CC (1) Theoscillatorneedscapacitorsatbothterminals,withvaluesspecifiedbythecrystalmanufacturer. (2) Appliesonlywhenusinganexternallogic-levelclocksource.Notapplicablewhenusingacrystalorresonator. 5.21 USART0(1) overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V =2.2V,SYNC=0,UARTmode 200 430 800 CC t USART0deglitchtime ns (τ) V =3V,SYNC=0,UARTmode 150 280 500 CC (1) ThesignalappliedtotheUSART0receivesignal/terminal(URXD0)shouldmeetthetimingrequirementsoft toensurethattheURXS (τ) flip-flopisset.TheURXSflip-flopissetwithnegativepulsesmeetingtheminimumtimingconditionoft .Theoperatingconditionsto (τ) settheflagmustbemetindependentlyfromthistimingconstraint.Thedeglitchcircuitryisactiveonlyonnegativetransitionsonthe URXD0line. 26 Specifications Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 5.22 12-Bit ADC, Power Supply and Input Range Conditions(1) overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT AV andDV areconnectedtogether, CC CC AV Analogsupplyvoltage AV andDV areconnectedtogether, 2.2 3.6 V CC SS SS V =V =0V (AVSS) (DVSS) AllexternalAxterminals,Analoginputsselectedin V Analoginputvoltagerange(2) ADC12MCTLxregisterandP6Sel.x=1, 0 V V (P6.x/Ax) AVCC V ≤V ≤V (AVSS) Ax (AVCC) f =5.0MHz, V =2.2V 0.65 1.3 Operatingsupplycurrentintothe ADC12CLK CC IADC12 AVCCterminal(3) ASDHCT012=O0N,S=H1T,1R=EF0O,AND=C01,2DIV=0 VCC=3V 0.8 1.6 mA f =5.0MHz, ADC12CLK ADC12ON=0, V =3V 0.5 0.8 mA CC Operatingsupplycurrentintothe REFON=1,REF2_5V=1 IREF+ AVCCterminal(4) f =5.0MHz, V =2.2V 0.5 0.8 ADC12CLK CC ADC12ON=0 mA REFON=1,REF2_5V=0 VCC=3V 0.5 0.8 Onlyoneterminalcanbeselectedatone C Inputcapacitance V =2.2V 40 pF I time,Ax CC R InputMUXONresistance 0V≤V ≤V V =3V 2000 Ω I Ax AVCC CC (1) TheleakagecurrentisdefinedintheleakagecurrenttablewithAxparameter. (2) TheanaloginputvoltagerangemustbewithintheselectedreferencevoltagerangeV toV forvalidconversionresults. R+ R– (3) TheinternalreferencesupplycurrentisnotincludedincurrentconsumptionparameterI . ADC12 (4) TheinternalreferencecurrentissuppliedviaterminalAVCC.ConsumptionisindependentoftheADC12ONcontrolbit,unlessa conversionisactive.TheREFONbitenablestosettlethebuilt-inreferencebeforestartinganA/Dconversion. 5.23 12-Bit ADC, External Reference(1) overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V Positiveexternalreference V >V /V (2) 1.4 V V eREF+ voltageinput eREF+ REF– eREF– AVCC V /V Negativeexternalreference V >V /V (3) 0 1.2 V REF– eREF– voltageinput eREF+ REF– eREF– (VeREF+– Differentialexternalreference V >V /V (4) 1.4 V V V /V ) voltageinput eREF+ REF– eREF– AVCC REF– eREF– I Staticinputcurrent 0V≤V ≤V V =2.2V,3V ±1 µA VeREF+ eREF+ AVCC CC I Staticinputcurrent 0V≤V ≤V V =2.2V,3V ±1 µA VREF–/VeREF– eREF– AVCC CC (1) Theexternalreferenceisusedduringconversiontochargeanddischargethecapacitancearray.Theinputcapacitance,C,isalsothe I dynamicloadforanexternalreferenceduringconversion.Thedynamicimpedanceofthereferencesupplyshouldfollowthe recommendationsonanalog-sourceimpedancetoallowthechargetosettlefor12-bitaccuracy. (2) Theaccuracylimitstheminimumpositiveexternalreferencevoltage.Lowerreferencevoltagelevelsmaybeappliedwithreduced accuracyrequirements. (3) Theaccuracylimitsthemaximumnegativeexternalreferencevoltage.Higherreferencevoltagelevelsmaybeappliedwithreduced accuracyrequirements. (4) Theaccuracylimitsminimumexternaldifferentialreferencevoltage.Lowerdifferentialreferencevoltagelevelsmaybeappliedwith reducedaccuracyrequirements. Copyright©2004–2014,TexasInstrumentsIncorporated Specifications 27 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 5.24 12-Bit ADC, Built-In Reference overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC REF2_5V=1for2.5V, 3V 2.4 2.5 2.6 Positivebuiltinreference IVREF+max≤IVREF+≤IVREF+min V V REF+ voltageoutput REF2_5V=0for1.5V, 2.2V,3V 1.44 1.5 1.56 I max≤I ≤I min VREF+ VREF+ VREF+ REF2_5V=0, 2.2 I max≤I ≤I min VREF+ VREF+ VREF+ AV minimumvoltage, REF2_5V=1, 2.8 AV CC V CC(min) Positivebuiltinreferenceactive I min≥I ≥–0.5mA VREF+ VREF+ REF2_5V=1, 2.9 I min≥I ≥–1mA VREF+ VREF+ LoadcurrentoutofV 2.2V 0.01 –0.5 I REF+ mA VREF+ terminal 3V 0.01 –1 I =500µA±100µA, 2.2V ±2 VREF+ Analoginputvoltage≈0.75V, LSB Load-currentregulation,V REF2_5V=0 3V ±2 I REF+ L(VREF)+ terminal I =500µA±100µA, VREF+ Analoginputvoltage≈1.25V, 3V ±2 LSB REF2_5V=1 I =100µA→900µA, Loadcurrentregulation,V VREF+ I REF+ C =5µF,ax≈0.5×V , 3V 20 ns DL(VREF)+ terminal VREF+ REF+ Errorofconversionresult≤1LSB C CapacitanceatpinV (1) REFON=1, 2.2V,3V 5 10 µF VREF+ REF+ 0mA≤I ≤I max VREF+ VREF+ Temperaturecoefficientofbuilt- I isaconstantintherangeof T VREF+ 2.2V,3V ±100 ppm/°C REF+ inreference 0mA≤I ≤1mA VREF+ Settletimeofinternalreference I =0.5mA,C =10µF, tREFON voltage(seeFigure5-18) (2) VVREF+=1.5V,V VRE=F+2.2V 17 ms REF+ AVCC (1) Theinternalbufferoperationalamplifierandtheaccuracyspecificationsrequireanexternalcapacitor.AllINLandDNLtestsusestwo capacitorsbetweenpinsV andAV andV /V andAV :10µFtantalumand100nFceramic. REF+ SS REF-– eREF– SS (2) Theconditionisthattheerrorinaconversionstartedaftert islessthan±0.5LSB.Thesettlingtimedependsontheexternal REFON capacitiveload. C VREF+ 100 mF t ».66 x C [ms] with C inmF 10mF REFON VREF+ VREF+ 1mF 0 1 ms 10 ms 100 ms t REFON Figure5-18.TypicalSettlingTimeofInternalReferencet vsExternalCapacitoronV REFON REF+ 28 Specifications Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 DV CC1/2 + From Power Supply - DV SS1/2 10µF 100 nF AV + CC MSP430FG43x - AV SS 10µF 100 nF ApplyExternalReference[VeREF+] or Use Internal Reference [VREF+] VREF+or VeREF+ + - 10µF 100 nF Apply External Reference V -/V + REF eREF- - 10µF 100nF Figure5-19.SupplyVoltageandReferenceVoltageDesignV /V ExternalSupply REF– eREF– DV CC1/2 + From Power Supply - DV SS1/2 10µF 100nF AV + CC MSP430FG43x - AV SS 10µ F 100nF ApplyExternalReference[VeREF+] or Use Internal Reference [VREF+] VREF+or VeREF+ + - 10µF 100nF Reference Is Internally V /V SwitchedtoAVSS REF- eREF- Figure5-20.SupplyVoltageandReferenceVoltageDesignV /V =AV ,InternallyConnected REF– eREF– SS Copyright©2004–2014,TexasInstrumentsIncorporated Specifications 29 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 5.25 12-Bit ADC, Timing Parameters overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC ForspecifiedperformanceofADC12 f ADC12clockfrequency 2.2V,3V 0.45 5 6.3 MHz ADC12CLK linearityparameters f InternalADC12oscillator ADC12DIV=0,f =f 2.2V,3V 3.7 5 6.3 MHz ADC12OSC ADC12CLK ADC12OSC C ≥5µF,Internaloscillator, VREF+ 2.2V,3V 2.06 3.51 µs f =3.7MHzto6.3MHz ADC12OSC tCONVERT Conversiontime 13× Externalf fromACLK,MCLK,or ADC12CLK ADC12DIV× µs SMCLK,ADC12SSEL≠0 1/f ADC12CLK t Turnonsettlingtimeof See (1) 100 ns ADC12ON theADC R =400Ω,R =1000Ω, 3V 1220 tSample Samplingtime CSI=30pF,τ=I [RS+RI]×CI (2) 2.2V 1400 ns (1) Theconditionisthattheerrorinaconversionstartedaftert islessthan±0.5LSB.Thereferenceandinputsignalarealready ADC12ON settled. (2) ApproximatelytenTau(τ)areneededtogetanerroroflessthan±0.5LSB: t =ln(2n+1)×(R +R)xC +800ns,wheren=ADCresolution=12,R =externalsourceresistance. Sample S I I S 5.26 12-Bit ADC, Linearity Parameters overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 1.4V≤(V –V /V )min≤1.6V ±2 eREF+ REF– eREF– E Integrallinearityerror 2.2V,3V LSB I 1.6V<(V –V /V )min≤V ±1.7 eREF+ REF– eREF– AVCC (V –V /V )min≤(V –V /V ), E Differentiallinearityerror eREF+ REF– eREF– eREF+ REF– eREF– 2.2V,3V ±1 LSB D C =10µF(tantalum)and100nF(ceramic) VREF+ (V –V /V )min≤(V –V /V ), eREF+ REF– eREF– eREF+ REF– eREF– E Offseterror InternalimpedanceofsourceRS<100Ω, 2.2V,3V ±2 ±4 LSB O C =10µF(tantalum)and100nF(ceramic) VREF+ (V –V /V )min≤(V –V /V ), E Gainerror eREF+ REF– eREF– eREF+ REF– eREF– 2.2V,3V ±1.1 ±2 LSB G C =10µF(tantalum)and100nF(ceramic) VREF+ (V –V /V )min≤(V –V /V ), E Totalunadjustederror eREF+ REF– eREF– eREF+ REF– eREF– 2.2V,3V ±2 ±5 LSB T C =10µF(tantalum)and100nF(ceramic) VREF+ 30 Specifications Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 5.27 12-Bit ADC, Temperature Sensor and Built-In V MID overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC Operatingsupplycurrentinto REFON=0,INCH=0Ah, 2.2V 40 120 ISENSOR AVCCterminal(1) ADC12ON=NA,TA=25°C 3V 60 160 µA V See (2) ADC12ON=1,INCH=0Ah, 2.2V, 986 mV SENSOR T =0°C 3V A 2.2V, TC ADC12ON=1,INCH=0Ah 3.55±3% mV/°C SENSOR 3V Sampletimerequiredif ADC12ON=1,INCH=0Ah, 2.2V 30 tSENSOR(sample) channel10isselected(3) Errorofconversionresult≤1LSB 3V 30 µs Currentintodividerat 2.2V NA IVMID channel11(4) ADC12ON=1,INCH=0Bh 3V NA µA 1.10± 2.2V 1.1 ADC12ON=1,INCH=0Bh, 0.04 V AV divideratchannel11 V MID CC VMID≈0.5×VAVCC 1.50± 3V 1.5 0.04 Sampletimerequiredif ADC12ON=1,INCH=0Bh, 2.2V 1400 tVMID(sample) channel11isselected(5) Errorofconversionresult≤1LSB 3V 1220 ns (1) ThesensorcurrentI isconsumedif(ADC12ON=1andREFON=1),or(ADC12ON=1ANDINCH=0Ahandsamplesignalis SENSOR high).WhenREFON=1,I isalreadyincludedinI . SENSOR REF+ (2) Thetemperaturesensoroffsetcanbeasmuchas±20°C.Asingle-pointcalibrationisrecommendedinordertominimizetheoffseterror ofthebuilt-intemperaturesensor. (3) Thetypicalequivalentimpedanceofthesensoris51kΩ.Thesampletimerequiredincludesthesensor-ontimet SENSOR(on) (4) Noadditionalcurrentisneeded.TheV isusedduringsampling. MID (5) Theon-timet isincludedinthesamplingtimet ;noadditionalontimeisneeded. VMID(on) VMID(sample) 5.28 12-Bit DAC, Supply Specifications overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC AV Analogsupplyvoltage AV =DV ,AV =DV =0V 2.2 3.6 V CC CC CC SS SS DAC12AMPx=2,DAC12IR=0, 50 110 DAC12_xDAT=0800h DAC12AMPx=2,DAC12IR=1, 50 110 Supplycurrent,singleDAC DAC12_xDAT=0800h,VeREF+=VREF+=AVCC 2.2V, IDD channel(1) (2) DAC12AMPx=5,DAC12IR=1, 3V µA 200 440 DAC12_xDAT=0800h,V =V =AV eREF+ REF+ CC DAC12AMPx=7,DAC12IR=1, 700 1500 DAC12_xDAT=0800h,V =V =AV eREF+ REF+ CC DAC12_xDAT=0800h,V =1.5V, REF 2.2V ΔAV =100mV PSRR Power-supplyrejectionratio(3) (4) CC 70 dB DAC12_xDAT=0800h,V =1.5Vor2.5V, REF 3V ΔAV =100mV CC (1) Noloadattheoutputpin,DAC0orDAC1,assumingthatthecontrolbitsforthesharedpinsaresetproperly. (2) Currentintoreferenceterminalsnotincluded.IfDAC12IR=1,currentflowsthroughtheinputdivider(seeReferenceInput specifications). (3) PSRR=20×log(ΔAV /ΔV ). CC DAC12_xOUT (4) V isappliedexternally.Theinternalreferenceisnotused. REF Copyright©2004–2014,TexasInstrumentsIncorporated Specifications 31 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 5.29 12-Bit DAC, Linearity Specifications overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure5-21) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC Resolution 12-bitmonotonic 12 bits V =1.5V, ref 2.2V DAC12AMPx=7,DAC12IR=1 INL Integralnonlinearity(1) ±2.0 ±8.0 LSB V =2.5V, ref 3V DAC12AMPx=7,DAC12IR=1 V =1.5V, ref 2.2V DAC12AMPx=7,DAC12IR=1 DNL Differentialnonlinearity(1) ±0.4 ±1.0 LSB V =2.5V, ref 3V DAC12AMPx=7,DAC12IR=1 V =1.5V, ref 2.2V DAC12AMPx=7,DAC12IR=1 Offsetvoltagewithoutcalibration(1) (2) ±21 V =2.5V, ref 3V DAC12AMPx=7,DAC12IR=1 E mV O V =1.5V, ref 2.2V DAC12AMPx=7,DAC12IR=1 Offsetvoltagewithcalibration(1) (2) ±2.5 V =2.5V, ref 3V DAC12AMPx=7,DAC12IR=1 d /d Offseterrortemperaturecoefficient(1) 2.2V,3V ±30 µV/°C E(O) T V =1.5V 2.2V E Gainerror(1) REF ±3.5 %FSR G V =2.5V 3V REF d /d Gaintemperaturecoefficient(1) 2.2V,3V 10 ppmof E(G) T FSR/°C DAC12AMPx=2 100 t Timeforoffsetcalibration(3) DAC12AMPx=3,5 2.2V,3V 32 ms OffsetCal DAC12AMPx=4,6,7 6 (1) Parameterscalculatedfromthebest-fitcurvefrom0x0Ato0xFFF.Thebest-fitcurvemethodisusedtodelivercoefficients"a"and"b"of thefirst-orderequation:y=a+b×x.V =E +(1+E )×(V /4095)×DAC12_xDAT,DAC12IR=1. DAC12_xOUT O G eREF+ (2) Theoffsetcalibrationworksontheoutputoperationalamplifier.OffsetCalibrationistriggeredsettingbitDAC12CALON. (3) TheoffsetcalibrationcanbedoneifDAC12AMPx={2,3,4,5,6,7}.TheoutputoperationalamplifierisswitchedoffwithDAC12AMPx= {0,1}.ItisrecommendedthattheDAC12modulebeconfiguredpriortoinitiatingcalibration.Portactivityduringcalibrationmayaffect accuracyandisnotrecommended. DAC VOUT DAC Output RLoad = VR+ Ideal transfer AVCC function 2 Offset Error Gain Error CLoad = 100pF Positive Negative DAC Code Figure5-21.LinearityTestLoadConditionsandGain/OffsetDefinition 32 Specifications Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 4 VCC=2.2V,VREF= 1.5V B 3 DAC12AMPx = 7 LS DAC12IR = 1 r- 2 o r r E y 1 rit a e nlin 0 o N al -1 r g e nt -2 I - L N I -3 -4 0 512 1024 1536 2048 2560 3072 3584 4095 DAC12_xDAT- DigitalCode Figure5-22. TypicalINLErrorvsDigitalInputData 2.0 B VCC=2.2V,VREF= 1.5V LS 1.5 DAC12AMPx = 7 - DAC12IR = 1 r o r 1.0 r E y arit 0.5 e n onli 0.0 N al nti -0.5 e r e Diff -1.0 - L N -1.5 D -2.0 0 512 1024 1536 2048 2560 3072 3584 4095 DAC12_xDAT- DigitalCode Figure5-23. TypicalDNLErrorvsDigitalInputData Copyright©2004–2014,TexasInstrumentsIncorporated Specifications 33 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 5.30 12-Bit DAC, Output Specifications overrecommendedoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC NoLoad,V =AV , eREF+ CC DAC12_xDAT=0h,DAC12IR=1, 0 0.005 DAC12AMPx=7 NoLoad,V =AV , eREF+ CC AV – DAC12_xDAT=0FFFh,DAC12IR=1, CC AV 0.05 CC Outputvoltagerange(1) DAC12AMPx=7 2.2V, V V O (seeFigure5-24) R =3kΩ,V =AV , 3V Load eREF+ CC DAC12_xDAT=0h,DAC12IR=1, 0 0.1 DAC12AMPx=7 R =3kΩ,V =AV , Load eREF+ CC AV – DAC12_xDAT=0FFFh,DAC12IR=1, CC AV 0.13 CC DAC12AMPx=7 MaximumDAC12load 2.2V, C 100 pF L(DAC12) capacitance 3V MaximumDAC12load 2.2V –0.5 +0.5 I mA L(DAC12) current 3V –1.0 +1.0 R =3kΩ,V <0.3V, Load O/P(DAC12) 150 250 DAC12AMPx=7,DAC12_xDAT=0h R =3kΩ, Load Outputresistance(see V >AV –0.3V, 2.2V, 150 250 R O/P(DAC12) CC Ω O/P(DAC12) Figure5-24) DAC12AMPx=7,DAC12_xDAT=0FFFh 3V R =3kΩ, Load 0.3V≤V ≤AV –0.3V 1 4 O/P(DAC12) CC DAC12AMPx=7 (1) Dataisvalidaftertheoffsetcalibrationoftheoutputamplifier. RO/P(DAC12_x) Max ILoad RLoad AVCC DAC12 2 O/P(DAC12_x) CLoad= 100pF Min 0.3 AVCC-0.3V VOUT AVCC Figure5-24.DAC12_xOutputResistanceTests 34 Specifications Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 5.31 12-Bit DAC, Reference Input Specifications overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC Referenceinputvoltage DAC12IR=0(1) (2) AVCC/3 AVCC+0.2 Ve 2.2V,3V V REF+ range DAC12IR=1(3) (4) AV AV +0.2 CC CC DAC12_0IR=DAC12_1IR=0 20 MΩ DAC12_0IR=1,DAC12_1IR=0 40 48 56 Ri , Referenceinput (R(iV(VReERFE+F)+) resistance DAC12_0IR=0,DAC12_1IR=1 2.2V,3V 40 48 56 kΩ DAC12_0IR=DAC12_1IR=1, DAC12_0SREFx=DAC12_1SREFx(5) 20 24 28 (1) Forafull-scaleoutput,thereferenceinputvoltagecanbeashighas1/3ofthemaximumoutputvoltageswing(AV ). CC (2) ThemaximumvoltageappliedatreferenceinputvoltageterminalVe =[AV –V ]/[3×(1+E )]. REF+ CC E(O) G (3) Forafull-scaleoutput,thereferenceinputvoltagecanbeashighasthemaximumoutputvoltageswing(AV ). CC (4) ThemaximumvoltageappliedatreferenceinputvoltageterminalVe =[AV –V ]/(1+E ). REF+ CC E(O) G (5) WhenDAC12IR=1andDAC12SREFx=0or1forbothchannels,thereferenceinputresistivedividersforeachDACareinparallel, reducingthereferenceinputresistance. 5.32 12-Bit DAC, Dynamic Specifications V =V ,DAC12IR=1,overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure5-25 ref CC andFigure5-26) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC DAC12AMPx=0→{2,3,4} 60 120 DAC12_xDAT=800h, t DAC12ontime Error <±0.5LSB(1) DAC12AMPx=0→{5,6} 2.2V,3V 15 30 µs ON V(O) (seeFigure5-25) DAC12AMPx=0→7 6 12 DAC12AMPx=2 100 200 Settlingtime, DAC12_xDAT= t DAC12AMPx=3,5 2.2V,3V 40 80 µs S(FS) fullscale 80h→F7Fh→80h DAC12AMPx=4,6,7 15 30 DAC12AMPx=2 5 DAC12_xDAT= Settlingtime, t 3F8h→408h→3F8h DAC12AMPx=3,5 2.2V,3V 2 µs S(C–C) codetocode BF8h→C08h→BF8h DAC12AMPx=4,6,7 1 DAC12AMPx=2 0.05 0.12 DAC12_xDAT= SR Slewrate 80h→F7Fh→80h(2) DAC12AMPx=3,5 2.2V,3V 0.35 0.7 V/µs DAC12AMPx=4,6,7 1.5 2.7 DAC12AMPx=2 10 Glitchenergy, DAC12_xDAT= DAC12AMPx=3,5 2.2V,3V 10 nV-s fullscale 80h→F7Fh→80h DAC12AMPx=4,6,7 10 (1) R andC connectedtoAV (notAV /2)inFigure5-25. Load Load SS CC (2) Slewrateappliestooutputvoltagesteps≥200mV. Conversion 1 Conversion 2 Conversion 3 DAC Output VOUT Glitch +/- 1/2 LSB RLoad= 3 kW Energy ILoad AVCC 2 +/- 1/2 LSB CLoad = 100pF RO/P(DAC12.x) tsettleLH tsettleHL Figure5-25.SettlingTimeandGlitchEnergyTesting Copyright©2004–2014,TexasInstrumentsIncorporated Specifications 35 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com Conversion 1 Conversion 2 Conversion 3 VOUT 90% 90% 10% 10% tSRLH tSRHL Figure5-26.SlewRateTesting 5.33 12-Bit DAC, Dynamic Specifications (Continued) T =25°Cunlessotherwisenoted A PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC DAC12AMPx={2,3,4},DAC12SREFx=2, 40 DAC12IR=1,DAC12_xDAT=800h 3-dBbandwidth, DAC12AMPx={5,6},DAC12SREFx=2, BW V =1.5V,V =0.1VPP 2.2V,3V 180 kHz –3dB DC AC DAC12IR=1,DAC12_xDAT=800h (seeFigure5-27) DAC12AMPx=7,DAC12SREFx=2, 550 DAC12IR=1,DAC12_xDAT=800h DAC12_0DAT=800h,NoLoad, DAC12_1DAT=80h↔F7Fh,R =3kΩ –80 Load Channel-to-channel f =10kHzwith50/50dutycycle crosstalk(1) DAC12_1OUT 2.2V,3V dB (seeFigure5-28) DAC12_0DAT=80h↔F7Fh,RLoad=3kΩ, DAC12_1DAT=800h,NoLoad, –80 f =10kHzwith50/50dutycycle DAC12_0OUT (1) R =3kΩ,C =100pF LOAD LOAD RLoad= 3 kW ILoad Ve REF+ AV DAC12_x CC DACx 2 AC CLoad= 100pF DC Figure5-27.TestConditionsfor3-dBBandwidthSpecification RLoad ILoad DAC12_0 AVCC DAC12_xDAT 080h 7F7h 080h 7F7h 080h DAC0 2 VOUT CLoad= 100pF VREF+ VDAC12_yOUT RLoad ILoad DAC12_1 AVCC VDAC12_xOUT DAC1 2 fToggle CLoad= 100pF Figure5-28.CrosstalkTestConditions 36 Specifications Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 5.34 Operational Amplifier (OA), Supply Specifications overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC V Supplyvoltage 2.2 3.6 V CC FastMode,RRIPOFF 180 290 MediumMode,RRIPOFF 110 190 SlowMode,RRIPOFF 50 80 I Supplycurrent(1) 2.2V,3V µA CC FastMode,RRIPON 300 490 MediumMode,RRIPON 190 350 SlowMode,RRIPON 90 190 PSRR Powersupplyrejectionratio Non-inverting 2.2V,3V 70 dB (1) P6SEL.x=1foreachcorrespondingpinwhenusedinOAinputorOAoutputmode. 5.35 Operational Amplifier (OA), Input/Output Specifications overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC RRIPOFF –0.1 V –1.2 CC V Voltagesupply,I/P V I/P RRIPON –0.1 V +0.1 CC Inputleakagecurrent, TA=–40°Cto+55°C –5 ±0.5 5 IIkg I/P(1) (2) T =+55°Cto+85°C –20 ±5 20 nA A FastMode 50 MediumMode f =1kHz 80 V(I/P) SlowMode 140 V Voltagenoisedensity,I/P nV/√Hz n FastMode 30 MediumMode f =10kHz 50 V(I/P) SlowMode 65 V Offsetvoltage,I/P 2.2V,3V ±10 mV IO Offsettemperaturedrift, See (3) 2.2V,3V ±10 µV/°C I/P Offsetvoltagedriftwith 0.3V≤V ≤V –0.3V IN CC 2.2V,3V ±1.5 mV/V supply,I/P ΔV ≤±10%,T =25°C CC A High-leveloutputvoltage, FastMode,ISOURCE≤–500µA 2.2V VCC–0.2 VCC V V OH O/P SlowMode,I ≤–150µA 3V V –0.1 V SOURCE CC CC Low-leveloutputvoltage, FastMode,ISOURCE≤+500µA 2.2V VSS 0.2 V V OL O/P SlowMode,I ≤+150µA 3V V 0.1 SOURCE SS R =3kΩ,C =50pF,RRIPON, Load Load 150 250 V <0.2V O/P(OAx) Outputresistance(4)(see R =3kΩ,C =50pF,RRIPON, RO/P(OAx) Figure5-29) VLoad >AVLoa–d0.2V 2.2V,3V 150 250 Ω O/P(OAx) CC R =3kΩ,C =50pF,RRIPON, Load Load 0.2V≤V ≤AV –0.2V 0.1 4 O/P(OAx) CC Common-moderejection CMRR Non-inverting 2.2V,3V 70 dB ratio (1) ESDdamagecandegradeinputcurrentleakage. (2) Theinputbiascurrentisoverriddenbytheinputleakagecurrent. (3) Calculatedusingtheboxmethod. (4) Specificationvalidforvoltage-followerOAxconfiguration. Copyright©2004–2014,TexasInstrumentsIncorporated Specifications 37 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com RO/P(OAx) Max ILoad RLoad AVCC OAx 2 O/P(OAx) CLoad Min 0.2V AVCC-0.2V AVCC VOUT Figure5-29.OAxOutputResistanceTests 5.36 Operational Amplifier (OA), Dynamic Specifications overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC FastMode 1.2 SR Slewrate MediumMode 0.8 V/µs SlowMode 0.3 Open-loopvoltagegain 100 dB φ Phasemargin C =50pF 60 deg m L Gainmargin C =50pF 20 dB L Non-inverting,FastMode, 2.2 R =47kΩ,C =50pF L L 1.4 Gain-bandwidthproduct Non-inverting,MediumMode, GBW 2.2V,3V MHz (seeFigure5-30andFigure5-31) R =300kΩ,C =50pF L L 0.5 Non-inverting,SlowMode, R =300kΩ,C =50pF L L t Enabletimeon t ,non-inverting,Gain=1 2.2V,3V 10 20 µs en(on) on t Enabletimeoff 2.2V,3V 1 µs en(off) 5.37 OA Dynamic Specifications Typical Characteristics 140 0 120 Fast Mode 100 -50 80 Medium Mode Fast Mode 60 es B re -100 = d 40 deg ain 20 e - Medium Mode G s a -150 0 Slow Mode Ph Slow Mode -20 -40 -200 -60 -80 0.001 0.01 0.1 1 10 100 1000 10000 -250 1 10 100 1000 10000 Input Frequency - kHz Input Frequency - kHz Figure5-30.TypicalOpen-LoopGainvsFrequency Figure5-31.TypicalPhasevsFrequency 38 Specifications Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 5.38 Flash Memory overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) TEST PARAMETER V MIN TYP MAX UNIT CONDITIONS CC V Programanderasesupplyvoltage 2.7 3.6 V CC(PGM/ERASE) f Flashtiminggeneratorfrequency 257 476 kHz FTG I SupplycurrentfromDV duringprogram 2.7V,3.6V 3 5 mA PGM CC I SupplycurrentfromDV duringerase 2.7V,3.6V 3 7 mA ERASE CC t Cumulativeprogramtime See (1) 2.7V,3.6V 10 ms CPT t Cumulativemasserasetime See (2) 2.7V,3.6V 200 ms CMErase Programanderaseendurance 104 105 cycles t Dataretentionduration T =25°C 100 years Retention J t Wordorbyteprogramtime 35 Word t Blockprogramtimeforfirstbyteorword 30 Block,0 Blockprogramtimeforeachadditionalbyteor t 21 Block,1-63 word See (3) t FTG t Blockprogramend-sequencewaittime 6 Block,End t Masserasetime 5297 MassErase t Segmenterasetime 4819 SegErase (1) Thecumulativeprogramtimemustnotbeexceededwhenwritingtoa64-byteflashblock.Thisparameterappliestoallprogramming methods:individualwordorbytewriteandblockwritemodes. (2) Themasserasedurationgeneratedbytheflashtiminggeneratorisatleast11.1ms(=5297×1/f =5297×1/476kHz).To FTG,max achievetherequiredcumulativemasserasetimetheFlashController'smasseraseoperationcanberepeateduntilthistimeismet.(A worstcaseminimumof19cyclesarerequired). (3) Thesevaluesarehard-wiredintotheflashcontroller'sstatemachine(t =1/f ). FTG FTG 5.39 JTAG Interface overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 2.2V 0 5 MHz f TCKinputfrequency See (1) TCK 3V 0 10 MHz R InternalpullupresistanceonTMS,TCK,TDI/TCLK See (2) 2.2V,3V 25 60 90 kΩ Internal (1) f mayberestrictedtomeetthetimingrequirementsofthemoduleselected. TCK (2) TMS,TDI/TCLK,andTCKpullupresistorsareimplementedinallversions. 5.40 JTAG Fuse(1) overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT V Supplyvoltageduringfuse-blowcondition T =25°C 2.5 V CC(FB) A V VoltagelevelonTDI/TCLKforfuse-blow 6 7 V FB I SupplycurrentintoTDI/TCLKduringfuseblow 100 mA FB t Timetoblowfuse 1 ms FB (1) Afterthefuseisblown,nofurtheraccesstotheMSP430JTAG/Testandemulationfeaturesispossible.TheJTAGblockisswitchedto bypassmode. Copyright©2004–2014,TexasInstrumentsIncorporated Specifications 39 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 6 Detailed Description 6.1 CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with sevenaddressingmodesforsourceoperandandfouraddressingmodesfordestinationoperand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to- registeroperationexecutiontimeisonecycleoftheCPUclock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constantgeneratorrespectively.Theremainingregistersaregeneral-purposeregisters. PeripheralsareconnectedtotheCPUusingdata,address,andcontrolbuses,andcanbehandledwithall instructions. Program Counter PC/R0 Stack Pointer SP/R1 Status Register SR/CG1/R2 Constant Generator CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 40 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.2 Instruction Set The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Table 6-1 shows examples of the three types of instruction formats; Table 6-2 lists the address modes. Table6-1.InstructionWordFormats INSTRUCTIONFORMAT EXAMPLE OPERATION Dualoperands,source-destination ADDR4,R5 R4+R5→R5 Singleoperands,destinationonly CALLR8 PC→(TOS),R8→PC Relativejump,un/conditional JNE Jump-on-equalbit=0 Table6-2.AddressModeDescriptions ADDRESSMODE S(1) D(1) SYNTAX EXAMPLE OPERATION Register ✓ ✓ MOVRs,Rd MOVR10,R11 R10→R11 Indexed ✓ ✓ MOVX(Rn),Y(Rm) MOV2(R5),6(R6) M(2+R5)→M(6+R6) Symbolic(PCrelative) ✓ ✓ MOVEDE,TONI M(EDE)→M(TONI) Absolute ✓ ✓ MOV&MEM,&TCDAT M(MEM)→M(TCDAT) Indirect ✓ MOV@Rn,Y(Rm) MOV@R10,Tab(R6) M(R10)→M(Tab+R6) M(R10)→R11 Indirectautoincrement ✓ MOV@Rn+,Rm MOV@R10+,R11 R10+2→R10 Immediate ✓ MOV#X,TONI MOV#45,TONI #45→M(TONI) (1) S=sourceD=destination Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 41 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 6.3 Operating Modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restorebacktothelow-powermodeonreturnfromtheinterruptprogram. Thefollowingsixoperatingmodescanbeconfiguredbysoftware: • Activemode(AM) – Allclocksareactive • Low-powermode0(LPM0) – CPUisdisabled – ACLKandSMCLKremainactive.MCLKisdisabled – FLL+loopcontrolremainsactive • Low-powermode1(LPM1) – CPUisdisabled – FLL+loopcontrolisdisabled – ACLKandSMCLKremainactive.MCLKisdisabled • Low-powermode2(LPM2) – CPUisdisabled – MCLK,FLL+loopcontrolandDCOCLKaredisabled – DCO'sdc-generatorremainsenabled – ACLKremainsactive • Low-powermode3(LPM3) – CPUisdisabled – MCLK,FLL+loopcontrol,andDCOCLKaredisabled – DCO'sdc-generatorisdisabled – ACLKremainsactive • Low-powermode4(LPM4) – CPUisdisabled – ACLKisdisabled – MCLK,FLL+loopcontrol,andDCOCLKaredisabled – DCO'sdc-generatorisdisabled – Crystaloscillatorisstopped 42 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.4 Interrupt Vector Addresses Theinterruptvectorsandthepower-upstartaddressarelocatedintheaddressrange0FFFFhto0FFC0h. Thevectorcontainsthe16-bitaddressoftheappropriateinterrupt-handlerinstructionsequence. Table6-3.InterruptSources,Flags,andVectorsofMSP430FG43xConfigurations SYSTEM WORD INTERRUPTSOURCE INTERRUPTFLAG PRIORITY INTERRUPT ADDRESS Power-Up ExternalReset WDTIFG Watchdog KEYV (1) Reset 0FFFEh 15,highest FlashMemory NMI NMIIFG (1) (Non)maskable(2) OscillatorFault OFIFG(1) (Non)maskable 0FFFCh 14 FlashMemoryAccessViolation ACCVIFG(1) (Non)maskable Timer_B3 TBCCR0CCIFG0(3) Maskable 0FFFAh 13 TBCCR1CCIFG1andTBCCR2CCIFG2, Timer_B3 TBIFG(1) (3) Maskable 0FFF8h 12 Comparator_A CAIFG Maskable 0FFF6h 11 WatchdogTimer WDTIFG Maskable 0FFF4h 10 USART0Receive URXIFG0 Maskable 0FFF2h 9 USART0Transmit UTXIFG0 Maskable 0FFF0h 8 ADC12 ADC12IFG (1) (3) Maskable 0FFEEh 7 Timer_A3 TACCR0CCIFG0(3) Maskable 0FFECh 6 TACCR1CCIFG1andTACCR2CCIFG2, Timer_A3 TAIFG(1) (3) Maskable 0FFEAh 5 I/OPortP1(EightFlags) P1IFG.0toP1IFG.7(1) (3) Maskable 0FFE8h 4 DAC12DMA DAC12.0IFG,DAC12.1IFG,DMA0IFG(1) (3) Maskable 0FFE6h 3 0FFE4h 2 I/OPortP2(EightFlags) P2IFG.0toP2IFG.7 (1) (3) Maskable 0FFE2h 1 BasicTimer1 BTIFG Maskable 0FFE0h 0,lowest (1) Multiplesourceflags (2) (Non)maskable:theindividualinterrupt-enablebitcandisableaninterruptevent,butthegeneral-interruptenablecannotdisableit. (3) Interruptflagsarelocatedinthemodule. Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 43 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 6.5 Special Function Registers (SFRs) The MSP430 SFRs are located in the lowest address space and are organized as byte-mode registers. SFRsshouldbeaccessedwithbyteinstructions. Legend rw Bitcanbereadandwritten. rw-0,rw-1 Bitcanbereadandwritten.ItisResetorSetbyPUC. rw-(0),rw-1 Bitcanbereadandwritten.ItisResetorSetbyPOR. SFRbitisnotpresentindevice. 6.5.1 Interrupt Enable Registers 1 and 2 Figure6-1.InterruptEnableRegister1(Address=0h) 7 6 5 4 3 2 1 0 UTXIE0 URXIE0 ACCVIE NMIIE OFIE WDTIE rw–0 rw–0 rw–0 rw–0 rw–0 rw–0 Table6-4.InterruptEnableRegister1FieldDescriptions BIT FIELD TYPE RESET DESCRIPTION 7 UTXIE0 RW 0h USART0:UARTandSPItransmit-interruptenable 6 URXIE0 RW 0h USART0:UARTandSPIreceive-interruptenable 5 ACCVIE RW 0h Flashaccessviolationinterruptenable 4 NMIIE RW 0h Nonmaskable-interruptenable 1 OFIE RW 0h Oscillator-fault-interruptenable 0 WDTIE RW 0h Watchdog-timerinterruptenable.Inactiveifwatchdogmodeisselected. Activeifwatchdogtimerisconfiguredasageneral-purposetimer. Figure6-2.InterruptEnableRegister2(Address=1h) 7 6 5 4 3 2 1 0 BTIE rw–0 Table6-5.InterruptEnableRegister2FieldDescriptions BIT FIELD TYPE RESET DESCRIPTION 7 BTIE RW 0h Basictimerinterruptenable 44 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.5.2 Interrupt Flag Registers 1 and 2 Figure6-3.InterruptFlagRegister1(Address=2h) 7 6 5 4 3 2 1 0 UTXIFG0 URXIFG0 NMIIFG OFIFG WDTIFG rw–1 rw–0 rw–0 rw–1 rw–(0) Table6-6.InterruptFlagRegister1FieldDescriptions BIT FIELD TYPE RESET DESCRIPTION 7 UTXIFG0 RW 1h USART0:UARTandSPItransmitflag 6 URXIFG0 RW 0h USART0:UARTandSPIreceiveflag 4 NMIIFG RW 0h SetbyRST/NMIpin 1 OFIFG RW 1h Flagsetonoscillatorfault 0 WDTIFG RW 0h Setonwatchdogtimeroverflow(inwatchdogmode)orsecuritykeyviolation ResetonV power-onoraresetconditionattheRST/NMIpininresetmode CC Figure6-4.InterruptFlagRegister2(Address=3h) 7 6 5 4 3 2 1 0 BTIFG rw–0 Table6-7.InterruptFlagRegister2FieldDescriptions BIT FIELD TYPE RESET DESCRIPTION 7 BTIFG RW 0h Basictimerflag 6.5.3 Module Enable Registers 1 and 2 Figure6-5.ModuleEnableRegister1(Address=4h) 7 6 5 4 3 2 1 0 UTXE0 URXE0 USPIE0 rw–0 rw–0 Table6-8.ModuleEnableRegister1FieldDescriptions BIT FIELD TYPE RESET DESCRIPTION 7 UTXE0 RW 0h USART0:UARTmodetransmitenable URXE0 RW 0h USART0:UARTmodereceiveenable 6 USPIE0 RW 0h USART0:SPImodetransmitandreceiveenable Figure6-6.ModuleEnableRegister2(Address=5h) 7 6 5 4 3 2 1 0 Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 45 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 6.6 Memory Organization Table6-9showsthememoryorganizationforalldevicevariants. Table6-9.MemoryOrganization MSP430FG437 MSP430FG438 MSP430FG439 Memory Size 32KB 48KB 60KB Main:interruptvector Flash 0FFFFh-0FFE0h 0FFFFh-0FFE0h 0FFFFh-0FFE0h Main:codememory Flash 0FFFFh-08000h 0FFFFh-04000h 0FFFFh-01100h Informationmemory Size 256Byte 256Byte 256Byte Flash 010FFh-01000h 010FFh-01000h 010FFh-01000h Bootmemory Size 1KB 1KB 1KB ROM 0FFFh-0C00h 0FFFh-0C00h 0FFFh-0C00h RAM Size 1KB 2KB 2KB 05FFh-0200h 09FFh-0200h 09FFh-0200h Peripherals 16-bit 01FFh-0100h 01FFh-0100h 01FFh-0100h 8-bit 0FFh-010h 0FFh-010h 0FFh-010h 8-bitSFR 0Fh-00h 0Fh-00h 0Fh-00h 46 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.7 Bootstrap Loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For completedescriptionofthefeaturesoftheBSLanditsimplementation,see MSP430ProgrammingViathe BootstrapLoader(BSL)(SLAU319). BSLFUNCTION PNPACKAGEPINS ZCAPACKAGEPINS DataTransmit 67–P1.0 D8–P1.0 DataReceiver 66–P1.1 D9–P1.1 6.8 Flash Memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memoryinclude: • Flash memory has n segments of main memory and two segments of information memory (A and B) of 128byteseach.Eachsegmentinmainmemoryis512bytesinsize. • Segments0tonmaybeerasedinonestep,oreachsegmentmaybeindividuallyerased. • Segments A and B can be erased individually, or as a group with segments 0 to n. Segments A and B arealsocalledinformationmemory. • New devices may have some bytes programmed in the information memory (needed for test during manufacturing).Theusershouldperformaneraseoftheinformationmemorypriortothefirstuse. 32KB 48KB 60KB 0FFFFh 0FFFFh 0FFFFh Segment0 withInterruptVectors 0FE00h 0FE00h 0FE00h 0FDFFh 0FDFFh 0FDFFh Segment 1 0FC00h 0FC00h 0FC00h 0FBFFh 0FBFFh 0FBFFh Segment 2 0FA00h 0FA00h 0FA00h 0F9FFh 0F9FFh 0F9FFh Main Memory 08400h 04400h 01400h 083FFh 043FFh 013FFh Segment n-1 08200h 04200h 01200h 081FFh 041FFh 011FFh Segment n (see Note A) 08000h 04000h 01100h 010FFh 010FFh 010FFh Segment A 01080h 01080h 01080h Information 0107Fh 0107Fh 0107Fh Memory Segment B 01000h 01000h 01000h A. MSP430FG43xflashsegmentn=256bytes. Figure6-7.FlashMemorySegments Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 47 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 6.9 Peripherals PeripheralsareconnectedtotheCPUthroughdata,address,andcontrolbusesandcanbehandledusing allinstructions.Forcompletemoduledescriptions,seethe MSP430x4xxFamilyUser'sGuide(SLAU056). 6.9.1 DMA Controller The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without havingtoawakentomovedatatoorfromaperipheral. 6.9.2 Oscillator and System Clock The clock system in the MSP430FG43x family of devices is supported by the FLL+ module, which includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a high frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizesinlessthan6 µs.TheFLL+moduleprovidesthefollowingclocksignals: • Auxiliaryclock(ACLK),sourcedfroma32768-Hzwatchcrystalorahigh-frequencycrystal • Mainclock(MCLK),thesystemclockusedbytheCPU • Sub-Mainclock(SMCLK),thesubsystemclockusedbytheperipheralmodules • ACLK/n,thebufferedoutputofACLK,ACLK/2,ACLK/4,orACLK/8 6.9.3 Brownout, Supply Voltage Supervisor The brownout circuit is implemented to provide the proper internal reset signal to the device during power- on and power-off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) andsupplyvoltagemonitoring(thedeviceisnotautomaticallyreset). The CPU begins code execution after the brownout circuit releases the device reset. However, V may CC not have ramped to V at that time. The user must make sure that the default FLL+ settings are not CC(min) changed until V reaches V . If desired, the SVS circuit can be used to determine when V CC CC(min) CC reachesV . CC(min) 6.9.4 Digital I/O Therearesix8-bitI/Oportsimplemented—portsP1throughP6: • AllindividualI/Obitsareindependentlyprogrammable. • Anycombinationofinput,output,andinterruptconditionsispossible. • Edge-selectableinterruptinputcapabilityforalltheeightbitsofportsP1andP2. • Readandwriteaccesstoport-controlregistersissupportedbyallinstructions 6.9.5 Basic Timer1 The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. The Basic Timer1 can be used to generate periodic interruptsandclockfortheLCDmodule. 48 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.9.6 LCD Drive The LCD driver generates the segment and common signals required to drive an LCD display. The LCD controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral. 6.9.7 OA The MSP430FG43x has three configurable low-current general-purpose operational amplifiers. Each OA input and output terminal is software-selectable and offers a flexible choice of connections for various applications. The OA op amps primarily support front-end analog signal conditioning prior to analog-to- digitalconversion. 6.9.8 Watchdog Timer (WDT) TheprimaryfunctionoftheWDTmoduleistoperformacontrolledsystemrestartafterasoftwareproblem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not neededinanapplication,themodulecanbeconfiguredasanintervaltimerandcangenerateinterruptsat selectedtimeintervals. 6.9.9 USART0 The MSP430FG43x has one hardware universal synchronous/asynchronous receive transmit (USART) peripheralmodulethatisusedforserialdatacommunication.TheUSARTsupportssynchronousSPI(3or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. 6.9.10 Timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compareregisters. Table6-10.Timer_A3SignalConnections INPUTPINNUMBER MODULE OUTPUTPINNUMBER DEVICEINPUT MODULE MODULE OUTPUT ZCA PN SIGNAL INPUTNAME BLOCK SIGNAL PN ZCA B10-P1.5 62-P1.5 TACLK TACLK ACLK ACLK SMCLK SMCLK Timer NA B10-P1.5 62-P1.5 TACLK INCLK D8-P1.0 67-P1.0 TA0 CCI0A 67-P1.0 D8-P1.0 D9-P1.1 66-P1.1 TA0 CCI0B DVSS GND CCR0 TA0 DVCC VCC B9-P1.2 65-P1.2 TA1 CCI1A 65-P1.2 B9-P1.2 CAOUT ADC12 CCI1B (internal) (internal) DVSS GND CCR1 TA1 DVCC VCC C11-P2.0 59-P2.0 TA2 CCI2A 59-P2.0 C11-P2.0 ACLK(internal) CCI2B DVSS GND CCR2 TA2 DVCC VCC Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 49 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 6.9.11 Timer_B3 Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compareregisters. Table6-11.Timer_B3SignalConnections INPUTPINNUMBER MODULE OUTPUTPINNUMBER DEVICEINPUT MODULE MODULE OUTPUT ZCA PN SIGNAL INPUTNAME BLOCK SIGNAL PN ZCA E9-P1.4 63-P1.4 TBCLK TBCLK ACLK ACLK SMCLK SMCLK Timer NA E9-P1.4 63-P1.4 TBCLK INCLK D11-P2.1 58-P2.1 TB0 CCI0A 58-P2.1 D11-P2.1 ADC12 D11-P2.1 58-P2.1 TB0 CCI0B (internal) DVSS GND CCR0 TB0 DVCC VCC E11-P2.2 57-P2.2 TB1 CCI1A 57-P2.2 E11-P2.2 ADC12 E11-P2.2 57-P2.2 TB1 CCI1B (internal) DVSS GND CCR1 TB1 DVCC VCC F11-P2.3 56-P2.3 TB2 CCI2A 56-P2.3 F11-P2.3 F11-P2.3 56-P2.3 TB2 CCI2B DVSS GND CCR2 TB2 DVCC VCC 6.9.12 Comparator_A The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,battery-voltagesupervision,andmonitoringofexternalanalogsignals. 6.9.13 ADC12 The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored withoutanyCPUintervention. 6.9.14 DAC12 The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode, and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present,theymaybegroupedtogetherforsynchronousoperation. 50 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.9.15 Peripheral File Map Table 6-12 shows peripherals with word-access registers, and Table 6-13 shows peripherals with byte- accessregisters. Table6-12.PeripheralsWithWordAccess PERIPHERAL REGISTERNAME ACRONYM OFFSET Watchdog Watchdogtimercontrol WDTCTL 0120h Timer_B3 Capture/compareregister2 TBCCR2 0196h Capture/compareregister1 TBCCR1 0194h Capture/compareregister0 TBCCR0 0192h Timer_Bregister TBR 0190h Capture/comparecontrol2 TBCCTL2 0186h Capture/comparecontrol1 TBCCTL1 0184h Capture/comparecontrol0 TBCCTL0 0182h Timer_Bcontrol TBCTL 0180h Timer_Binterruptvector TBIV 011Eh Capture/compareregister2 TACCR2 0176h Capture/compareregister1 TACCR1 0174h Capture/compareregister0 TACCR0 0172h Timer_A3 Timer_Aregister TAR 0170h Capture/comparecontrol2 TACCTL2 0166h Capture/comparecontrol1 TACCTL1 0164h Capture/comparecontrol0 TACCTL0 0162h Timer_Acontrol TACTL 0160h Timer_Ainterruptvector TAIV 012Eh Flash Flashcontrol3 FCTL3 012Ch Flashcontrol2 FCTL2 012Ah Flashcontrol1 FCTL1 0128h DMA DMAmodulecontrol0 DMACTL0 0122h DMAmodulecontrol1 DMACTL1 0124h DMAchannel0control DMA0CTL 01E0h DMAchannel0sourceaddress DMA0SA 01E2h DMAchannel0destinationaddress DMA0DA 01E4h DMAchannel0transfersize DMA0SZ 01E6h Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 51 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com Table6-12.PeripheralsWithWordAccess(continued) PERIPHERAL REGISTERNAME ACRONYM OFFSET ADC12 Conversionmemory15 ADC12MEM15 015Eh (SeealsoTable6-13) Conversionmemory14 ADC12MEM14 015Ch Conversionmemory13 ADC12MEM13 015Ah Conversionmemory12 ADC12MEM12 0158h Conversionmemory11 ADC12MEM11 0156h Conversionmemory10 ADC12MEM10 0154h Conversionmemory9 ADC12MEM9 0152h Conversionmemory8 ADC12MEM8 0150h Conversionmemory7 ADC12MEM7 014Eh Conversionmemory6 ADC12MEM6 014Ch Conversionmemory5 ADC12MEM5 014Ah Conversionmemory4 ADC12MEM4 0148h Conversionmemory3 ADC12MEM3 0146h Conversionmemory2 ADC12MEM2 0144h Conversionmemory1 ADC12MEM1 0142h Conversionmemory0 ADC12MEM0 0140h Interrupt-vector-wordregister ADC12IV 01A8h Interrupt-enableregister ADC12IE 01A6h Interrupt-flagregister ADC12IFG 01A4h Controlregister1 ADC12CTL1 01A2h Controlregister0 ADC12CTL0 01A0h DAC12 DAC12_1data DAC12_1DAT 01CAh DAC12_1control DAC12_1CTL 01C2h DAC12_0data DAC12_0DAT 01C8h DAC12_0control DAC12_0CTL 01C0h Table6-13.PeripheralsWithByteAccess PERIPHERAL REGISTERNAME ACRONYM OFFSET OA2 OperationalAmplifier2controlregister1 OA2CTL1 0C5h OperationalAmplifier2controlregister0 OA2CTL0 0C4h OA1 OperationalAmplifier1controlregister1 OA1CTL1 0C3h OperationalAmplifier1controlregister0 OA1CTL0 0C2h OA0 OperationalAmplifier0controlregister1 OA0CTL1 0C1h OperationalAmplifier0controlregister0 OA0CTL0 0C0h LCD LCDmemory20 LCDM20 0A4h ⋮ ⋮ ⋮ LCDmemory16 LCDM16 0A0h LCDmemory15 LCDM15 09Fh ⋮ ⋮ ⋮ LCDmemory1 LCDM1 091h LCDcontrolandmode LCDCTL 090h 52 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 Table6-13.PeripheralsWithByteAccess(continued) PERIPHERAL REGISTERNAME ACRONYM OFFSET ADC12 ADCmemory-controlregister15 ADC12MCTL15 08Fh (Memorycontrol ADCmemory-controlregister14 ADC12MCTL14 08Eh registersrequirebyte access) ADCmemory-controlregister13 ADC12MCTL13 08Dh ADCmemory-controlregister12 ADC12MCTL12 08Ch ADCmemory-controlregister11 ADC12MCTL11 08Bh ADCmemory-controlregister10 ADC12MCTL10 08Ah ADCmemory-controlregister9 ADC12MCTL9 089h ADCmemory-controlregister8 ADC12MCTL8 088h ADCmemory-controlregister7 ADC12MCTL7 087h ADCmemory-controlregister6 ADC12MCTL6 086h ADCmemory-controlregister5 ADC12MCTL5 085h ADCmemory-controlregister4 ADC12MCTL4 084h ADCmemory-controlregister3 ADC12MCTL3 083h ADCmemory-controlregister2 ADC12MCTL2 082h ADCmemory-controlregister1 ADC12MCTL1 081h ADCmemory-controlregister0 ADC12MCTL0 080h USART0 Transmitbuffer U0TXBUF 077h (UARTorSPImode) Receivebuffer U0RXBUF 076h Baudrate U0BR1 075h Baudrate U0BR0 074h Modulationcontrol U0MCTL 073h Receivecontrol U0RCTL 072h Transmitcontrol U0TCTL 071h USARTcontrol U0CTL 070h Comparator_A Comparator_Aportdisable CAPD 05Bh Comparator_Acontrol2 CACTL2 05Ah Comparator_Acontrol1 CACTL1 059h BrownOUT,SVS SVScontrolregister(Resetbybrownoutsignal) SVSCTL 056h FLL+Clock FLL+Control1 FLL_CTL1 054h FLL+Control0 FLL_CTL0 053h Systemclockfrequencycontrol SCFQCTL 052h Systemclockfrequencyintegrator SCFI1 051h Systemclockfrequencyintegrator SCFI0 050h BasicTimer1 BTcounter2 BTCNT2 047h BTcounter1 BTCNT1 046h BTcontrol BTCTL 040h PortP6 PortP6selection P6SEL 037h PortP6direction P6DIR 036h PortP6output P6OUT 035h PortP6input P6IN 034h PortP5 PortP5selection P5SEL 033h PortP5direction P5DIR 032h PortP5output P5OUT 031h PortP5input P5IN 030h Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 53 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com Table6-13.PeripheralsWithByteAccess(continued) PERIPHERAL REGISTERNAME ACRONYM OFFSET PortP4 PortP4selection P4SEL 01Fh PortP4direction P4DIR 01Eh PortP4output P4OUT 01Dh PortP4input P4IN 01Ch PortP3 PortP3selection P3SEL 01Bh PortP3direction P3DIR 01Ah PortP3output P3OUT 019h PortP3input P3IN 018h PortP2 PortP2selection P2SEL 02Eh PortP2interruptenable P2IE 02Dh PortP2interrupt-edgeselect P2IES 02Ch PortP2interruptflag P2IFG 02Bh PortP2direction P2DIR 02Ah PortP2output P2OUT 029h PortP2input P2IN 028h PortP1 PortP1selection P1SEL 026h PortP1interruptenable P1IE 025h PortP1interrupt-edgeselect P1IES 024h PortP1interruptflag P1IFG 023h PortP1direction P1DIR 022h PortP1output P1OUT 021h PortP1input P1IN 020h Specialfunctions SFRmoduleenable2 ME2 005h SFRmoduleenable1 ME1 004h SFRinterruptflag2 IFG2 003h SFRinterruptflag1 IFG1 002h SFRinterruptenable2 IE2 001h SFRinterruptenable1 IE1 000h 54 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.10 Input/Output Schematics 6.10.1 Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger Pad Logic DVSS DVSS CAPD.x P1SEL.x 0:Input P1DIR.x 0 1:Output Direction Control 1 From Module 0 P1OUT.x 1 Module X OUT Bus P1.0/TA0 Keeper P1.1/TA0/MCLK P1.2/TA1 P1IN.x P1.3/TBOUTH/SVSOUT P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK EN Module X IN D P1IE.x P1IRQ.x EN Interrupt Q Edge P1IFG.x Set Select P1IES.x P1SEL.x Note:0≤x≤5 Note:Port function is active if CAPD.x = 0 Direction ModuleX PnSEL.x PnDIR.x Control PnOUT.x PnIN.x ModuleXIN PnIE.x PnIFG.x PnIES.x OUT FromModule P1SEL.0 P1DIR.0 P1DIR.0 P1OUT0 Out0sig.(1) P1IN.0 CCI0A(1) P1IE.0 P1IFG.0 P1IES.0 P1SEL.1 P1DIR.1 P1DIR.1 P1OUT.1 MCLK P1IN.1 CCI0B(1) P1IE.1 P1IFG.1 P1IES.1 P1SEL.2 P1DIR.2 P1DIR.2 P1OUT.2 Out1sig.(1) P1IN.2 CCI1A(1) P1IE.2 P1IFG.2 P1IES.2 P1SEL.3 P1DIR.3 P1DIR.3 P1OUT.3 SVSOUT P1IN.3 TBOUTH(2) P1IE.3 P1IFG.3 P1IES.3 P1SEL.4 P1DIR.4 P1DIR.4 P1OUT.4 SMCLK P1IN.4 TBCLK(2) P1IE.4 P1IFG.4 P1IES.4 P1SEL.5 P1DIR.5 P1DIR5 P1OUT.5 ACLK P1IN.5 TACLK(1) P1IE.5 P1IFG.5 P1IES.5 (1) Timer_A (2) Timer_B Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 55 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 6.10.2 Port P1, P1.6 and P1.7, Input/Output With Schmitt Trigger PadLogic Note: Port function is active if CAPD.6 = 0 CAPD.6 P1SEL.6 0:Input 0 P1DIR.6 1:Output P1.6/ 1 P1DIR.6 CA0 0 P1OUT.6 1 DVSS Bus Keeper P1IN.6 EN unused D P1IE.7 P1IRQ.07 EN Interrupt P1IFG.7 Q Edge Set Select P1IES.x P1SEL.x Comparator_A P2CA AVcc CAREF CAEX CA0 CAF + CCI1B CA1 toTimer_Ax - 2 CAREF ReferenceBlock PadLogic Note: Port function is active if CAPD.7 = 0 CAPD.7 P1SEL.7 0:input 0 P1DIR.7 1:output 1 P1.7/ P1DIR.7 CA1 0 P1OUT.7 1 DVSS Bus P1IN.7 keeper EN unused D P1IE.7 P1IRQ.07 EN Interrupt P1IFG.7 Q Edge Set Select P1IES.7 P1SEL.7 56 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.10.3 Port P2, P2.0 and P2.4 to P2.5, Input/Output With Schmitt Trigger Pad Logic DVSS DVSS P2SEL.x 0:Input 0 P2DIR.x 1:Output Direction Control 1 From Module 0 P2OUT.x 1 Module X OUT Bus Keeper P2.0/TA2 P2.4/UTXD0 P2IN.x P2.5/URXD0 EN Module X IN D P2IE.x P2IRQ.x EN Interrupt Q Edge P2IFG.x Set Select P2IES.x P2SEL.x Note: x {0,4,5} Direction ModuleX PnSel.x PnDIR.x Control PnOUT.x PnIN.x ModuleXIN PnIE.x PnIFG.x PnIES.x OUT FromModule P2Sel.0 P2DIR.0 P2DIR.0 P2OUT.0 Out2sig.(1) P2IN.0 CCI2A(1) P2IE.0 P2IFG.0 P2IES.0 P2Sel.4 P2DIR.4 DVCC P2OUT.4 UTXD0(2) P2IN.4 unused P2IE.4 P2IFG.4 P2IES.4 P2Sel.5 P2DIR.5 DVSS P2OUT.5 DVSS P2IN.5 URXD0(2) P2IE.5 P2IFG.5 P2IES.5 (1) Timer_A (2) USART0 Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 57 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 6.10.4 Port P2, P2.1 to P2.3, Input/Output With Schmitt Trigger Pad Logic DVSS DVSS ModuleINofpin P1.3/TBOUTH/SVSOUT P1DIR.3 P1SEL.3 P2SEL.x 0:Input 0 P2DIR.x 1:Output Direction Control 1 From Module P2OUT.x 0 1 Module X OUT Bus Keeper P2.1/TB0 P2.2/TB1 P2IN.x P2.3/TB2 EN Module X IN D P2IE.x P2IRQ.x EN Interrupt Q Edge P2IFG.x Set Select P2IES.x P2SEL.x Note:1≤x≤3 Direction ModuleX PnSel.x PnDIR.x Control PnOUT.x PnIN.x ModuleXIN PnIE.x PnIFG.x PnIES.x OUT FromModule P2Sel.1 P2DIR.1 P2DIR.1 P2OUT.1 Out0sig.(1) P2IN.1 CCI0A(1) P2IE.1 P2IFG.1 P2IES.1 CCI0B P2Sel.2 P2DIR.2 P2DIR.2 P2OUT.2 Out1sig.(1) P2IN.2 CCI1A(1) P2IE.2 P2IFG.2 P2IES.2 CCI1B P2Sel.3 P2DIR.3 P2DIR.3 P2OUT.3 Out2sig.(1) P2IN.3 CCI2A(1) P2IE.3 P2IFG.3 P2IES.3 CCI2B (1) Timer_B 58 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.10.5 Port P2, P2.6 and P2.7, Input/Output With Schmitt Trigger 0:Port active 1:Segment xx function active Pad Logic Port/LCD Segmentxx P2SEL.x 0:Input 0 P2DIR.x 1:Output Direction Control 1 From Module 0 P2OUT.x 1 Module X OUT Bus P2.6/CAOUT/S19 Keeper P2.7/ADC12CLK/S18 P2IN.x EN Module X IN D P2IE.x P2IRQ.x EN Interrupt Q P2IFG.x Edge Set Select P2IES.x P2SEL.x Note:6≤x≤7 Direction Control ModuleX ModuleX PnSel.x PnDIR.x PnOUT.x PnIN.x PnIE.x PnIFG.x PnIES.x Port/LCD From OUT IN Module P2Sel.6 P2DIR.6 P2DIR.6 P2OUT.6 CAOUT(1) P2IN.6 unused P2IE.6 P2IFG.6 P2IES.6 0:LCDPx<02h ADC12CLK P2Sel.7 P2DIR.7 P2DIR.7 P2OUT.7 (2) P2IN.7 unused P2IE.7 P2IFG.7 P2IES.7 0:LCDPx<02h (1) Comparator_A (2) ADC12 Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 59 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 6.10.6 Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger LCDPx[0] MSP430x43xIPN (80-Pin) Only 0:Port active LCDPx[1] 1:Segment xx function active LCDPx[2] Pad Logic x43xIPZ and x44xIPZ have not segment Segment xx Function on Port P3:Both lines are low. P3SEL.x 0:Input 0 P3DIR.x 1:Output Direction Control 1 From Module 0 P3OUT.x 1 Module X OUT Bus Keeper P3.0/STE0/S31 P3.1/SIMO0/S30 P3.2/SOMI0/S29 P3IN.x P3.3/UCLK0/S28 EN Module X IN D Note:0≤x≤3 DirectionControl PnSel.x PnDIR.x PnOUT.x ModuleXOUT PnIN.x ModuleXIN FromModule P3Sel.0 P3DIR.0 DVSS P3OUT.0 DVSS P3IN.0 STE0(in) P3Sel.1 P3DIR.1 DCM_SIMO0 P3OUT.1 SIMO0(out) P3IN.1 SIMO0(in) P3Sel.2 P3DIR.2 DCM_SOMI0 P3OUT.2 SOMIO(out) P3IN.2 SOMI0(in) P3Sel.3 P3DIR.3 DCM_UCLK0 P3OUT.3 UCLK0(out) P3IN.3 UCLK0(in) DirectionControlforSIMO0andUCLK0 Direction Control for SOMI0 SYNC SYNC DCM_SIMO0 MM MM DCM_SOMI0 DCM_UCLK0 STC STC STE STE 60 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.10.7 Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger 0:Port active 1:Segment xx function active Pad Logic LCDPx[2] Segmentxx P3SEL.x 0:Input 0 P3DIR.x 1:Output Direction Control 1 From Module 0 P3OUT.x 1 Module X OUT Bus P3.4/S27 Keeper P3.5/S26 P3.6/S25/DMAE0 P3IN.x P3.7/S24 EN Module X IN D Note:4≤x≤7 DirectionControl PnSel.x PnDIR.x PnOUT.x ModuleXOUT PnIN.x ModuleXIN FromModule P3SEL.4 P3DIR.4 P3DIR.4 P3OUT.4 DVSS P3IN.4 unused P3SEL.5 P3DIR.5 P3DIR.5 P3OUT.5 DVSS P3IN.5 unused P3SEL.6 P3DIR.6 P3DIR.6 P3OUT.6 DVSS P3IN.6 DMAE0 P3SEL.7 P3DIR.7 P3DIR.7 P3OUT.7 DVSS P3IN.7 unused Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 61 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 6.10.8 Port P4, P4.0 to P4.5, Input/Output With Schmitt Trigger 0:Port active 1:Segment xx function active Port/LCD Pad Logic Segment xx P4SEL.x 0:Input 0 P4DIR.x 1:Output Direction Control 1 From Module 0 P4OUT.x 1 Module X OUT Bus P4.0/S9 Keeper P4.1/S8 P4.2/S7 P4IN.x P4.3/S6 P4.4/S5 EN P4.5/S4 Module X IN D Note:0≤x≤5 DirectionControl PnSEL.x PnDIR.x PnOUT.x ModuleXOUT PnIN.x ModuleXIN FromModule P4SEL.0 P4DIR.0 P4DIR.0 P4OUT.0 DVSS P4IN.0 unused P4SEL.1 P4DIR.1 P4DIR.1 P4OUT.1 DVSS P4IN.1 unused P4SEL.2 P4DIR.2 P4DIR.2 P4OUT.2 DVSS P4IN.2 unused P4SEL.3 P4DIR.3 P4DIR.3 P4OUT.3 DVSS P4IN.3 unused P4SEL.4 P4DIR.4 P4DIR.4 P4OUT.4 DVSS P4IN.4 unused P4SEL.5 P4DIR.5 P4DIR.5 P4OUT.5 DVSS P4IN.5 unused DEVICE PORTBITS PORTFUNCTION LCDSEGMENTFUNCTION MSP430FG43x P4.0toP4.5 LCDPx<01h LCDPx≥01h 62 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.10.9 Port P4, P4.6, Input/Output With Schmitt Trigger INCH=15(1) a15(1) 0:SegmentS3disabled 1:SegmentS3enabled 1,IfLCDPx≥01h PadLogic SegmentS3 P4SEL.6 0:input P4DIR.6 0 1:output DirectionControl 1 FromModule P4OUT.6 0 1 ModuleXOUT Bus keeper P4.6/S3/A15 P4IN.6 EN ModuleXIN D (1)SignalfromortoADC12 DirectionControl PnSEL.x PnDIR.x PnOUT.x ModuleXOUT PnIN.x ModuleXIN FromModule P4SEL.6 P4DIR.6 P4DIR.6 P4OUT.6 DVSS P4IN.6 unused DEVICE PORTBITS PORTFUNCTION LCDSEGMENTFUNCTION MSP430FG43x P4.6 LCDPx<01h LCDPx≥01h Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 63 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 6.10.10 Port P4, P4.7, Input/Output With Schmitt Trigger OAADC0 INCH=14(1) a14(1) 0:SegmentS2disabled 1:SegmentS2enabled 1,IfLCDPx≥01h PadLogic SegmentS2 P4SEL.7 0:input P4DIR.7 0 1:output DirectionControl 1 FromModule P4OUT.7 0 1 ModuleXOUT Bus keeper P4.7/S2/A14 P4IN.7 EN ModuleXIN D (1)SignalfromortoADC12 DirectionControl PnSel.x PnDIR.x PnOUT.x ModuleXOUT PnIN.x ModuleXIN FromModule P4Sel.7 P4DIR.7 P4DIR.7 P4OUT.7 DVSS P4IN.7 Unused DEVICE PORTBITS PORTFUNCTION LCDSEGMENTFUNCTION MSP430FG43x P4.7 LCDPx<01h LCDPx≥01h 64 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.10.11 Port P5, P5.0, Input/Output With Schmitt Trigger OAADC0 INCH=13(1) a13(1) 0:SegmentS1disabled 1:SegmentS1enabled 1,IfLCDPx≥01h PadLogic SegmentS1 P5SEL.0 0:input P5DIR.0 0 1:output DirectionControl 1 FromModule P5OUT.0 0 1 ModuleXOUT Bus keeper P5.0/S1/A13 P5IN.0 EN ModuleXIN D (1)SignalfromortoADC12 DirectionControl PnSEL.x PnDIR.x PnOUT.x ModuleXOUT PnIN.x ModuleXIN FromModule P5SEL.0 P5DIR.0 P5DIR.0 P5OUT.0 DVSS P5IN.0 unused DEVICE PORTBITS PORTFUNCTION LCDSEGMENTFUNCTION MSP430FG43x P5.0 LCDPx<01h LCDPx≥01h Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 65 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 6.10.12 Port P5, P5.1, Input/Output With Schmitt Trigger OAADC0 INCH=12(1) a12(1) 0:Segment S0 disabled 1:Segment S0 enabled 1, If LCDPx≥01h Pad Logic DAC12.1OPS Segment S0 P5SEL.1 0:input 0 P5DIR.1 1:output Direction Control 1 From Module P5OUT.1 0 1 Module XOUT Bus keeper P5.1/S0/ A12/DAC1 P5IN.1 EN Module X IN D ’0’,ifDAC12.1CALON=0AND DAC12.1AMPx>1ANDDAC12.1OPS=1 + 1 0 - ’1’, if DAC12.1AMPx>1 ’1’, if DAC12.1AMPx=1 DAC12.1OPS DAC12.1OPS 1 P6.7/A7/ DAC1_2_OA DAC1/SVSIN 0 (1)SignalfromortoADC12 Function Description P5SEL.1 LCDPx DAC12.1OPS DAC12.1AMPx 3-State X X 1 0 0V X X 1 1 DAC12 DAC1output X X 1 >1 (theoutputvoltagecanbeconvertedwithADC12,channelA12) ADC12 Channel12,A12 1 X 0 X LCD SegmentS0,initialstate 0 ≥01h 0 X Port P5.1 0 <01h 0 X Direction PnSEL.x PnDIR.x ControlFrom PnOUT.x ModuleXOUT PnIN.x ModuleXIN Segment Port/LCD Module P5SEL.1 P5DIR.1 P5DIR.1 P5OUT.1 DVSS P5IN.1 Unused S0 0:LCDPx<01h 66 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.10.13 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger 0:Port active 1:LCD function active Pad Logic Port/LCD LCD signal P5SEL.x 0:Input 0 P5DIR.x 1:Output Direction Control 1 From Module 0 P5OUT.x 1 Module X OUT Bus Keeper P5.2/COM1 P5.3/COM2 P5.4/COM3 P5IN.x EN Module X IN D Note: 2≤x≤4 Direction PnSel.x PnDIR.x ControlFrom PnOUT.x ModuleXOUT PnIN.x ModuleXIN LCDsignal Port/LCD Module P5Sel.2 P5DIR.2 P5DIR.2 P5OUT.2 DVSS P5IN.2 Unused COM1 P5SEL.2 P5Sel.3 P5DIR.3 P5DIR.3 P5OUT.3 DVSS P5IN.3 Unused COM2 P5SEL.3 P5Sel.4 P5DIR.4 P5DIR.4 P5OUT.4 DVSS P5IN.4 Unused COM3 P5SEL.4 Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 67 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 6.10.14 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger 0:Port active 1:LCD function active Pad Logic Port/LCD LCD signal P5SEL.x 0:Input 0 P5DIR.x 1:Output Direction Control 1 From Module 0 P5OUT.x 1 Module X OUT Bus Keeper P5.5/R13 P5.6/R23 P5.7/R33 P5IN.x EN Module X IN D Note: 5≤x≤7 Direction PnSel.x PnDIR.x ControlFrom PnOUT.x ModuleXOUT PnIN.x ModuleXIN LCDsignal Port/LCD Module P5Sel.5 P5DIR.5 P5DIR.5 P5OUT.5 DVSS P5IN.5 Unused R13 P5SEL.5 P5Sel.6 P5DIR.6 P5DIR.6 P5OUT.6 DVSS P5IN.6 Unused R23 P5SEL.6 P5Sel.7 P5DIR.7 P5DIR.7 P5OUT.7 DVSS P5IN.7 Unused R33 P5SEL.7 68 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.10.15 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger (1)(2) INCH=x (1)(2) ax (1) P6SEL.x PadLogic (1) 0 0:input P6DIR.x 1:output DirectionControl 1 FromModule P6OUT.x(1) 0 1 ModuleXOUT Bus keeper P6.0/A0/OA0I0 P6.2/A2/OA0I1 (1) P6.4/A4/OA1I0 P6IN.x EN (1) ModuleXIN D + - (1) x = {0, 2, 4} OA0/OA1 (2) SignalfromortoADC12 PnSel.x(1) PnDIR.x DirectionControl PnOUT.x ModuleXOUT PnIN.x ModuleXIN FromModule P6Sel.0 P6DIR.0 P6DIR.0 P6OUT.0 DVSS P6IN.0 unused P6Sel.2 P6DIR.2 P6DIR.2 P6OUT.2 DVSS P6IN.2 unused P6Sel.4 P6DIR.4 P6DIR.4 P6OUT.4 DVSS P6IN.4 unused (1) ThesignalatpinP6.x/Axisusedbythe12-bitADCmodule. Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 69 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 6.10.16 Port P6, P6.1, Input/Output With Schmitt Trigger INCH=1(1) a1(1) P6SEL.1 PadLogic 0 0:input P6DIR.1 1:output DirectionControl 1 FromModule P6OUT.1 0 1 ModuleXOUT Bus keeper P6.1/A1/OA0O P6IN.1 EN ModuleXIN D ’1’, if OAADC1 = 1 OR OAFCx = 0 + 0 OA0 - 1 (1)SignalfromortoADC12 OA0 PnSel.x(1) PnDIR.x DirectionControl PnOUT.x ModuleXOUT PnIN.x ModuleXIN FromModule P6Sel.1 P6DIR.1 P6DIR.1 P6OUT.1 DVSS P6IN.1 unused (1) ThesignalatpinP6.x/Axisusedbythe12-bitADCmodule. 70 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.10.17 Port P6, P6.3, Input/Output With Schmitt Trigger INCH=3(1) a3(1) P6SEL.3 PadLogic 0 0:input P6DIR.3 1:output DirectionControl 1 FromModule P6OUT.3 0 1 ModuleXOUT Bus keeper P6.3/A3/OA1I1/OA1O P6IN.3 EN ModuleXIN D ’1’,ifOAADC1=1OROAFCx=0 + 0 OA1 - 1 (1)SignalfromortoADC12 OA1 PnSel.x(1) PnDIR.x DirectionControl PnOUT.x ModuleXOUT PnIN.x ModuleXIN FromModule P6Sel.3 P6DIR.3 P6DIR.3 P6OUT.3 DVSS P6IN.3 unused (1) ThesignalatpinP6.x/Axisusedbythe12-bitADCmodule. Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 71 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 6.10.18 Port P6, P6.5, Input/Output With Schmitt Trigger INCH=5(1) a5(1) P6SEL.5 PadLogic 0 0:input P6DIR.5 1:output DirectionControl 1 FromModule P6OUT.5 0 1 ModuleXOUT Bus keeper P6.5/A5/OA2I1/OA2O P6IN.5 EN ModuleXIN D ’1’, if OAADC1 = 1 OR OAFCx = 0 + 0 OA2 - 1 (1)SignalfromortoADC12 OA2 PnSel.x(1) PnDIR.x DirectionControl PnOUT.x ModuleXOUT PnIN.x ModuleXIN FromModule P6Sel.5 P6DIR.5 P6DIR.5 P6OUT.5 DVSS P6IN.5 unused (1) ThesignalatpinsP6.x/Axisusedbythe12-bitADCmodule. 72 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.10.19 Port P6, P6.6, Input/Output With Schmitt Trigger 0:Portactive,T-Switchoff 1:T-Switchison,Portdisabled INCH=6(1) a6(1) ’1’,ifDAC12.0AMP>0 P6SEL.6 0:input PadLogic 0 P6DIR.6 1:output P6DIR.6 1 P6OUT.6 0 1 DVSS Bkeuesper P6.6/A6/DAC0/OA2I0 P6IN.6 EN D ’0’,ifDAC12CALON=0AND DAC12AMPx>1ANDDAC12OPS=0 + 1 - 0 ’1’, if DAC12AMPx>1 (1)SignalfromortoADC12 ’1’,ifDAC12AMPx=1 DAC12OPS DAC12OPS 0 DAC0_2_OA VeREF+/DAC0 1 PnSel.x(1) PnDIR.x DirectionControl PnOUT.x ModuleXOUT PnIN.x ModuleXIN FromModule P6Sel.6 P6DIR.6 P6DIR.6 P6OUT.6 DVSS P6IN.6 unused (1) ThesignalatpinsP6.x/Axisusedbythe12-bitADCmodule. Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 73 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 6.10.20 Port P6, P6.7, Input/Output With Schmitt Trigger To SVS Mux (15)(2) 0: Port active,T−Switch off 1:T−Switch is on, Port disabled INCH=7(1) a7(1) ’1’, if DAC12.1AMP>0 DAC12.1OPS ’1’, if VLD=15(3) Pad Logic P6SEL.7 0: input P6DIR.7 0 1: output P6DIR.7 1 P6OUT.7 0 1 DVSS Bus keeper P6.7/A7/ DAC1/SVSIN P6IN.7 EN D ’0’, if DAC12CALON = 0AND DAC12AMPx>1AND DAC12OPS = 0 + 1 − 0 ’1’, if DAC12AMPx>1 ’1’, if DAC12AMPx=1 DAC12OPS DAC12OPS 0 P5.1/S0/ DAC1_2_OA A12/DAC1 1 (1)Signal from or to ADC12 (2)Signal to SVS block, selected if VLD=15 (3)VLD control bits are located in SVS PnSel.x(1) PnDIR.x DirectionControl PnOUT.x ModuleXOUT PnIN.x ModuleXIN FromModule P6Sel.7 P6DIR.7 P6DIR.7 P6OUT.7 DVSS P6IN.7 unused (1) ThesignalatpinsP6.x/Axisusedbythe12-bitADCmodule.ThesignalatpinP6.7/A7/SVSINisalsoconnectedtotheinputmultiplexer inthemodulebrownout/supplyvoltagesupervisor. 74 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.10.21 VeREF+/DAC0 DAC12.0OPS 0 DAC0_2_OA P6.6/A6/DAC0/OA2I0 1 ReferenceVoltage to DAC1 ReferenceVoltagetoADC12 ReferenceVoltage to DAC0(1) Ve /DAC0 REF+ ’0’, if DAC12CALON = 0 DAC12AMPx>1ANDDAC12OPS=1 + 1 0 - ’1’, if DAC12AMPx>1 ’1’, if DAC12AMPx=1 DAC12OPS (1)If the reference of DAC0 is taken from pinVe /DAC0,unpredictablevoltagelevelswillbeonpin. REF+ In this situation, the DAC0 output is fed back to its own reference input. Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 75 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 6.10.22 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output TDO ControlledbyJTAG ControlledbyJTAG TDO/TDI JTAG Controlled DV byJTAG CC TDI BurnandTest Fuse TDI/TCLK Test DV and CC Emulation TMS Module TMS DV CC TCK TCK RST/NMI Tau ~ 50 ns D Brownout G U S D TCK U G S 76 DetailedDescription Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 6.10.23 JTAG Fuse Check Mode MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current (I ) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse (TF) is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overallsystempowerconsumption. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. AftereachPORthefusecheckmodehasthepotentialtobeactivated. The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see Figure 6-8). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). The JTAG pins are terminated internally and therefore do not require external termination. TimeTMSGoesLowAfterPOR TMS I(TF) ITDI/TCLK Figure6-8.FuseCheckModeCurrent Copyright©2004–2014,TexasInstrumentsIncorporated DetailedDescription 77 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 7 Device and Documentation Support 7.1 Device Support 7.1.1 Development Support TI offers an extensive line of development tools, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code ComposerStudio™IntegratedDevelopmentEnvironment(IDE). ThefollowingproductssupportdevelopmentoftheMSP430FG43xdeviceapplications: Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE): includingEditorC/C++/AssemblyCodeGeneration,andDebugplusadditionaldevelopmenttools. For a complete listing of development-support tools for the MSP430FG43x platform, visit the Texas Instruments website at www.ti.com. For information on pricing and availability, contact the nearest TI field salesofficeorauthorizeddistributor. 7.1.1.1 DevelopmentKit The MSP-FET430U80 is a powerful flash emulation tool that includes the hardware and software required toquicklybeginapplicationdevelopmentontheMSP430MCU.ItincludesaZIFsockettargetboardanda USB debugging interface (MSP-FET) used to program and debug the MSP430 in-system through the JTAG interface or the pin saving Spy Bi-Wire (2-wire JTAG) protocol. The flash memory can be erased and programmed in seconds with only a few keystrokes, and because the MSP430 flash is ultra-low power,noexternalpowersupplyisrequired. The debugging tool interfaces the MSP430 to the included integrated software environment and includes codetostartyourdesignimmediately. 7.1.2 Device and Development Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of three prefixes: MSP, PMS, or XMS (for example, MSP430F5259). Texas Instruments recommends two of three possible prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionarystagesofproductdevelopmentfromengineeringprototypes(withXMSfordevicesandMSPX fortools)throughfullyqualifiedproductiondevicesandtools(withMSPfordevicesandMSPfortools). Devicedevelopmentevolutionaryflow: XMS – Experimental device that is not necessarily representative of the final device's electrical specifications PMS – Final silicon die that conforms to the device's electrical specifications but has not completed quality andreliabilityverification MSP–Fullyqualifiedproductiondevice Supporttooldevelopmentevolutionaryflow: MSPX – Development-support product that has not yet completed Texas Instruments internal qualification testing. MSP–Fully-qualifieddevelopment-supportproduct XMS and PMS devices and MSPX development-support tools are shipped against the following disclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." 78 DeviceandDocumentationSupport Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 MSP devices and MSP development-support tools have been characterized fully, and the quality and reliabilityofthedevicehavebeendemonstratedfully.TI'sstandardwarrantyapplies. Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production systembecausetheirexpectedend-usefailureratestillisundefined.Onlyqualifiedproductiondevicesare tobeused. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PZP) and temperature range (for example, T). Figure 7-1 provides a legend forreadingthecompletedevicenameforanyfamilymember. MSP 430 F 5 438 A I ZQW T XX Processor Family Optional:Additional Features 430 MCU Platform Optional:Tape and Reel DeviceType Packaging Series Optional:Temperature Range Feature Set Optional:A= Revision Processor Family CC = Embedded RF Radio MSP= Mixed Signal Processor XMS = Experimental Silicon PMS = Prototype Device 430 MCU Platform TI’s Low Power Microcontroller Platform Device Type Memory Type SpecializedApplication C = ROM AFE =Analog Front End F = Flash BT= Preprogrammed withBluetooth FR = FRAM BQ = Contactless Power G = Flash or FRAM (Value Line) CG = ROM Medical L= No Nonvolatile Memory FE = Flash Energy Meter FG = Flash Medical FW = Flash Electronic Flow Meter Series 1 Series = Up to 8 MHz 5 Series = Up to 25 MHz 2 Series = Up to 16 MHz 6 Series = Up to 25 MHz w/ LCD 3 Series = Legacy 0 = Low Voltage Series 4 Series = Up to 16 MHz w/ LCD Feature Set Various Levels of Integration Within a Series Optional:A= Revision N/A Optional: Temperature Range S = 0°C to 50°C C = 0°C to 70°C I = -40°C to 85°C T= -40°C to 105°C Packaging www.ti.com/packaging Optional: Tape and Reel T= Small Reel R = Large Reel No Markings =Tube orTray Optional:Additional Features -EP= Enhanced Product (-40°C to 105°C) -HT= ExtremeTemperature Parts (-55°C to 150°C) -Q1 =Automotive Q100 Qualified Figure7-1.DeviceNomenclature Copyright©2004–2014,TexasInstrumentsIncorporated DeviceandDocumentationSupport 79 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 SLAS380D–APRIL2004–REVISEDNOVEMBER2014 www.ti.com 7.2 Documentation Support The following documents describe the MSP430FG43x microcontrollers. Copies of these documents are availableontheInternetatwww.ti.com. SLAU056 MSP430x4xx Family User's Guide. Detailed description of all modules and peripherals availableinthisdevicefamily. SLAZ365 MSP430FG439 Device Erratasheet. Describes the known exceptions to the functional specificationsforallsiliconrevisionsofthisdevice. SLAZ364 MSP430FG438 Device Erratasheet. Describes the known exceptions to the functional specificationsforallsiliconrevisionsofthisdevice. SLAZ363 MSP430FG437 Device Erratasheet. Describes the known exceptions to the functional specificationsforallsiliconrevisionsofthisdevice. 7.2.1 Related Links Table 7-1 lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table7-1.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY MSP430FG439 Clickhere Clickhere Clickhere Clickhere Clickhere MSP430FG438 Clickhere Clickhere Clickhere Clickhere Clickhere MSP430FG437 Clickhere Clickhere Clickhere Clickhere Clickhere 7.2.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; seeTI'sTermsofUse. TIE2E™Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. TIEmbeddedProcessorsWiki TexasInstrumentsEmbeddedProcessorsWiki.Establishedtohelpdevelopersgetstartedwithembedded processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardwareandsoftwaresurroundingthesedevices. 7.3 Trademarks MSP430,E2EaretrademarksofTexasInstruments. 7.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 7.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 80 DeviceandDocumentationSupport Copyright©2004–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

MSP430FG439,MSP430FG438,MSP430FG437 www.ti.com SLAS380D–APRIL2004–REVISEDNOVEMBER2014 8 Mechanical Packaging and Orderable Information 8.1 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revisionofthisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2004–2014,TexasInstrumentsIncorporated MechanicalPackagingandOrderableInformation 81 SubmitDocumentationFeedback ProductFolderLinks:MSP430FG439 MSP430FG438 MSP430FG437

PACKAGE OPTION ADDENDUM www.ti.com 31-May-2017 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MSP430FG437IPN ACTIVE LQFP PN 80 119 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 M430FG437 & no Sb/Br) MSP430FG437IPNR ACTIVE LQFP PN 80 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 M430FG437 & no Sb/Br) MSP430FG437IZCAR ACTIVE NFBGA ZCA 113 2500 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 FG437 & no Sb/Br) MSP430FG437IZCAT ACTIVE NFBGA ZCA 113 250 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 FG437 & no Sb/Br) MSP430FG438IPN ACTIVE LQFP PN 80 119 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 M430FG438 & no Sb/Br) MSP430FG438IPNR ACTIVE LQFP PN 80 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 M430FG438 & no Sb/Br) MSP430FG438IZCAR ACTIVE NFBGA ZCA 113 2500 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 FG438 & no Sb/Br) MSP430FG438IZCAT ACTIVE NFBGA ZCA 113 250 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 FG438 & no Sb/Br) MSP430FG439IPN ACTIVE LQFP PN 80 119 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 M430FG439 & no Sb/Br) MSP430FG439IPNR ACTIVE LQFP PN 80 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 M430FG439 & no Sb/Br) MSP430FG439IZCAR ACTIVE NFBGA ZCA 113 2500 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 FG439 & no Sb/Br) MSP430FG439IZCAT ACTIVE NFBGA ZCA 113 250 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 FG439 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 31-May-2017 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 27-Jun-2015 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) MSP430FG437IPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2 MSP430FG437IZCAR NFBGA ZCA 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 MSP430FG437IZCAT NFBGA ZCA 113 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 MSP430FG438IPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2 MSP430FG438IZCAR NFBGA ZCA 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 MSP430FG438IZCAT NFBGA ZCA 113 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 MSP430FG439IPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2 MSP430FG439IZCAR NFBGA ZCA 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 MSP430FG439IZCAT NFBGA ZCA 113 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 27-Jun-2015 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) MSP430FG437IPNR LQFP PN 80 1000 367.0 367.0 45.0 MSP430FG437IZCAR NFBGA ZCA 113 2500 341.0 336.6 31.8 MSP430FG437IZCAT NFBGA ZCA 113 250 341.0 336.6 31.8 MSP430FG438IPNR LQFP PN 80 1000 367.0 367.0 45.0 MSP430FG438IZCAR NFBGA ZCA 113 2500 341.0 336.6 31.8 MSP430FG438IZCAT NFBGA ZCA 113 250 341.0 336.6 31.8 MSP430FG439IPNR LQFP PN 80 1000 367.0 367.0 45.0 MSP430FG439IZCAR NFBGA ZCA 113 2500 341.0 336.6 31.8 MSP430FG439IZCAT NFBGA ZCA 113 250 341.0 336.6 31.8 PackMaterials-Page2

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MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 M 0,17 60 41 61 40 0,13 NOM 80 21 1 20 Gage Plane 9,50 TYP 12,20 0,25 SQ 11,80 0,05 MIN 0°–7° 14,20 SQ 13,80 0,75 1,45 0,45 1,35 Seating Plane 1,60 MAX 0,08 4040135/B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

IMPORTANTNOTICE TexasInstrumentsIncorporated(TI)reservestherighttomakecorrections,enhancements,improvementsandotherchangestoits semiconductorproductsandservicesperJESD46,latestissue,andtodiscontinueanyproductorserviceperJESD48,latestissue.Buyers shouldobtainthelatestrelevantinformationbeforeplacingordersandshouldverifythatsuchinformationiscurrentandcomplete. TI’spublishedtermsofsaleforsemiconductorproducts(http://www.ti.com/sc/docs/stdterms.htm)applytothesaleofpackagedintegrated circuitproductsthatTIhasqualifiedandreleasedtomarket.AdditionaltermsmayapplytotheuseorsaleofothertypesofTIproductsand services. ReproductionofsignificantportionsofTIinformationinTIdatasheetsispermissibleonlyifreproductioniswithoutalterationandis accompaniedbyallassociatedwarranties,conditions,limitations,andnotices.TIisnotresponsibleorliableforsuchreproduced documentation.Informationofthirdpartiesmaybesubjecttoadditionalrestrictions.ResaleofTIproductsorserviceswithstatements differentfromorbeyondtheparametersstatedbyTIforthatproductorservicevoidsallexpressandanyimpliedwarrantiesforthe associatedTIproductorserviceandisanunfairanddeceptivebusinesspractice.TIisnotresponsibleorliableforanysuchstatements. BuyersandotherswhoaredevelopingsystemsthatincorporateTIproducts(collectively,“Designers”)understandandagreethatDesigners remainresponsibleforusingtheirindependentanalysis,evaluationandjudgmentindesigningtheirapplicationsandthatDesignershave fullandexclusiveresponsibilitytoassurethesafetyofDesigners'applicationsandcomplianceoftheirapplications(andofallTIproducts usedinorforDesigners’applications)withallapplicableregulations,lawsandotherapplicablerequirements.Designerrepresentsthat,with respecttotheirapplications,Designerhasallthenecessaryexpertisetocreateandimplementsafeguardsthat(1)anticipatedangerous consequencesoffailures,(2)monitorfailuresandtheirconsequences,and(3)lessenthelikelihoodoffailuresthatmightcauseharmand takeappropriateactions.DesigneragreesthatpriortousingordistributinganyapplicationsthatincludeTIproducts,Designerwill thoroughlytestsuchapplicationsandthefunctionalityofsuchTIproductsasusedinsuchapplications. TI’sprovisionoftechnical,applicationorotherdesignadvice,qualitycharacterization,reliabilitydataorotherservicesorinformation, including,butnotlimitedto,referencedesignsandmaterialsrelatingtoevaluationmodules,(collectively,“TIResources”)areintendedto assistdesignerswhoaredevelopingapplicationsthatincorporateTIproducts;bydownloading,accessingorusingTIResourcesinany way,Designer(individuallyor,ifDesignerisactingonbehalfofacompany,Designer’scompany)agreestouseanyparticularTIResource solelyforthispurposeandsubjecttothetermsofthisNotice. TI’sprovisionofTIResourcesdoesnotexpandorotherwisealterTI’sapplicablepublishedwarrantiesorwarrantydisclaimersforTI products,andnoadditionalobligationsorliabilitiesarisefromTIprovidingsuchTIResources.TIreservestherighttomakecorrections, enhancements,improvementsandotherchangestoitsTIResources.TIhasnotconductedanytestingotherthanthatspecifically describedinthepublisheddocumentationforaparticularTIResource. Designerisauthorizedtouse,copyandmodifyanyindividualTIResourceonlyinconnectionwiththedevelopmentofapplicationsthat includetheTIproduct(s)identifiedinsuchTIResource.NOOTHERLICENSE,EXPRESSORIMPLIED,BYESTOPPELOROTHERWISE TOANYOTHERTIINTELLECTUALPROPERTYRIGHT,ANDNOLICENSETOANYTECHNOLOGYORINTELLECTUALPROPERTY RIGHTOFTIORANYTHIRDPARTYISGRANTEDHEREIN,includingbutnotlimitedtoanypatentright,copyright,maskworkright,or otherintellectualpropertyrightrelatingtoanycombination,machine,orprocessinwhichTIproductsorservicesareused.Information regardingorreferencingthird-partyproductsorservicesdoesnotconstitutealicensetousesuchproductsorservices,orawarrantyor endorsementthereof.UseofTIResourcesmayrequirealicensefromathirdpartyunderthepatentsorotherintellectualpropertyofthe thirdparty,oralicensefromTIunderthepatentsorotherintellectualpropertyofTI. TIRESOURCESAREPROVIDED“ASIS”ANDWITHALLFAULTS.TIDISCLAIMSALLOTHERWARRANTIESOR REPRESENTATIONS,EXPRESSORIMPLIED,REGARDINGRESOURCESORUSETHEREOF,INCLUDINGBUTNOTLIMITEDTO ACCURACYORCOMPLETENESS,TITLE,ANYEPIDEMICFAILUREWARRANTYANDANYIMPLIEDWARRANTIESOF MERCHANTABILITY,FITNESSFORAPARTICULARPURPOSE,ANDNON-INFRINGEMENTOFANYTHIRDPARTYINTELLECTUAL PROPERTYRIGHTS.TISHALLNOTBELIABLEFORANDSHALLNOTDEFENDORINDEMNIFYDESIGNERAGAINSTANYCLAIM, INCLUDINGBUTNOTLIMITEDTOANYINFRINGEMENTCLAIMTHATRELATESTOORISBASEDONANYCOMBINATIONOF PRODUCTSEVENIFDESCRIBEDINTIRESOURCESOROTHERWISE.INNOEVENTSHALLTIBELIABLEFORANYACTUAL, DIRECT,SPECIAL,COLLATERAL,INDIRECT,PUNITIVE,INCIDENTAL,CONSEQUENTIALOREXEMPLARYDAMAGESIN CONNECTIONWITHORARISINGOUTOFTIRESOURCESORUSETHEREOF,ANDREGARDLESSOFWHETHERTIHASBEEN ADVISEDOFTHEPOSSIBILITYOFSUCHDAMAGES. UnlessTIhasexplicitlydesignatedanindividualproductasmeetingtherequirementsofaparticularindustrystandard(e.g.,ISO/TS16949 andISO26262),TIisnotresponsibleforanyfailuretomeetsuchindustrystandardrequirements. WhereTIspecificallypromotesproductsasfacilitatingfunctionalsafetyorascompliantwithindustryfunctionalsafetystandards,such productsareintendedtohelpenablecustomerstodesignandcreatetheirownapplicationsthatmeetapplicablefunctionalsafetystandards andrequirements.Usingproductsinanapplicationdoesnotbyitselfestablishanysafetyfeaturesintheapplication.Designersmust ensurecompliancewithsafety-relatedrequirementsandstandardsapplicabletotheirapplications.DesignermaynotuseanyTIproductsin life-criticalmedicalequipmentunlessauthorizedofficersofthepartieshaveexecutedaspecialcontractspecificallygoverningsuchuse. Life-criticalmedicalequipmentismedicalequipmentwherefailureofsuchequipmentwouldcauseseriousbodilyinjuryordeath(e.g.,life support,pacemakers,defibrillators,heartpumps,neurostimulators,andimplantables).Suchequipmentincludes,withoutlimitation,all medicaldevicesidentifiedbytheU.S.FoodandDrugAdministrationasClassIIIdevicesandequivalentclassificationsoutsidetheU.S. TImayexpresslydesignatecertainproductsascompletingaparticularqualification(e.g.,Q100,MilitaryGrade,orEnhancedProduct). Designersagreethatithasthenecessaryexpertisetoselecttheproductwiththeappropriatequalificationdesignationfortheirapplications andthatproperproductselectionisatDesigners’ownrisk.Designersaresolelyresponsibleforcompliancewithalllegalandregulatory requirementsinconnectionwithsuchselection. DesignerwillfullyindemnifyTIanditsrepresentativesagainstanydamages,costs,losses,and/orliabilitiesarisingoutofDesigner’snon- compliancewiththetermsandprovisionsofthisNotice. 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