Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 MSP430F5310, MSP430F530x Mixed-Signal Microcontrollers 1 Device Overview 1.1 Features 1 • LowSupply-VoltageRange: – Low-PowerLow-FrequencyInternalClock 3.6VDownto1.8V Source(VLO) • Ultra-LowPowerConsumption – Low-FrequencyTrimmedInternalReference Source(REFO) – ActiveMode(AM) AllSystemClocksActive – 32-kHzWatchCrystals(XT1) – 195 µA/MHz(Typical)at8MHz,3V,Flash – High-FrequencyCrystalsupto32MHz(XT2) ProgramExecution • 16-BitTimerTA0,Timer_AWithFive – 115 µA/MHz(Typical)at8MHz,3V,RAM Capture/CompareRegisters ProgramExecution • 16-BitTimerTA1,Timer_AWithThree – StandbyMode(LPM3) Capture/CompareRegisters – Real-TimeClock(RTC)WithCrystal, • 16-BitTimerTA2,Timer_AWithThree Watchdog,andSupplySupervisor Capture/CompareRegisters Operational,FullRAMRetention,Fast • 16-BitTimerTB0,Timer_BWithSeven Wakeup: Capture/CompareShadowRegisters 1.9 µA(Typical)at2.2V, • TwoUniversalSerialCommunicationInterfaces 2.1 µA(Typical)at3V (USCIs) – Low-PowerOscillator(VLO),General- – USCI_A0andUSCI_A1 PurposeCounter,Watchdog,andSupply – EnhancedUARTSupportsAutomaticBaud- SupervisorOperational,FullRAMRetention, RateDetection FastWakeup: – IrDAEncoderandDecoder 1.4 µA(Typical)at3V – SynchronousSPI – OffMode(LPM4) – USCI_B0andUSCI_B1 FullRAMRetention,SupplySupervisor Operational,FastWakeup: – I2C 1.1 µAat3V(Typical) – SynchronousSPI – ShutdownMode(LPM4.5) • Integrated3.3-VPowerSystem 0.18µAat3V(Typical) • 10-BitAnalog-to-DigitalConverter(ADC)With • WakeupFromStandbyModeinLessThan5µs WindowComparator • 16-BitRISCArchitecture,ExtendedMemory,upto • Comparator 25-MHzSystemClock • HardwareMultiplierSupports32-BitOperations • FlexiblePower-ManagementSystem • SerialOnboardProgramming,NoExternal – FullyIntegratedLDOWithProgrammable ProgrammingVoltageNeeded RegulatedCoreSupplyVoltage • 3-ChannelInternalDMA – SupplyVoltageSupervision,Monitoring,and • BasicTimerWithRTCFeature Brownout • DeviceComparisonSummarizestheAvailable • UnifiedClockSystem(UCS) FamilyMembers – FLLControlLoopforFrequencyStabilization 1.2 Applications • AnalogandDigitalSensorSystems • Thermostats • DigitalMotorControl • DigitalTimers • RemoteControls • Hand-HeldMeters 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 1.3 Description The TI MSP family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to activemodeinlessthan5 µs. The MSP430F5310, MSP430F5309, and MSP430F5308 devices are microcontroller configurations with a 3.3-V LDO, four 16-bit timers, a high-performance 10-bit ADC, two USCIs (1), a hardware multiplier, DMA, anRTCmodulewithalarmcapabilities,and31or47I/Opins. The MSP430F5304 device is a configuration with a 3.3-V LDO, four 16-bit timers, a high-performance 10- bitADC,oneUSCI,ahardwaremultiplier,DMA,anRTCmodulewithalarmcapabilities,and31I/Opins. Forcompletemoduledescriptions,seethe MSP430F5xxandMSP430F6xxFamilyUser'sGuide. (1) Inthe48-pinpackages,theUSCIfunctionsthatarepinnedoutarelimitedtowhattheuserconfiguresonport4withtheportmapping controller.Itmaynotbepossibletobringoutallfunctionssimultaneously. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(2) MSP430F5310RGC VQFN(64) 9mm×9mm MSP430F5310ZQE BGA(80) 5mm×5mm MSP430F5310PT LQFP(48) 7mm×7mm MSP430F5310RGZ VQFN(48) 7mm×7mm (1) Forthemostcurrentpart,package,andorderinginformation,seethePackageOptionAddendumin Section8,orseetheTIwebsiteatwww.ti.com. (2) Thesizesshownhereareapproximations.Forthepackagedimensionswithtolerances,seethe MechanicalDatainSection8. 2 DeviceOverview Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 1.4 Functional Block Diagrams Figure1-1throughFigure1-3 showthefunctionalblockdiagrams. XIN XOUT RST/NMI DVCCDVSSVCORE AVCC AVSS PA PB PC P1.x P2.x P3.x P4.x P5.x P6.x XT2IN SYS REF COMP_B ADC10_A Unified ACLK Power I/O Ports I/O Ports I/O Ports XT2OUT SCylsotcekm SMCLK 321246KKKBBB 6KB Management WPoartct hMdaopg I2nP×te18r, rIPu/Op2st, 11P××358, IIP//OO4ss 11P××568, IIP//OO6ss 20100 K BSiPtS MCLK Flash RAM SVLMD/SOVS C(oPn4tr)ol Wakeup (1120 Cehxat,n2n einlst) Brownout PA PB PC Window 1×16 I/Os 1×13 I/Os 1×14 I/Os Comparator CPUXV2 MAB DMA and Working MDB 3 Channel Registers EEM (S:3+1) USCI0,1 PU Port JTAG, TA0 TA1 TA2 TB0 InSteBrfWace MPY32 Timer_A Timer_A Timer_A Timer_B RTC_A CRC16 AIrxD: AU,A SRPTI, LDO 5 CC 3 CC 3 CC 7 CC Registers Registers Registers Registers Bx: SPI, I2C PU.0, PU.1 Copyright © 2016,Texas Instruments Incorporated Figure1-1.'FunctionalBlockDiagram – MSP430F5310IRGC,MSP430F5309IRGC,MSP430F5308IRG, MSP430F5310IZQE,MSP430F5309IZQE,MSP430F5308IZQE Copyright©2010–2018,TexasInstrumentsIncorporated DeviceOverview 3 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com XIN XOUT RST/NMI DVCCDVSS VCORE AVCC AVSS PA PB PC P1.x P2.x P3.x P4.x P5.x P6.x XT2IN SYS REF COMP_B ADC10_A Unified ACLK Power I/O Ports I/O Ports I/O Ports XT2OUT SCylsotcekm SMCLK 321246KKKBBB 6KB Management WPoartct hMdaopg 11P××181, IIP//OO2ss 1×8P 4I/Os 11P××564, IIP//OO6ss 20100 K BSiPtS MCLK Flash RAM SVLMD/SOVS C(oPn4tr)ol IWntaekrreuuppt, (86 Cehxat,n2n einlst) Brownout PA PB PC Window 1×9 I/Os 1×8 I/Os 1×10 I/Os Comparator CPUXV2 MAB DMA and Working MDB 3 Channel Registers EEM (S:3+1) USCI0,1 PU Port JTAG, TA0 TA1 TA2 TB0 InSteBrfWace MPY32 Timer_A Timer_A Timer_A Timer_B RTC_A CRC16 AIrxD: AU,A SRPTI, LDO 5 CC 3 CC 3 CC 7 CC Registers Registers Registers Registers Bx: SPI, I2C PU.0, PU.1 Copyright © 2016,Texas Instruments Incorporated NOTE: SeeTable3-1forlimitationsonthesimultaneousavailabilityofUSCImodulesignals. Figure1-2.FunctionalBlockDiagram – MSP430F5310IRGZ,MSP430F5309IRGZ,MSP430F5308IRGZ, MSP430F5310IPT,MSP430F5309IPT,MSP430F5308IPT XIN XOUT RST/NMI DVCC DVSS VCOREAVCC AVSS PA PB PC P1.x P2.x P3.x P4.x P5.x P6.x XT2IN SYS REF ADC10_A Unified ACLK Power I/O Ports I/O Ports I/O Ports XT2OUT SCylsotcekm SMCLK 8KB 6KB Management Watchdog 1P×18, IP/O2s 1×8P 4I/Os 1P×56, IP/O6s 20100 K BSiPtS MCLK Flash RAM SVLMD/SOVS PCo(orPtn 4Mtr)oalp I1Wn×tae1kr rIeu/Ouppst, 1×4 I/Os (86 Cinhta, n2n eexlst) Brownout PA PB PC Window 1×9 I/Os 1×8 I/Os 1×10 I/Os Comparator CPUXV2 MAB DMA and Working MDB 3 Channel Registers EEM (S:3+1) USCI1 PU Port JTAG, TA0 TA1 TA2 TB0 InSteBrfWace MPY32 Timer_A Timer_A Timer_A Timer_B RTC_A CRC16 AIr1D: AU,A SRPTI, LDO 5 CC 3 CC 3 CC 7 CC Registers Registers Registers Registers B1: SPI, I2C PU.0, PU.1 Copyright © 2016,Texas Instruments Incorporated Figure1-3.FunctionalBlockDiagram – MSP430F5304IRGZ,MSP430F5304IPT 4 DeviceOverview Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 Table of Contents 1 DeviceOverview......................................... 1 5.23 PMM,SVSLowSide................................ 28 .............................................. ............................... 1.1 Features 1 5.24 PMM,SVMLowSide 28 1.2 Applications........................................... 1 5.25 Wake-upTimesFromLow-PowerModesand ................................................ ............................................ Reset 29 1.3 Description 2 ............................................. ........................... 5.26 Timer_A 29 1.4 FunctionalBlockDiagrams 3 ............................................. 2 Revision History......................................... 6 5.27 Timer_B 29 .............. 3 DeviceComparison ..................................... 7 5.28 USCI(UARTMode)ClockFrequency 30 ................................. ..................................... 5.29 USCI(UARTMode) 30 3.1 RelatedProducts 7 ......... 4 TerminalConfigurationandFunctions.............. 8 5.30 USCI(SPIMasterMode)ClockFrequency 30 ............................ ......................................... 5.31 USCI(SPIMasterMode) 30 4.1 PinDiagrams 8 ............................. .................................. 5.32 USCI(SPISlaveMode) 32 4.2 SignalDescriptions 12 5 Specifications........................................... 16 5.33 USCI(I2CMode).................................... 34 ......................... 5.34 10-BitADC,PowerSupplyandInputRange 5.1 AbsoluteMaximumRatings 16 ........................................... Conditions 35 ........................................ 5.2 ESDRatings 16 .................... 5.35 10-BitADC,TimingParameters 35 ............... 5.3 RecommendedOperatingConditions 16 ................... 5.36 10-BitADC,LinearityParameters 36 5.4 ActiveModeSupplyCurrentIntoV Excluding CC ........................... ..................................... 5.37 REF,ExternalReference 36 External Current 17 ............................. 5.5 Low-PowerModeSupplyCurrents(IntoV ) 5.38 REF,Built-InReference 37 CC .......................... ....................................... ExcludingExternalCurrent 18 5.39 Comparator_B 38 ................ ................................ 5.6 ThermalResistanceCharacteristics 19 5.40 PortsPU.0andPU.1 39 5.7 Schmitt-TriggerInputs–General-PurposeI/O 5.41 LDO-PWR(LDOPowerSystem)................... 40 (P1.0toP1.7,P2.0toP2.7,P3.0toP3.4,P4.0toP4.7) ....................................... 5.42 FlashMemory 41 (P5.0toP5.5,P6.0toP6.7,PJ.0toPJ.3, RST/NMI)............................................ 20 5.43 JTAGandSpy-Bi-WireInterface.................... 41 5.8 Inputs–PortsP1andP2 6 DetailedDescription................................... 42 (P1.0toP1.7,P2.0toP2.7)......................... 20 6.1 CPU(LinktoUser'sGuide)......................... 42 5.9 LeakageCurrent–General-PurposeI/O 6.2 OperatingModes.................................... 43 (P1.0toP1.7,P2.0toP2.7,P3.0toP3.4,P4.0toP4.7) .......................... 6.3 InterruptVectorAddresses 44 (P5.0toP5.5,P6.0toP6.7,PJ.0toPJ.3, RST/NMI)............................................ 20 6.4 Memory Organization............................... 45 .................................... 5.10 Outputs–General-PurposeI/O(FullDriveStrength) 6.5 Bootloader(BSL) 46 (P1.0toP1.7,P2.0toP2.7,P3.0toP3.4,P4.0to ..................................... 6.6 JTAGOperation 46 ..... P4.7,P5.0toP5.5,P6.0toP6.7,PJ.0toPJ.3) 20 ............... 6.7 FlashMemory(LinktoUser'sGuide) 47 5.11 Outputs–General-PurposeI/O(ReducedDrive ......................... Strength) 6.8 RAM(LinktoUser'sGuide) 47 (P1.0toP1.7,P2.0toP2.7,P3.0toP3.4,P4.0to 6.9 Peripherals.......................................... 47 ..... P4.7,P5.0toP5.5,P6.0toP6.7,PJ.0toPJ.3) 21 ................................. 6.10 PeripheralFileMap 58 5.12 OutputFrequency–General-PurposeI/O .............................. 6.11 Input/OutputDiagrams 69 (P1.0toP1.7,P2.0toP2.7,P3.0toP3.4,P4.0to P4.7,P5.0toP5.5,P6.0toP6.7,PJ.0toPJ.3)..... 21 6.12 Device Descriptors.................................. 85 5.13 TypicalCharacteristics–Outputs,ReducedDrive 7 DeviceandDocumentationSupport............... 88 Strength(PxDS.y=0)............................... 22 7.1 GettingStartedandNextSteps..................... 88 5.14 CrystalOscillator,XT1,Low-FrequencyMode ..... 23 7.2 Device Nomenclature............................... 88 5.15 CrystalOscillator,XT2.............................. 24 7.3 ToolsandSoftware................................. 90 5.16 InternalVery-Low-PowerLow-FrequencyOscillator 7.4 DocumentationSupport............................. 92 ................................................ (VLO) 25 ........................................ 7.5 RelatedLinks 93 5.17 InternalReference,Low-FrequencyOscillator .............................. .............................................. 7.6 CommunityResources 93 (REFO) 25 .......................................... ..................................... 7.7 Trademarks 93 5.18 DCO Frequency 26 ..................... ....................... 7.8 ElectrostaticDischargeCaution 93 5.19 PMM,BrownoutReset(BOR) 27 ............................................. ................................. 7.9 Glossary 93 5.20 PMM,CoreVoltage 27 ............................... 8 Mechanical,Packaging,andOrderable 5.21 PMM,SVSHighSide 27 Information.............................................. 94 ............................... 5.22 PMM,SVMHighSide 28 Copyright©2010–2018,TexasInstrumentsIncorporated TableofContents 5 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 2 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromNovember23,2013toSeptember25,2018 Page • Documentformatchangesthroughout,includingchangestoorganizationandadditionofsectionnumbering ......... 1 • AddedDeviceInformationtable .................................................................................................... 2 • AddedSection1.4andmovedallfunctionalblockdiagramstoit.............................................................. 3 • ChangednumberofUSCImodulesinFigure1-2andaddednote............................................................ 4 • ChangedfromUSCI0toUSCI1inFigure1-3 .................................................................................... 4 • AddedSection3,DeviceComparison,andmovedTable3-1,FamilyMembers,toit ...................................... 7 • InTable3-1,changedthenumberofUSCImodulesinthe48-pinpackagesfrom1to2andaddednoteabout limitationsonsimultaneoususe..................................................................................................... 7 • AddedSection3.1,RelatedProducts.............................................................................................. 7 • ChangedthetitleofTable4-1fromTerminalFunctionstoSignalDescriptions............................................ 12 • Added"withportinterrupt"toP2.7descriptioninTable4-1,SignalDescriptions.......................................... 13 • Added"PortUissuppliedbytheLDOOrail"tothePU.0andPU.1descriptionsinTable4-1,SignalDescriptions . 14 • AddedtypicalconditionsstatementsatthebeginningofSection5,Specifications........................................ 16 • AddedSection5andmovedallelectricalspecificationstoit ................................................................. 16 • AddedSection5.2,ESDRatings.................................................................................................. 16 • MovedSection5.6,ThermalResistanceCharacteristics...................................................................... 19 • ChangedtheTYPvalueoftheC parameterwithTestConditionsof"XTS=0,XCAPx=0"from2pFto1pF L,eff inSection5.14,CrystalOscillator,XT1,Low-FrequencyMode............................................................... 23 • ChangedtheMINvalueoftheV parameterfrom60mVto50mVinSection5.19,PMM,Brownout (DVCC_BOR_hys) Reset(BOR)......................................................................................................................... 27 • Updatednotes(1)and(2)andaddednote(3)inSection5.25,Wake-upTimesFromLow-PowerModesand Reset ................................................................................................................................. 29 • Changed(corrected)theportpinsmuxedwithADC10pinsinV TestConditionsinSection5.34,10-BitADC, (Ax) PowerSupplyandInputRangeConditions...................................................................................... 35 • RemovedADC10DIVfromtheformulafortheTYPvalueinthesecondrowofthet parameterin CONVERT Section5.35,10-BitADC,TimingParameters,becauseADC10CLKisafterdivision..................................... 35 • UpdatedTestConditionsforallparametersinSection5.36,10-BitADC,LinearityParameters:changedfrom "C =20pF"to"C =20pF";changedfrom"(V –V )min≤(V –V )"to VREF+ VeREF+ eREF+ eREF– eREF+ eREF– "1.4V≤(V –V )".......................................................................................................... 36 eREF+ eREF– • Added"C =20pF"toE TestConditionsinSection5.36,10-BitADC,LinearityParameters..................... 36 VeREF+ I • Added"ADC10SREFx=11b"toTestConditionsforE andE inSection5.36,10-BitADC,LinearityParameters. 36 G T • ChangedtheMINvalueofAV withTestConditionsof"REFVSEL={0}for1.5V"from2.2Vto1.8Vin CC(min) Section5.38,REF,Built-InReference............................................................................................ 37 • ChangedthevalueofCBREFACCinbothTestConditionsfortheI parameter(changedfirstrowfrom0 AVCC_REF to1;changedsecondrowfrom1to0)inSection5.39,Comparator_B..................................................... 38 • ChangedtheMAXvalueofthet parameterwithTestConditionsof"CBPWRMD=10"from1.5µsto EN_CMP 100µsinSection5.39,Comparator_B........................................................................................... 38 • Changedthenotethatstarts"ToolsthataccesstheSpy-Bi-WireandBSLinterfaces..."................................. 41 • Throughoutdocument,changedallinstancesof"bootstraploader"to"bootloader"....................................... 46 • CorrectedspellingofNMIIFGinTable6-8,SystemModuleInterruptVectorRegisters................................... 51 • ChangedFigure6-8,PortP5(P5.3)Diagram,(addedP5SEL.2andXT2BYPASSinputswithANDandORgates). 77 • ChangedP5SEL.3columnfromXto0for"P5.3(I/O)"rowsinTable6-48,PortP5(P5.2andP5.3)PinFunctions. 77 • ChangedFigure6-10,PortP5(P5.5)Diagram,(addedP5SEL.5inputandORgate).................................... 79 • ChangedP5SEL.5columnfromXto0for"P5.5(I/O)"rowsinTable6-49,PortP5(P5.4andP5.5)PinFunctions. 79 • ChangedTable6-51,PortPU.0,PU.1Functions............................................................................... 82 • AddedZQEandPTpackagesinheadingrowofTable6-53,DeviceDescriptors......................................... 85 • AddedSection7,DeviceandDocumentationSupport......................................................................... 88 • AddedSection8,Mechanical,Packaging,andOrderableInformation...................................................... 94 6 RevisionHistory Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 3 Device Comparison Table3-1summarizestheavailablefamilymembers. Table3-1.FamilyMembers(1)(2) USCI PROGRAM DEVICE ME(MKBO)RY S(RKABM) Timer_A(3) Timer_B(4) CUHAARNTN,ELLINA,: CHSAPNIN,IE2CLB: AD(CC1H0)_A Co(mCHp)_B I/Os PACKAGE IrDA,SPI 64RGC, 2 2 10ext,2int 8 47 80ZQE MSP430F5310 32 6 5,3,3 7 2(5) 2(5) 6ext,2int 4 31 48PT, 48RGZ 64RGC, 2 2 10ext,2int 8 47 80ZQE MSP430F5309 24 6 5,3,3 7 2(5) 2(5) 6ext,2int 4 31 48PT, 48RGZ, 64RGC, 2 2 10ext,2int 8 47 80ZQE MSP430F5308 16 6 5,3,3 7 2(5) 2(5) 6ext,2int 4 31 48PT, 48RGZ, 48PT, MSP430F5304 8 6 5,3,3 7 1 1 6ext,2int - 31 48RGZ (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) Packagedrawings,standardpackingquantities,thermaldata,symbolization,andPCBdesignguidelinesareavailableat www.ti.com/packaging. (3) EachnumberinthesequencerepresentsaninstantiationofTimer_AwithitsassociatednumberofcapturecompareregistersandPWM outputgeneratorsavailable.Forexample,anumbersequenceof3,5wouldrepresenttwoinstantiationsofTimer_A,thefirst instantiationhaving3andthesecondinstantiationhaving5capturecompareregistersandPWMoutputgenerators,respectively. (4) EachnumberinthesequencerepresentsaninstantiationofTimer_BwithitsassociatednumberofcapturecompareregistersandPWM outputgeneratorsavailable.Forexample,anumbersequenceof3,5wouldrepresenttwoinstantiationsofTimer_B,thefirst instantiationhaving3andthesecondinstantiationhaving5capturecompareregistersandPWMoutputgenerators,respectively. (5) TwoUSCIsareavailable;however,pinnedoutfunctionsarelimitedtowhattheuserconfiguresonport4withtheportmapping controller(seeSection6.9.2).Itmaynotbepossibletobringoutallfunctionssimultaneously. 3.1 Related Products Forinformationaboutotherdevicesinthisfamilyofproductsorrelatedproducts,seethefollowinglinks. ProductsforTIMicrocontrollers TI's low-power and high-performance MCUs, with wired and wireless connectivityoptions,areoptimizedforabroadrangeofapplications. ProductsforMSP430Ultra-Low-PowerMicrocontrollers One platform. One ecosystem. Endless possibilities. Enabling the connected world with innovations in ultra-low-power microcontrollerswithadvancedperipheralsforprecisesensingandmeasurement. CompanionProductsforMSP430F5310 Review products that are frequently purchased or used in conjunctionwiththisproduct. ReferenceDesignsforMSP430F5310 Find reference designs that leverage the best in TI technology to solveyoursystem-levelchallenges. Copyright©2010–2018,TexasInstrumentsIncorporated DeviceComparison 7 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 4 Terminal Configuration and Functions 4.1 Pin Diagrams Figure 4-1 shows the pinout for the MSP430F5310, MSP430F5309, and MSP430F5308 devices in the 64- pinRGCpackage. O DI T K MI/SBW CK MS DI/TCLK DO SBWTC T2OUT T2IN ST/N J.3/T J.2/T J.1/T J.0/T EST/ 5.3/X 5.2/X VSS2 C DOO DOI U.1 C U.0 USS R P P P P T P P A N L L P N P V 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P6.0/CB0/A0 1 48 P4.7/PM_NONE P6.1/CB1/A1 2 47 P4.6/PM_NONE P6.2/CB2/A2 3 46 P4.5/PM_UCA1RXD/PM_UCA1SOMI P6.3/CB3/A3 4 45 P4.4/PM_UCA1TXD/PM_UCA1SIMO P6.4/CB4/A4 5 44 P4.3/PM_UCB1CLK/PM_UCA1STE P6.5/CB5/A5 6 43 P4.2/PM_UCB1SOMI/PM_UCB1SCL P6.6/CB6/A6 7 42 P4.1/PM_UCB1SIMO/PM_UCB1SDA P6.7/CB7/A7 8 41 P4.0/PM_UCB1STE/PM_UCA1CLK P5.0/A8/VeREF+ 9 40 DVCC2 P5.1/A9/VeREF− 10 39 DVSS2 AVCC1 11 38 P3.4/UCA0RXD/UCA0SOMI P5.4/XIN 12 37 P3.3/UCA0TXD/UCA0SIMO P5.5/XOUT 13 36 P3.2/UCB0CLK/UCA0STE AVSS1 14 35 P3.1/UCB0SOMI/UCB0SCL DVCC1 15 34 P3.0/UCB0SIMO/UCB0SDA DVSS1 16 33 P2.7/UCB0STE/UCA0CLK 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RE LK 0.0 0.1 0.2 0.3 0.4 UT 1.0 1.1 1.2 LK 2.0 2.1 2.2 E0 O C A A A A A O A A A C A A A A VC CLK/A P1.1/T P1.2/T P1.3/T P1.4/T P1.5/T LK/CB P1.7/T P2.0/T P2.1/T LK/SM P2.3/T P2.4/T P2.5/T LK/DM 0 C C C 0/TA TA1 TA2 RTC P1. P1.6/ P2.2/ P2.6/ NOTE: TIrecommendsconnectionofexposedthermalpadtoV . SS Figure4-1.64-PinRGCPackage(TopView) 8 TerminalConfigurationandFunctions Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 Figure 4-2 shows the pinout for the MSP430F5310, MSP430F5309, and MSP430F5308 devices in the 80- pinZQEpackage. A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C4 C5 C6 C7 C8 C9 D1 D2 D3 D4 D5 D6 D7 D8 D9 E1 E2 E3 E4 E5 E6 E7 E8 E9 F1 F2 F3 F4 F5 F6 F7 F8 F9 G1 G2 G3 G4 G5 G6 G7 G8 G9 H1 H2 H3 H4 H5 H6 H7 H8 H9 J1 J2 J3 J4 J5 J6 J7 J8 J9 Figure4-2.80-PinZQEPackage(TopView) Copyright©2010–2018,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 9 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com Figure 4-3 shows the pinout for the MSP430F5310, MSP430F5309, and MSP430F5308 devices in the 48- pinRGZandPTpackages. O DI T K W C T B T U S W O N ST/NMI/ EST/SB 5.3/XT2 5.2/XT2I VSS2 C DOO DOI U.1 C U.0 SSU R T P P A N L L P N P V 48 47 46 45 44 43 42 41 40 39 38 37 P6.0/CB0/A0 1 36 P4.7/PM_NONE P6.1/CB1/A1 2 35 P4.6/PM_NONE P6.2/CB2/A2 3 34 P4.5/PM_UCA1RXD/PM_UCA1SOMI P6.3/CB3/A3 4 33 P4.4/PM_UCA1TXD/PM_UCA1SIMO P5.0/A8/VeREF+ 5 32 P4.3/PM_UCB1CLK/PM_UCA1STE P5.1/A9/VeREF- 6 31 P4.2/PM_UCB1SOMI/PM_UCB1SCL AVCC1 7 30 P4.1/PM_UCB1SIMO/PM_UCB1SDA P5.4/XIN 8 29 P4.0/PM_UCB1STE/PM_UCA1CLK P5.5/XOUT 9 28 DVCC2 AVSS1 10 27 DVSS2 DVCC1 11 26 PJ.3/TCK DVSS1 12 25 PJ.2/TMS 13 14 15 16 17 18 19 20 21 22 23 24 E K 0 1 2 3 4 T 0 1 O K R L 0. 0. 0. 0. 0. U 1. 1. D L O C A A A A A O A A T C VC 0/TA0CLK/A P1.1/T P1.2/T P1.3/T P1.4/T P1.5/T TA1CLK/CB P1.7/T P2.0/T PJ.0/ PJ.1/TDI/T 1. 6/ P 1. P NOTE: FortheRGZpackage,TIrecommendsconnectionofexposedthermalpadtoV . SS Figure4-3.48-PinRGZorPTPackage(TopView) – MSP430F5310,MSP430F5309,MSP430F5308 10 TerminalConfigurationandFunctions Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 Figure4-4showsthepinoutfortheMSP430F5304deviceinthe48-pinRGZandPTpackages. O DI T K W C T B T U S W O N ST/NMI/ EST/SB 5.3/XT2 5.2/XT2I VSS2 C DOO DOI U.1 C U.0 SSU R T P P A N L L P N P V 48 47 46 45 44 43 42 41 40 39 38 37 P6.0/A0 1 36 P4.7/PM_NONE P6.1/A1 2 35 P4.6/PM_NONE P6.2/A2 3 34 P4.5/PM_UCA1RXD/PM_UCA1SOMI P6.3/A3 4 33 P4.4/PM_UCA1TXD/PM_UCA1SIMO P5.0/A8/VeREF+ 5 32 P4.3/PM_UCB1CLK/PM_UCA1STE P5.1/A9/VeREF- 6 31 P4.2/PM_UCB1SOMI/PM_UCB1SCL AVCC1 7 30 P4.1/PM_UCB1SIMO/PM_UCB1SDA P5.4/XIN 8 29 P4.0/PM_UCB1STE/PM_UCA1CLK P5.5/XOUT 9 28 DVCC2 AVSS1 10 27 DVSS2 DVCC1 11 26 PJ.3/TCK DVSS1 12 25 PJ.2/TMS 13 14 15 16 17 18 19 20 21 22 23 24 E K 0 1 2 3 4 T 0 1 O K R L 0. 0. 0. 0. 0. U 1. 1. D L O C A A A A A O A A T C VC 0/TA0CLK/A P1.1/T P1.2/T P1.3/T P1.4/T P1.5/T TA1CLK/CB P1.7/T P2.0/T PJ.0/ PJ.1/TDI/T 1. 6/ P 1. P NOTE: FortheRGZpackage,TIrecommendsconnectionofexposedthermalpadtoV . SS Figure4-4.48-PinRGZorRTPackage(TopView) –MSP430F5304 Copyright©2010–2018,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 11 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 4.2 Signal Descriptions Table4-1describesthesignalsforalldevicevariantsandpackageoptions. Table4-1.SignalDescriptions TERMINAL NO. I/O(1) DESCRIPTION NAME RGZ, RGC ZQE PT General-purposedigitalI/O P6.4/CB4/A4 5 N/A C1 I/O Comparator_BinputCB4(notavailableonRGZorPTpackagedevices) AnaloginputA4forADC(notavailableonRGZorPTpackagedevices) General-purposedigitalI/O P6.5/CB5/A5 6 N/A D2 I/O Comparator_BinputCB5(notavailableonRGZorPTpackagedevices) AnaloginputA5forADC(notavailableonRGZorPTpackagedevices) General-purposedigitalI/O P6.6/CB6/A6 7 N/A D1 I/O Comparator_BinputCB6(notavailableonRGZorPTpackagedevices) AnaloginputA6forADC(notavailableonRGZorPTpackagedevices) General-purposedigitalI/O P6.7/CB7/A7 8 N/A D3 I/O Comparator_BinputCB7(notavailableonRGZorPTpackagedevices) AnaloginputA7forADC(notavailableonRGZorPTpackagedevices) General-purposedigitalI/O P5.0/A8/VeREF+ 9 5 E1 I/O AnaloginputA8forADC InputforanexternalreferencevoltagetotheADC General-purposedigitalI/O P5.1/A9/VeREF- 10 6 E2 I/O AnaloginputA9forADC NegativeterminalforanexternallyprovidedADCreference AVCC1 11 7 F2 Analogpowersupply General-purposedigitalI/O P5.4/XIN 12 8 F1 I/O InputterminalforcrystaloscillatorXT1 General-purposedigitalI/O P5.5/XOUT 13 9 G1 I/O OutputterminalofcrystaloscillatorXT1 AVSS1 14 10 G2 Analoggroundsupply DVCC1 15 11 H1 Digitalpowersupply DVSS1 16 12 J1 Digitalgroundsupply VCORE(2) 17 13 J2 Regulatedcorepowersupplyoutput(internaluseonly,noexternalcurrent loading) General-purposedigitalI/Owithportinterrupt P1.0/TA0CLK/ACLK 18 14 H2 I/O TA0clocksignalTA0CLKinput ACLKoutput(dividedby1,2,4,8,16,or32) General-purposedigitalI/Owithportinterrupt P1.1/TA0.0 19 15 H3 I/O TA0CCR0capture:CCI0Ainput,compare:Out0output BSLtransmitoutput General-purposedigitalI/Owithportinterrupt P1.2/TA0.1 20 16 J3 I/O TA0CCR1capture:CCI1Ainput,compare:Out1output BSLreceiveinput General-purposedigitalI/Owithportinterrupt P1.3/TA0.2 21 17 G4 I/O TA0CCR2capture:CCI2Ainput,compare:Out2output General-purposedigitalI/Owithportinterrupt P1.4/TA0.3 22 18 H4 I/O TA0CCR3capture:CCI3Ainputcompare:Out3output General-purposedigitalI/Owithportinterrupt P1.5/TA0.4 23 19 J4 I/O TA0CCR4capture:CCI4Ainput,compare:Out4output General-purposedigitalI/Owithportinterrupt P1.6/TA1CLK/CBOUT 24 20 G5 I/O TA1clocksignalTA1CLKinput Comparator_Boutput General-purposedigitalI/Owithportinterrupt P1.7/TA1.0 25 21 H5 I/O TA1CCR0capture:CCI0Ainput,compare:Out0output (1) I=input,O=output,N/A=notavailable (2) VCOREisforinternaluseonly.Noexternalcurrentloadingispossible.VCOREshouldonlybeconnectedtotherecommended capacitorvalue,C . VCORE 12 TerminalConfigurationandFunctions Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 Table4-1.SignalDescriptions(continued) TERMINAL NO. I/O(1) DESCRIPTION NAME RGZ, RGC ZQE PT General-purposedigitalI/Owithportinterrupt P2.0/TA1.1 26 22 J5 I/O TA1CCR1capture:CCI1Ainput,compare:Out1output General-purposedigitalI/Owithportinterrupt P2.1/TA1.2 27 N/A G6 I/O TA1CCR2capture:CCI2Ainput,compare:Out2output General-purposedigitalI/Owithportinterrupt P2.2/TA2CLK/SMCLK 28 N/A J6 I/O TA2clocksignalTA2CLKinput;SMCLKoutput General-purposedigitalI/Owithportinterrupt P2.3/TA2.0 29 N/A H6 I/O TA2CCR0capture:CCI0Ainput,compare:Out0output General-purposedigitalI/Owithportinterrupt P2.4/TA2.1 30 N/A J7 I/O TA2CCR1capture:CCI1Ainput,compare:Out1output General-purposedigitalI/Owithportinterrupt P2.5/TA2.2 31 N/A J8 I/O TA2CCR2capture:CCI2Ainput,compare:Out2output General-purposedigitalI/Owithportinterrupt P2.6/RTCCLK/DMAE0 32 N/A J9 I/O RTCclockoutputforcalibration DMAexternaltriggerinput General-purposedigitalI/Owithportinterrupt Slavetransmitenable–USCI_B0SPImode P2.7/UCB0STE/UCA0CLK 33 N/A H7 I/O Clocksignalinput–USCI_A0SPIslavemode Clocksignaloutput–USCI_A0SPImastermode General-purposedigitalI/O P3.0/UCB0SIMO/UCB0SDA 34 N/A H8 I/O Slavein,masterout–USCI_B0SPImode I2Cdata–USCI_B0I2Cmode General-purposedigitalI/O P3.1/UCB0SOMI/UCB0SCL 35 N/A H9 I/O Slaveout,masterin–USCI_B0SPImode I2Cclock–USCI_B0I2Cmode General-purposedigitalI/O Clocksignalinput–USCI_B0SPIslavemode P3.2/UCB0CLK/UCA0STE 36 N/A G8 I/O Clocksignaloutput–USCI_B0SPImastermode Slavetransmitenable–USCI_A0SPImode General-purposedigitalI/O P3.3/UCA0TXD/UCA0SIMO 37 N/A G9 I/O Transmitdata–USCI_A0UARTmode Slavein,masterout–USCI_A0SPImode General-purposedigitalI/O P3.4/UCA0RXD/UCA0SOMI 38 N/A G7 I/O Receivedata–USCI_A0UARTmode Slaveout,masterin–USCI_A0SPImode General-purposedigitalI/Owithreconfigurableportmappingsecondary function P4.0/PM_UCB1STE/ 41 29 E8 I/O Defaultmapping:Slavetransmitenable–USCI_B1SPImode PM_UCA1CLK Defaultmapping:Clocksignalinput–USCI_A1SPIslavemode Defaultmapping:Clocksignaloutput–USCI_A1SPImastermode General-purposedigitalI/Owithreconfigurableportmappingsecondary P4.1/PM_UCB1SIMO/ function 42 30 E7 I/O PM_UCB1SDA Defaultmapping:Slavein,masterout–USCI_B1SPImode Defaultmapping:I2Cdata–USCI_B1I2Cmode General-purposedigitalI/Owithreconfigurableportmappingsecondary P4.2/PM_UCB1SOMI/ function 43 31 D9 I/O PM_UCB1SCL Defaultmapping:Slaveout,masterin–USCI_B1SPImode Defaultmapping:I2Cclock–USCI_B1I2Cmode General-purposedigitalI/Owithreconfigurableportmappingsecondary function P4.3/PM_UCB1CLK/ 44 32 D8 I/O Defaultmapping:Clocksignalinput–USCI_B1SPIslavemode PM_UCA1STE Defaultmapping:Clocksignaloutput–USCI_B1SPImastermode Defaultmapping:Slavetransmitenable–USCI_A1SPImode DVSS2 39 27 F9 Digitalgroundsupply DVCC2 40 28 E9 Digitalpowersupply Copyright©2010–2018,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 13 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com Table4-1.SignalDescriptions(continued) TERMINAL NO. I/O(1) DESCRIPTION NAME RGZ, RGC ZQE PT General-purposedigitalI/Owithreconfigurableportmappingsecondary P4.4/PM_UCA1TXD/ function 45 33 D7 I/O PM_UCA1SIMO Defaultmapping:Transmitdata–USCI_A1UARTmode Defaultmapping:Slavein,masterout–USCI_A1SPImode General-purposedigitalI/Owithreconfigurableportmappingsecondary P4.5/PM_UCA1RXD/ function 46 34 C9 I/O PM_UCA1SOMI Defaultmapping:Receivedata–USCI_A1UARTmode Defaultmapping:Slaveout,masterin–USCI_A1SPImode General-purposedigitalI/Owithreconfigurableportmappingsecondary P4.6/PM_NONE 47 35 C8 I/O function Defaultmapping:nosecondaryfunction. General-purposedigitalI/Owithreconfigurableportmappingsecondary P4.7/PM_NONE 48 36 C7 I/O function Defaultmapping:nosecondaryfunction. B8, VSSU 49 37 PUgroundsupply B9 General-purposedigitalI/O-controlledbyPUcontrolregister. PU.0 50 38 A9 I/O PortUissuppliedbytheLDOOrail. NC 51 39 B7 I/O Noconnect. General-purposedigitalI/O-controlledbyPUcontrolregister PU.1 52 40 A8 I/O PortUissuppliedbytheLDOOrail. LDOI 53 41 A7 LDOinput LDOO 54 42 A6 LDOoutput NC 55 43 B6 Noconnect. AVSS2 56 44 A5 Analoggroundsupply General-purposedigitalI/O P5.2/XT2IN 57 45 B5 I/O InputterminalforcrystaloscillatorXT2 General-purposedigitalI/O P5.3/XT2OUT 58 46 B4 I/O OutputterminalofcrystaloscillatorXT2 Testmodepin–selectdigitalI/OonJTAGpins TEST/SBWTCK 59 47 A4 I Spy-Bi-Wireinputclock General-purposedigitalI/O PJ.0/TDO 60 23 C5 I/O Testdataoutputport General-purposedigitalI/O PJ.1/TDI/TCLK 61 24 C4 I/O Testdatainputortestclockinput General-purposedigitalI/O PJ.2/TMS 62 25 A3 I/O Testmodeselect General-purposedigitalI/O PJ.3/TCK 63 26 B3 I/O Testclock Resetinputactivelow(3) RST/NMI/SBWTDIO 64 48 A2 I/O Nonmaskableinterruptinput Spy-Bi-Wiredatainput/output General-purposedigitalI/O P6.0/CB0/A0 1 1 A1 I/O Comparator_BinputCB0(notavailableonF5304device) AnaloginputA0forADC General-purposedigitalI/O P6.1/CB1/A1 2 2 B2 I/O Comparator_BinputCB1(notavailableonF5304device) AnaloginputA1forADC General-purposedigitalI/O P6.2/CB2/A2 3 3 B1 I/O Comparator_BinputCB2(notavailableonF5304device) AnaloginputA2forADC (3) Whenthispinisconfiguredasreset,theinternalpullupresistorisenabledbydefault. 14 TerminalConfigurationandFunctions Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 Table4-1.SignalDescriptions(continued) TERMINAL NO. I/O(1) DESCRIPTION NAME RGZ, RGC ZQE PT General-purposedigitalI/O P6.3/CB3/A3 4 4 C2 I/O Comparator_BinputCB3(notavailableonF5304device) AnaloginputA3forADC Reserved N/A N/A (4) ExposedthermalpadonQFNpackages.TIrecommendsconnectiontoV ThermalPad Pad Pad N/A SS (notavailableonPTpackagedevices). (4) C6,D4,D5,D6,E3,E4,E5,E6,F3,F4,F5,F6,F7,F8,G3arereservedandshouldbeconnectedtoground. Copyright©2010–2018,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 15 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 5 Specifications Allgraphsinthissectionarefortypicalconditions,unlessotherwisenoted. Typical(TYP)valuesarespecifiedatV =3.3VandT =25°C,unlessotherwisenoted. CC A 5.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT VoltageappliedatV toV –0.3 4.1 V CC SS Voltageappliedtoanypin(excludingVCORE,LDOI)(2) –0.3 V +0.3 V CC Diodecurrentatanydevicepin ±2 mA Maximumjunctiontemperature,T 95 °C J Storagetemperature,T (3) –55 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesreferencedtoV .VCOREisforinternaldeviceuseonly.NoexternalDCloadingorvoltageshouldbeapplied. SS (3) HighertemperaturemaybeappliedduringboardsolderingaccordingtothecurrentJEDECJ-STD-020specificationwithpeakreflow temperaturesnothigherthanclassifiedonthedevicelabelontheshippingboxesorreels. 5.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±1000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±250 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.Manufacturingwith lessthan500-VHBMispossiblewiththenecessaryprecautions.Pinslistedas±1000Vmayactuallyhavehigherperformance. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.Manufacturingwith lessthan250-VCDMispossiblewiththenecessaryprecautions.Pinslistedas±250Vmayactuallyhavehigherperformance. 5.3 Recommended Operating Conditions MIN NOM MAX UNIT PMMCOREVx=0 1.8 3.6 Supplyvoltageduringprogramexecutionandflash PMMCOREVx=0,1 2.0 3.6 VCC programming(AVCC=DVCC1=DVCC2=VCC)(1)(2) PMMCOREVx=0,1,2 2.2 3.6 V PMMCOREVx=0,1,2,3 2.4 3.6 V Supplyvoltage(AV =DV =DV ) 0 V SS SS SS1/2 SS T Operatingfree-airtemperature –40 85 °C A T Operatingjunctiontemperature –40 85 °C J C CapacitoratVCORE(3) 470 nF VCORE C / DVCC CapacitorratioofDVCCtoVCORE 10 C VCORE PMMCOREVx=0, 1.8V≤V ≤3.6V 0 8.0 CC (defaultcondition) PMMCOREVx=1, fSYSTEM PFirgoucreess5o-1r)frequency(maximumMCLKfrequency) (4)(see 2.0V≤VCC≤3.6V 0 12.0 MHz PMMCOREVx=2, 0 20.0 2.2V≤V ≤3.6V CC PMMCOREVx=3, 0 25.0 2.4V≤V ≤3.6V CC (1) TIrecommendspoweringAVCCandDVCCfromthesamesource.Amaximumdifferenceof0.3VbetweenAVCCandDVCCcanbe toleratedduringpowerupandoperation. (2) TheminimumsupplyvoltageisdefinedbythesupervisorSVSlevelswhenitisenabled.SeethethresholdparametersinSection5.21 fortheexactvaluesandfurtherdetails. (3) Acapacitortoleranceof±20%orbetterisrequired. (4) Modulesmayhaveadifferentmaximuminputclockspecification.Seethespecificationoftherespectivemoduleinthisdatasheet. 16 Specifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 25 3 20 z H M 2 2, 3 y - c n 12 e u q e 1 1, 2 1, 2, 3 Fr m 8 e st y S 0 0, 1 0, 1, 2 0, 1, 2, 3 0 1.8 2.0 2.2 2.4 3.6 Supply Voltage - V NOTE:The numbers within the fields denote the supported PMMCOREVx settings. Figure5-1.MaximumSystemFrequency 5.4 Active Mode Supply Current Into V Excluding External Current CC overrecommendedoperatingfree-airtemperature(unlessotherwisenoted) (1) (2) (3) FREQUENCY(f =f =f ) DCO MCLK SMCLK EXECUTION PARAMETER V PMMCOREVx 1MHz 8MHz 12MHz 20MHz 25MHz UNIT MEMORY CC TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX 0 0.25 0.27 1.55 1.68 1 0.28 1.74 2.58 2.78 I Flash 3V mA AM,Flash 2 0.30 1.91 2.84 4.68 5.06 3 0.32 2.09 3.10 5.13 6.0 6.5 0 0.17 0.19 0.91 1.00 1 0.19 1.03 1.54 1.67 I RAM 3V mA AM,RAM 2 0.20 1.16 1.73 2.84 3.11 3 0.21 1.24 1.87 3.1 3.9 4.3 (1) Allinputsaretiedto0VortoV .Outputsdonotsourceorsinkanycurrent. CC (2) ThecurrentsarecharacterizedwithaMicroCrystalMS1V-T1Kcrystalwithaloadcapacitanceof12.5pF.Theinternalandexternalload capacitancearechosentocloselymatchtherequired12.5pF. (3) Characterizedwithprogramexecutingtypicaldataprocessing.LDOdisabled(LDOEN=0). f =32786Hz,f =f =f atspecifiedfrequency. ACLK DCO MCLK SMCLK XTS=CPUOFF=SCG0=SCG1=OSCOFF=SMCLKOFF=0. Copyright©2010–2018,TexasInstrumentsIncorporated Specifications 17 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 5.5 Low-Power Mode Supply Currents (Into V ) Excluding External Current CC overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) (1) (2) TEMPERATURE(T ) A PARAMETER V PMMCOREVx –40°C 25°C 60°C 85°C UNIT CC TYP MAX TYP MAX TYP MAX TYP MAX 2.2V 0 73 77 85 80 80 97 Low-powermode0 (3)(4) µA LPM0,1MHz 3V 3 79 83 92 88 95 105 2.2V 0 6.5 6.5 8 7.5 8 11 I Low-powermode2 (5)(4) µA LPM2 3V 3 7.0 7.0 9 7.9 8.9 13 0 1.60 1.90 2.6 3.4 2.2V 1 1.65 2.00 2.7 3.6 2 1.75 2.15 2.9 3.8 Low-powermode3, ILPM3,XT1LF crystalmode (6) (4) 0 1.8 2.1 2.6 2.8 3.6 6.0 µA 1 1.9 2.3 2.9 3.8 3V 2 2.0 2.4 3.0 4.0 3 2.0 2.5 3.0 3.1 4.0 6.5 0 1.1 1.3 1.8 1.9 2.7 5.0 Low-powermode3, 1 1.1 1.4 2.0 2.8 ILPM3,VLO VLOmode(7)(4) 3V 2 1.2 1.5 2.1 2.9 µA 3 1.3 1.5 2.0 2.2 3.0 5.5 0 0.9 1.1 1.5 1.8 2.5 4.8 1 1.1 1.2 2.0 2.6 I Low-powermode4(8)(4) 3V µA LPM4 2 1.2 1.2 2.1 2.7 3 1.3 1.3 1.6 2.2 2.8 5.0 I Low-powermode4.5(9) 3V 0.15 0.18 0.35 0.26 0.45 0.8 µA LPM4.5 (1) Allinputsaretiedto0VortoV .Outputsdonotsourceorsinkanycurrent. CC (2) ThecurrentsarecharacterizedwithaMicroCrystalMS1V-T1Kcrystalwithaloadcapacitanceof12.5pF.Theinternalandexternalload capacitancearechosentocloselymatchtherequired12.5pF. (3) CurrentforwatchdogtimerclockedbySMCLKincluded.ACLK=low-frequencycrystaloperation(XTS=0,XT1DRIVEx=0). CPUOFF=1,SCG0=0,SCG1=0,OSCOFF=0(LPM0),f =32768Hz,f =0MHz,f =f =1MHz ACLK MCLK SMCLK DCO LDOdisabled(LDOEN=0). (4) Currentforbrownout,high-sidesupervisor(SVS )normalmodeincluded.Low-sidesupervisor(SVS )andlow-sidemonitor(SVM ) H L L disabled.High-sidemonitor(SVM )disabled.RAMretentionenabled. H (5) CurrentforwatchdogtimerandRTCclockedbyACLKincluded.ACLK=low-frequencycrystaloperation(XTS=0,XT1DRIVEx=0). CPUOFF=1,SCG0=0,SCG1=1,OSCOFF=0(LPM2),f =32768Hz,f =0MHz,f =f =0MHz;DCOsetting=1- ACLK MCLK SMCLK DCO MHzoperation,DCObiasgeneratorenabled. LDOdisabled(LDOEN=0) (6) CurrentforwatchdogtimerandRTCclockedbyACLKincluded.ACLK=low-frequencycrystaloperation(XTS=0,XT1DRIVEx=0). CPUOFF=1,SCG0=1,SCG1=1,OSCOFF=0(LPM3),f =32768Hz,f =f =f =0MHz ACLK MCLK SMCLK DCO LDOdisabled(LDOEN=0) (7) CurrentforwatchdogtimerandRTCclockedbyACLKincluded.ACLK=VLO. CPUOFF=1,SCG0=1,SCG1=1,OSCOFF=0(LPM3),f =f ,f =f =f =0MHz ACLK VLO MCLK SMCLK DCO LDOdisabled(LDOEN=0) (8) CPUOFF=1,SCG0=1,SCG1=1,OSCOFF=1(LPM4),f =f = f =f =0MHz DCO ACLK MCLK SMCLK LDOdisabled(LDOEN=0) (9) Internalregulatordisabled.Nodataretention. CPUOFF=1,SCG0=1,SCG1=1,OSCOFF=1,PMMREGOFF=1(LPM4.5),f =f = f =f =0MHz DCO ACLK MCLK SMCLK 18 Specifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 5.6 Thermal Resistance Characteristics(1) THERMALMETRIC VALUE UNIT VQFN(RGC) 30 VQFN(RGZ) 28.6 Rθ Junction-to-ambientthermalresistance,stillair (2) °C/W JA LQFP(PT) 62.8 BGA(ZQE) 55.5 VQFN(RGC) 15.6 VQFN(RGZ) 14.4 Rθ Junction-to-case(top)thermalresistance (3) °C/W JC(TOP) LQFP(PT) 18.2 BGA(ZQE) 21.2 VQFN(RGC) 1.6 VQFN(RGZ) 1.6 Rθ Junction-to-case(bottom)thermalresistance (4) °C/W JC(BOTTOM) LQFP(PT) N/A BGA(ZQE) N/A VQFN(RGC) 8.9 VQFN(RGZ) 5.5 Rθ Junction-to-boardthermalresistance (5) °C/W JB LQFP(PT) 28.3 BGA(ZQE) 19.3 (1) N/A=notapplicable (2) Thejunction-to-ambientthermalresistanceundernaturalconvectionisobtainedinasimulationonaJEDEC-standard,High-Kboard,as specifiedinJESD51-7,inanenvironmentdescribedinJESD51-2a. (3) Thejunction-to-case(top)thermalresistanceisobtainedbysimulatingacoldplatetestonthepackagetop.NospecificJEDEC-standard testexists,butaclosedescriptioncanbefoundintheANSISEMIstandardG30-88. (4) Thejunction-to-case(bottom)thermalresistanceisobtainedbysimulatingacoldplatetestontheexposed(power)pad.Nospecific JEDECstandardtestexists,butaclosedescriptioncanbefoundintheANSISEMIstandardG30-88. (5) Thejunction-to-boardthermalresistanceisobtainedbysimulatinginanenvironmentwitharingcoldplatefixturetocontrolthePCB temperature,asdescribedinJESD51-8. Copyright©2010–2018,TexasInstrumentsIncorporated Specifications 19 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 5.7 Schmitt-Trigger Inputs – General-Purpose I/O(1) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 1.8V 0.80 1.40 V Positive-goinginputthresholdvoltage V IT+ 3V 1.50 2.10 1.8V 0.45 1.00 V Negative-goinginputthresholdvoltage V IT– 3V 0.75 1.65 1.8V 0.3 0.85 V Inputvoltagehysteresis(V –V ) V hys IT+ IT– 3V 0.4 1.0 R Pulluporpulldownresistor(2) Forpullup:VIN=VSS 20 35 50 kΩ Pull Forpulldown:V =V IN CC C Inputcapacitance V =V orV 5 pF I IN SS CC (1) ThesameparametricsapplytotheclockinputpinwhenthecrystalbypassmodeisusedonXT1(XIN)orXT2(XT2IN). (2) AlsoappliestotheRSTpinwhenitspulluporpulldownresistorisenabled. 5.8 Inputs – Ports P1 and P2(1) (P1.0 to P1.7, P2.0 to P2.7) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC t Externalinterrupttiming (2) PortP1,P2:P1.xtoP2.x,Externaltriggerpulseduration 2.2V,3V 20 ns (int) tosetinterruptflag (1) Somedevicesmaycontainadditionalportswithinterrupts.Seetheblockdiagramandterminalfunctiondescriptions. (2) Anexternalsignalsetstheinterruptflageverytimetheminimuminterruptpulsedurationt ismet.Itmaybesetbytriggersignals (int) shorterthant . (int) 5.9 Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC I High-impedanceleakagecurrent (1) (2) 1.8V,3V ±50 nA lkg(Px.y) (1) TheleakagecurrentismeasuredwithV orV appliedtothecorrespondingpin(s),unlessotherwisenoted. SS CC (2) Theleakageofthedigitalportpinsismeasuredindividually.Theportpinisselectedforinputandthepulluporpulldownresistoris disabled. 5.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC I =–3mA (1) V –0.25 V (OHmax) CC CC 1.8V I =–10mA (2) V –0.60 V (OHmax) CC CC V High-leveloutputvoltage V OH I =–5mA (1) V –0.25 V (OHmax) CC CC 3V I =–15mA (2) V –0.60 V (OHmax) CC CC I =3mA (1) V V +0.25 (OLmax) SS SS 1.8V I =10mA (2) V V +0.60 (OLmax) SS SS Low-leveloutputvoltage V OL I =5mA (1) V V +0.25 (OLmax) SS SS 3V I =15mA (2) V V +0.60 (OLmax) SS SS (1) Themaximumtotalcurrent,I andI ,foralloutputscombinedshouldnotexceed±48mAtoholdthemaximumvoltagedrop (OHmax) (OLmax) specified. (2) Themaximumtotalcurrent,I andI ,foralloutputscombinedshouldnotexceed±100mAtoholdthemaximumvoltage (OHmax) (OLmax) dropspecified. 20 Specifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 5.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) (1) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC I =–1mA (2) V –0.25 V (OHmax) CC CC 1.8V I =–3mA (3) V –0.60 V (OHmax) CC CC V High-leveloutputvoltage V OH I =–2mA (2) V –0.25 V (OHmax) CC CC 3V I =–6mA (3) V –0.60 V (OHmax) CC CC I =1mA (2) V V +0.25 (OLmax) SS SS 1.8V I =3mA (3) V V +0.60 (OLmax) SS SS V Low-leveloutputvoltage V OL I =2mA (2) V V +0.25 (OLmax) SS SS 3V I =6mA (3) V V +0.60 (OLmax) SS SS (1) SelectingreduceddrivestrengthmayreduceEMI. (2) Themaximumtotalcurrent,I andI ,foralloutputscombined,shouldnotexceed±48mAtoholdthemaximumvoltagedrop (OHmax) (OLmax) specified. (3) Themaximumtotalcurrent,I andI ,foralloutputscombined,shouldnotexceed±100mAtoholdthemaximumvoltage (OHmax) (OLmax) dropspecified. 5.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT V =1.8V CC 16 PMMCOREVx=0 f Portoutputfrequency(withload) See (1) (2) MHz Px.y V =3V CC 25 PMMCOREVx=3 V =1.8V CC 16 ACLK,SMCLK,MCLK, PMMCOREVx=0 fPort_CLK Clockoutputfrequency CL=20pF (2) VCC=3V 25 MHz PMMCOREVx=3 (1) Aresistivedividerwith2×R1 betweenV andV isusedasload.Theoutputisconnectedtothecentertapofthedivider.Forfull CC SS drivestrength,R1=550Ω.Forreduceddrivestrength,R1=1.6kΩ.C =20pFisconnectedtotheoutputtoV . L SS (2) Theoutputvoltagereachesatleast10%and90%V atthespecifiedtogglefrequency. CC Copyright©2010–2018,TexasInstrumentsIncorporated Specifications 21 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) 25.0 8.0 VCC= 3.0 V VCC= 1.8 V TA= 25°C mA Px.y A 7.0 Px.y T = 25°C m ent– 20.0 A nt– 6.0 TA= 85°C put Curr 15.0 TA= 85°C ut Curre 5.0 Out utp vel el O 4.0 e v ow-L 10.0 w-Le 3.0 L o cal al L 2.0 ypi 5.0 pic T y I–OL –TOL 1.0 I 0.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0 Figure5-2.TypicaVlOLL–owLo-Lwe-vLeelveOl uOtputuptuCt Vuorrlteangtev–sVLow-Level Figure5-3.TypicVaOlLL–oLwow-L-eLveevellO Ouutptpuutt CVoulrtraegnet–vsVLow-Level OutputVoltage OutputVoltage 0.0 0.0 V = 3.0 V V = 1.8 V CC CC A Px.y A Px.y m m −1.0 – – nt −5.0 nt e e −2.0 urr urr C C ut ut −3.0 p −10.0 p ut ut O O el el −4.0 v v e e L L T = 85°C gh- −15.0 T = 85°C gh- −5.0 A Hi A Hi al al Typic −20.0 TA= 25°C Typic −6.0 TA= 25°C – – −7.0 IOH IOH −25.0 −8.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0 Figure5-4.TypicaVlHOHig–hH-Ligehv-LeelvOeul tOpuuttpuCtu Vroreltnatgevs–HVigh-Level Figure5-5.TypicaVlOHH–igHhi-gLhe-vLeelveOl uOtpuutptuCt Vuorrlteangtev–sVHigh-Level OutputVoltage OutputVoltage 22 Specifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 5.14 Crystal Oscillator, XT1, Low-Frequency Mode(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC f =32768Hz,XTS=0, OSC XT1BYPASS=0,XT1DRIVEx=1, 0.075 T =25°C A DifferentialXT1oscillatorcrystal f =32768Hz,XTS=0, OSC ΔI currentconsumptionfromlowest XT1BYPASS=0,XT1DRIVEx=2, 3V 0.170 µA DVCC.LF drivesetting,LFmode T =25°C A f =32768Hz,XTS=0, OSC XT1BYPASS=0,XT1DRIVEx=3, 0.290 T =25°C A XT1oscillatorcrystalfrequency, f XTS=0,XT1BYPASS=0 32768 Hz XT1,LF0 LFmode f XT1oscillatorlogic-levelsquare- XTS=0,XT1BYPASS=1 (2) (3) 10 32.768 50 kHz XT1,LF,SW waveinputfrequency,LFmode XTS=0, XT1BYPASS=0,XT1DRIVEx=0, 210 Oscillationallowancefor fXT1,LF=32768Hz,CL,eff=6pF OALF LFcrystals (4) XTS=0, kΩ XT1BYPASS=0,XT1DRIVEx=1, 300 f =32768Hz,C =12pF XT1,LF L,eff XTS=0,XCAPx=0(6) 1 Integratedeffectiveload XTS=0,XCAPx=1 5.5 CL,eff capacitance,LFmode (5) XTS=0,XCAPx=2 8.5 pF XTS=0,XCAPx=3 12.0 XTS=0,MeasuredatACLK, Dutycycle,LFmode 30% 70% f =32768Hz XT1,LF fFault,LF O(7)scillatorfaultfrequency,LFmode XTS=0 (8) 10 10000 Hz f =32768Hz,XTS=0, OSC XT1BYPASS=0,XT1DRIVEx=0, 1000 T =25°C,C =6pF A L,eff t Start-uptime,LFmode 3V ms START,LF f =32768Hz,XTS=0, OSC XT1BYPASS=0,XT1DRIVEx=3, 500 T =25°C,C =12pF A L,eff (1) ToimproveEMIontheXT1oscillator,thefollowingguidelinesshouldbeobserved. • Keepthetracebetweenthedeviceandthecrystalasshortaspossible. • Designagoodgroundplanearoundtheoscillatorpins. • PreventcrosstalkfromotherclockordatalinesintooscillatorpinsXINandXOUT. • AvoidrunningPCBtracesunderneathoradjacenttotheXINandXOUTpins. • UseassemblymaterialsandprocessesthatavoidanyparasiticloadontheoscillatorXINandXOUTpins. • Ifconformalcoatingisused,makesurethatitdoesnotinducecapacitiveorresistiveleakagebetweentheoscillatorpins. (2) WhenXT1BYPASSisset,XT1circuitsareautomaticallypowereddown.Inputsignalisadigitalsquarewavewithparametricsdefinedin theSchmitt-triggerInputssectionofthisdatasheet. (3) Maximumfrequencyofoperationoftheentiredevicecannotbeexceeded. (4) Oscillationallowanceisbasedonasafetyfactorof5forrecommendedcrystals.Theoscillationallowanceisafunctionofthe XT1DRIVExsettingsandtheeffectiveload.Ingeneral,comparableoscillatorallowancecanbeachievedbasedonthefollowing guidelines,butshouldbeevaluatedbasedontheactualcrystalselectedfortheapplication: • ForXT1DRIVEx=0,C ≤6pF. L,eff • ForXT1DRIVEx=1,6pF≤C ≤9pF. L,eff • ForXT1DRIVEx=2,6pF≤C ≤10pF. L,eff • ForXT1DRIVEx=3,C ≥6pF. L,eff (5) Includesparasiticbondandpackagecapacitance(approximately2pFperpin). BecausethePCBaddsadditionalcapacitance,verifythecorrectloadbymeasuringtheACLKfrequency.Foracorrectsetup,the effectiveloadcapacitanceshouldalwaysmatchthespecificationoftheusedcrystal. (6) Requiresexternalcapacitorsatbothterminals.Valuesarespecifiedbycrystalmanufacturers. (7) FrequenciesbelowtheMINspecificationsetthefaultflag.FrequenciesabovetheMAXspecificationdonotsetthefaultflag. FrequenciesbetweentheMINandMAXspecificationsmightsettheflag. (8) Measuredwithlogic-levelinputfrequencybutalsoappliestooperationwithcrystals. Copyright©2010–2018,TexasInstrumentsIncorporated Specifications 23 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 5.15 Crystal Oscillator, XT2 overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) (1) (2) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC f =4MHz,XT2OFF=0, OSC 200 XT2BYPASS=0,XT2DRIVEx=0,T =25°C A f =12MHz,XT2OFF=0, OSC 260 XT2oscillatorcrystalcurrent XT2BYPASS=0,XT2DRIVEx=1,TA=25°C I 3V µA DVCC.XT2 consumption f =20MHz,XT2OFF=0, OSC 325 XT2BYPASS=0,XT2DRIVEx=2,T =25°C A f =32MHz,XT2OFF=0, OSC 450 XT2BYPASS=0,XT2DRIVEx=3,T =25°C A f XT2oscillatorcrystal XT2DRIVEx=0,XT2BYPASS=0 (3) 4 8 MHz XT2,HF0 frequency,mode0 f XT2oscillatorcrystal XT2DRIVEx=1,XT2BYPASS=0 (3) 8 16 MHz XT2,HF1 frequency,mode1 f XT2oscillatorcrystal XT2DRIVEx=2,XT2BYPASS=0 (3) 16 24 MHz XT2,HF2 frequency,mode2 f XT2oscillatorcrystal XT2DRIVEx=3,XT2BYPASS=0 (3) 24 32 MHz XT2,HF3 frequency,mode3 XT2oscillatorlogic-level f square-waveinputfrequency, XT2BYPASS=1 (4) (3) 0.7 32 MHz XT2,HF,SW bypassmode XT2DRIVEx=0,XT2BYPASS=0, 450 f =6MHz,C =15pF XT2,HF0 L,eff XT2DRIVEx=1,XT2BYPASS=0, 320 Oscillationallowancefor fXT2,HF1=12MHz,CL,eff=15pF OAHF HFcrystals (5) XT2DRIVEx=2,XT2BYPASS=0, Ω 200 f =20MHz,C =15pF XT2,HF2 L,eff XT2DRIVEx=3,XT2BYPASS=0, 200 f =32MHz,C =15pF XT2,HF3 L,eff f =6MHz, OSC XT2BYPASS=0,XT2DRIVEx=0, 0.5 T =25°C,C =15pF A L,eff t Start-uptime 3V ms START,HF f =20MHz OSC XT2BYPASS=0,XT2DRIVEx=2, 0.3 T =25°C,C =15pF A L,eff Integratedeffectiveload CL,eff capacitance,HFmode (6) (1) 1 pF Dutycycle MeasuredatACLK,f =20MHz 40% 50% 60% XT2,HF2 f Oscillatorfaultfrequency (7) XT2BYPASS=1 (8) 30 300 kHz Fault,HF (1) Requiresexternalcapacitorsatbothterminals.Valuesarespecifiedbycrystalmanufacturers. (2) ToimproveEMIontheXT2oscillatorthefollowingguidelinesshouldbeobserved. • Keepthetracesbetweenthedeviceandthecrystalasshortaspossible. • Designagoodgroundplanearoundtheoscillatorpins. • PreventcrosstalkfromotherclockordatalinesintooscillatorpinsXT2INandXT2OUT. • AvoidrunningPCBtracesunderneathoradjacenttotheXT2INandXT2OUTpins. • UseassemblymaterialsandprocessesthatavoidanyparasiticloadontheoscillatorXT2INandXT2OUTpins. • Ifconformalcoatingisused,makesurethatitdoesnotinducecapacitiveorresistiveleakagebetweentheoscillatorpins. (3) Thisrepresentsthemaximumfrequencythatcanbeinputtothedeviceexternally.Maximumfrequencyachievableonthedevice operationisbasedonthefrequenciespresentonACLK,MCLK,andSMCLKcannotbeexceedforagivenrangeofoperation. (4) WhenXT2BYPASSisset,theXT2circuitisautomaticallypowereddown.Inputsignalisadigitalsquarewavewithparametricsdefined intheSchmitt-TriggerInputssectionofthisdatasheet. (5) Oscillationallowanceisbasedonasafetyfactorof5forrecommendedcrystals. (6) Includesparasiticbondandpackagecapacitance(approximately2pFperpin). BecausethePCBaddsadditionalcapacitance,verifythecorrectloadbymeasuringtheACLKfrequency.Foracorrectsetup,the effectiveloadcapacitanceshouldalwaysmatchthespecificationoftheusedcrystal. (7) FrequenciesbelowtheMINspecificationsetthefaultflag.FrequenciesabovetheMAXspecificationdonotsetthefaultflag. FrequenciesbetweentheMINandMAXspecificationsmightsettheflag. (8) Measuredwithlogic-levelinputfrequencybutalsoappliestooperationwithcrystals. 24 Specifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 5.16 Internal Very-Low-Power Low-Frequency Oscillator (VLO) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC f VLOfrequency MeasuredatACLK 1.8Vto3.6V 6 9.4 14 kHz VLO df /d VLOfrequencytemperaturedrift MeasuredatACLK(1) 1.8Vto3.6V 0.5 %/°C VLO T df /dV VLOfrequencysupplyvoltagedrift MeasuredatACLK(2) 1.8Vto3.6V 4 %/V VLO CC Dutycycle MeasuredatACLK 1.8Vto3.6V 40% 50% 60% (1) Calculatedusingtheboxmethod:(MAX(–40°Cto85°C)–MIN(–40°Cto85°C))/MIN(–40°Cto85°C)/(85°C–(–40°C)) (2) Calculatedusingtheboxmethod:(MAX(1.8Vto3.6V)–MIN(1.8Vto3.6V))/MIN(1.8Vto3.6V)/(3.6V–1.8V) 5.17 Internal Reference, Low-Frequency Oscillator (REFO) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC I REFOoscillatorcurrentconsumption T =25°C 1.8Vto3.6V 3 µA REFO A REFOfrequencycalibrated MeasuredatACLK 1.8Vto3.6V 32768 Hz f Fulltemperaturerange 1.8Vto3.6V ±3.5% REFO REFOabsolutetolerancecalibrated T =25°C 3V ±1.5% A df /d REFOfrequencytemperaturedrift MeasuredatACLK(1) 1.8Vto3.6V 0.01 %/°C REFO T df /dV REFOfrequencysupplyvoltagedrift MeasuredatACLK(2) 1.8Vto3.6V 1.0 %/V REFO CC Dutycycle MeasuredatACLK 1.8Vto3.6V 40% 50% 60% t REFOstartuptime 40%/60%dutycycle 1.8Vto3.6V 25 µs START (1) Calculatedusingtheboxmethod:(MAX(–40°Cto85°C)–MIN(–40°Cto85°C))/MIN(–40°Cto85°C)/(85°C–(–40°C)) (2) Calculatedusingtheboxmethod:(MAX(1.8Vto3.6V)–MIN(1.8Vto3.6V))/MIN(1.8Vto3.6V)/(3.6V–1.8V) Copyright©2010–2018,TexasInstrumentsIncorporated Specifications 25 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 5.18 DCO Frequency overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT f DCOfrequency(0,0)(1) DCORSELx=0,DCOx=0,MODx=0 0.07 0.20 MHz DCO(0,0) f DCOfrequency(0,31)(1) DCORSELx=0,DCOx=31,MODx=0 0.70 1.70 MHz DCO(0,31) f DCOfrequency(1,0)(1) DCORSELx=1,DCOx=0,MODx=0 0.15 0.36 MHz DCO(1,0) f DCOfrequency(1,31)(1) DCORSELx=1,DCOx=31,MODx=0 1.47 3.45 MHz DCO(1,31) f DCOfrequency(2,0)(1) DCORSELx=2,DCOx=0,MODx=0 0.32 0.75 MHz DCO(2,0) f DCOfrequency(2,31)(1) DCORSELx=2,DCOx=31,MODx=0 3.17 7.38 MHz DCO(2,31) f DCOfrequency(3,0)(1) DCORSELx=3,DCOx=0,MODx=0 0.64 1.51 MHz DCO(3,0) f DCOfrequency(3,31)(1) DCORSELx=3,DCOx=31,MODx=0 6.07 14.0 MHz DCO(3,31) f DCOfrequency(4,0)(1) DCORSELx=4,DCOx=0,MODx=0 1.3 3.2 MHz DCO(4,0) f DCOfrequency(4,31)(1) DCORSELx=4,DCOx=31,MODx=0 12.3 28.2 MHz DCO(4,31) f DCOfrequency(5,0)(1) DCORSELx=5,DCOx=0,MODx=0 2.5 6.0 MHz DCO(5,0) f DCOfrequency(5,31)(1) DCORSELx=5,DCOx=31,MODx=0 23.7 54.1 MHz DCO(5,31) f DCOfrequency(6,0)(1) DCORSELx=6,DCOx=0,MODx=0 4.6 10.7 MHz DCO(6,0) f DCOfrequency(6,31)(1) DCORSELx=6,DCOx=31,MODx=0 39.0 88.0 MHz DCO(6,31) f DCOfrequency(7,0)(1) DCORSELx=7,DCOx=0,MODx=0 8.5 19.6 MHz DCO(7,0) f DCOfrequency(7,31)(1) DCORSELx=7,DCOx=31,MODx=0 60 135 MHz DCO(7,31) Frequencystepbetweenrange S S =f /f 1.2 2.3 ratio DCORSEL DCORSELandDCORSEL+1 RSEL DCO(DCORSEL+1,DCO) DCO(DCORSEL,DCO) FrequencystepbetweentapDCO S S =f /f 1.02 1.12 ratio DCO andDCO+1 DCO DCO(DCORSEL,DCO+1) DCO(DCORSEL,DCO) Dutycycle MeasuredatSMCLK 40% 50% 60% df /dT DCOfrequencytemperaturedrift(2) f =1MHz, 0.1 %/°C DCO DCO df /dV DCOfrequencyvoltagedrift(3) f =1MHz 1.9 %/V DCO CC DCO (1) WhenselectingtheproperDCOfrequencyrange(DCORSELx),thetargetDCOfrequency,f ,shouldbesettoresidewithinthe DCO rangeoff ≤f ≤f ,wheref representsthemaximumfrequencyspecifiedfortheDCOfrequency, DCO(n,0),MAX DCO DCO(n,31),MIN DCO(n,0),MAX rangen,tap0(DCOx=0)andf representstheminimumfrequencyspecifiedfortheDCOfrequency,rangen,tap31 DCO(n,31),MIN (DCOx=31).ThisensuresthatthetargetDCOfrequencyresideswithintherangeselected.Itshouldalsobenotedthatiftheactual f frequencyfortheselectedrangecausestheFLLortheapplicationtoselecttap0or31,theDCOfaultflagissettoreportthatthe DCO selectedrangeisatitsminimumormaximumtapsetting. (2) Calculatedusingtheboxmethod:(MAX(–40°Cto85°C)–MIN(–40°Cto85°C))/MIN(–40°Cto85°C)/(85°C–(–40°C)) (3) Calculatedusingtheboxmethod:(MAX(1.8Vto3.6V)–MIN(1.8Vto3.6V))/MIN(1.8Vto3.6V)/(3.6V–1.8V) 100 V = 3.0 V CC T = 25°C A 10 z H M – O fDC DCOx = 31 1 DCOx = 0 0.1 0 1 2 3 4 5 6 7 DCORSEL Figure5-6.TypicalDCOFrequency 26 Specifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 5.19 PMM, Brownout Reset (BOR) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V (DVCC_BOR_IT BOR onvoltage,DV fallinglevel |dDV /d |<3V/s 1.45 V H CC CC t –) V (DVCC_BOR_IT BOR offvoltage,DV risinglevel |dDV /d |<3V/s 0.80 1.30 1.50 V H CC CC t +) V (DVCC_BOR_h BOR hysteresis 50 250 mV H ys) t PulsedurationrequiredatRST/NMIpintoacceptareset 2 µs RESET 5.20 PMM, Core Voltage overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V (AM) Corevoltage,activemode,PMMCOREV=3 2.4V≤DV ≤3.6V 1.90 V CORE3 CC V (AM) Corevoltage,activemode,PMMCOREV=2 2.2V≤DV ≤3.6V 1.80 V CORE2 CC V (AM) Corevoltage,activemode,PMMCOREV=1 2.0V≤DV ≤3.6V 1.60 V CORE1 CC V (AM) Corevoltage,activemode,PMMCOREV=0 1.8V≤DV ≤3.6V 1.40 V CORE0 CC V (LPM) Corevoltage,low-currentmode,PMMCOREV=3 2.4V≤DV ≤3.6V 1.94 V CORE3 CC V (LPM) Corevoltage,low-currentmode,PMMCOREV=2 2.2V≤DV ≤3.6V 1.84 V CORE2 CC V (LPM) Corevoltage,low-currentmode,PMMCOREV=1 2.0V≤DV ≤3.6V 1.64 V CORE1 CC V (LPM) Corevoltage,low-currentmode,PMMCOREV=0 1.8V≤DV ≤3.6V 1.44 V CORE0 CC 5.21 PMM, SVS High Side overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SVSHE=0,DV =3.6V 0 CC nA I SVScurrentconsumption SVSHE=1,DV =3.6V,SVSHFP=0 200 (SVSH) CC SVSHE=1,DV =3.6V,SVSHFP=1 1.5 µA CC SVSHE=1,SVSHRVL=0 1.57 1.68 1.78 SVSHE=1,SVSHRVL=1 1.79 1.88 1.98 V SVS onvoltagelevel(1) V (SVSH_IT–) H SVSHE=1,SVSHRVL=2 1.98 2.08 2.21 SVSHE=1,SVSHRVL=3 2.10 2.18 2.31 SVSHE=1,SVSMHRRL=0 1.62 1.74 1.85 SVSHE=1,SVSMHRRL=1 1.88 1.94 2.07 SVSHE=1,SVSMHRRL=2 2.07 2.14 2.28 SVSHE=1,SVSMHRRL=3 2.20 2.30 2.42 V SVS offvoltagelevel(1) V (SVSH_IT+) H SVSHE=1,SVSMHRRL=4 2.32 2.40 2.55 SVSHE=1,SVSMHRRL=5 2.52 2.70 2.88 SVSHE=1,SVSMHRRL=6 2.90 3.10 3.23 SVSHE=1,SVSMHRRL=7 2.90 3.10 3.23 SVSHE=1,dV /dt=10mV/µs, DVCC 2.5 SVSHFP=1 t SVS propagationdelay µs pd(SVSH) H SVSHE=1,dV /dt=1mV/µs, DVCC 20 SVSHFP=0 SVSHE=0→1,SVSHFP=1 12.5 t SVS onoroffdelaytime µs (SVSH) H SVSHE=0→1,SVSHFP=0 100 dV /dt DV risetime 0 1000 V/s DVCC CC (1) TheSVS settingsthatareavailabledependontheVCORE(PMMCOREVx)setting.SeethePower-ManagementModuleandSupply H VoltageSupervisorchapterintheMSP430F5xxandMSP430F6xxFamilyUser'sGuideforrecommendedsettingsanduse. Copyright©2010–2018,TexasInstrumentsIncorporated Specifications 27 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 5.22 PMM, SVM High Side overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SVMHE=0,DV =3.6V 0 CC nA I SVM currentconsumption SVMHE=1,DV =3.6V,SVMHFP=0 200 (SVMH) H CC SVMHE=1,DV =3.6V,SVMHFP=1 1.5 µA CC SVMHE=1,SVSMHRRL=0 1.62 1.74 1.85 SVMHE=1,SVSMHRRL=1 1.88 1.94 2.07 SVMHE=1,SVSMHRRL=2 2.07 2.14 2.28 SVMHE=1,SVSMHRRL=3 2.20 2.30 2.42 V SVM onoroffvoltagelevel (1) SVMHE=1,SVSMHRRL=4 2.32 2.40 2.55 V (SVMH) H SVMHE=1,SVSMHRRL=5 2.52 2.70 2.88 SVMHE=1,SVSMHRRL=6 2.90 3.10 3.23 SVMHE=1,SVSMHRRL=7 2.90 3.10 3.23 SVMHE=1,SVMHOVPE=1 3.75 SVMHE=1,dV /dt=10mV/µs, DVCC 2.5 SVMHFP=1 t SVM propagationdelay µs pd(SVMH) H SVMHE=1,dV /dt=1mV/µs, DVCC 20 SVMHFP=0 SVMHE=0→1,SVMHFP=1 12.5 t SVM onoroffdelaytime µs (SVMH) H SVMHE=0→1,SVMHFP=0 100 (1) TheSVM settingsavailabledependontheVCORE(PMMCOREVx)setting.SeethePower-ManagementModuleandSupplyVoltage H SupervisorchapterintheMSP430F5xxandMSP430F6xxFamilyUser'sGuideonrecommendedsettingsanduse. 5.23 PMM, SVS Low Side overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SVSLE=0,PMMCOREV=2 0 nA I SVS currentconsumption SVSLE=1,PMMCOREV=2,SVSLFP=0 200 (SVSL) L SVSLE=1,PMMCOREV=2,SVSLFP=1 2.0 µA SVSLE=1,dV /dt=10mV/µs,SVSLFP=1 2.5 CORE t SVS propagationdelay µs pd(SVSL) L SVSLE=1,dV /dt=1mV/µs,SVSLFP=0 20 CORE SVSLE=0→1,SVSLFP=1 12.5 t SVS onoroffdelaytime µs (SVSL) L SVSLE=0→1,SVSLFP=0 100 5.24 PMM, SVM Low Side overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SVMLE=0,PMMCOREV=2 0 nA I SVM currentconsumption SVMLE=1,PMMCOREV=2,SVMLFP=0 200 (SVML) L SVMLE=1,PMMCOREV=2,SVMLFP=1 1.5 µA SVMLE=1,dV /dt=10mV/µs,SVMLFP=1 2.5 CORE t SVM propagationdelay µs pd(SVML) L SVMLE=1,dV /dt=1mV/µs,SVMLFP=0 20 CORE SVMLE=0→1,SVMLFP=1 12.5 t SVM onoroffdelaytime µs (SVML) L SVMLE=0→1,SVMLFP=0 100 28 Specifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 5.25 Wake-up Times From Low-Power Modes and Reset overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Wake-uptimefromLPM2, PMMCOREV=SVSMLRRL=n f ≥4.0MHz 5 MCLK t LPM3,orLPM4toactive (wheren=0,1,2,or3), µs WAKE-UP-FAST mode(1) SVSLFP=1 fMCLK<4.0MHz 6 Wake-uptimefromLPM2, PMMCOREV=SVSMLRRL=n t LPM3,orLPM4toactive (wheren=0,1,2,or3), 150 165 µs WAKE-UP-SLOW mode(2)(3) SVSLFP=0 Wake-uptimefromLPM4.5to tWAKE-UP-LPM5 activemode(4) 2 3 ms Wake-uptimefromRSTor tWAKE-UP-RESET BOReventtoactivemode(4) 2 3 ms (1) Thisvaluerepresentsthetimefromthewake-upeventtothefirstactiveedgeofMCLK.Thewake-uptimedependsontheperformance modeofthelow-sidesupervisor(SVS )andlow-sidemonitor(SVM ).t ispossiblewithSVS andSVM infullperformance L L WAKE-UP-FAST L L modeordisabled.Forspecificregistersettings,seetheLow-SideSVSandSVMControlandPerformanceModeSelectionsectionin thePowerManagementModuleandSupplyVoltageSupervisorchapteroftheMSP430F5xxandMSP430F6xxFamilyUser'sGuide. (2) Thisvaluerepresentsthetimefromthewake-upeventtothefirstactiveedgeofMCLK.Thewake-uptimedependsontheperformance modeofthelow-sidesupervisor(SVS )andlow-sidemonitor(SVM ).t issetwithSVS andSVM innormalmode(low L L WAKE-UP-SLOW L L currentmode).Forspecificregistersettings,seetheLow-SideSVSandSVMControlandPerformanceModeSelectionsectioninthe PowerManagementModuleandSupplyVoltageSupervisorchapteroftheMSP430F5xxandMSP430F6xxFamilyUser'sGuide. (3) Thewake-uptimesfromLPM0andLPM1toAMarenotspecified.TheyareproportionaltoMCLKcycletimebutarenotaffectedbythe performancemodesettingsasforLPM2,LPM3,andLPM4. (4) Thisvaluerepresentsthetimefromthewake-upeventtotheresetvectorexecution. 5.26 Timer_A overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC Internal:SMCLKorACLK, f Timer_Ainputclockfrequency External:TACLK, 1.8V,3V 25 MHz TA Dutycycle=50%±10% Allcaptureinputs, t Timer_Acapturetiming 1.8V,3V 20 ns TA,cap Minimumpulsedurationrequiredforcapture 5.27 Timer_B overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC Internal:SMCLKorACLK, f Timer_Binputclockfrequency External:TBCLK, 1.8V,3V 25 MHz TB Dutycycle=50%±10% Allcaptureinputs,minimumpulsedurationrequired t Timer_Bcapturetiming 1.8V,3V 20 ns TB,cap forcapture Copyright©2010–2018,TexasInstrumentsIncorporated Specifications 29 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 5.28 USCI (UART Mode) Clock Frequency PARAMETER CONDITIONS V MIN MAX UNIT CC Internal:SMCLKorACLK, f USCIinputclockfrequency External:UCLK, f MHz USCI SYSTEM Dutycycle=50%±10% BITCLKclockfrequency f 1 MHz BITCLK (equalsbaudrateinMBaud) 5.29 USCI (UART Mode) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER V MIN MAX UNIT CC 2.2V 50 600 t UARTreceivedeglitchtime (1) ns τ 3V 50 600 (1) PulsesontheUARTreceiveinput(UCxRX)shorterthantheUARTreceivedeglitchtimearesuppressed.Toensurethatpulsesare correctlyrecognized,theirdurationshouldexceedthemaximumspecificationofthedeglitchtime. 5.30 USCI (SPI Master Mode) Clock Frequency PARAMETER CONDITIONS MIN MAX UNIT Internal:SMCLKorACLK, f USCIinputclockfrequency f MHz USCI Dutycycle=50%±10% SYSTEM 5.31 USCI (SPI Master Mode) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) (seeFigure5-7andFigure5-8) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC SMCLKorACLK, f USCIinputclockfrequency f MHz USCI Dutycycle=50%±10% SYSTEM 1.8V 55 PMMCOREV=0 3V 38 t SOMIinputdatasetuptime ns SU,MI 2.4V 30 PMMCOREV=3 3V 25 1.8V 0 PMMCOREV=0 3V 0 t SOMIinputdataholdtime ns HD,MI 2.4V 0 PMMCOREV=3 3V 0 UCLKedgetoSIMOvalid, 1.8V 20 CL=20pF,PMMCOREV=0 3V 18 t SIMOoutputdatavalidtime (2) ns VALID,MO UCLKedgetoSIMOvalid, 2.4V 16 CL=20pF,PMMCOREV=3 3V 15 1.8V –10 C =20pF,PMMCOREV=0 L 3V –8 t SIMOoutputdataholdtime (3) ns HD,MO 2.4V –10 C =20pF,PMMCOREV=3 L 3V –8 (1) f =1/2t witht ≥max(t +t ,t +t ) UCxCLK LO/HI LO/HI VALID,MO(USCI) SU,SI(Slave) SU,MI(USCI) VALID,SO(Slave) Fortheslaveparameterst andt ,seetheSPIparametersoftheattachedslave. SU,SI(Slave) VALID,SO(Slave) (2) SpecifiesthetimetodrivethenextvaliddatatotheSIMOoutputaftertheoutputchangingUCLKclockedge.Seethetimingdiagrams inFigure5-7andFigure5-8. (3) SpecifieshowlongdataontheSIMOoutputisvalidaftertheoutputchangingUCLKclockedge.Negativevaluesindicatethatthedata ontheSIMOoutputcanbecomeinvalidbeforetheoutputchangingclockedgeobservedonUCLK.SeethetimingdiagramsinFigure5- 7andFigure5-8. 30 Specifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 1/f UCxCLK CKPL= 0 UCLK CKPL= 1 t t LO/HI LO/HI t SU,MI t HD,MI SOMI t HD,MO t VALID,MO SIMO Figure5-7.SPIMasterMode,CKPH=0 1/f UCxCLK CKPL= 0 UCLK CKPL= 1 t t LO/HI LO/HI t t HD,MI SU,MI SOMI t HD,MO t VALID,MO SIMO Figure5-8.SPIMasterMode,CKPH=1 Copyright©2010–2018,TexasInstrumentsIncorporated Specifications 31 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 5.32 USCI (SPI Slave Mode) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) (seeFigure5-9andFigure5-10) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC 1.8V 11 PMMCOREV=0 3V 8 t STEleadtime,STElowtoclock ns STE,LEAD 2.4V 7 PMMCOREV=3 3V 6 1.8V 3 PMMCOREV=0 3V 3 t STElagtime,LastclocktoSTEhigh ns STE,LAG 2.4V 3 PMMCOREV=3 3V 3 1.8V 66 PMMCOREV=0 3V 50 t STEaccesstime,STElowtoSOMIdataout ns STE,ACC 2.4V 36 PMMCOREV=3 3V 30 1.8V 30 PMMCOREV=0 STEdisabletime,STEhightoSOMIhigh 3V 23 t ns STE,DIS impedance 2.4V 16 PMMCOREV=3 3V 13 1.8V 5 PMMCOREV=0 3V 5 t SIMOinputdatasetuptime ns SU,SI 2.4V 2 PMMCOREV=3 3V 2 1.8V 5 PMMCOREV=0 3V 5 t SIMOinputdataholdtime ns HD,SI 2.4V 5 PMMCOREV=3 3V 5 UCLKedgetoSOMIvalid, 1.8V 76 CL=20pF,PMMCOREV=0 3V 60 t SOMIoutputdatavalidtime (2) ns VALID,SO UCLKedgetoSOMIvalid, 2.4V 44 CL=20pF,PMMCOREV=3 3V 40 1.8V 18 C =20pF,PMMCOREV=0 L 3V 12 t SOMIoutputdataholdtime (3) ns HD,SO 2.4V 10 C =20pF,PMMCOREV=3 L 3V 8 (1) f =1/2t witht ≥max(t +t ,t +t ) UCxCLK LO/HI LO/HI VALID,MO(Master) SU,SI(USCI) SU,MI(Master) VALID,SO(USCI) Forthemasterparameterst andt ,seetheSPIparametersoftheattachedmaster. SU,MI(Master) VALID,MO(Master) (2) SpecifiesthetimetodrivethenextvaliddatatotheSOMIoutputaftertheoutputchangingUCLKclockedge.Seethetimingdiagrams inFigure5-9andFigure5-10. (3) SpecifieshowlongdataontheSOMIoutputisvalidaftertheoutputchangingUCLKclockedge.SeethetimingdiagramsinFigure5-9 andFigure5-10. 32 Specifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 t t STE,LEAD STE,LAG STE 1/f UCxCLK CKPL= 0 UCLK CKPL= 1 t t t LO/HI LO/HI SU,SI t HD,SI SIMO t HD,SO t t t STE,ACC VALID,SO STE,DIS SOMI Figure5-9.SPISlaveMode,CKPH=0 t t STE,LEAD STE,LAG STE 1/f UCxCLK CKPL= 0 UCLK CKPL= 1 t t LO/HI LO/HI t HD,SI t SU,SI SIMO t HD,MO t t t STE,ACC VALID,SO STE,DIS SOMI Figure5-10.SPISlaveMode,CKPH=1 Copyright©2010–2018,TexasInstrumentsIncorporated Specifications 33 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 5.33 USCI (I2C Mode) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(seeFigure5-11) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC Internal:SMCLKorACLK, f USCIinputclockfrequency External:UCLK, f MHz USCI SYSTEM Dutycycle=50%±10% f SCLclockfrequency 2.2V,3V 0 400 kHz SCL f ≤100kHz 4.0 SCL t Holdtime(repeated)START 2.2V,3V µs HD,STA f >100kHz 0.6 SCL f ≤100kHz 4.7 SCL t SetuptimeforarepeatedSTART 2.2V,3V µs SU,STA f >100kHz 0.6 SCL t Dataholdtime 2.2V,3V 0 ns HD,DAT t Datasetuptime 2.2V,3V 250 ns SU,DAT f ≤100kHz 4.0 SCL t SetuptimeforSTOP 2.2V,3V µs SU,STO f >100kHz 0.6 SCL 2.2V 50 600 t Pulsedurationofspikessuppressedbyinputfilter ns SP 3V 50 600 t t t t HD,STA SU,STA HD,STA BUF SDA t t t LOW HIGH SP SCL t t SU,DAT SU,STO t HD,DAT Figure5-11.I2CModeTiming 34 Specifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 5.34 10-Bit ADC, Power Supply and Input Range Conditions overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC AV andDV areconnectedtogether, CC CC AV Analogsupplyvoltage AV andDV areconnectedtogether, 1.8 3.6 V CC SS SS V =V =0V (AVSS) (DVSS) V Analoginputvoltagerange (2) AllADC10_Apins:P6.0toP6.7,P5.0,andP5.1 0 AV V (Ax) terminals CC Operatingsupplycurrentinto f =5MHz,ADC10ON=1,REFON=0, 2.2V 60 100 ADC10CLK AVCCterminal.REFmodule SHT0=0,SHT1=0,ADC10DIV =0, andreferencebufferoff. ADC10SREF=00 3V 75 110 Operatingsupplycurrentinto f =5MHz,ADC10ON=1,REFON=1, ADC10CLK AVCCterminal.REFmodule SHT0=0,SHT1=0,ADC10DIV =0, 3V 113 150 on,referencebufferon. ADC10SREF=01 I µA ADC10_A Operatingsupplycurrentinto f =5MHz,ADC10ON=1,REFON=0, ADC10CLK AVCCterminal.REFmodule SHT0=0,SHT1=0,ADC10DIV =0, 3V 105 140 off,referencebufferon. ADC10SREF=10,VEREF=2.5V Operatingsupplycurrentinto f =5MHz,ADC10ON=1,REFON=0, ADC10CLK AVCCterminal.REFmodule SHT0=0,SHT1=0,ADC10DIV =0, 3V 70 110 off,referencebufferoff. ADC10SREF=11,VEREF=2.5V OnlyoneterminalAxcanbeselectedatonetime C Inputcapacitance fromthepadtotheADC10_Acapacitorarray 2.2V 3.5 pF I includingwiringandpad. AV >2.0V,0V≤V ≤AV 36 CC Ax CC R InputMUXONresistance kΩ I 1.8V<AV <2.0V,0V≤V ≤AV 96 CC Ax CC (1) TheleakagecurrentisdefinedintheleakagecurrenttablewithP6.x/Axparameter. (2) TheanaloginputvoltagerangemustbewithintheselectedreferencevoltagerangeV toV forvalidconversionresults.Theexternal R+ R– referencevoltagerequiresdecouplingcapacitors.Twodecouplingcapacitors,10µFand100nF,shouldbeconnectedtoVeREFto decouplethedynamiccurrentrequiredforanexternalreferencesourceifitisusedfortheADC10_A.SeealsotheMSP430F5xxand MSP430F6xxFamilyUser'sGuide. 5.35 10-Bit ADC, Timing Parameters overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC ForspecifiedperformanceofADC10_A f 2.2V,3V 0.45 5 5.5 MHz ADC10CLK linearityparameters InternalADC10_A fADC10OSC oscillator (1) ADC10DIV=0,fADC10CLK=fADC10OSC 2.2V,3V 4.2 4.8 5.4 MHz REFON=0,Internaloscillator, 12ADC10CLKcycles,10-bitmode, 2.2V,3V 2.4 3.0 tCONVERT Conversiontime fADC10OSC=4MHzto5MHz µs Externalf fromACLK,MCLKor 12× ADC10CLK SMCLK,ADC10SSEL≠0 1/f ADC10CLK t Turnonsettlingtimeof See (2) 100 ns ADC10ON theADC R =1000Ω,R =96kΩ,C =3.5pF(3) 1.8V 3 µs S I I t Samplingtime Sample R =1000Ω,R =36kΩ,C =3.5pF(3) 3V 1 µs S I I (1) TheADC10OSCissourceddirectlyfromMODOSCinsidetheUCS. (2) Theconditionisthattheerrorinaconversionstartedaftert islessthan±0.5LSB.Thereferenceandinputsignalarealready ADC10ON settled. (3) Approximately8Tau(τ)arerequiredforanerroroflessthan±0.5LSB Copyright©2010–2018,TexasInstrumentsIncorporated Specifications 35 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 5.36 10-Bit ADC, Linearity Parameters overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 1.4V≤(V –V )≤1.6V,C =20pF ±1.0 eREF+ eREF– VeREF+ E Integrallinearityerror 2.2V,3V LSB I 1.6V<(V –V )≤V ,C =20pF ±1.0 eREF+ eREF– AVCC VeREF+ Differential E 1.4V≤(V –V ),C =20pF 2.2V,3V ±1.0 LSB D linearityerror eREF+ eREF– VeREF+ 1.4V≤(V –V ),C =20pF, E Offseterror eREF+ eREF– VeREF+ 2.2V,3V ±1.0 LSB O InternalimpedanceofsourceR <100Ω S 1.4V≤(V –V ),C =20pF, E Gainerror eREF+ eREF– VeREF+ 2.2V,3V ±1.0 LSB G ADC10SREFx=11b 1.4V≤(V –V ),C =20pF, E Totalunadjustederror eREF+ eREF– VeREF+ 2.2V,3V ±1.0 ±2.0 LSB T ADC10SREFx=11b 5.37 REF, External Reference overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC V Positiveexternalreference V >V (2) 1.4 AV V eREF+ voltageinput eREF+ eREF– CC V Negativeexternalreference V >V (3) 0 1.2 V eREF– voltageinput eREF+ eREF– (VeREF+– Differentialexternalreference V >V (4) 1.4 AV V V ) voltageinput eREF+ eREF– CC eREF– 1.4V≤V ≤V ,V =0V, eREF+ AVCC eREF– f =5MHz,ADC10SHTx=0x0001, ±8.5 ±26 ADC10CLK I Conversionrate200ksps VeREF+ Staticinputcurrent 2.2V,3V µA IVeREF– 1.4V≤VeREF+≤VAVCC,VeREF– =0V, f =5MHz,ADC10SHTX=0x1000, ±1 ADC10CLK Conversionrate20ksps C CapacitanceatVeREF+or (5) 10 µF VREF+/- VeREF-terminal (1) TheexternalreferenceisusedduringADCconversiontochargeanddischargethecapacitancearray.Theinputcapacitance,C,isalso I thedynamicloadforanexternalreferenceduringconversion.Thedynamicimpedanceofthereferencesupplyshouldfollowthe recommendationsonanalog-sourceimpedancetoallowthechargetosettlefor10-bitaccuracy. (2) Theaccuracylimitstheminimumpositiveexternalreferencevoltage.Lowerreferencevoltagelevelsmaybeappliedwithreduced accuracyrequirements. (3) Theaccuracylimitsthemaximumnegativeexternalreferencevoltage.Higherreferencevoltagelevelsmaybeappliedwithreduced accuracyrequirements. (4) Theaccuracylimitsminimumexternaldifferentialreferencevoltage.Lowerdifferentialreferencevoltagelevelsmaybeappliedwith reducedaccuracyrequirements. (5) Twodecouplingcapacitors,10µFand100nF,shouldbeconnectedtoVeREFtodecouplethedynamiccurrentrequiredforanexternal referencesourceifitisusedfortheADC10_A.SeealsotheMSP430F5xxandMSP430F6xxFamilyUser'sGuide. 36 Specifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 5.38 REF, Built-In Reference overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC REFVSEL={2}for2.5V,REFON=1 3V 2.51 ±1.5% Positivebuilt-inreference V REFVSEL={1}for2.0V,REFON=1 3V 1.99 ±1.5% V REF+ voltage REFVSEL={0}for1.5V,REFON=1 2.2V,3V 1.5 ±1.5% REFVSEL={0}for1.5V 1.8 AVCCminimumvoltage, AV REFVSEL={1}for2.0V 2.2 V CC(min) Positivebuilt-inreferenceactive REFVSEL={2}for2.5V 2.7 f =5.0MHz, ADC10CLK REFON=1,REFBURST=0, 3V 18 24 REFVSEL={2}for2.5V f =5.0MHz, Operatingsupplycurrentinto ADC10CLK IREF+ AVCCterminal (2) REFON=1,REFBURST=0, 3V 15.5 21 µA REFVSEL={1}for2.0V f =5.0MHz, ADC10CLK REFON=1,REFBURST=0, 3V 13.5 21 REFVSEL={0}for1.5V Temperaturecoefficientofbuilt- I =0A, ppm/ TCREF+ inreference (3) RVEREFFV+SEL={0,1,2},REFON=1 30 50 °C Operatingsupplycurrentinto REFON=0,INCH=0Ah, 2.2V 20 22 ISENSOR AVCCterminal (4) ADC10ON=NA,TA=30°C 3V 20 22 µA V See (5) ADC10ON=1,INCH=0Ah, 2.2V 770 mV SENSOR TA=30°C 3V 770 ADC10ON=1,INCH=0Bh, 2.2V 1.06 1.1 1.14 V AVCCdivideratchannel11 V MID VMID≈0.5×VAVCC 3V 1.46 1.5 1.54 Sampletimerequiredif ADC10ON=1,INCH=0Ah, tSENSOR(sample) channel10isselected (6) Errorofconversionresult≤1LSB 30 µs Sampletimerequiredif ADC10ON=1,INCH=0Bh, tVMID(sample) channel11isselected (7) Errorofconversionresult≤1LSB 1 µs AV =AV toAV , Powersupplyrejectionratio CC CC(min) CC(max) PSRR_DC T =25°C, 120 µV/V (DC) A REFVSEL={0,1,2},REFON=1 AV =AV toAV , Powersupplyrejectionratio CC CC(min) CC(max) PSRR_AC T =25°C,f=1kHz,ΔVpp=100mV, 6.4 mV/V (AC) A REFVSEL={0,1,2},REFON=1 Settlingtimeofreference AV =AV toAV , tSETTLE voltage(8) RECFCVSEL=CC{(0m,in1),2},RCECF(mOaNx)=0→1 75 µs (1) TheleakagecurrentisdefinedintheleakagecurrenttablewithP6.x/Axparameter. (2) TheinternalreferencecurrentissuppliedthroughtheAVCCterminal.ConsumptionisindependentoftheADC10ONcontrolbit,unlessa conversionisactive.TheREFONbitenablestosettlethebuilt-inreferencebeforestartinganA/Dconversion. (3) Calculatedusingtheboxmethod:(MAX(–40°Cto85°C)–MIN(–40°Cto85°C))/MIN(–40°Cto85°C)/(85°C–(–40°C)). (4) ThesensorcurrentI isconsumedif(ADC10ON=1andREFON=1)or(ADC10ON=1andINCH=0Ahandsamplesignalis SENSOR high).WhenREFON=1,I isalreadyincludedinI . SENSOR REF+ (5) Thetemperaturesensoroffsetcanbesignificant.TIrecommendsasingle-pointcalibrationtominimizetheoffseterrorofthebuilt-in temperaturesensor. (6) Thetypicalequivalentimpedanceofthesensoris51kΩ.Thesampletimerequiredincludesthesensor-ontimet . SENSOR(on) (7) Theon-timet isincludedinthesamplingtimet ;noadditionalontimeisneeded. VMID(on) VMID(sample) (8) Theconditionisthattheerrorinaconversionstartedaftert islessthan±0.5LSB. REFON Copyright©2010–2018,TexasInstrumentsIncorporated Specifications 37 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 5.39 Comparator_B overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC V Supplyvoltage 1.8 3.6 V CC 1.8V 40 CBPWRMD=00,CBON=1, 2.2V 30 50 CBRSx=00 Comparatoroperatingsupply 3V 40 65 I currentintoAVCC,Excludes µA AVCC_COMP CBPWRMD=01,CBON=1, 2.2V, referenceresistorladder 10 17 CBRSx=00 3V CBPWRMD=10,CBON=1, 2.2V, 0.1 0.5 CBRSx=00 3V CBREFACC=1,CBREFLx=01, 2.2V, Quiescentcurrentofresistor CBRSx=10,REFON=0,CBON=0 3V 10 17 I ladderintoAVCC,IncludingREF µA AVCC_REF modulecurrent CBREFACC=0,CBREFLx=01, 2.2V, 22 CBRSx=10,REFON=0,CBON=0 3V V Commonmodeinputrange 0 V –1 V IC CC CBPWRMD=00 ±20 V Inputoffsetvoltage mV OFFSET CBPWRMD=01,10 ±10 C Inputcapacitance 5 pF IN On(switchclosed) 3 4 kΩ R Seriesinputresistance SIN Off(switchopen) 50 MΩ CBPWRMD=00,CBF=0 450 ns t Propagationdelay,responsetime CBPWRMD=01,CBF=0 600 PD CBPWRMD=10,CBF=0 50 µs CBPWRMD=00,CBON=1, 0.35 0.6 1.0 CBF=1,CBFDLY=00 CBPWRMD=00,CBON=1, 0.6 1.0 1.8 CBF=1,CBFDLY=01 t Propagationdelaywithfilteractive µs PD,filter CBPWRMD=00,CBON=1, 1.0 1.8 3.4 CBF=1,CBFDLY=10 CBPWRMD=00,CBON=1, 1.8 3.4 6.5 CBF=1,CBFDLY=11 CBON=0toCBON=1, 1 2 CBPWRMD=00,01 t Comparatorenabletime µs EN_CMP CBON=0toCBON=1, 100 CBPWRMD=10 t Resistorreferenceenabletime CBON=0toCBON=1 1 1.5 µs EN_REF VIN× VIN× VIN× VIN=referenceintoresistorladder, (n+ (n+ V Referencevoltageforagiventap (n+1) V CB_REF n=0to31 0.5) 1.5) /32 /32 /32 38 Specifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 5.40 Ports PU.0 and PU.1 overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT V =3.3V±10%,I =–25mA, V High-leveloutputvoltage LDOO OH 2.4 V OH SeeFigure5-13fortypicalcharacteristics V =3.3V±10%,I =25mA, V Low-leveloutputvoltage LDOO OL 0.4 V OL SeeFigure5-12fortypicalcharacteristics V =3.3V±10%, V High-levelinputvoltage LDOO 2.0 V IH SeeFigure5-14fortypicalcharacteristics V =3.3V±10%, V Low-levelinputvoltage LDOO 0.8 V IL SeeFigure5-14fortypicalcharacteristics 90 V = 3.0 V V = 3.0 V urrent - mA 7800 TACC= 25ºC TVTACACCC=== 82 515º.º8CC V C 60 ut utp 50 O evel 40 VTCC== 8 15.º8C V w-L 30 A o L al 20 pic Ty 10 - IOL 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 V - Low-Level Output Voltage - V OL Figure5-12.PortsPU.0,PU.1TypicalLow-LevelOutputCharacteristics A 0 m nt - -10 e urr -20 C ut -30 p V = 1.8 V Out -40 TACC= 85 ºC el ev -50 gh-L -60 VTCC== 8 35. 0ºC V Hi V = 1.8 V A pical -70 TACC= 25 ºC VTCC== 2 35. 0ºC V Ty -80 A - IOH -900.5 1 1.5 2 2.5 3 V - High-Level Output Voltage - V OH Figure5-13.PortsPU.0,PU.1TypicalHigh-LevelOutputCharacteristics 2.0 T = 25°C, 85°C 1.8 A 1.6 V , postive-going input threshold IT+ 1.4 V d - 1.2 ol h V , negative-going input threshold es1.0 IT– hr T ut0.8 p n I0.6 0.4 0.2 0.0 1.8 2.2 2.6 3 3.4 LDOO Supply Voltage, V - V LDOO Figure5-14.PortsPU.0,PU.1TypicalInputThresholdCharacteristics Copyright©2010–2018,TexasInstrumentsIncorporated Specifications 39 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 5.41 LDO-PWR (LDO Power System) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V LDOinputdetectionthreshold 3.75 V LAUNCH V LDOinputvoltage 3.76 5.5 V LDOI V LDOoutputvoltage 3.3 ±9% V LDO V LDOOterminalinputvoltagewithLDOdisabled LDOdisabled 1.8 3.6 V LDO_EXT I MaximumexternalcurrentfromLDOOterminal LDOison 20 mA LDOO I LDOcurrentoverloaddetection (1) 60 100 mA DET C LDOIterminalrecommendedcapacitance 4.7 µF LDOI C LDOOterminalrecommendedcapacitance 220 nF LDOO Within2%,recommended t SettlingtimeV 2 ms ENABLE LDO capacitances (1) AcurrentoverloadwillbedetectedwhenthetotalcurrentsuppliedfromtheLDOexceedsthisvalue. 40 Specifications Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 5.42 Flash Memory overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER T MIN TYP MAX UNIT J DV Programorerasesupplyvoltage 1.8 3.6 V CC(PGM/ERASE) t Readaccesstimeduringmarginmode 200 ns READMARGIN I SupplycurrentfromDVCCduringprogram 3 5 mA PGM I SupplycurrentfromDVCCduringerase 2 6.5 mA ERASE I ,I SupplycurrentfromDVCCduringmasseraseorbankerase 2 6.5 mA MERASE BANK t Cumulativeprogramtime(1) 16 ms CPT Programanderaseendurance 104 105 cycles t Dataretentionduration 25°C 100 years Retention t Wordorbyteprogramtime(2) 64 85 µs Word t Blockprogramtimeforfirstbyteorword(2) 49 65 µs Block,0 Blockprogramtimeforeachadditionalbyteorword,exceptforlastbyte tBlock,1–(N–1) orword(2) 37 49 µs t Blockprogramtimeforlastbyteorword(2) 55 73 µs Block,N t Erasetimeforsegment,masserase,andbankerasewhenavailable(2) 23 32 ms Erase (1) Thecumulativeprogramtimemustnotbeexceededwhenwritingtoa128-byteflashblock.Thisparameterappliestoallprogramming methods:individualwordorbytewriteandblockwritemodes. (2) Thesevaluesarehardwiredintothestatemachineoftheflashcontroller. 5.43 JTAG and Spy-Bi-Wire Interface overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER V MIN TYP MAX UNIT CC f Spy-Bi-Wireinputfrequency 2.2V,3V 0 20 MHz SBW t Spy-Bi-Wirelowclockpulseduration 2.2V,3V 0.025 15 µs SBW,Low t Spy-Bi-Wireenabletime(TESThightoacceptanceoffirstclockedge)(1) 2.2V,3V 1 µs SBW,En t Spy-Bi-Wirereturntonormaloperationtime 15 100 µs SBW,Rst 2.2V 0 5 MHz f TCKinputfrequency,4-wireJTAG(2) TCK 3V 0 10 MHz R InternalpulldownresistanceonTEST 2.2V,3V 45 60 80 kΩ internal (1) ToolsthataccesstheSpy-Bi-WireandBSLinterfacesmustwaitforthet timeafterthefirsttransitionoftheTEST/SBWTCKpin SBW,En (lowtohigh),beforethesecondtransitionofthepin(hightolow)duringtheentrysequence. (2) f mayberestrictedtomeetthetimingrequirementsofthemoduleselected. TCK Copyright©2010–2018,TexasInstrumentsIncorporated Specifications 41 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 6 Detailed Description 6.1 CPU (Link to User's Guide) The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with sevenaddressingmodesforsourceoperandandfouraddressingmodesfordestinationoperand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to- register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remainingregistersaregeneral-purposeregisters(seeFigure6-1). Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be managedwithallinstructions. The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and bytedata. Program Counter PC/R0 Stack Pointer SP/R1 Status Register SR/CG1/R2 Constant Generator CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 Figure6-1.IntegratedCPURegisters 42 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 6.2 Operating Modes These microcontrollers have one active mode and six software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restorebacktothelow-powermodeonreturnfromtheinterruptprogram. Softwarecanconfigurethefollowingoperatingmodes: • Activemode(AM) – Allclocksareactive • Low-powermode0(LPM0) – CPUisdisabled – ACLKandSMCLKremainactive,MCLKisdisabled – FLLloopcontrolremainsactive • Low-powermode1(LPM1) – CPUisdisabled – FLLloopcontrolisdisabled – ACLKandSMCLKremainactive,MCLKisdisabled • Low-powermode2(LPM2) – CPUisdisabled – MCLK,FLLloopcontrol,andDCOCLKaredisabled – DCgeneratoroftheDCOremainsenabled – ACLKremainsactive • Low-powermode3(LPM3) – CPUisdisabled – MCLK,FLLloopcontrol,andDCOCLKaredisabled – DCgeneratoroftheDCOisdisabled – ACLKremainsactive • Low-powermode4(LPM4) – CPUisdisabled – ACLKisdisabled – MCLK,FLLloopcontrol,andDCOCLKaredisabled – DCgeneratoroftheDCOisdisabled – Crystaloscillatorisstopped – Completedataretention • Low-powermode4.5(LPM4.5) – Internalregulatordisabled – Nodataretention – Wake-upinputfromRST/NMI,P1,andP2 Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 43 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 6.3 Interrupt Vector Addresses The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 6-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table6-1.InterruptSources,Flags,andVectors SYSTEM WORD INTERRUPTSOURCE INTERRUPTFLAG PRIORITY INTERRUPT ADDRESS SystemReset Powerup Externalreset WDTIFG,KEYV(SYSRSTIV) (1) (2) Reset 0FFFEh 63,highest Watchdogtime-out,password violation Flashmemorypasswordviolation SystemNMI SVMLIFG,SVMHIFG,DLYLIFG,DLYHIFG, PMM VLRLIFG,VLRHIFG,VMAIFG,JMBNIFG, (Non)maskable 0FFFCh 62 Vacantmemoryaccess JMBOUTIFG(SYSSNIV) (1) JTAGmailbox UserNMI NMI NMIIFG,OFIFG,ACCVIFG,BUSIFG(SYSUNIV) Oscillatorfault (1) (2) (Non)maskable 0FFFAh 61 Flashmemoryaccessviolation Comp_B ComparatorBinterruptflags(CBIV) (1) (3) Maskable 0FFF8h 60 TB0 TB0CCR0CCIFG0 (3) Maskable 0FFF6h 59 TB0CCR1CCIFG1toTB0CCR6CCIFG6, TB0 TB0IFG(TB0IV) (1) (3) Maskable 0FFF4h 58 WatchdogTimer_Aintervaltimer WDTIFG Maskable 0FFF2h 57 mode USCI_A0receiveortransmit UCA0RXIFG,UCA0TXIFG(UCA0IV) (1) (3) Maskable 0FFF0h 56 USCI_B0receiveortransmit UCB0RXIFG,UCB0TXIFG(UCAB0IV) (1) (3) Maskable 0FFEEh 55 ADC10_A ADC10IFG0 (1) (3) (4) Maskable 0FFECh 54 TA0 TA0CCR0CCIFG0 (3) Maskable 0FFEAh 53 TA0CCR1CCIFG1toTA0CCR4CCIFG4, TA0 TA0IFG(TA0IV) (1) (3) Maskable 0FFE8h 52 LDO-PWR LDOOFFIG,LDOONIFG,LDOOVLIFG Maskable 0FFE6h 51 DMA DMA0IFG,DMA1IFG,DMA2IFG(DMAIV) (1) (3) Maskable 0FFE4h 50 TA1 TA1CCR0CCIFG0 (3) Maskable 0FFE2h 49 TA1CCR1CCIFG1toTA1CCR2CCIFG2, TA1 TA1IFG(TA1IV) (1) (3) Maskable 0FFE0h 48 I/OportP1 P1IFG.0toP1IFG.7(P1IV) (1) (3) Maskable 0FFDEh 47 USCI_A1receiveortransmit UCA1RXIFG,UCA1TXIFG(UCA1IV) (1) (3) Maskable 0FFDCh 46 USCI_B1receiveortransmit UCB1RXIFG,UCB1TXIFG(UCB1IV) (1) (3) Maskable 0FFDAh 45 TA2 TA2CCR0CCIFG0 (3) Maskable 0FFD8h 44 TA2CCR1CCIFG1toTA2CCR2CCIFG2, TA2 TA2IFG(TA2IV) (1) (3) Maskable 0FFD6h 43 I/OportP2 P2IFG.0toP2IFG.7(P2IV) (1) (3) Maskable 0FFD4h 42 RTCRDYIFG,RTCTEVIFG,RTCAIFG, RTC_A RT0PSIFG,RT1PSIFG(RTCIV) (1) (3) Maskable 0FFD2h 41 (1) Multiplesourceflags (2) AresetisgeneratediftheCPUtriestofetchinstructionsfromwithinperipheralspaceorvacantmemoryspace. (Non)maskable:theindividualinterruptenablebitcandisableaninterruptevent,butthegeneralinterruptenablebitcannotdisableit. (3) Interruptflagsareinthemodule. (4) OnlyondeviceswithADC,otherwisereserved. 44 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 Table6-1.InterruptSources,Flags,andVectors(continued) SYSTEM WORD INTERRUPTSOURCE INTERRUPTFLAG PRIORITY INTERRUPT ADDRESS 0FFD0h 40 Reserved Reserved (5) ⋮ ⋮ 0FF80h 0,lowest (5) Reservedinterruptvectorsataddressesarenotusedinthisdeviceandcanbeusedforregularprogramcodeifnecessary.Tomaintain compatibilitywithotherdevices,TIrecommendsreservingtheselocations. 6.4 Memory Organization Table6-2summarizesthememorymapforalldevicevariants. Table6-2.MemoryOrganization(1) MSP430F5304 MSP430F5308 MSP430F5309 MSP430F5310 Memory(flash) 8KB 16KB 24KB 32KB Main:interruptvector TotalSize 00FFFFhto00FF80h 00FFFFhto00FF80h 00FFFFhto00FF80h 00FFFFhto00FF80h Main:codememory 00FFFFhto00E000h 00FFFFhto00C000h 00FFFFhto00A000h 00FFFFhto008000h 2KB 2KB 2KB 2KB Sector1 0033FFhto002C00h 0033FFhto002C00h 0033FFhto002C00h 0033FFhto002C00h 2KB 2KB 2KB 2KB RAM Sector0 002BFFhto002400h 002BFFhto002400h 002BFFhto002400h 002BFFhto002400h 2KB 2KB 2KB 2KB Sector7 0023FFhto001C00h 0023FFhto001C00h 0023FFhto001C00h 0023FFhto001C00h 128B 128B 128B 128B InfoA 0019FFhto001980h 0019FFhto001980h 0019FFhto001980h 0019FFhto001980h 128B 128B 128B 128B InfoB Informationmemory 00197Fhto001900h 00197Fhto001900h 00197Fhto001900h 00197Fhto001900h (flash) 128B 128B 128B 128B InfoC 0018FFhto001880h 0018FFhto001880h 0018FFhto001880h 0018FFhto001880h 128B 128B 128B 128B InfoD 00187Fhto001800h 00187Fhto001800h 00187Fhto001800h 00187Fhto001800h 512B 512B 512B 512B BSL3 0017FFhto001600h 0017FFhto001600h 0017FFhto001600h 0017FFhto001600h 512B 512B 512B 512B BSL2 Bootloader(BSL) 0015FFhto001400h 0015FFhto001400h 0015FFhto001400h 0015FFhto001400h memory(flash) 512B 512B 512B 512B BSL1 0013FFhto001200h 0013FFhto001200h 0013FFhto001200h 0013FFhto001200h 512B 512B 512B 512B BSL0 0011FFhto001000h 0011FFhto001000h 0011FFhto001000h 0011FFhto001000h 4KB 4KB 4KB 4KB Peripherals Size 000FFFhto0h 000FFFhto0h 000FFFhto0h 000FFFhto0h (1) N/A=Notavailable Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 45 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 6.5 Bootloader (BSL) TheBSLenablesuserstoprogramtheflashmemoryorRAMusingaUARTserialinterface.Accesstothe device memory through the BSL is protected by user-defined password. Use of the UART BSL requires external access to six pins (see Table 6-3). For complete description of the features of the BSL and its implementation, see MSP430 Flash Device Bootloader (BSL) User's Guide. Table 6-3 lists the BSL pin requirements. Table6-3.BSLPinFunctions DEVICESIGNAL BSLFUNCTION RST/NMI/SBWTDIO Entrysequencesignal TEST/SBWTCK Entrysequencesignal P1.1 Datatransmit P1.2 Datareceive VCC Powersupply VSS Groundsupply 6.6 JTAG Operation 6.6.1 JTAG Standard Interface The MSP430 family supports the standard JTAG interface, which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430 development tools and device programmers. Table 6-4 lists the JTAG pin requirements. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the JTAG interface and its implementation,see MSP430ProgrammingWiththeJTAGInterface. Table6-4.JTAGPinRequirementsandFunctions DEVICESIGNAL DIRECTION FUNCTION PJ.3/TCK IN JTAGclockinput PJ.2/TMS IN JTAGstatecontrol PJ.1/TDI/TCLK IN JTAGdatainput,TCLKinput PJ.0/TDO OUT JTAGdataoutput TEST/SBWTCK IN EnableJTAGpins RST/NMI/SBWTDIO IN Externalreset VCC Powersupply VSS Groundsupply 6.6.2 Spy-Bi-Wire Interface In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 6-5 lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the JTAG interface and its implementation, see MSP430 ProgrammingWiththeJTAGInterface. 46 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 Table6-5.Spy-Bi-WirePinRequirementsandFunctions DEVICESIGNAL DIRECTION FUNCTION TEST/SBWTCK IN Spy-Bi-Wireclockinput RST/NMI/SBWTDIO IN,OUT Spy-Bi-Wiredatainputandoutput VCC Powersupply VSS Groundsupply 6.7 Flash Memory (Link to User's Guide) The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Featuresoftheflashmemoryinclude: • Flash memory has n segments of main memory and four segments of information memory (A to D) of 128byteseach.Eachsegmentinmainmemoryis512bytesinsize. • Segments0tonmaybeerasedinonestep,oreachsegmentmaybeindividuallyerased. • Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are alsocalledinformationmemory. • SegmentAcanbelockedseparately. 6.8 RAM (Link to User's Guide) The RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however,alldataarelost.FeaturesoftheRAMinclude: • RAMhasnsectors.SeeSection6.4 forthesizeofasector. • Eachsector0toncanbecompletelydisabled;however,dataretentionislost. • Eachsector0tonautomaticallyenterslowpowerretentionmodewhenpossible. 6.9 Peripherals Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be handled using all instructions. For complete module descriptions, see the MSP430F5xx and MSP430F6xx FamilyUser'sGuide. 6.9.1 Digital I/O (Link to User's Guide) Up to six 8-bit I/O ports are implemented: For 64-pin options, P1, P2, P4, and P6 are complete, P5 is reduced to 6-bit I/O, and P3 is reduced to 5-bit I/O. For 48-pin options, P6 is reduced to 4-bit I/O, P2 is reduced to 1-bit I/O, and P3 is completely removed. Port PJ contains four individual I/O ports, common to alldevices. • AllindividualI/Obitsareindependentlyprogrammable. • Anycombinationofinput,output,andinterruptconditionsispossible. • Pulluporpulldownonallportsisprogrammable. • Drivestrengthonallportsisprogrammable. • Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2. • Readandwriteaccesstoport-controlregistersissupportedbyallinstructions. • Portscanbeaccessedbyte-wise(P1throughP6)orword-wiseinpairs(PAthroughPC). Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 47 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 6.9.2 Port Mapping Controller (Link to User's Guide) The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4 (seeTable6-6).Table6-7 liststhedefaultsettingsforallpinsthatsupportportmapping. Table6-6.PortMappingMnemonicsandFunctions VALUE PxMAPyMNEMONIC INPUTPINFUNCTION OUTPUTPINFUNCTION 0 PM_NONE None DVSS PM_CBOUT0 – Comparator_Boutput 1 PM_TB0CLK TB0clockinput – PM_ADC10CLK – ADC10CLK 2 PM_DMAE0 DMAE0input – PM_SVMOUT – SVMoutput 3 PM_TB0OUTH TB0highimpedanceinputTB0OUTH – 4 PM_TB0CCR0A TB0CCR0captureinputCCI0A TB0CCR0compareoutputOut0 5 PM_TB0CCR1A TB0CCR1captureinputCCI1A TB0CCR1compareoutputOut1 6 PM_TB0CCR2A TB0CCR2captureinputCCI2A TB0CCR2compareoutputOut2 7 PM_TB0CCR3A TB0CCR3captureinputCCI3A TB0CCR3compareoutputOut3 8 PM_TB0CCR4A TB0CCR4captureinputCCI4A TB0CCR4compareoutputOut4 9 PM_TB0CCR5A TB0CCR5captureinputCCI5A TB0CCR5compareoutputOut5 10 PM_TB0CCR6A TB0CCR6captureinputCCI6A TB0CCR6compareoutputOut6 PM_UCA1RXD USCI_A1UARTRXD(DirectioncontrolledbyUSCI–input) 11 PM_UCA1SOMI USCI_A1SPIslaveoutmasterin(directioncontrolledbyUSCI) PM_UCA1TXD USCI_A1UARTTXD(DirectioncontrolledbyUSCI–output) 12 PM_UCA1SIMO USCI_A1SPIslaveinmasterout(directioncontrolledbyUSCI) PM_UCA1CLK USCI_A1clockinput/output(directioncontrolledbyUSCI) 13 PM_UCB1STE USCI_B1SPIslavetransmitenable(directioncontrolledbyUSCI) PM_UCB1SOMI USCI_B1SPIslaveoutmasterin(directioncontrolledbyUSCI) 14 PM_UCB1SCL USCI_B1I2Cclock(opendrainanddirectioncontrolledbyUSCI) PM_UCB1SIMO USCI_B1SPIslaveinmasterout(directioncontrolledbyUSCI) 15 PM_UCB1SDA USCI_B1I2Cdata(opendrainanddirectioncontrolledbyUSCI) PM_UCB1CLK USCI_B1clockinput/output(directioncontrolledbyUSCI) 16 PM_UCA1STE USCI_A1SPIslavetransmitenable(directioncontrolledbyUSCI) 17 PM_CBOUT1 None Comparator_Boutput 18 PM_MCLK None MCLK 19 PM_RTCCLK None RTCCLKoutput PM_UCA0RXD USCI_A0UARTRXD(DirectioncontrolledbyUSCI–input) 20 PM_UCA0SOMI USCI_A0SPIslaveoutmasterin(directioncontrolledbyUSCI) PM_UCA0TXD USCI_A0UARTTXD(DirectioncontrolledbyUSCI–output) 21 PM_UCA0SIMO USCI_A0SPIslaveinmasterout(directioncontrolledbyUSCI) PM_UCA0CLK USCI_A0clockinput/output(directioncontrolledbyUSCI) 22 PM_UCB0STE USCI_B0SPIslavetransmitenable(directioncontrolledbyUSCI) PM_UCB0SOMI USCI_B0SPIslaveoutmasterin(directioncontrolledbyUSCI) 23 PM_UCB0SCL USCI_B0I2Cclock(opendrainanddirectioncontrolledbyUSCI) PM_UCB0SIMO USCI_B0SPIslaveinmasterout(directioncontrolledbyUSCI) 24 PM_UCB0SDA USCI_B0I2Cdata(opendrainanddirectioncontrolledbyUSCI) PM_UCB0CLK USCI_B0clockinput/output(directioncontrolledbyUSCI) 25 PM_UCA0STE USCI_A0SPIslavetransmitenable(directioncontrolledbyUSCI) 26-30 Reserved None DVSS 48 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 Table6-6.PortMappingMnemonicsandFunctions(continued) VALUE PxMAPyMNEMONIC INPUTPINFUNCTION OUTPUTPINFUNCTION 31(0FFh)(1) PM_ANALOG DisablestheoutputdriveraswellastheinputSchmitt-triggertoprevent parasiticcrosscurrentswhenapplyinganalogsignals. (1) ThevalueofthePM_ANALOGmnemonicissetto0FFh.Theportmappingregistersare5bitswide,andtheupperbitsareignored, whichresultsinareadvalueof31. Table6-7.DefaultMapping PIN PxMAPyMNEMONIC INPUTPINFUNCTION OUTPUTPINFUNCTION USCI_B1SPIslavetransmitenable(directioncontrolledbyUSCI) P4.0/P4MAP0 PM_UCB1STE/PM_UCA1CLK USCI_A1clockinput/output(directioncontrolledbyUSCI) USCI_B1SPIslaveinmasterout(directioncontrolledbyUSCI) P4.1/P4MAP1 PM_UCB1SIMO/PM_UCB1SDA USCI_B1I2Cdata(opendrainanddirectioncontrolledbyUSCI) USCI_B1SPIslaveoutmasterin(directioncontrolledbyUSCI) P4.2/P4MAP2 PM_UCB1SOMI/PM_UCB1SCL USCI_B1I2Cclock(opendrainanddirectioncontrolledbyUSCI) USCI_A1SPIslavetransmitenable(directioncontrolledbyUSCI) P4.3/P4MAP3 PM_UCB1CLK/PM_UCA1STE USCI_B1clockinput/output(directioncontrolledbyUSCI) USCI_A1UARTTXD(DirectioncontrolledbyUSCI–output) P4.4/P4MAP4 PM_UCA1TXD/PM_UCA1SIMO USCI_A1SPIslaveinmasterout(directioncontrolledbyUSCI) USCI_A1UARTRXD(DirectioncontrolledbyUSCI–input) P4.5/P4MAP5 PM_UCA1RXD/PM_UCA1SOMI USCI_A1SPIslaveoutmasterin(directioncontrolledbyUSCI) P4.6/P4MAP6 PM_NONE None DVSS P4.7/P4MAP7 PM_NONE None DVSS 6.9.3 Oscillator and System Clock (Link to User's Guide) The clock system is supported by the Unified Clock System (UCS) module that includes support for a 32- kHz watch crystal oscillator (XT1 LF mode; XT1 HF mode not supported), an internal very low-power low- frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator (XT2). The UCS module is designedtomeettherequirementsofbothlowsystemcostandlowpowerconsumption.TheUCSmodule features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal DCO provides a fast turnon clock source and stabilizes in less than 5 µs. The UCS module providesthefollowingclocksignals: • Auxiliary clock (ACLK), sourced from a 32 kHz watch crystal (XT1), a high-frequency crystal (XT2), the internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitallycontrolledoscillator(DCO). • Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made availabletoACLK. • Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourcedbysamesourcesmadeavailabletoACLK. • ACLK/n,thebufferedoutputofACLK,ACLK/2,ACLK/4,ACLK/8,ACLK/16,ACLK/32. Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 49 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 6.9.4 Power-Management Module (PMM) (Link to User's Guide) The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, and brownout protection. The brownout circuit provides the proper internal reset signal to the device during power on and power off. The SVSandSVMcircuitrydetectsifthesupplyvoltagedropsbelowauser-selectablelevelandsupportsboth supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is notautomaticallyreset).SVSandSVMcircuitryisavailableontheprimarysupplyandcoresupply. 6.9.5 Hardware Multiplier (Link to User's Guide) The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication aswellassignedandunsignedmultiply-and-accumulateoperations. 6.9.6 Real-Time Clock (RTC_A) (Link to User's Guide) The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar mode integrates an internal calendar which compensates for months with less than 31 days and includes leap year correction. The RTC_A also supports flexible alarm functions and offset- calibrationhardware. 6.9.7 Watchdog Timer (WDT_A) (Link to User's Guide) The primary function of the WDT_A module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interruptsatselectedtimeintervals. 50 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 6.9.8 System Module (SYS) (Link to User's Guide) The SYS module handles many of the system functions within the device. These include power-on reset and power-up clear handling, NMI source selection and management, reset interrupt vector generators (see Table 6-8), bootloader entry mechanisms, and configuration management (device descriptors). The SYS module also includes a data exchange mechanism through JTAG called a JTAG mailbox that can be usedintheapplication. Table6-8.SystemModuleInterruptVectorRegisters INTERRUPTVECTORREGISTER ADDRESS INTERRUPTEVENT VALUE PRIORITY Nointerruptpending 00h Brownout(BOR) 02h Highest RST/NMI(POR) 04h PMMSWBOR(BOR) 06h WakeupfromLPMx.5 08h Securityviolation(BOR) 0Ah SVSL(POR) 0Ch SVSH(POR) 0Eh SVML_OVP(POR) 10h SYSRSTIV,SystemReset 019Eh SVMH_OVP(POR) 12h PMMSWPOR(POR) 14h WDTtime-out(PUC) 16h WDTpasswordviolation(PUC) 18h KEYVflashpasswordviolation(PUC) 1Ah Reserved 1Ch Peripheralareafetch(PUC) 1Eh PMMpasswordviolation(PUC) 20h Reserved 22hto3Eh Lowest Nointerruptpending 00h SVMLIFG 02h Highest SVMHIFG 04h SVSMLDLYIFG 06h SVSMHDLYIFG 08h SYSSNIV,SystemNMI 019Ch VMAIFG 0Ah JMBINIFG 0Ch JMBOUTIFG 0Eh SVMLVLRIFG 10h SVMHVLRIFG 12h Reserved 14hto1Eh Lowest Nointerruptpending 00h NMIIFG 02h Highest OFIFG 04h SYSUNIV,UserNMI 019Ah ACCVIFG 06h Reserved 08h Reserved 0Ahto1Eh Lowest Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 51 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 6.9.9 DMA Controller (Link to User's Guide) The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC10_A conversion register to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without havingtoawakentomovedatatoorfromaperipheral.Table6-9liststhetriggersforDMAtransfers. Table6-9.DMATriggerAssignments (1) CHANNEL TRIGGER 0 1 2 0 DMAREQ DMAREQ DMAREQ 1 TA0CCR0CCIFG TA0CCR0CCIFG TA0CCR0CCIFG 2 TA0CCR2CCIFG TA0CCR2CCIFG TA0CCR2CCIFG 3 TA1CCR0CCIFG TA1CCR0CCIFG TA1CCR0CCIFG 4 TA1CCR2CCIFG TA1CCR2CCIFG TA1CCR2CCIFG 5 TA2CCR0CCIFG TA2CCR0CCIFG TA2CCR0CCIFG 6 TA2CCR2CCIFG TA2CCR2CCIFG TA2CCR2CCIFG 7 TB0CCR0CCIFG TB0CCR0CCIFG TB0CCR0CCIFG 8 TB0CCR2CCIFG TB0CCR2CCIFG TB0CCR2CCIFG 9 Reserved Reserved Reserved 10 Reserved Reserved Reserved 11 Reserved Reserved Reserved 12 Reserved Reserved Reserved 13 Reserved Reserved Reserved 14 Reserved Reserved Reserved 15 Reserved Reserved Reserved 16 UCA0RXIFG UCA0RXIFG UCA0RXIFG 17 UCA0TXIFG UCA0TXIFG UCA0TXIFG 18 UCB0RXIFG UCB0RXIFG UCB0RXIFG 19 UCB0TXIFG UCB0TXIFG UCB0TXIFG 20 UCA1RXIFG UCA1RXIFG UCA1RXIFG 21 UCA1TXIFG UCA1TXIFG UCA1TXIFG 22 UCB1RXIFG UCB1RXIFG UCB1RXIFG 23 UCB1TXIFG UCB1TXIFG UCB1TXIFG 24 ADC10IFG0 (2) ADC10IFG0 (2) ADC10IFG0 (2) 25 Reserved Reserved Reserved 26 Reserved Reserved Reserved 27 reserved reserved reserved 28 reserved reserved reserved 29 MPYready MPYready MPYready 30 DMA2IFG DMA0IFG DMA1IFG 31 DMAE0 DMAE0 DMAE0 (1) Ifareservedtriggersourceisselected,notriggerisgenerated. (2) OnlyondeviceswithADC.ReservedondeviceswithoutADC. 52 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 6.9.10 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode) The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3- or 4-pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baud-rate detection, and IrDA. Each USCI module containstwoportions,AandB. TheUSCI_AnmoduleprovidessupportforSPI(3-or4-pin),UART,enhancedUART,orIrDA. TheUSCI_BnmoduleprovidessupportforSPI(3-or4-pin)orI2C. TheMSP430F53xxseriesincludesoneortwocompleteUSCImodules. 6.9.11 TA0 (Link to User's Guide) TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-10). TA0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compareregisters. Table6-10.TA0SignalConnections INPUTPINNUMBER DEVICE MODULE MODULE DEVICE OUTPUTPINNUMBER MODULE INPUT INPUT OUTPUT OUTPUT RGC,ZQE RGZ,PT SIGNAL SIGNAL BLOCK SIGNAL SIGNAL RGC,ZQE RGZ,PT 18,H2-P1.0 14-P1.0 TA0CLK TACLK ACLK ACLK (internal) Timer NA NA SMCLK SMCLK (internal) 18,H2-P1.0 14-P1.0 TA0CLK TACLK 19,H3-P1.1 15-P1.1 TA0.0 CCI0A 19,H3-P1.1 15-P1.1 DV CCI0B SS CCR0 TA0 TA0.0 DV GND SS DV V CC CC 20,J3-P1.2 16-P1.2 TA0.1 CCI1A 20,J3-P1.2 16-P1.2 ADC10(internal) ADC10(internal) CBOUT (1) (1) CCI1B (internal) CCR1 TA1 TA0.1 ADC10SHSx= ADC10SHSx= {1} {1} DV GND SS DV V CC CC 21,G4-P1.3 17-P1.3 TA0.2 CCI2A 21,G4-P1.3 17-P1.3 ACLK CCI2B (internal) CCR2 TA2 TA0.2 DV GND SS DV V CC CC 22,H4-P1.4 18-P1.4 TA0.3 CCI3A 22,H4-P1.4 18-P1.4 DV CCI3B SS CCR3 TA3 TA0.3 DV GND SS DV V CC CC 23,J4-P1.5 19-P1.5 TA0.4 CCI4A 23,J4-P1.5 19-P1.5 DV CCI4B SS CCR4 TA4 TA0.4 DV GND SS DV V CC CC (1) OnlyondeviceswithADC. Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 53 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 6.9.12 TA1 (Link to User's Guide) TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-11). TA1 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each ofthecapture/compareregisters. Table6-11.TA1SignalConnections INPUTPINNUMBER DEVICE MODULE MODULE DEVICE OUTPUTPINNUMBER MODULE INPUT INPUT OUTPUT OUTPUT RGC,ZQE RGZ,PT SIGNAL SIGNAL BLOCK SIGNAL SIGNAL RGC,ZQE RGZ,PT 24,G5-P1.6 20-P1.6 TA1CLK TACLK ACLK ACLK (internal) Timer NA NA SMCLK SMCLK (internal) 24,G5-P1.6 20-P1.6 TA1CLK TACLK 25,H5-P1.7 21-P1.7 TA1.0 CCI0A 25,H5-P1.7 21-P1.7 DV CCI0B SS CCR0 TA0 TA1.0 DV GND SS DV V CC CC 26,J5-P2.0 22-P2.0 TA1.1 CCI1A 26,J5-P2.0 22-P2.0 CBOUT CCI1B (internal) CCR1 TA1 TA1.1 DV GND SS DV V CC CC 27,G6-P2.1 TA1.2 CCI2A 27,G6-P2.1 ACLK CCI2B (internal) CCR2 TA2 TA1.2 DV GND SS DV V CC CC 54 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 6.9.13 TA2 (Link to User's Guide) TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA2 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-12). TA2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each ofthecapture/compareregisters. Table6-12.TA2SignalConnections INPUTPINNUMBER DEVICE MODULE MODULE DEVICE OUTPUTPINNUMBER MODULE INPUT INPUT OUTPUT OUTPUT RGC,ZQE RGZ,PT SIGNAL SIGNAL BLOCK SIGNAL SIGNAL RGC,ZQE RGZ,PT 28,J6-P2.2 TA2CLK TACLK ACLK ACLK (internal) Timer NA NA SMCLK SMCLK (internal) 28,J6-P2.2 TA2CLK TACLK 29,H6-P2.3 TA2.0 CCI0A 29,H6-P2.3 DV CCI0B SS CCR0 TA0 TA2.0 DV GND SS DV V CC CC 30,J7-P2.4 TA2.1 CCI1A 30,J7-P2.4 CBOUT CCI1B (internal) CCR1 TA1 TA2.1 DV GND SS DV V CC CC 31,J8-P2.5 TA2.2 CCI2A 31,J8-P2.5 ACLK CCI2B (internal) CCR2 TA2 TA2.2 DV GND SS DV V CC CC Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 55 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 6.9.14 TB0 (Link to User's Guide) TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-13). TB0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each ofthecapture/compareregisters. Table6-13.TB0SignalConnections INPUTPINNUMBER DEVICE MODULE MODULE DEVICE OUTPUTPINNUMBER MODULE INPUT INPUT OUTPUT OUTPUT RGC,ZQE(1) RGZ,PT(1) SIGNAL SIGNAL BLOCK SIGNAL SIGNAL RGC,ZQE(1) RGZ,PT(1) TB0CLK TBCLK ACLK ACLK (internal) Timer NA NA SMCLK SMCLK (internal) TB0CLK TBCLK ADC10 ADC10 (internal)(2) (internal)(2) TB0.0 CCI0A ADC10SHSx= ADC10SHSx= {2} {2} CCR0 TB0 TB0.0 TB0.0 CCI0B DV GND SS DV V CC CC ADC10(internal) ADC10(internal) TB0.1 CCI1A ADC10SHSx= ADC10SHSx= {3} {3} CBOUT CCI1B CCR1 TB1 TB0.1 (internal) DV GND SS DV V CC CC TB0.2 CCI2A TB0.2 CCI2B CCR2 TB2 TB0.2 DV GND SS DV V CC CC TB0.3 CCI3A TB0.3 CCI3B CCR3 TB3 TB0.3 DV GND SS DV V CC CC TB0.4 CCI4A TB0.4 CCI4B CCR4 TB4 TB0.4 DV GND SS DV V CC CC TB0.5 CCI5A TB0.5 CCI5B CCR5 TB5 TB0.5 DV GND SS DV V CC CC TB0.6 CCI6A ACLK CCI6B (internal) CCR6 TB6 TB0.6 DV GND SS DV V CC CC (1) Timerfunctionsselectablebytheportmappingcontroller. (2) OnlyondeviceswithADC. 56 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 6.9.15 Comparator_B (Link to User's Guide) The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,batteryvoltagesupervision,andmonitoringofexternalanalogsignals. 6.9.16 ADC10_A (Link to User's Guide) The ADC10_A module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and a conversion result buffer. A window comparator with lower and upper limits allows CPU-independent result monitoring with three window comparatorinterruptflags. 6.9.17 CRC16 (Link to User's Guide) The CRC16 module produces a signature based on a sequence of entered data values and can be used fordatacheckingpurposes.TheCRC16modulesignatureisbasedontheCRC-CCITTstandard. 6.9.18 Reference (REF) Module Voltage Reference (Link to User's Guide) TheREFgeneratesallcriticalreferencevoltagesthatcanbeusedbythevariousanalogperipheralsinthe device. 6.9.19 LDO and Port U The integrated 3.3-V power system incorporates an integrated 3.3-V LDO regulator that allows the entire microcontroller to be powered from nominal 5-V LDOI when it is made available for the system. Alternatively, the power system can supply power only to other components within the system, or it can be unused altogether. The Port U Pins (PU.0 and PU.1) function as general-purpose high-current I/O pins. These pins must be configured together as either both inputs or both outputs. Port U is supplied by the LDOO rail. If the 3.3-V LDO is not being used in the system (disabled), the LDOO pin can be supplied externally. 6.9.20 Embedded Emulation Module (EEM) (S Version) (Link to User's Guide) TheEEMsupportsreal-timein-systemdebugging.TheSversionoftheEEMhasthefollowingfeatures: • Threehardwaretriggersorbreakpointsonmemoryaccess • OnehardwaretriggerorbreakpointonCPUregisterwriteaccess • Uptofourhardwaretriggerscanbecombinedtoformcomplextriggersorbreakpoints • Onecyclecounter • Clockcontrolonmodulelevel Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 57 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 6.10 Peripheral File Map Table6-14liststheregisterbaseaddressforallsupportedperipherals. Table6-14.Peripherals OFFSETADDRESS MODULENAME BASEADDRESS RANGE SpecialFunctions(seeTable6-15) 0100h 000hto01Fh PMM(seeTable6-16) 0120h 000hto01Fh FlashControl(seeTable6-17) 0140h 000hto00Fh CRC16(seeTable6-18) 0150h 000hto007h RAMControl(seeTable6-19) 0158h 000hto001h Watchdog(seeTable6-20) 015Ch 000hto001h UCS(seeTable6-21) 0160h 000hto01Fh SYS(seeTable6-22) 0180h 000hto01Fh SharedReference(seeTable6-23) 01B0h 000hto001h PortMappingControl(seeTable6-24) 01C0h 000hto002h PortMappingPortP4(seeTable6-24) 01E0h 000hto007h PortP1,P2(seeTable6-25) 0200h 000hto01Fh PortP3,P4(seeTable6-26) 0220h 000hto00Bh PortP5,P6(seeTable6-27) 0240h 000hto00Bh PortPJ(seeTable6-28) 0320h 000hto01Fh TA0(seeTable6-29) 0340h 000hto02Eh TA1(seeTable6-30) 0380h 000hto02Eh TB0(seeTable6-31) 03C0h 000hto02Eh TA2(seeTable6-32) 0400h 000hto02Eh Real-TimeClock(RTC_A)(seeTable6-33) 04A0h 000hto01Bh 32-BitHardwareMultiplier(seeTable6-34) 04C0h 000hto02Fh DMAGeneralControl(seeTable6-35) 0500h 000hto00Fh DMAChannel0(seeTable6-35) 0510h 000hto00Ah DMAChannel1(seeTable6-35) 0520h 000hto00Ah DMAChannel2(seeTable6-35) 0530h 000hto00Ah USCI_A0(seeTable6-36) 05C0h 000hto01Fh USCI_B0(seeTable6-37) 05E0h 000hto01Fh USCI_A1(seeTable6-38) 0600h 000hto01Fh USCI_B1(seeTable6-39) 0620h 000hto01Fh ADC10_A(seeTable6-40) 0740h 000hto01Fh Comparator_B(seeTable6-41) 08C0h 000hto00Fh LDO-PWRandPortUConfiguration 0900h 000hto014h (seeTable6-42) 58 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 Table6-15.SpecialFunctionRegisters(BaseAddress:0100h) REGISTERDESCRIPTION REGISTER OFFSET SFRinterruptenable SFRIE1 00h SFRinterruptflag SFRIFG1 02h SFRresetpincontrol SFRRPCR 04h Table6-16.PMMRegisters(BaseAddress:0120h) REGISTERDESCRIPTION REGISTER OFFSET PMMcontrol0 PMMCTL0 00h PMMcontrol1 PMMCTL1 02h SVShigh-sidecontrol SVSMHCTL 04h SVSlow-sidecontrol SVSMLCTL 06h PMMinterruptflags PMMIFG 0Ch PMMinterruptenable PMMIE 0Eh PMMpowermode5control PM5CTL0 10h Table6-17.FlashControlRegisters(BaseAddress:0140h) REGISTERDESCRIPTION REGISTER OFFSET Flashcontrol1 FCTL1 00h Flashcontrol3 FCTL3 04h Flashcontrol4 FCTL4 06h Table6-18.CRC16Registers(BaseAddress:0150h) REGISTERDESCRIPTION REGISTER OFFSET CRCdatainput CRC16DI 00h CRCdatainputreversebyte CRCDIRB 02h CRCinitializationandresult CRCINIRES 04h CRCresultreversebyte CRCRESR 06h Table6-19.RAMControlRegisters(BaseAddress:0158h) REGISTERDESCRIPTION REGISTER OFFSET RAMcontrol0 RCCTL0 00h Table6-20.WatchdogRegisters(BaseAddress:015Ch) REGISTERDESCRIPTION REGISTER OFFSET Watchdogtimercontrol WDTCTL 00h Table6-21.UCSRegisters(BaseAddress:0160h) REGISTERDESCRIPTION REGISTER OFFSET UCScontrol0 UCSCTL0 00h UCScontrol1 UCSCTL1 02h UCScontrol2 UCSCTL2 04h UCScontrol3 UCSCTL3 06h UCScontrol4 UCSCTL4 08h UCScontrol5 UCSCTL5 0Ah UCScontrol6 UCSCTL6 0Ch UCScontrol7 UCSCTL7 0Eh Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 59 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com Table6-21.UCSRegisters(BaseAddress:0160h)(continued) REGISTERDESCRIPTION REGISTER OFFSET UCScontrol8 UCSCTL8 10h Table6-22.SYSRegisters(BaseAddress:0180h) REGISTERDESCRIPTION REGISTER OFFSET Systemcontrol SYSCTL 00h Bootloaderconfigurationarea SYSBSLC 02h JTAGmailboxcontrol SYSJMBC 06h JTAGmailboxinput0 SYSJMBI0 08h JTAGmailboxinput1 SYSJMBI1 0Ah JTAGmailboxoutput0 SYSJMBO0 0Ch JTAGmailboxoutput1 SYSJMBO1 0Eh Buserrorvectorgenerator SYSBERRIV 18h UserNMIvectorgenerator SYSUNIV 1Ah SystemNMIvectorgenerator SYSSNIV 1Ch Resetvectorgenerator SYSRSTIV 1Eh Table6-23.SharedReferenceRegisters(BaseAddress:01B0h) REGISTERDESCRIPTION REGISTER OFFSET Sharedreferencecontrol REFCTL 00h Table6-24.PortMappingRegisters (BaseAddressofPortMappingControl:01C0h,PortP4:01E0h) REGISTERDESCRIPTION REGISTER OFFSET Portmappingpassword PMAPPWD 00h Portmappingcontrol PMAPCTL 02h PortP4.0mapping P4MAP0 00h PortP4.1mapping P4MAP1 01h PortP4.2mapping P4MAP2 02h PortP4.3mapping P4MAP3 03h PortP4.4mapping P4MAP4 04h PortP4.5mapping P4MAP5 05h PortP4.6mapping P4MAP6 06h PortP4.7mapping P4MAP7 07h 60 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 Table6-25.PortP1,P2Registers(BaseAddress:0200h) REGISTERDESCRIPTION REGISTER OFFSET PortP1input P1IN 00h PortP1output P1OUT 02h PortP1direction P1DIR 04h PortP1resistorenable P1REN 06h PortP1drivestrength P1DS 08h PortP1selection P1SEL 0Ah PortP1interruptvectorword P1IV 0Eh PortP1interruptedgeselect P1IES 18h PortP1interruptenable P1IE 1Ah PortP1interruptflag P1IFG 1Ch PortP2input P2IN 01h PortP2output P2OUT 03h PortP2direction P2DIR 05h PortP2resistorenable P2REN 07h PortP2drivestrength P2DS 09h PortP2selection P2SEL 0Bh PortP2interruptvectorword P2IV 1Eh PortP2interruptedgeselect P2IES 19h PortP2interruptenable P2IE 1Bh PortP2interruptflag P2IFG 1Dh Table6-26.PortP3,P4Registers(BaseAddress:0220h) REGISTERDESCRIPTION REGISTER OFFSET PortP3input P3IN 00h PortP3output P3OUT 02h PortP3direction P3DIR 04h PortP3resistorenable P3REN 06h PortP3drivestrength P3DS 08h PortP3selection P3SEL 0Ah PortP4input P4IN 01h PortP4output P4OUT 03h PortP4direction P4DIR 05h PortP4resistorenable P4REN 07h PortP4drivestrength P4DS 09h PortP4selection P4SEL 0Bh Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 61 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com Table6-27.PortP5,P6Registers(BaseAddress:0240h) REGISTERDESCRIPTION REGISTER OFFSET PortP5input P5IN 00h PortP5output P5OUT 02h PortP5direction P5DIR 04h PortP5resistorenable P5REN 06h PortP5drivestrength P5DS 08h PortP5selection P5SEL 0Ah PortP6input P6IN 01h PortP6output P6OUT 03h PortP6direction P6DIR 05h PortP6resistorenable P6REN 07h PortP6drivestrength P6DS 09h PortP6selection P6SEL 0Bh Table6-28.PortJRegisters(BaseAddress:0320h) REGISTERDESCRIPTION REGISTER OFFSET PortPJinput PJIN 00h PortPJoutput PJOUT 02h PortPJdirection PJDIR 04h PortPJresistorenable PJREN 06h PortPJdrivestrength PJDS 08h Table6-29.TA0Registers(BaseAddress:0340h) REGISTERDESCRIPTION REGISTER OFFSET TA0control TA0CTL 00h Capture/comparecontrol0 TA0CCTL0 02h Capture/comparecontrol1 TA0CCTL1 04h Capture/comparecontrol2 TA0CCTL2 06h Capture/comparecontrol3 TA0CCTL3 08h Capture/comparecontrol4 TA0CCTL4 0Ah TA0counter TA0R 10h Capture/compare0 TA0CCR0 12h Capture/compare1 TA0CCR1 14h Capture/compare2 TA0CCR2 16h Capture/compare3 TA0CCR3 18h Capture/compare4 TA0CCR4 1Ah TA0expansion0 TA0EX0 20h TA0interruptvector TA0IV 2Eh 62 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 Table6-30.TA1Registers(BaseAddress:0380h) REGISTERDESCRIPTION REGISTER OFFSET TA1control TA1CTL 00h Capture/comparecontrol0 TA1CCTL0 02h Capture/comparecontrol1 TA1CCTL1 04h Capture/comparecontrol2 TA1CCTL2 06h TA1counter TA1R 10h Capture/compare0 TA1CCR0 12h Capture/compare1 TA1CCR1 14h Capture/compare2 TA1CCR2 16h TA1expansion0 TA1EX0 20h TA1interruptvector TA1IV 2Eh Table6-31.TB0Registers(BaseAddress:03C0h) REGISTERDESCRIPTION REGISTER OFFSET TB0control TB0CTL 00h Capture/comparecontrol0 TB0CCTL0 02h Capture/comparecontrol1 TB0CCTL1 04h Capture/comparecontrol2 TB0CCTL2 06h Capture/comparecontrol3 TB0CCTL3 08h Capture/comparecontrol4 TB0CCTL4 0Ah Capture/comparecontrol5 TB0CCTL5 0Ch Capture/comparecontrol6 TB0CCTL6 0Eh TB0counter TB0R 10h Capture/compare0 TB0CCR0 12h Capture/compare1 TB0CCR1 14h Capture/compare2 TB0CCR2 16h Capture/compare3 TB0CCR3 18h Capture/compare4 TB0CCR4 1Ah Capture/compare5 TB0CCR5 1Ch Capture/compare6 TB0CCR6 1Eh TB0expansion0 TB0EX0 20h TB0interruptvector TB0IV 2Eh Table6-32.TA2Registers(BaseAddress:0400h) REGISTERDESCRIPTION REGISTER OFFSET TA2control TA2CTL 00h Capture/comparecontrol0 TA2CCTL0 02h Capture/comparecontrol1 TA2CCTL1 04h Capture/comparecontrol2 TA2CCTL2 06h TA2counter TA2R 10h Capture/compare0 TA2CCR0 12h Capture/compare1 TA2CCR1 14h Capture/compare2 TA2CCR2 16h TA2expansion0 TA2EX0 20h TA2interruptvector TA2IV 2Eh Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 63 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com Table6-33.Real-TimeClockRegisters(BaseAddress:04A0h) REGISTERDESCRIPTION REGISTER OFFSET RTCcontrol0 RTCCTL0 00h RTCcontrol1 RTCCTL1 01h RTCcontrol2 RTCCTL2 02h RTCcontrol3 RTCCTL3 03h RTCprescaler0control RTCPS0CTL 08h RTCprescaler1control RTCPS1CTL 0Ah RTCprescaler0 RTCPS0 0Ch RTCprescaler1 RTCPS1 0Dh RTCinterruptvectorword RTCIV 0Eh RTCseconds/counter1 RTCSEC/RTCNT1 10h RTCminutes/counter2 RTCMIN/RTCNT2 11h RTChours/counter3 RTCHOUR/RTCNT3 12h RTCdayofweek/counter4 RTCDOW/RTCNT4 13h RTCdays RTCDAY 14h RTCmonth RTCMON 15h RTCyearlow RTCYEARL 16h RTCyearhigh RTCYEARH 17h RTCalarmminutes RTCAMIN 18h RTCalarmhours RTCAHOUR 19h RTCalarmdayofweek RTCADOW 1Ah RTCalarmdays RTCADAY 1Bh 64 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 Table6-34.32-BitHardwareMultiplierRegisters(BaseAddress:04C0h) REGISTERDESCRIPTION REGISTER OFFSET 16-bitoperand1–multiply MPY 00h 16-bitoperand1–signedmultiply MPYS 02h 16-bitoperand1–multiplyaccumulate MAC 04h 16-bitoperand1–signedmultiplyaccumulate MACS 06h 16-bitoperand2 OP2 08h 16×16resultlowword RESLO 0Ah 16×16resulthighword RESHI 0Ch 16×16sumextension SUMEXT 0Eh 32-bitoperand1–multiplylowword MPY32L 10h 32-bitoperand1–multiplyhighword MPY32H 12h 32-bitoperand1–signedmultiplylowword MPYS32L 14h 32-bitoperand1–signedmultiplyhighword MPYS32H 16h 32-bitoperand1–multiplyaccumulatelowword MAC32L 18h 32-bitoperand1–multiplyaccumulatehighword MAC32H 1Ah 32-bitoperand1–signedmultiplyaccumulatelowword MACS32L 1Ch 32-bitoperand1–signedmultiplyaccumulatehighword MACS32H 1Eh 32-bitoperand2–lowword OP2L 20h 32-bitoperand2–highword OP2H 22h 32×32result0–leastsignificantword RES0 24h 32×32result1 RES1 26h 32×32result2 RES2 28h 32×32result3–mostsignificantword RES3 2Ah MPY32control0 MPY32CTL0 2Ch Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 65 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com Table6-35.DMARegisters(BaseAddressDMAGeneralControl:0500h, DMAChannel0:0510h,DMAChannel1:0520h,DMAChannel2:0530h) REGISTERDESCRIPTION REGISTER OFFSET DMAchannel0control DMA0CTL 00h DMAchannel0sourceaddresslow DMA0SAL 02h DMAchannel0sourceaddresshigh DMA0SAH 04h DMAchannel0destinationaddresslow DMA0DAL 06h DMAchannel0destinationaddresshigh DMA0DAH 08h DMAchannel0transfersize DMA0SZ 0Ah DMAchannel1control DMA1CTL 00h DMAchannel1sourceaddresslow DMA1SAL 02h DMAchannel1sourceaddresshigh DMA1SAH 04h DMAchannel1destinationaddresslow DMA1DAL 06h DMAchannel1destinationaddresshigh DMA1DAH 08h DMAchannel1transfersize DMA1SZ 0Ah DMAchannel2control DMA2CTL 00h DMAchannel2sourceaddresslow DMA2SAL 02h DMAchannel2sourceaddresshigh DMA2SAH 04h DMAchannel2destinationaddresslow DMA2DAL 06h DMAchannel2destinationaddresshigh DMA2DAH 08h DMAchannel2transfersize DMA2SZ 0Ah DMAmodulecontrol0 DMACTL0 00h DMAmodulecontrol1 DMACTL1 02h DMAmodulecontrol2 DMACTL2 04h DMAmodulecontrol3 DMACTL3 06h DMAmodulecontrol4 DMACTL4 08h DMAinterruptvector DMAIV 0Ah Table6-36.USCI_A0Registers(BaseAddress:05C0h) REGISTERDESCRIPTION REGISTER OFFSET USCIcontrol1 UCA0CTL1 00h USCIcontrol0 UCA0CTL0 01h USCIbaudrate0 UCA0BR0 06h USCIbaudrate1 UCA0BR1 07h USCImodulationcontrol UCA0MCTL 08h USCIstatus UCA0STAT 0Ah USCIreceivebuffer UCA0RXBUF 0Ch USCItransmitbuffer UCA0TXBUF 0Eh USCILINcontrol UCA0ABCTL 10h USCIIrDAtransmitcontrol UCA0IRTCTL 12h USCIIrDAreceivecontrol UCA0IRRCTL 13h USCIinterruptenable UCA0IE 1Ch USCIinterruptflags UCA0IFG 1Dh USCIinterruptvectorword UCA0IV 1Eh 66 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 Table6-37.USCI_B0Registers(BaseAddress:05E0h) REGISTERDESCRIPTION REGISTER OFFSET USCIsynchronouscontrol1 UCB0CTL1 00h USCIsynchronouscontrol0 UCB0CTL0 01h USCIsynchronousbitrate0 UCB0BR0 06h USCIsynchronousbitrate1 UCB0BR1 07h USCIsynchronousstatus UCB0STAT 0Ah USCIsynchronousreceivebuffer UCB0RXBUF 0Ch USCIsynchronoustransmitbuffer UCB0TXBUF 0Eh USCII2Cownaddress UCB0I2COA 10h USCII2Cslaveaddress UCB0I2CSA 12h USCIinterruptenable UCB0IE 1Ch USCIinterruptflags UCB0IFG 1Dh USCIinterruptvectorword UCB0IV 1Eh Table6-38.USCI_A1Registers(BaseAddress:0600h) REGISTERDESCRIPTION REGISTER OFFSET USCIcontrol1 UCA1CTL1 00h USCIcontrol0 UCA1CTL0 01h USCIbaudrate0 UCA1BR0 06h USCIbaudrate1 UCA1BR1 07h USCImodulationcontrol UCA1MCTL 08h USCIstatus UCA1STAT 0Ah USCIreceivebuffer UCA1RXBUF 0Ch USCItransmitbuffer UCA1TXBUF 0Eh USCILINcontrol UCA1ABCTL 10h USCIIrDAtransmitcontrol UCA1IRTCTL 12h USCIIrDAreceivecontrol UCA1IRRCTL 13h USCIinterruptenable UCA1IE 1Ch USCIinterruptflags UCA1IFG 1Dh USCIinterruptvectorword UCA1IV 1Eh Table6-39.USCI_B1Registers(BaseAddress:0620h) REGISTERDESCRIPTION REGISTER OFFSET USCIsynchronouscontrol1 UCB1CTL1 00h USCIsynchronouscontrol0 UCB1CTL0 01h USCIsynchronousbitrate0 UCB1BR0 06h USCIsynchronousbitrate1 UCB1BR1 07h USCIsynchronousstatus UCB1STAT 0Ah USCIsynchronousreceivebuffer UCB1RXBUF 0Ch USCIsynchronoustransmitbuffer UCB1TXBUF 0Eh USCII2Cownaddress UCB1I2COA 10h USCII2Cslaveaddress UCB1I2CSA 12h USCIinterruptenable UCB1IE 1Ch USCIinterruptflags UCB1IFG 1Dh USCIinterruptvectorword UCB1IV 1Eh Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 67 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com Table6-40.ADC10_ARegisters(BaseAddress:0740h) REGISTERDESCRIPTION REGISTER OFFSET ADC10_Acontrol0 ADC10CTL0 00h ADC10_Acontrol1 ADC10CTL1 02h ADC10_Acontrol2 ADC10CTL2 04h ADC10_Awindowcomparatorlowthreshold ADC10LO 06h ADC10_Awindowcomparatorhighthreshold ADC10HI 08h ADC10_Amemorycontrol0 ADC10MCTL0 0Ah ADC10_Aconversionmemory ADC10MEM0 12h ADC10_Ainterruptenable ADC10IE 1Ah ADC10_Ainterruptflags ADC10IGH 1Ch ADC10_Ainterruptvectorword ADC10IV 1Eh Table6-41.Comparator_BRegisters(BaseAddress:08C0h) REGISTERDESCRIPTION REGISTER OFFSET Comp_Bcontrol0 CBCTL0 00h Comp_Bcontrol1 CBCTL1 02h Comp_Bcontrol2 CBCTL2 04h Comp_Bcontrol3 CBCTL3 06h Comp_Binterrupt CBINT 0Ch Comp_Binterruptvectorword CBIV 0Eh Table6-42.LDOandPortUConfigurationRegisters(BaseAddress:0900h) REGISTERDESCRIPTION REGISTER OFFSET LDOkey/ID LDOKEYPID 00h PUportcontrol PUCTL 04h LDOpowercontrol LDOPWRCTL 08h 68 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 6.11 Input/Output Diagrams 6.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger Figure6-2showstheportdiagram.Table6-43 summarizestheselectionofthepinfunctions. Pad Logic P1REN.x DV 0 SS DV 1 1 CC P1DIR.x 0 Direction From module 1 0: Input 1: Output P1OUT.x 0 From module 1 P1.0/TA0CLK/ACLK P1DS.x P1.1/TA0.0 P1SEL.x 0: Low drive P1.2/TA0.1 1: High drive P1.3/TA0.2 P1IN.x P1.4/TA0.3 P1.5/TA0.4 P1.6/TA1CLK/CBOUT EN P1.7/TA1.0 To module D P1IE.x EN P1IRQ.x Q P1IFG.x Set P1SEL.x Interrupt Edge P1IES.x Select Figure6-2.PortP1(P1.0toP1.7)Diagram Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 69 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com Table6-43.PortP1(P1.0toP1.7)PinFunctions CONTROLBITSORSIGNALS PINNAME(P1.x) x FUNCTION P1DIR.x P1SEL.x P1.0(I/O) I:0;O:1 0 P1.0/TA0CLK/ACLK 0 TA0CLK 0 1 ACLK 1 1 P1.1(I/O) I:0;O:1 0 P1.1/TA0.0 1 TA0.CCI0A 0 1 TA0.0 1 1 P1.2(I/O) I:0;O:1 0 P1.2/TA0.1 2 TA0.CCI1A 0 1 TA0.1 1 1 P1.3(I/O) I:0;O:1 0 P1.3/TA0.2 3 TA0.CCI2A 0 1 TA0.2 1 1 P1.4(I/O) I:0;O:1 0 P1.4/TA0.3 4 TA0.CCI3A 0 1 TA0.3 1 1 P1.5(I/O) I:0;O:1 0 P1.5/TA0.4 5 TA0.CCI4A 0 1 TA0.4 1 1 P1.6(I/O) I:0;O:1 0 P1.6/TA1CLK/CBOUT 6 TA1CLK 0 1 CBOUTcomparatorB 1 1 P1.7(I/O) I:0;O:1 0 P1.7/TA1.0 7 TA1.CCI0A 0 1 TA1.0 1 1 70 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 6.11.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger Figure6-3showstheportdiagram.Table6-44 summarizestheselectionofthepinfunctions. Pad Logic P2REN.x DV 0 SS DV 1 1 CC P2DIR.x 0 Direction From module 1 0: Input 1: Output P2OUT.x 0 From module 1 P2.0/TA1.1 P2DS.x P2.1/TA1.2 P2SEL.x 0: Low drive P2.2/TA2CLK/SMCLK 1: High drive P2.3/TA2.0 P2IN.x P2.4/TA2.1 P2.5/TA2.2 P2.6/RTCCLK/DMAE0 EN P2.7/UB0STE/UCA0CLK To module D P2IE.x EN To module Q P2IFG.x Set P2SEL.x Interrupt Edge P2IES.x Select Figure6-3.PortP2(P2.0toP2.7)Diagram Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 71 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com Table6-44.PortP2(P2.0toP2.7)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P2.x) x FUNCTION P2DIR.x P2SEL.x P2.0(I/O) I:0;O:1 0 P2.0/TA1.1 0 TA1.CCI1A 0 1 TA1.1 1 1 P2.1(I/O) I:0;O:1 0 P2.1/TA1.2 1 TA1.CCI2A 0 1 TA1.2 1 1 P2.2(I/O) I:0;O:1 0 P2.2/TA2CLK/SMCLK 2 TA2CLK 0 1 SMCLK 1 1 P2.3(I/O) I:0;O:1 0 P2.3/TA2.0 3 TA2.CCI0A 0 1 TA2.0 1 1 P2.4(I/O) I:0;O:1 0 P2.4/TA2.1 4 TA2.CCI1A 0 1 TA2.1 1 1 P2.5(I/O) I:0;O:1 0 P2.5/TA2.2 5 TA2.CCI2A 0 1 TA2.2 1 1 P2.6(I/O) I:0;O:1 0 P2.6/RTCCLK/DMAE0 6 DMAE0 0 1 RTCCLK 1 1 P2.7(I/O) I:0;O:1 0 P2.7/UCB0STE/UCA0CLK 7 UCB0STE/UCA0CLK(2) (3) X 1 (1) X=Don'tcare (2) ThepindirectioniscontrolledbytheUSCImodule. (3) UCA0CLKfunctiontakesprecedenceoverUCB0STEfunction.IfthepinisrequiredasUCA0CLKinputoroutput,USCI_B0isforcedto 3-wireSPImodeif4-wireSPImodeisselected. 72 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 6.11.3 Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger Figure6-4showstheportdiagram.Table6-45 summarizestheselectionofthepinfunctions. Pad Logic P3REN.x DV 0 SS DV 1 1 CC P3DIR.x 0 Direction From module 1 0: Input 1: Output P3OUT.x 0 From module 1 P3.0/UCB0SIMO/UCB0SDA P3DS.x P3.1/UCB0SOMI/UCB0SCL P3SEL.x 0: Low drive P3.2/UCB0CLK/UCA0STE 1: High drive P3.3/UCA0TXD/UCA0SIMO P3IN.x P3.4/UCA0RXD/UCA0SOMI EN To module D Figure6-4.PortP3(P3.0toP3.7)Diagram Table6-45.PortP3(P3.0toP3.7)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P3.x) x FUNCTION P3DIR.x P3SEL.x P3.0(I/O) I:0;O:1 0 P3.0/UCB0SIMO/UCB0SDA 0 UCB0SIMO/UCB0SDA(2) (3) X 1 P3.1(I/O) I:0;O:1 0 P3.1/UCB0SOMI/UCB0SCL 1 UCB0SOMI/UCB0SCL(2) (3) X 1 P3.2(I/O) I:0;O:1 0 P3.2/UCB0CLK/UCA0STE 2 UCB0CLK/UCA0STE(2) (4) X 1 P3.3(I/O) I:0;O:1 0 P3.3/UCA0TXD/UCA0SIMO 3 UCA0TXD/UCA0SIMO(2) X 1 P3.4(I/O) I:0;O:1 0 P3.4/UCA0RXD/UCA0SOMI 4 UCA0RXD/UCA0SOMI(2) X 1 (1) X=Don'tcare (2) ThepindirectioniscontrolledbytheUSCImodule. (3) IftheI2Cfunctionalityisselected,theoutputdrivesonlythelogical0toV level. SS (4) UCB0CLKfunctiontakesprecedenceoverUCA0STEfunction.IfthepinisrequiredasUCB0CLKinputoroutput,USCI_A0isforcedto 3-wireSPImodeif4-wireSPImodeisselected. Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 73 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 6.11.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger Figure6-5showstheportdiagram.Table6-46 summarizestheselectionofthepinfunctions. Pad Logic P4REN.x DV 0 SS DV 1 1 CC P4DIR.x 0 Direction From Port Mapping Control 1 0: Input 1: Output P4OUT.x 0 From Port Mapping Control 1 P4.0/P4MAP0 P4DS.x P4.1/P4MAP1 P4SEL.x 0: Low drive P4.2/P4MAP2 1: High drive P4.3/P4MAP3 P4IN.x P4.4/P4MAP4 P4.5/P4MAP5 P4.6/P4MAP6 EN P4.7/P4MAP7 To Port Mapping Control D Figure6-5.PortP4(P4.0toP4.7)Diagram Table6-46.PortP4(P4.0toP4.7)PinFunctions CONTROLBITSORSIGNALS PINNAME(P4.x) x FUNCTION P4DIR.x(1) P4SEL.x P4MAPx P4.0(I/O) I:0;O:1 0 X P4.0/P4MAP0 0 Mappedsecondarydigitalfunction X 1 ≤30 P4.1(I/O) I:0;O:1 0 X P4.1/P4MAP1 1 Mappedsecondarydigitalfunction X 1 ≤30 P4.2(I/O) I:0;O:1 0 X P4.2/P4MAP2 2 Mappedsecondarydigitalfunction X 1 ≤30 P4.3(I/O) I:0;O:1 0 X P4.3/P4MAP3 3 Mappedsecondarydigitalfunction X 1 ≤30 P4.4(I/O) I:0;O:1 0 X P4.4/P4MAP4 4 Mappedsecondarydigitalfunction X 1 ≤30 P4.5(I/O) I:0;O:1 0 X P4.5/P4MAP5 5 Mappedsecondarydigitalfunction X 1 ≤30 P4.6(I/O) I:0;O:1 0 X P4.6/P4MAP6 6 Mappedsecondarydigitalfunction X 1 ≤30 P4.7(I/O) I:0;O:1 0 X P4.7/P4MAP7 7 Mappedsecondarydigitalfunction X 1 ≤30 (1) Thedirectionofsomemappedsecondaryfunctionsarecontrolleddirectlybythemodule.SeeTable6-6forspecificdirectioncontrol informationofmappedsecondaryfunctions. 74 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 6.11.5 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger Figure6-6showstheportdiagram.Table6-47 summarizestheselectionofthepinfunctions. Pad Logic To or from Reference toADC10 INCHx = x P5REN.x DV 0 SS DV 1 1 CC P5DIR.x 0 1 P5OUT.x 0 From module 1 P5.0/(A8/VeREF+) P5DS.x P5.1/(A9/VeREF–) P5SEL.x 0: Low drive 1: High drive P5IN.x EN Bus Keeper To module D Figure6-6.PortP5(P5.0andP5.1)Diagram Table6-47.PortP5(P5.0andP5.1)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P5.x) x FUNCTION P5DIR.x P5SEL.x P5.0(I/O)(3) I:0;O:1 0 P5.0/A8/VeREF+(2) 0 A8/VeREF+(4) X 1 P5.1(I/O)(3) I:0;O:1 0 P5.1/A9/VeREF–(5) 1 A9/VeREF–(6) X 1 (1) X=Don'tcare (2) VeREF+availableondeviceswithADC10_A. (3) Defaultcondition (4) SettingtheP5SEL.0bitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplyinganalog signals.AnexternalvoltagecanbeappliedtoVeREF+andusedasthereferencefortheADC10_Awhenavailable. (5) VeREF-availableondeviceswithADC10_A. (6) SettingtheP5SEL.1bitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplyinganalog signals.AnexternalvoltagecanbeappliedtoVeREF-andusedasthereferencefortheADC10_Awhenavailable. Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 75 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 6.11.6 Port P5 (P5.2) Input/Output With Schmitt Trigger Figure6-7showstheportdiagram.Table6-48 summarizestheselectionofthepinfunctions. Pad Logic To XT2 P5REN.2 DV 0 SS DV 1 1 CC P5DIR.2 0 1 P5OUT.2 0 Module X OUT 1 P5.2/XT2IN P5DS.2 P5SEL.2 0: Low drive 1: High drive P5IN.2 EN Bus Keeper Module X IN D Figure6-7.PortP5(P5.2)Diagram 76 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 6.11.7 Port P5 (P5.3) Input/Output With Schmitt Trigger Figure6-8showstheportdiagram.Table6-48 summarizestheselectionofthepinfunctions. Pad Logic To XT2 P5REN.3 DV 0 SS DV 1 1 CC P5DIR.3 0 1 P5OUT.3 0 Module X OUT 1 P5.3/XT2OUT P5SEL.2 P5DS.3 0: Low drive XT2BYPASS 1: High drive P5SEL.3 P5IN.3 EN Bus Keeper Module X IN D Figure6-8.PortP5(P5.3)Diagram Table6-48.PortP5(P5.2andP5.3)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P5.x) x FUNCTION P5DIR.x P5SEL.2 P5SEL.3 XT2BYPASS P5.2(I/O) I:0;O:1 0 X X P5.2/XT2IN 2 XT2INcrystalmode(2) X 1 X 0 XT2INbypassmode(2) X 1 X 1 P5.3(I/O) I:0;O:1 0 0 X P5.3/XT2OUT 3 XT2OUTcrystalmode(3) X 1 X 0 P5.3(I/O)(3) X 1 0 1 (1) X=Don'tcare (2) SettingP5SEL.2causesthegeneral-purposeI/Otobedisabled.PendingthesettingofXT2BYPASS,P5.2isconfiguredforcrystal modeorbypassmode. (3) SettingP5SEL.2causesthegeneral-purposeI/Otobedisabledincrystalmode.Whenusingbypassmode,P5.3canbeusedas general-purposeI/O. Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 77 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 6.11.8 Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger Figure 6-9 and Figure 6-10 show the port diagrams. Table 6-49 summarizes the selection of the pin functions. Pad Logic to XT1 P5REN.4 DV 0 SS DV 1 1 CC P5DIR.4 0 1 P5OUT.4 0 Module X OUT 1 P5.4/XIN P5DS.4 P5SEL.4 0: Low drive 1: High drive P5IN.4 EN Bus Keeper Module X IN D Figure6-9.PortP5(P5.4)Diagram 78 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 Pad Logic to XT1 P5REN.5 DV 0 SS DV 1 1 P5DIR.5 0 CC 1 P5OUT.5 0 Module X OUT 1 P5.5/XOUT P5SEL.4 P5DS.5 0: Low drive XT1BYPASS 1: High drive P5SEL.5 P5IN.5 EN Bus Keeper Module X IN D Figure6-10.PortP5(P5.5)Diagram Table6-49.PortP5(P5.4andP5.5)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P7.x) x FUNCTION P5DIR.x P5SEL.4 P5SEL.5 XT1BYPASS P5.4(I/O) I:0;O:1 0 X X P5.4/XIN 4 XINcrystalmode(2) X 1 X 0 XINbypassmode(2) X 1 X 1 P5.5(I/O) I:0;O:1 0 0 X P5.5/XOUT 5 XOUTcrystalmode(3) X 1 X 0 P5.5(I/O)(3) X 1 0 1 (1) X=Don'tcare (2) SettingP5SEL.4causesthegeneral-purposeI/Otobedisabled.PendingthesettingofXT1BYPASS,P5.4isconfiguredforcrystal modeorbypassmode. (3) SettingP5SEL.4causesthegeneral-purposeI/Otobedisabledincrystalmode.Whenusingbypassmode,P5.5canbeusedas general-purposeI/O. Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 79 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 6.11.9 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger Figure6-11showstheportdiagram.Table6-50summarizestheselectionofthepinfunctions. Pad Logic toADC10 INCHx = x to Comparator_B from Comparator_B CBPD.x P6REN.x DVSS 0 DVCC 1 1 P6DIR.x 0 Direction 0: Input 1 1: Output P6OUT.x 0 From module 1 P6.0/CB0/(A0) P6DS.x P6.1/CB1/(A1) P6SEL.x 0: Low drive P6.2/CB2/(A2) 1: High drive P6.3/CB3/(A3) P6IN.x P6.4/CB4/(A4) P6.5/CB5/(A5) P6.6/CB6/(A6) EN Bus P6.7/CB7/(A7) Keeper To module D Figure6-11.PortP6(P6.0toP6.7)Diagram 80 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 Table6-50.PortP6(P6.0toP6.7)PinFunctions CONTROLBITSORSIGNALS PINNAME(P6.x) x FUNCTION P6DIR.x P6SEL.x CBPD P6.0(I/O) I:0;O:1 0 0 P6.0/CB0/(A0) 0 A0(onlyondeviceswithADC) X 1 X CB0(1) X X 1 P6.1(I/O) I:0;O:1 0 0 P6.1/CB1/(A1) 1 A1(onlyondeviceswithADC) X 1 X CB1(1) X X 1 P6.2(I/O) I:0;O:1 0 0 P6.2/CB2/(A2) 2 A2(onlyondeviceswithADC) X 1 X CB2(1) X X 1 P6.3(I/O) I:0;O:1 0 0 P6.3/CB3/(A3) 3 A3(onlyondeviceswithADC) X 1 X CB3(1) X X 1 P6.4(I/O) I:0;O:1 0 0 P6.4/CB4/(A4) 4 A4(onlyondeviceswithADC) X 1 X CB4(1) X X 1 P6.5(I/O) I:0;O:1 0 0 P6.5/CB5/(A5) 5 A5(onlyondeviceswithADC) X 1 X CB5(1) X X 1 P6.6(I/O) I:0;O:1 0 0 P6.6/CB6/(A6) 6 A6(onlyondeviceswithADC) X 1 X CB6(1) X X 1 P6.7(I/O) I:0;O:1 0 0 P6.7/CB7/(A7) 7 A7(onlyondeviceswithADC) X 1 X CB7(1) X X 1 (1) SettingtheCBPD.xbitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplyinganalog signals.SelectingtheCBxinputpintothecomparatormultiplexerwiththeCBxbitsautomaticallydisablesoutputdriverandinputbuffer forthatpin,regardlessofthestateoftheassociatedCBPD.xbit. Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 81 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 6.11.10 Port U (PU.0 and PU.1) Input/Output Figure6-12showstheportdiagram.Table6-51summarizestheselectionofthepinfunctions. LDOO VSSU Pad Logic PUOPE PUOUT0 PU.0 PUIN0 PUIPE PUIN1 PUOUT1 PU.1 Figure6-12.PortU(PU.0andPU.1)Diagram Table6-51.PortU(PU.0andPU.1)PinFunctions(1) PUIPE PUOPE PUOUT1 PUOUT0 PU.1 PU.0 PORTUFUNCTION 0 1 0 0 Outputlow Outputlow Outputsenabled 0 1 0 1 Outputlow Outputhigh Outputsenabled 0 1 1 0 Outputhigh Outputlow Outputsenabled 0 1 1 1 Outputhigh Outputhigh Outputsenabled 1 0 X X Inputenabled Inputenabled Inputsenabled 0 0 X X Hi-Z Hi-Z Outputsandinputsdisabled (1) PU.1andPU.0inputsandoutputsaresuppliedfromLDOO.LDOOcanbegeneratedbythedeviceusingtheintegrated3.3-VLDO whenenabled.LDOOcanalsobesuppliedexternallywhenthe3.3-VLDOisnotbeingusedandisdisabled. 82 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 6.11.11 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output Figure6-13showstheportdiagram.Table6-52summarizestheselectionofthepinfunctions. Pad Logic PJREN.0 DV 0 SS DV 1 1 CC PJDIR.0 0 DVCC 1 PJOUT.0 0 From JTAG 1 PJ.0/TDO PJDS.0 From JTAG 0: Low drive 1: High drive PJIN.0 EN D Figure6-13.PortPJ(PJ.0)Diagram Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 83 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 6.11.12 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output Figure6-14showstheportdiagram.Table6-52summarizestheselectionofthepinfunctions. Pad Logic PJREN.x DV 0 SS DV 1 1 CC PJDIR.x 0 DVSS 1 PJOUT.x 0 From JTAG 1 PJ.1/TDI/TCLK PJDS.x PJ.2/TMS From JTAG 0: Low drive PJ.3/TCK 1: High drive PJIN.x EN To JTAG D Figure6-14.PortPJ(PJ.1toPJ.3)Diagram Table6-52.PortPJ(PJ.0toPJ.3)PinFunctions CONTROLBITSOR PINNAME(PJ.x) x FUNCTION SIGNALS(1) PJDIR.x PJ.0(I/O)(2) I:0;O:1 PJ.0/TDO 0 TDO(3) X PJ.1(I/O)(2) I:0;O:1 PJ.1/TDI/TCLK 1 TDI/TCLK(3) (4) X PJ.2(I/O)(2) I:0;O:1 PJ.2/TMS 2 TMS(3) (4) X PJ.3(I/O)(2) I:0;O:1 PJ.3/TCK 3 TCK(3) (4) X (1) X=Don'tcare (2) Defaultcondition (3) ThepindirectioniscontrolledbytheJTAGmodule. (4) InJTAGmode,pullupsareactivatedautomaticallyonTMS,TCK,andTDI/TCLK.PJREN.xaredon'tcare. 84 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 6.12 Device Descriptors Table 6-53 lists the complete contents of the device descriptor tag-length-value (TLV) structure for each devicetype. Table6-53.DeviceDescriptors(1) VALUE DESCRIPTION ADDRESS SIZE F5308 F5308 F5309 F5309 F5310 F5310 (bytes) F5304 RGC, RGZ, RGC, RGZ, RGC, RGZ, ZQE PT ZQE PT ZQE PT Infolength 01A00h 1 06h 06h 06h 06h 06h 06h 06h CRClength 01A01h 1 06h 06h 06h 06h 06h 06h 06h CRCvalue 01A02h 2 Perunit Perunit Perunit Perunit Perunit Perunit Perunit InfoBlock DeviceID 01A04h 1 12h 13h 13h 14h 14h 15h 15h DeviceID 01A05h 1 81h 81h 81h 81h 81h 81h 81h Hardwarerevision 01A06h 1 Perunit Perunit Perunit Perunit Perunit Perunit Perunit Firmwarerevision 01A07h 1 Perunit Perunit Perunit Perunit Perunit Perunit Perunit Dierecordtag 01A08h 1 08h 08h 08h 08h 08h 08h 08h Dierecordlength 01A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah Lot/waferID 01A0Ah 4 Perunit Perunit Perunit Perunit Perunit Perunit Perunit DieRecord DieXposition 01A0Eh 2 Perunit Perunit Perunit Perunit Perunit Perunit Perunit DieYposition 01A10h 2 Perunit Perunit Perunit Perunit Perunit Perunit Perunit Testresults 01A12h 2 Perunit Perunit Perunit Perunit Perunit Perunit Perunit ADC10CalibrationTag 01A14h 1 13h 13h 13h 13h 13h 13h 13h ADC10CalibrationLength 01A15h 1 10h 10h 10h 10h 10h 10h 10h ADCGainFactor 01A16h 2 Perunit Perunit Perunit Perunit Perunit Perunit Perunit ADCOffset 01A18h 2 Perunit Perunit Perunit Perunit Perunit Perunit Perunit ADC1.5-VReference 01A1Ah 2 Perunit Perunit Perunit Perunit Perunit Perunit Perunit Temperaturesensor30°C ADC1.5-VReference ADC10 Temperaturesensor85°C 01A1Ch 2 Perunit Perunit Perunit Perunit Perunit Perunit Perunit Calibration ADC2.0-VReference 01A1Eh 2 Perunit Perunit Perunit Perunit Perunit Perunit Perunit Temperaturesensor30°C ADC2.0-VReference 01A20h 2 Perunit Perunit Perunit Perunit Perunit Perunit Perunit Temperaturesensor85°C ADC2.5-VReference 01A22h 2 Perunit Perunit Perunit Perunit Perunit Perunit Perunit Temperaturesensor30°C ADC2.5-VReference 01A24h 2 Perunit Perunit Perunit Perunit Perunit Perunit Perunit Temperaturesensor85°C REFcalibrationtag 01A26h 1 12h 12h 12h 12h 12h 12h 12h REFcalibrationlength 01A27h 1 06h 06h 06h 06h 06h 06h 06h REF REF1.5-Vreferencefactor 01A28h 2 Perunit Perunit Perunit Perunit Perunit Perunit Perunit Calibration REF2.0-Vreferencefactor 01A2Ah 2 Perunit Perunit Perunit Perunit Perunit Perunit Perunit REF2.5-Vreferencefactor 01A2Ch 2 Perunit Perunit Perunit Perunit Perunit Perunit Perunit (1) N/A=Notapplicable Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 85 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com Table6-53.DeviceDescriptors(1) (continued) VALUE DESCRIPTION ADDRESS SIZE F5308 F5308 F5309 F5309 F5310 F5310 (bytes) F5304 RGC, RGZ, RGC, RGZ, RGC, RGZ, ZQE PT ZQE PT ZQE PT Peripheraldescriptortag 01A2Eh 1 02h 02h 02h 02h 02h 02h 02h Peripheraldescriptorlength 01A2Fh 1 5Ch 60h 60h 61h 61h 60h 60h 08h 08h 08h 08h 08h 08h 08h Memory1 2 8Ah 8Ah 8Ah 8Ah 8Ah 8Ah 8Ah 0Ch 0Ch 0Ch 0Ch 0Ch 0Ch 0Ch Memory2 2 86h 86h 86h 86h 86h 86h 86h 0Eh 0Eh 0Eh 0Eh 0Eh 0Eh 0Eh Memory3 2 2Dh 2Dh 2Dh 2Dh 2Dh 2Dh 2Dh 2Ah 2Ah 2Ah 2Ah 2Ah 2Ah 2Ah Memory4 2 70h 60h 60h 50h 50h 40h 40h 91h 91h Memory5 2/1 8Eh 90h 90h 92h 92h 8Eh 8Eh Delimiter 1 00h 00h 00h 00h 00h 00h 00h Peripheralcount 1 1Eh 20h 20h 20h 20h 20h 20h 00h 00h 00h 00h 00h 00h 00h MSP430CPUXV2 2 23h 23h 23h 23h 23h 23h 23h 00h 00h 00h 00h 00h 00h 00h JTAG 2 09h 09h 09h 09h 09h 09h 09h 00h 00h 00h 00h 00h 00h 00h SBW 2 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 00h 00h 00h 00h 00h 00h 00h EEM-S 2 03h 03h 03h 03h 03h 03h 03h 00h 00h 00h 00h 00h 00h 00h TIBSL 2 FCh FCh FCh FCh FCh FCh FCh 10h 10h 10h 10h 10h 10h 10h Peripheral SFR 2 41h 41h 41h 41h 41h 41h 41h Descriptor 02h 02h 02h 02h 02h 02h 02h PMM 2 30h 30h 30h 30h 30h 30h 30h 02h 02h 02h 02h 02h 02h 02h FCTL 2 38h 38h 38h 38h 38h 38h 38h 01h 01h 01h 01h 01h 01h 01h CRC16 2 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 00h 00h 00h 00h 00h 00h 00h CRC16_RB 2 3Dh 3Dh 3Dh 3Dh 3Dh 3Dh 3Dh 00h 00h 00h 00h 00h 00h 00h RAMCTL 2 44h 44h 44h 44h 44h 44h 44h 00h 00h 00h 00h 00h 00h 00h WDT_A 2 40h 40h 40h 40h 40h 40h 40h 01h 01h 01h 01h 01h 01h 01h UCS 2 48h 48h 48h 48h 48h 48h 48h 02h 02h 02h 02h 02h 02h 02h SYS 2 42h 42h 42h 42h 42h 42h 42h 03h 03h 03h 03h 03h 03h 03h REF 2 A0h A0h A0h A0h A0h A0h A0h 01h 01h 01h 01h 01h 01h 01h PortMapping 2 10h 10h 10h 10h 10h 10h 10h 04h 04h 04h 04h 04h 04h 04h Port1and2 2 51h 51h 51h 51h 51h 51h 51h 02h 02h 02h 02h 02h 02h 02h Port3and4 2 52h 52h 52h 52h 52h 52h 52h 02h 02h 02h 02h 02h 02h 02h Port5and6 2 53h 53h 53h 53h 53h 53h 53h 86 DetailedDescription Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 Table6-53.DeviceDescriptors(1) (continued) VALUE DESCRIPTION ADDRESS SIZE F5308 F5308 F5309 F5309 F5310 F5310 (bytes) F5304 RGC, RGZ, RGC, RGZ, RGC, RGZ, ZQE PT ZQE PT ZQE PT 0Eh 0Eh 0Eh 0Eh 0Eh 0Eh 0Eh JTAG 2 5Fh 5Fh 5Fh 5Fh 5Fh 5Fh 5Fh 02h 02h 02h 02h 02h 02h 02h TA0 2 62h 62h 62h 62h 62h 62h 62h 04h 04h 04h 04h 04h 04h 04h TA1 2 61h 61h 61h 61h 61h 61h 61h 04h 04h 04h 04h 04h 04h 04h TB0 2 67h 67h 67h 67h 67h 67h 67h 04h 04h 04h 04h 04h 04h 04h TA2 2 61h 61h 61h 61h 61h 61h 61h 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah RTC 2 68h 68h 68h 68h 68h 68h 68h Peripheral 02h 02h 02h 02h 02h 02h 02h Descriptor MPY32 2 85h 85h 85h 85h 85h 85h 85h (continued) 04h 04h 04h 04h 04h 04h 04h DMA-3 2 47h 47h 47h 47h 47h 47h 47h 10h 0Ch 0Ch 0Ch 0Ch 0Ch 0Ch USCI_A,USCI_B 2 90h 90h 90h 90h 90h 90h 90h 04h 04h 04h 04h 04h 04h USCI_A,USCI_B 2 N/A 90h 90h 90h 90h 90h 90h 14h 14h 14h 14h 14h 14h 14h ADC10_A 2 D3h D3h D3h D3h D3h D3h D3h 18h 18h 18h 18h 18h 18h COMP_B 2 N/A A8h A8h A8h A8h A8h A8h 1Ch 04h 04h 04h 04h 04h 04h LDO 2 5Ch 5Ch 5Ch 5Ch 5Ch 5Ch 5Ch COMP_B 1 01h A8h A8h A8h A8h A8h A8h TB0.CCIFG0 1 64h 64h 64h 64h 64h 64h 64h TB0.CCIFG1..6 1 65h 65h 65h 65h 65h 65h 65h WDTIFG 1 40h 40h 40h 40h 40h 40h 40h USCI_A0 1 01h 90h 90h 90h 90h 90h 90h USCI_B0 1 01h 91h 91h 91h 91h 91h 91h ADC10_A 1 D0h D0h D0h D0h D0h D0h D0h TA0.CCIFG0 1 60h 60h 60h 60h 60h 60h 60h TA0.CCIFG1..4 1 61h 61h 61h 61h 61h 61h 61h LDO-PWR 1 5Ch 5Ch 5Ch 5Ch 5Ch 5Ch 5Ch Interrupts DMA 1 46h 46h 46h 46h 46h 46h 46h TA1.CCIFG0 1 62h 62h 62h 62h 62h 62h 62h TA1.CCIFG1..2 1 63h 63h 63h 63h 63h 63h 63h P1 1 50h 50h 50h 50h 50h 50h 50h USCI_A1 1 92h 92h 92h 92h 92h 92h 92h USCI_B1 1 93h 93h 93h 93h 93h 93h 93h TA1.CCIFG0 1 66h 66h 66h 66h 66h 66h 66h TA1.CCIFG1..2 1 67h 67h 67h 67h 67h 67h 67h P2 1 51h 51h 51h 51h 51h 51h 51h RTC_A 1 68h 68h 68h 68h 68h 68h 68h Delimiter 1 00h 00h 00h 00h 00h 00h 00h Copyright©2010–2018,TexasInstrumentsIncorporated DetailedDescription 87 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 7 Device and Documentation Support 7.1 Getting Started and Next Steps For more information on the MSP430 family of devices and the tools and libraries that are available to helpwithyourdevelopment,visittheMSP430ultra-low-powersensingandmeasurementMCUsoverview. 7.2 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These prefixes represent evolutionary stages of product development from engineering prototypes (XMS) throughfullyqualifiedproductiondevices(MSP). XMS – Experimental device that is not necessarily representative of the final device's electrical specifications MSP–Fullyqualifiedproductiondevice XMSdevicesareshippedagainstthefollowingdisclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." MSP devices have been characterized fully, and the quality and reliability of the device have been demonstratedfully.TI'sstandardwarrantyapplies. Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-usefailureratestillisundefined.Onlyqualifiedproductiondevicesaretobeused. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature range, package type, and distribution format. Figure 7-1 provides a legend for reading the completedevicename. 88 DeviceandDocumentationSupport Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 MSP 430 F 5 438 A I ZQW T -EP Processor Family Optional:Additional Features MCU Platform Optional:Tape and Reel DeviceType Packaging Series Optional:Temperature Range Feature Set Optional:A= Revision Processor Family CC = Embedded RF Radio MSP= Mixed-Signal Processor XMS = Experimental Silicon PMS = Prototype Device MCU Platform 430 = MSP430 low-power microcontroller platform Device Type Memory Type SpecializedApplication C = ROM AFE =Analog Front End F = Flash BQ = Contactless Power FR = FRAM CG = ROM Medical G = Flash or FRAM (Value Line) FE = Flash Energy Meter L= No Nonvolatile Memory FG = Flash Medical FW = Flash Electronic Flow Meter Series 1 = Up to 8 MHz 5 = Up to 25 MHz 2 = Up to 16 MHz 6 = Up to 25 MHz with LCD 3 = Legacy 0 = Low-Voltage Series 4 = Up to 16 MHz with LCD Feature Set Various levels of integration within a series Optional:A= Revision N/A Optional: Temperature Range S = 0°C to 50°C C = 0°C to 70°C I =–40°C to 85°C T=–40°C to 105°C Packaging http://www.ti.com/packaging Optional: Tape and Reel T= Small reel R = Large reel No markings =Tube or tray Optional:Additional Features -EP= Enhanced Product (–40°C to 105°C) -HT= ExtremeTemperature Parts (–55°C to 150°C) -Q1 =Automotive Q100 Qualified Figure7-1.DeviceNomenclature Copyright©2010–2018,TexasInstrumentsIncorporated DeviceandDocumentationSupport 89 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 7.3 Tools and Software All MSP microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at MSP430 Ultra-Low-Power MCUs – Tools& software. Table 7-1 lists the debug features of the MSP430F530x and MSP430F5310 MCUs. See the Code ComposerStudioforMSP430User'sGuidefordetailsontheavailablefeatures. Table7-1.HardwareDebugFeatures BREAK- RANGE LPMx.5 MSP430 4-WIRE 2-WIRE CLOCK STATE TRACE POINTS BREAK- DEBUGGING ARCHITECTURE JTAG JTAG CONTROL SEQUENCER BUFFER (N) POINTS SUPPORT MSP430Xv2 Yes Yes 3 Yes Yes No No No DesignKitsandEvaluationModules 64-PinTargetDevelopmentBoardforMSP430F5xMCUs The MSP-TS430PN64B is a stand-alone 64- pinZIFsockettargetboardusedtoprogramanddebugtheMSP430MCUin-systemthrough theJTAGinterfaceortheSpyBi-Wire(2-wireJTAG)protocol. 64-PinTargetDevelopmentBoardandMSP-FETProgrammerBundleforMSP430F5xMCUs The MSP-FET is a powerful flash emulation tool to quickly begin application development on the MSP430 MCU. It includes USB debugging interface used to program and debug the MSP430 in-system through the JTAG interface or the pin saving Spy Bi-Wire (2-wire JTAG) protocol. The flash memory can be erased and programmed in seconds with only a few keystrokes, and because the MSP430 flash is ultra-low power, no external power supply is required. Software MSP430Ware™Software MSP430Ware software is a collection of code examples, data sheets, and other design resources for all MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing MSP430 MCU design resources, MSP430Ware software also includes a high-level API called MSP Driver Library. This library makes it easy to program MSP430 hardware. MSP430Ware software is available as a componentofCCSorasastand-alonepackage. MSP430F530x,MSP430F5310CodeExamples C code examples that configure each of the integrated peripheralsforvariousapplicationneeds. MSPDriverLibrary Driver Library's abstracted API keeps you above the bits and bytes of the MSP430 hardware by providing easy-to-use function calls. Thorough documentation is delivered through a helpful API Guide, which includes details on each function call and the recognized parameters. Developers can use Driver Library functions to write complete projects with minimaloverhead. MSPEnergyTrace™Technology EnergyTrace technology for MSP430 microcontrollers is an energy- based code analysis tool that measures and displays the application's energy profile and helpstooptimizeitforultra-low-powerconsumption. ULP(Ultra-LowPower)Advisor ULP Advisor™ software is a tool for guiding developers to write more efficient code to fully utilize the unique ultra-low power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new microcontroller developers, ULP Advisor checks your code against a thorough ULP checklist to squeeze every last nano amp out of your application. At build time, ULP Advisor will provide notifications and remarks to highlightareasofyourcodethatcanbefurtheroptimizedforlowerpower. IEC60730SoftwarePackage The IEC60730 MSP430 software package was developed to be useful in assisting customers in complying with IEC 60730-1:2010 (Automatic Electrical Controls for Household and Similar Use – Part 1: General Requirements) for up to Class B products, which includes home appliances, arc detectors, power converters, power tools, e-bikes, and many others. The IEC60730 MSP430 software package can be embedded in customer applications running on MSP430s to help simplify the customer’s certification efforts of functionalsafety-compliantconsumerdevicestoIEC60730-1:2010ClassB. 90 DeviceandDocumentationSupport Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 FixedPointMathLibraryforMSP The MSP IQmath and Qmath Libraries are a collection of highly optimizedandhigh-precisionmathematicalfunctionsforCprogrammerstoseamlesslyporta floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmath libraries, it is possible to achieve execution speeds considerably faster and energy consumptionconsiderablylowerthanequivalentcodewrittenusingfloating-pointmath. FloatingPointMathLibraryforMSP430 Continuing to innovate in the low power and low cost microcontroller space, TI brings you MSPMATHLIB. Leveraging the intelligent peripherals of our devices, this floating point math library of scalar functions brings you up to 26x better performance. Mathlib is easy to integrate into your designs. This library is free and is integrated in both Code Composer Studio and IAR IDEs. Read the user’s guide for an in depthlookatthemathlibraryandrelevantbenchmarks. DevelopmentTools CodeComposerStudio™IntegratedDevelopmentEnvironmentforMSPMicrocontrollers Code Composer Studio is an integrated development environment (IDE) that supports all MSP microcontroller devices. Code Composer Studio comprises a suite of embedded software utilities used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through each step of the application development flow. Familiar utilities and interfaces allow users to get started faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment for embedded developers. When using CCS with an MSP MCU, a unique and powerful set of plugins and embedded software utilitiesaremadeavailabletofullyleveragetheMSPmicrocontroller. Command-LineProgrammer MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary files (.txt or .hex) files directly to theMSPmicrocontrollerwithoutanIDE. MSPMCUProgrammerandDebugger The MSP-FET is a powerful emulation development tool – often called a debug probe – which allows users to quickly begin application development on MSP low-power microcontrollers (MCU). Creating MCU software usually requires downloading the resulting binary program to the MSP device for validation and debugging. The MSP-FET provides a debug communication pathway between a host computer and the target MSP. Furthermore, the MSP-FET also provides a Backchannel UART connection between the computer's USB interface and the MSP UART. This affords the MSP programmer a convenient method for communicating serially between the MSP and a terminal running on the computer. It also supports loading programs (often called firmware) to the MSP target usingtheBSL(bootloader)throughtheUARTandI2Ccommunicationprotocols. MSP-GANGProductionProgrammer The MSP Gang Programmer is an MSP430 or MSP432 device programmer that can program up to eight identical MSP430 or MSP432 Flash or FRAM devices at the same time. The MSP Gang Programmer connects to a host PC using a standard RS-232 or USB connection and provides flexible programming options that allow the user to fully customize the process. The MSP Gang Programmer is provided with an expansion board, called the Gang Splitter, that implements the interconnections between the MSP Gang Programmer and multiple target devices. Eight cables are provided that connect the expansion board to eight target devices (through JTAG or Spy-Bi-Wire connectors). The programming can be done with a PC or as a stand-alone device. A PC-side graphical user interfaceisalsoavailableandisDLL-based. Copyright©2010–2018,TexasInstrumentsIncorporated DeviceandDocumentationSupport 91 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 7.4 Documentation Support The following documents describe the MSP430F5310 and MSP430F530x devices. Copies of these documentsareavailableontheInternetatwww.ti.com. ReceivingNotificationofDocumentUpdates To receive notification of documentation updates—including silicon errata—go to the product folder for your device on ti.com (for links to the product folders, see Table 7-2). In the upper right corner, click the "Alert me" button. This registers you to receive a weekly digest of product information that has changed (if any).Forchangedetails,checktherevisionhistoryofanyreviseddocument. Errata MSP430F5310DeviceErratasheet Describes the known exceptions to the functional specifications for theMSP430F5310device. MSP430F5309DeviceErratasheet Describes the known exceptions to the functional specifications for theMSP430F5309device. MSP430F5308DeviceErratasheet Describes the known exceptions to the functional specifications for theMSP430F5308device. MSP430F5304DeviceErratasheet Describes the known exceptions to the functional specifications for theMSP430F5304device. User'sGuides MSP430F5xxandMSP430F6xxFamilyUser'sGuide Detailed information on the modules and peripheralsavailableinthisdevicefamily. MSP430FlashDeviceBootloader(BSL)User'sGuide The MSP430 bootloader (BSL) lets users communicate with embedded memory in the MSP430 microcontroller during the prototyping phase, final production, and in service. Both the programmable memory (flash memory) and thedatamemory(RAM)canbemodifiedasrequired.Donotconfusethebootloaderwiththe bootstrap loader programs found in some digital signal processors (DSPs) that automatically loadprogramcode(anddata)fromexternalmemorytotheinternalmemoryoftheDSP. MSP430ProgrammingWiththeJTAGInterface This document describes the functions that are required to erase, program, and verify the memory module of the MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition, it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This document describes device access using both the standard 4-wire JTAG interfaceandthe2-wireJTAGinterface,whichisalsoreferredtoasSpy-Bi-Wire(SBW). MSP430HardwareToolsUser'sGuide This manual describes the hardware of the TI MSP-FET430 FlashEmulationTool(FET).TheFETistheprogramdevelopmenttoolfortheMSP430ultra- low-power microcontroller. Both available interface types, the parallel port interface and the USBinterface,aredescribed. ApplicationReports MSP43032-kHzCrystalOscillators Selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the correct crystal for MSP430 ultra- low-power operation. In addition, hints and examples for correct board layout are given. The document also contains detailed information on the possible oscillator tests to ensure stable oscillatoroperationinmassproduction. MSP430System-LevelESDConsiderations System-Level ESD has become increasingly demanding as silicon technology scales to lower voltages and the need for designing cost-effective and ultra-low-power components. This application report addresses three ESD topics to help board designers and OEMs understand and design robust system-level designs: (1) Component-level ESD testing and system-level ESD testing; (2) General design guidelines for system-level ESD protection; (3) Introduction to System Efficient ESD Design (SEED), a co-design methodology of on-board and on-chip ESD protection. A few real-world system- levelESDprotectiondesignexamplesandtheirresultsarediscussed. 92 DeviceandDocumentationSupport Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 www.ti.com SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 7.5 Related Links Table 7-2 lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table7-2.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER ORDERNOW DOCUMENTS SOFTWARE COMMUNITY MSP430F5310 Clickhere Clickhere Clickhere Clickhere Clickhere MSP430F5309 Clickhere Clickhere Clickhere Clickhere Clickhere MSP430F5308 Clickhere Clickhere Clickhere Clickhere Clickhere MSP430F5304 Clickhere Clickhere Clickhere Clickhere Clickhere 7.6 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; seeTI's TermsofUse. TIE2E™Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. TIEmbeddedProcessorsWiki TexasInstrumentsEmbeddedProcessorsWiki.Establishedtohelpdevelopersgetstartedwithembedded processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardwareandsoftwaresurroundingthesedevices. 7.7 Trademarks MSP430Ware,EnergyTrace,ULPAdvisor,CodeComposerStudio,E2EaretrademarksofTexas Instruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 7.8 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 7.9 Glossary TIGlossary Thisglossarylistsandexplainsterms,acronyms,anddefinitions. Copyright©2010–2018,TexasInstrumentsIncorporated DeviceandDocumentationSupport 93 SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

MSP430F5310,MSP430F5309,MSP430F5308,MSP430F5304 SLAS677F–SEPTEMBER2010–REVISEDSEPTEMBER2018 www.ti.com 8 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revisionofthisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 94 Mechanical,Packaging,andOrderableInformation Copyright©2010–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MSP430F5304IPT ACTIVE LQFP PT 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F5304 & no Sb/Br) MSP430F5304IPTR ACTIVE LQFP PT 48 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F5304 & no Sb/Br) MSP430F5304IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430 & no Sb/Br) F5304 MSP430F5304IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430 & no Sb/Br) F5304 MSP430F5308IPT ACTIVE LQFP PT 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F5308 & no Sb/Br) MSP430F5308IPTR ACTIVE LQFP PT 48 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F5308 & no Sb/Br) MSP430F5308IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F5308 & no Sb/Br) MSP430F5308IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F5308 & no Sb/Br) MSP430F5308IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430 & no Sb/Br) F5308 MSP430F5308IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430 & no Sb/Br) F5308 MSP430F5309IPT ACTIVE LQFP PT 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F5309 & no Sb/Br) MSP430F5309IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F5309 & no Sb/Br) MSP430F5309IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F5309 & no Sb/Br) MSP430F5309IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430 & no Sb/Br) F5309 MSP430F5309IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430 & no Sb/Br) F5309 MSP430F5310IPT ACTIVE LQFP PT 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F5310 & no Sb/Br) MSP430F5310IPTR ACTIVE LQFP PT 48 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F5310 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MSP430F5310IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F5310 & no Sb/Br) MSP430F5310IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F5310 & no Sb/Br) MSP430F5310IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430 & no Sb/Br) F5310 MSP430F5310IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430 & no Sb/Br) F5310 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) MSP430F5304IPTR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2 MSP430F5304IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 MSP430F5308IPTR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2 MSP430F5308IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 MSP430F5308IRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 MSP430F5308IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 MSP430F5308IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 MSP430F5309IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 MSP430F5309IRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 MSP430F5309IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 MSP430F5310IPTR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2 MSP430F5310IRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 MSP430F5310IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) MSP430F5304IPTR LQFP PT 48 1000 350.0 350.0 43.0 MSP430F5304IRGZT VQFN RGZ 48 250 210.0 185.0 35.0 MSP430F5308IPTR LQFP PT 48 1000 350.0 350.0 43.0 MSP430F5308IRGCR VQFN RGC 64 2000 367.0 367.0 38.0 MSP430F5308IRGCT VQFN RGC 64 250 210.0 185.0 35.0 MSP430F5308IRGZR VQFN RGZ 48 2500 367.0 367.0 38.0 MSP430F5308IRGZT VQFN RGZ 48 250 210.0 185.0 35.0 MSP430F5309IRGCR VQFN RGC 64 2000 367.0 367.0 38.0 MSP430F5309IRGCT VQFN RGC 64 250 210.0 185.0 35.0 MSP430F5309IRGZT VQFN RGZ 48 250 210.0 185.0 35.0 MSP430F5310IPTR LQFP PT 48 1000 350.0 350.0 43.0 MSP430F5310IRGCT VQFN RGC 64 250 210.0 185.0 35.0 MSP430F5310IRGZT VQFN RGZ 48 250 210.0 185.0 35.0 PackMaterials-Page2

GENERIC PACKAGE VIEW RGC 64 VQFN - 1 mm max height 9 x 9, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224597/A www.ti.com

PACKAGE OUTLINE RGC0064B VQFN - 1 mm max height SCALE 1.500 PLASTIC QUAD FLATPACK - NO LEAD 9.15 A B 8.85 PIN 1 INDEX AREA 9.15 8.85 1.0 0.8 C SEATING PLANE 0.05 0.08 C 0.00 2X 7.5 EXPOSED SYMM (0.2) TYP THERMAL PAD 17 32 16 33 SYMM 65 2X 7.5 4.25 0.1 60X 0.5 1 48 0.30 64X PIN 1 ID 64 49 0.18 0.1 C A B 0.5 64X 0.3 0.05 4219010/A 10/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RGC0064B VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 4.25) SEE SOLDER MASK SYMM 64X (0.6) DETAIL 64 49 64X (0.24) 1 48 60X (0.5) (R0.05) TYP (1.18) TYP (8.8) 65 SYMM (0.695) TYP ( 0.2) TYP VIA 16 33 17 32 (0.695) TYP (1.18) TYP (8.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X 0.07 MIN 0.07 MAX ALL AROUND ALL AROUND METAL UNDER METAL EDGE SOLDER MASK EXPOSED METAL SOLDER MASK EXPOSED SOLDER MASK OPENING METAL OPENING NON SOLDER MASK DEFINED SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS 4219010/A 10/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RGC0064B VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD SYMM 64X (0.6) 64 49 64X (0.24) 1 48 60X (0.5) (R0.05) TYP 9X ( 1.19) 65 SYMM (8.8) (1.39) 16 33 17 32 (1.39) (8.8) SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 10X EXPOSED PAD 65 71% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE 4219010/A 10/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

GENERIC PACKAGE VIEW RGZ 48 VQFN - 1 mm max height 7 x 7, 0.5 mm pitch PLASTIC QUADFLAT PACK- NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224671/A www.ti.com

PACKAGE OUTLINE RGZ0048A VQFN - 1 mm max height PLASTIC QUADFLAT PACK- NO LEAD 7.1 A B 6.9 7.1 PIN 1 INDEX AREA 6.9 (0.1) TYP SIDE WALL DETAIL OPTIONAL METAL THICKNESS 1 MAX C SEATING PLANE 0.05 0.08 C 0.00 2X 5.5 5.15±0.1 (0.2) TYP 13 24 44X 0.5 12 25 SEE SIDE WALL DETAIL SYMM 2X 5.5 1 36 0.30 PIN1 ID 48X 0.18 (OPTIONAL) 48 37 SYMM 0.1 C A B 0.5 48X 0.3 0.05 C 4219044/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RGZ0048A VQFN - 1 mm max height PLASTIC QUADFLAT PACK- NO LEAD 2X (6.8) ( 5.15) SYMM 48X (0.6) 48 35 48X (0.24) 44X (0.5) 1 34 SYMM 2X 2X (5.5) (6.8) 2X (1.26) 2X (1.065) (R0.05) TYP 23 12 21X (Ø0.2) VIA TYP 13 22 2X (1.26) 2X (1.065) 2X (5.5) LAND PATTERN EXAMPLE SCALE: 15X 0.07 MAX 0.07 MIN SOLDER MASK ALL AROUND ALL AROUND OPENING EXPOSED METAL EXPOSED METAL METAL SOLDER MASK METAL UNDER OPENING NON SOLDER MASK SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4219044/B 08/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RGZ0048A VQFN - 1 mm max height PLASTIC QUADFLAT PACK- NO LEAD 2X (6.8) SYMM ( 1.06) 48X (0.6) 48X (0.24) 44X (0.5) SYMM 2X 2X (5.5) (6.8) 2X (0.63) 2X (1.26) (R0.05) TYP 2X 2X (0.63) (1.26) 2X (5.5) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 67% PRINTED COVERAGE BY AREA SCALE: 15X 4219044/B 08/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

MECHANICAL DATA MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996 PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 M 0,17 36 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 Gage Plane 9,20 SQ 8,80 0,25 1,45 0,05 MIN 0°–7° 1,35 0,75 Seating Plane 0,45 1,60 MAX 0,10 4040052/C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D. This may also be a thermally enhanced plastic package with leads conected to the die pads. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

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