MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 (cid:2) (cid:2) Low Supply-Voltage Range, 1.8 V to 3.6 V 32-Bit Hardware Multiplier (cid:2) (cid:2) Ultra-Low Power Consumption: Brownout Detector − Active Mode: 280 μA at 1 MHz, 2.2 V (cid:2) Supply Voltage Supervisor/Monitor With − Standby Mode: 1.1 μA Programmable Level Detection − Off Mode (RAM Retention): 0.2 μA (cid:2) Serial Onboard Programming, (cid:2) Five Power-Saving Modes No External Programming Voltage Needed (cid:2) Wake-Up From Standby Mode in Less Programmable Code Protection by Security Than 6 μs Fuse (cid:2) (cid:2) 16-Bit RISC Architecture, Bootstrap Loader 62.5-ns Instruction Cycle Time (cid:2) On Chip Emulation Module (cid:2) Three or Four 16-Bit Sigma-Delta (cid:2) Family Members Include: Analog-to-Digital (A/D) Converters With MSP430F4783: 48KB + 256B Flash Differential PGA Inputs 2KB RAM (cid:2) 16-Bit Timer_B With Three 3 Sigma-Delta ADCs Capture/Compare-With-Shadow Registers MSP430F4793: 60KB + 256B Flash (cid:2) 2.5KB RAM 16-Bit Timer_A With Three 3 Sigma-Delta ADCs Capture/Compare Registers (cid:2) MSP430F4784: 48KB + 256B Flash On-Chip Comparator 2KB RAM (cid:2) Four Universal Serial Communication 4 Sigma-Delta ADCs Interfaces (USCI) MSP430F4794: 60KB + 256B Flash − USCI_A0 and USCI_A1 2.5KB RAM − Enhanced UART Supporting 4 Sigma-Delta ADCs Auto-Baudrate Detection MSP430F47x3 and MSP430F47x4 Available − IrDA Encoder and Decoder In 100-Pin Plastic Quad Flatpack (QFP) − Synchronous SPI Package − USCI_B0 and USCI_B1 (cid:2) For Complete Module Descriptions, See the − I2C MSP430x4xx Family User’s Guide, − Synchronous SPI Literature Number SLAU056 (cid:2) Integrated LCD Driver With Contrast Control For Up To 160Segments description The Texas Instruments MSP430 family of ultra-low power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6μs. The MSP430F47xx series are microcontroller configurations targeted to single phase electricity meters with three or four 16-bit sigma-delta A/D converters. Each channel has a differential input pair and programmable input gain. Also integrated are two 16-bit timers, three universal serial communication interfaces (USCI), 72 I/O pins, and a liquid crystal driver (LCD) with integrated contrast control. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2011, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC 100-PIN QFP (PZ) MSP430F4783IPZ MSP430F4793IPZ −40°C to 85°C MSP430F4784IPZ MSP430F4794IPZ DEVELOPMENT TOOL SUPPORT All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging and programming through easy to use development tools. Recommended hardware options include the following: (cid:2) Debugging and Programming Interface − MSP−FET430UIF (USB) − MSP−FET430PIF (Parallel Port) (cid:2) Debugging and Programming Interface with Target Board − MSP−FET430U100 (cid:2) Production Programmer − MSP−GANG430 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 pin designation, MSP430F47xxIPZ PZ PACKAGE (TOP VIEW) T U OK VSCLK K SMCL L H/SA VCCVSS1VSS13.0−3.0+5.0/SVSINST/NMICKMS DI/TCLKDO/TDIT2INT2OUT1.0/TA01.1/TA0/MC1.2/TA11.3/TBOUT1.4/TBCLK/1.5/TACLK/1.6/CA01.7/CA1 2.0/TA22.1/TB02.2/TB1 2.3/TB2 ADA AAPRTT TTXXPPPPPPPP PPP P 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 0 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 8 7 7 7 7 1 DVCC1 1 75 P2.4/UCA0TXD/UCA0SIMO A0.0+ 2 74 P2.5/UCA0RXD/UCA0SOMI A0.0− 3 73 P2.6/CAOUT A1.0+ 4 72 P2.7 A1.0− 5 71 P3.0/UCB0STE/UCA0CLK A2.0+ 6 70 P3.1/UCB0SIMO/UCB0SDA A2.0− 7 69 P3.2/UCB0SOMI/UCB0SCL XIN 8 68 P3.3/UCB0CLK/UCA0STE XOUT 9 67 P3.4 VREF 10 66 P3.5 NC 11 65 P3.6 P5.1/S0 12 64 P3.7 S1 13 63 P4.0/UCA1TXD/UCA1SIMO P10.7/S2 14 MSP430F47x4IPZ 62 P4.1/UCA1RXD/UCA1SOMI P10.6/S3 15 61 DVSS2 P10.5/S4 16 60 DVCC2 P10.4/S5 17 59 LCDCAP/R33 P10.3/S6 18 58 P5.7/R23 P10.2/S7 19 57 P5.6/LCDREF/R13 P10.1/S8 20 56 P5.5/R03 P10.0/S9 21 55 P5.4/COM3 P9.7/S10 22 54 P5.3/COM2 P9.6/S11 23 53 P5.2/COM1 P9.5/S12 24 52 COM0 P9.4/S13 25 51 P4.2/UCB1STE/UCA1CLK/S39 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 456789 0123 456789012345678 111111 2222 222222333333333 SSSSSS SSSS SSSSSSSSSSSSSSS 3/2/1/0/7/6/ 5/4/3/2/ 1/0/7/6/5/4/3/2/1/0/7/6/E/L/A/ 9.9.9.9.8.8. 8.8.8.8. 8.8.7.7.7.7.7.7.7.7.4.4.TCD PPPPPP PPPP PPPPPPPPPPPPSSS 111 ABB CCC UUU K/MI/O/ CLOM 1SSI B11 CBB UCC P4.5/4.4/U4.3/U A3+ and A3− are not connected in MSP430x47x3 devices. PP POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 MSP430F47x3 functional block diagram XIN XOUT P3.x/P4.x P7.x/P8.x DVCC1/2 DVSS1/2 AVCC AVSS P1.x/P2.x XT2IN XT2OUT P5.x P9.x/P10.x 2 2 2x8 3x8 4x8/2x16 Ports P1/P2 Ports Ports Oscillators ACLK SD16_A P3/P4 P7/P8 Flash_A RAM (w/o BUF) 2x8I/O P5 P9/P10 FLL+ SMCLK 3 Comparator Interrupt 60kB 2.5kB Sigma− _A capability& 3x8I/O with 4x8/2x16I/O 48kB 2.0kB Delta A/D MCLK Converter pull−up/down pull−up/down pull−up/down Resistors Resistors Resistors 16MHz MAB CPU incl.16 Registers MDB Emulation (2BP) HMaurldtiwplaierer Timer_B3 LCD_A USCI_A0 USCI_A1 Brownout (32x32) Watchdog Timer_A3 (UART/LIN, (UART/LIN, JTAG Protection MPY, WDT+ 3CC Basic Timer 160 IrDA,SPI) IrDA,SPI) Interface 3CC Registers, SVS/SVM MPYS, 15/16−Bit Registers Shadow Segments USCI_B0 USCI_B1 MAC, Reg 1,2,3,4Mux (SPI,I2C) (SPI,I2C) MACS RST/NMI MSP430F47x4 functional block diagram XIN XOUT P3.x/P4.x P7.x/P8.x DVCC1/2 DVSS1/2 AVCC AVSS P1.x/P2.x XT2IN XT2OUT P5.x P9.x/P10.x 2 2 2x8 3x8 4x8/2x16 Ports P1/P2 Ports Ports Oscillators ACLK SD16_A P3/P4 P7/P8 Flash_A RAM (w/o BUF) 2x8I/O P5 P9/P10 FLL+ SMCLK 4 Comparator Interrupt 60kB 2.5kB Sigma− _A capability& 3x8I/O with 4x8/2x16I/O 48kB 2.0kB Delta A/D MCLK Converter pull−up/down pull−up/down pull−up/down Resistors Resistors Resistors 16MHz MAB CPU incl.16 Registers MDB Emulation (2BP) HMaurldtiwplaierer Timer_B3 LCD_A USCI_A0 USCI_A1 Brownout (32x32) Watchdog Timer_A3 (UART/LIN, (UART/LIN, JTAG Protection MPY, WDT+ 3CC Basic Timer 160 IrDA,SPI) IrDA,SPI) Interface 3CC Registers, SVS/SVM MPYS, 15/16−Bit Registers Shadow Segments USCI_B0 USCI_B1 MAC, Reg 1,2,3,4Mux (SPI,I2C) (SPI,I2C) MACS RST/NMI 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 Terminal Functions TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. DVCC1 1 Digital supply voltage, positive terminal. A0.0+ 2 I SD16_A positive analog input A0.0 (see Note 1) A0.0− 3 I SD16_A negative analog input A0.0 (see Note 1) A1.0+ 4 I SD16_A positive analog input A1.0 (see Note 1) A1.0− 5 I SD16_A negative analog input A1.0 (see Note 1) A2.0+ 6 I SD16_A positive analog input A2.0 (see Note 1) A2.0− 7 I SD16_A negative analog input A2.0 (see Note 1) XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT 9 O Output terminal of crystal oscillator XT1 Input for an external reference voltage / VREF 10 I/O Internal reference voltage output (can be used as mid-voltage) NC 11 Internally not connected. Can be connected to VSS. P5.1/S0 12 I/O General-purpose digital I/O / LCD segment output 0 S1 13 O LCD segment output 1 P10.7/S2 14 I/O General-purpose digital I/O / LCD segment output 2 P10.6/S3 15 I/O General-purpose digital I/O / LCD segment output 3 P10.5/S4 16 I/O General-purpose digital I/O / LCD segment output 4 P10.4/S5 17 I/O General-purpose digital I/O / LCD segment output 5 P10.3/S6 18 I/O General-purpose digital I/O / LCD segment output 6 P10.2/S7 19 I/O General-purpose digital I/O / LCD segment output 7 P10.1/S8 20 I/O General-purpose digital I/O / LCD segment output 8 P10.0/S9 21 I/O General-purpose digital I/O / LCD segment output 9 P9.7/S10 22 I/O General-purpose digital I/O / LCD segment output 10 P9.6/S11 23 I/O General-purpose digital I/O / LCD segment output 11 P9.5/S12 24 I/O General-purpose digital I/O / LCD segment output 12 P9.4/S13 25 I/O General-purpose digital I/O / LCD segment output 13 P9.3/S14 26 I/O General-purpose digital I/O / LCD segment output 14 P9.2/S15 27 I/O General-purpose digital I/O / LCD segment output 15 P9.1/S16 28 I/O General-purpose digital I/O / LCD segment output 16 P9.0/S17 29 I/O General-purpose digital I/O / LCD segment output 17 P8.7/S18 30 I/O General-purpose digital I/O / LCD segment output 18 P8.6/S19 31 I/O General-purpose digital I/O / LCD segment output 19 P8.5/S20 32 I/O General-purpose digital I/O / LCD segment output 20 P8.4/S21 33 I/O General-purpose digital I/O / LCD segment output 21 P8.3/S22 34 I/O General-purpose digital I/O / LCD segment output 22 P8.2/S23 35 I/O General-purpose digital I/O / LCD segment output 23 P8.1/S24 36 I/O General-purpose digital I/O / LCD segment output 24 P8.0/S25 37 I/O General-purpose digital I/O / LCD segment output 25 P7.7/S26 38 I/O General-purpose digital I/O / LCD segment output 26 P7.6/S27 39 I/O General-purpose digital I/O / LCD segment output 27 P7.5/S28 40 I/O General-purpose digital I/O / LCD segment output 28 P7.4/S29 41 I/O General-purpose digital I/O / LCD segment output 29 P7.3/S30 42 I/O General-purpose digital I/O / LCD segment output 30 NOTE 1: Open connection recommended for all unused analog inputs. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 Terminal Functions (Continued) TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. P7.2/S31 43 I/O General-purpose digital I/O / LCD segment output 31 P7.1/S32 44 I/O General-purpose digital I/O / LCD segment output 32 P7.0/S33 45 I/O General-purpose digital I/O / LCD segment output 33 P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34 P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35 P4.5/ General-purpose digital I/O / UCB1CLK/UCA1STE/ 48 I/O USCI_B1 clock input/output / USCI_A1 slave transmit enable / S36 LCD segment output 36 P4.4/ General-purpose digital I/O / UCB1SOMI/UCB1SCL/ 49 I/O USCI_B1 slave out/master in in SPI mode, SCL I2C clock in I2C mode / S37 LCD segment output 37 P4.3/ General-purpose digital I/O / UCB1SIMO/UCB1SDA/ 50 I/O USCI_B1 slave in/master out in SPI mode, SDA I2C data in I2C mode / S38 LCD segment output 38 P4.2/ General-purpose digital I/O / UCB1STE/UCA1CLK/ 51 I/O USCI_B1 slave transmit enable / USCI_A1 clock input/output / S39 LCD segment output 39 COM0 52 O COM0−3 are used for LCD backplanes. P5.2/COM1 53 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes. P5.3/COM2 54 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes. P5.4/COM3 55 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes. P5.5/R03 56 I/O General-purpose digital I/O / Input port of lowest analog LCD level (V5) General-purpose digital I/O / External reference voltage input for regulated LCD voltage / Input port P5.6/LCDREF/R13 57 I/O of third most positive analog LCD level (V4 or V3) P5.7/R23 58 I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2) LCDCAP/R33 59 I LCD Capacitor connection / Input/output port of most positive analog LCD level (V1) DVCC2 60 Digital supply voltage, positive terminal. DVSS2 61 Digital supply voltage, negative terminal. P4.1/ General-purpose digital I/O / 62 I/O UCA1RXD/UCA1SOMI USCI_A1 receive data input in UART mode, slave out/master in in SPI mode P4.0/ General-purpose digital I/O / 63 I/O UCA1TXD/UCA1SIMO USCI_A1 transmit data output in UART mode, slave in/master out in SPI mode P3.7 64 I/O General-purpose digital I/O P3.6 65 I/O General-purpose digital I/O P3.5 66 I/O General-purpose digital I/O P3.4 67 I/O General-purpose digital I/O P3.3/ General-purpose digital I/O / 68 I/O UCB0CLK/UCA0STE USCI_B0 clock input/output / USCI_A0 slave transmit enable P3.2/ General-purpose digital I/O / 69 I/O UCB0SOMI/UCB0SCL USCI_B1 slave out/master in in SPI mode, SCL I2C clock in I2C mode P3.1/ General-purpose digital I/O / 70 I/O UCB0SIMO/UCB0SDA USCI_B1 slave in/master out in SPI mode, SDA I2C data in I2C mode P3.0/ General-purpose digital I/O / 71 I/O UCB0STE/UCA0CLK USCI_B0 slave transmit enable / USCI_A0 clock input/output P2.7 72 I/O General-purpose digital I/O P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 Terminal Functions (Continued) TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. P2.5/ General-purpose digital I/O / USCI_A0 receive data input in UART mode, slave out/master in in SPI 74 I/O UCA0RXD/UCA0SOMI mode P2.4/ General-purpose digital I/O / USCI_A0 transmit data output in UART mode, slave in/master out in 75 I/O UCA0TXD/UCA0SIMO SPI mode P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B3 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output P2.2/TB1 77 I/O General-purpose digital I/O / Timer_B3 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output P2.1/TB0 78 I/O General-purpose digital I/O / Timer_B3 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output P2.0/TA2 79 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output P1.7/CA1 80 I/O General-purpose digital I/O / Comparator_A input P1.6/CA0 81 I/O General-purpose digital I/O / Comparator_A input P1.5/TACLK/ General-purpose digital I/O / Timer_A, clock signal TACLK input / 82 I/O ACLK ACLK output (divided by 1, 2, 4, or 8) P1.4/TBCLK/ General-purpose digital I/O / input clock TBCLK—Timer_B3 / 83 I/O SMCLK submain system clock SMCLK output P1.3/TBOUTH/ General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B3 TB0 84 I/O SVSOUT to TB2 / SVS: output of SVS comparator P1.2/TA1 85 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output. P1.1/TA0/MCLK 86 I/O Note: TA0 is only an input on this pin / BSL receive P1.0/TA0 87 I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit XT2OUT 88 O Output terminal of crystal oscillator XT2 XT2IN 89 I Input port for crystal oscillator XT2. Only standard crystals can be connected. TDO/TDI 90 I/O Test data output port. TDO/TDI data output or programming data input terminal TDI/TCLK 91 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TMS 92 I Test mode select. TMS is used as an input port for device programming and test. TCK 93 I Test clock. TCK is the clock input port for device programming and test. RST/NMI 94 I Reset input or nonmaskable interrupt input port P5.0/SVSIN 95 I/O General-purpose digital I/O / analog input to supply voltage supervisor A3.0+ SD16_A positive analog input A3.0 (see Note 2) 96 I (MSP430x47x4 only) Not connected in MSP430x47x3 devices, open connection recommended. A3.0− SD16_A negative analog input A3.0 (see Note 2) 97 I (MSP430x47x4 only) Not connected in MSP430x47x3 devices, open connection recommended. AVSS 98 Analog supply voltage, negative terminal. DVSS1 99 Digital supply voltage, negative terminal. AVCC 100 Analog supply voltage, positive terminal. Must not power up prior to DVCC1/DVCC2. NOTE 2: Open connection recommended for all unused analog inputs. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture Program Counter PC/R0 that is highly transparent to the application. All operations, other than program-flow instructions, Stack Pointer SP/R1 are performed as register operations in Status Register SR/CG1/R2 conjunction with seven addressing modes for source operand and four addressing modes for Constant Generator CG2/R3 destination operand. General-Purpose Register R4 The CPU is integrated with 16 registers that provide reduced instruction execution time. The General-Purpose Register R5 register-to-register operation execution time is one cycle of the CPU clock. General-Purpose Register R6 Four of the registers, R0 to R3, are dedicated as General-Purpose Register R7 program counter, stack pointer, status register, and constant generator respectively. The General-Purpose Register R8 remaining registers are general-purpose registers. General-Purpose Register R9 Peripherals are connected to the CPU using data, General-Purpose Register R10 address, and control buses, and can be handled with all instructions. General-Purpose Register R11 instruction set General-Purpose Register R12 The instruction set consists of 51 instructions with three formats and seven address modes. Each General-Purpose Register R13 instruction can operate on word and byte data. Table1 shows examples of the three types of General-Purpose Register R14 instruction formats; the address modes are listed General-Purpose Register R15 in Table2. Table 1. Instruction Word Formats Dual operands, source-destination e.g., ADD R4, R5 R4 + R5 −−−> R5 Single operands, destination only e.g., CALL R8 PC −−>(TOS), R8−−> PC Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0 Table 2. Address Mode Descriptions ADDRESS MODE S D SYNTAX EXAMPLE OPERATION (cid:2) (cid:2) Register MOV Rs, Rd MOV R10, R11 R10 −−> R11 (cid:2) (cid:2) Indexed MOV X(Rn), Y(Rm) MOV 2(R5), 6(R6) M(2+R5)−−> M(6+R6) (cid:2) (cid:2) Symbolic (PC relative) MOV EDE, TONI M(EDE) −−> M(TONI) (cid:2) (cid:2) Absolute MOV &MEM, &TCDAT M(MEM) −−> M(TCDAT) (cid:2) Indirect MOV @Rn, Y(Rm) MOV @R10, Tab(R6) M(R10) −−> M(Tab+R6) Indirect (cid:2) M(R10) −−> R11 MOV @Rn+, Rm MOV @R10+, R11 autoincrement R10 + 2−−> R10 (cid:2) Immediate MOV #X, TONI MOV #45, TONI #45 −−> M(TONI) NOTE: S = source D = destination 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 operating modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: (cid:2) Active mode AM − All clocks are active (cid:2) Low-power mode 0 (LPM0) − CPU is disabled. − ACLK and SMCLK remain active. − MCLK is disabled. − FLL+ loop control remains active (cid:2) Low-power mode 1(LPM1) − CPU is disabled. − FLL+ loop control is disabled. − ACLK and SMCLK remain active. − MCLK is disabled. (cid:2) Low-power mode 2 (LPM2) − CPU is disabled. − MCLK, FLL+ loop control, and DCOCLK are disabled. − DCO’s dc generator remains enabled. − ACLK remains active. (cid:2) Low-power mode 3 (LPM3) − CPU is disabled. − MCLK, FLL+ loop control, and DCOCLK are disabled. − DCO’s dc generator is disabled. − ACLK remains active. (cid:2) Low-power mode 4 (LPM4) − CPU is disabled. − ACLK is disabled. − MCLK, FLL+ loop control, and DCOCLK are disabled. − DCO’s dc generator is disabled. − Crystal oscillator is stopped. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU goes into LPM4 immediately after power-up. WORD INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT PRIORITY ADDRESS Power-Up PORIFG Reset 0FFFEh 15, highest External Reset RSTIFG Watchdog WDTIFG Flash Memory KEYV PC Out−of−Range (see Note 4) (see Note 1) NMI NMIIFG (see Notes 1 and 3) (Non)maskable Oscillator Fault OFIFG (see Notes 1 and 3) (Non)maskable 0FFFCh 14 Flash Memory Access Violation ACCVIFG (see Notes 1 and 3) (Non)maskable Timer_B3 TBCCR0 CCIFG (see Note 2) Maskable 0FFFAh 13 TBCCR1 to TBCCR2 CCIFGs Timer_B3 Maskable 0FFF8h 12 TBIFG (see Notes 1 and 2) Comparator_A CAIFG Maskable 0FFF6h 11 Watchdog Timer WDTIFG Maskable 0FFF4h 10 USCI_A0/B0 Receive UCA0RXIFG, UCB0RXIFG Maskable 0FFF2h 9 (see Note 1 and 5) USCI_A0/B0 Transmit UCA0TXIFG, UCB0TXIFG Maskable 0FFF0h 8 (see Note 1 and 6) SD16_A SD16CCTLx SD16OVIFG, Maskable 0FFEEh 7 SD16CCTLx SD16IFG (see Notes 1 and 2) Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 6 TACCR1 and TACCR2 CCIFGs, Timer_A3 Maskable 0FFEAh 5 TAIFG (see Notes 1 and 2) I/O Port P1 P1IFG.0 to P1IFG.7 Maskable 0FFE8h 4 (Eight Flags) (see Notes 1 and 2) USCI_A1/B1 Receive UCA1RXIFG, UCB1RXIFG Maskable 0FFE6h 3 (see Notes 1 and 2) USCI_A1/B1 Transmit UCA1TXIFG, UCB1TXIFG Maskable 0FFE4h 2 (see Notes 1 and 2) I/O Port P2 P2IFG.0 to P2IFG.7 Maskable 0FFE2h 1 (Eight Flags) (see Notes 1 and 2) Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest NOTES: 1. Multiple source flags 2. Interrupt flags are located in the module. 3. (Non)maskable: The individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. 4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh). 5. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG in register UCB0STAT. 6. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG. 7. In SPI mode: UCB1RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG in register UCB1STAT. 8. In UART/SPI mode: UCB1TXIFG. In I2C mode: UCB1RXIFG, UCB1TXIFG. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 special function registers Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access. interrupt enable 1 and 2 Address 7 6 5 4 3 2 1 0 00h ACCVIE NMIIE OFIE WDTIE rw−0 rw−0 rw−0 rw−0 WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. OFIE Oscillator fault enable NMIIE (Non)maskable interrupt enable ACCVIE Flash access violation interrupt enable Address 7 6 5 4 3 2 1 0 01h BTIE UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw−0 rw−0 rw−0 rw−0 rw−0 UCA0RXIE USCI_A0 receive interrupt enable UCA0TXIE USCI_A0 transmit interrupt enable UCB0RXIE USCI_B0 receive interrupt enable UCB0TXIE USCI_B0 transmit interrupt enable BTIE Basic timer interrupt enable POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 interrupt flag register 1 and 2 Address 7 6 5 4 3 2 1 0 02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw−0 rw−(0) rw−(1) rw−1 rw−(0) WDTIFG Set on watchdog timer overflow or security key violation. Reset on V power-up or a reset condition at RST/NMI pin in reset mode. CC OFIFG Flag set on oscillator fault RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up. PORIFG Power-on interrupt flag. Set on V power-up. CC NMIIFG Set via RST/NMI pin Address 7 6 5 4 3 2 1 0 UCB0 UCB0 UCA0 UCA0 03h BTIFG TXIFG RXIFG TXIFG RXIFG rw−0 rw−1 rw−0 rw−1 rw−0 UCA0RXIFG USCI_A0 receive interrupt flag UCA0TXIFG USCI_A0 transmit interrupt flag UCB0RXIFG USCI_B0 receive interrupt flag UCB0TXIFG USCI_B0 transmit interrupt flag BTIFG Basic Timer1 interrupt flag Legend rw: Bit can be read and written. rw-0, 1: Bit can be read and written. It is Reset or Set by PUC. rw-(0, 1): Bit can be read and written. It is Reset or Set by POR. SFR bit is not present in device 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 memory organization MSP430F4783/MSP430F4784 MSP430F4793/MSP430F4794 Memory Size 48KB 60KB Main: interrupt vector Flash 0FFFFh to 0FFE0h 0FFFFh to 0FFE0h Main: code memory Flash 0FFFFh to 04000h 0FFFFh to 01100h Information memory Size 256 Byte 256 Byte Flash 010FFh to 01000h 010FFh to 01000h Boot memory Size 1KB 1KB ROM 0FFFh to 0C00h 0FFFh to 0C00h RAM Size 2KB 2.5KB 09FFh to 0200h 0BFFh to 0200h Peripherals 16-bit 01FFh to 0100h 01FFh to 0100h 8-bit 0FFh to 010h 0FFh to 010h 8-bit SFR 0Fh to 00h 0Fh to 00h bootstrap loader (BSL) The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to device memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader, literature number SLAA089. BSL FUNCTION PZ PACKAGE PINS Data transmit 87 - P1.0 Data receive 86 - P1.1 flash memory, flash The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: (cid:2) Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size. (cid:2) Segments 0 to n may be erased in one step, or each segment may be individually erased. (cid:2) Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory. (cid:2) Segment A might contain calibration data. After reset, segment A is protected against programming or erasing. It can be unlocked but care should be taken not to erase this segment if the calibration data is required. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number SLAU056. digital I/O There are nine 8-bit I/O ports implemented—ports P1 through P5 and P7 through P10. (cid:2) All individual I/O bits are independently programmable. (cid:2) Any combination of input, output, and interrupt conditions is possible. (cid:2) Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. (cid:2) Read/write access to port-control registers is supported by all instructions. (cid:2) Ports P7/P8 and P9/P10 can be accessed word-wise as ports PA and PB respectively. (cid:2) Each I/O has an individually programmable pullup/pulldown resistor. oscillator and system clock The clock system in the MSP430x47xx is supported by the FLL+ module, which includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a 8-MHz high-frequency crystal oscillator (XT1), plus a 16-MHz high-frequency crystal oscillator (XT2). The FLL+ clock module is designed to meet the requirements of both low system cost and low power consumption. The FLL+ features digital frequency-locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The FLL+ module provides the following clock signals: (cid:2) Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal (cid:2) Main clock (MCLK), the system clock used by the CPU (cid:2) Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules (cid:2) ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8 brownout, supply voltage supervisor (SVS) The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, V may not CC have ramped to V at that time. The user must ensure the default FLL+ settings are not changed until V CC(min) CC reaches V . If desired, the SVS circuit can be used to determine when V reaches V . CC(min) CC CC(min) hardware multiplier The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply-and-accumulate operations. watchdog timer (WDT+) The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 universal serial communication interfaces (USCI_A0, USCI_B0, USCI_A1, USCI_B1) The universal serial communication interface (USCI) module is used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3-pin or 4-pin), I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA. USCI_A0 and USCI_A1 provide support for SPI (3-pin or 4-pin), UART, enhanced UART, and IrDA. USCI_B0 and USCI_B1 provide support for SPI (3-pin or 4-pin) and I2C. timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. TIMER_A3 SIGNAL CONNECTIONS INPUT PIN DEVICE INPUT MODULE INPUT MODULE OUTPUT OUTPUT PIN MODULE BLOCK NUMBER SIGNAL NAME SIGNAL NUMBER 82 - P1.5 TACLK TACLK ACLK ACLK TTiimmeerr NNAA SMCLK SMCLK 82 - P1.5 TACLK INCLK 87 - P1.0 TA0 CCI0A 87 - P1.0 86 - P1.1 TA0 CCI0B CCCCRR00 TTAA00 DVSS GND DVCC VCC 85 - P1.2 TA1 CCI1A 85 - P1.2 CAOUT (internal) CCI1B CCCCRR11 TTAA11 DVSS GND DVCC VCC 79 - P2.0 TA2 CCI2A 79 - P2.0 ACLK (internal) CCI2B CCCCRR22 TTAA22 DVSS GND DVCC VCC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 timer_B3 Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. TIMER_B3 SIGNAL CONNECTIONS INPUT PIN DEVICE INPUT MODULE INPUT MODULE OUTPUT OUTPUT PIN MODULE BLOCK NUMBER SIGNAL NAME SIGNAL NUMBER 83 - P1.4 TBCLK TBCLK ACLK ACLK TTiimmeerr NNAA SMCLK SMCLK 83 - P1.4 TBCLK INCLK 78 - P2.1 TB0 CCI0A 78 - P2.1 78 - P2.1 TB0 CCI0B CCCCRR00 TTBB00 DVSS GND DVCC VCC 77 - P2.2 TB1 CCI1A 77 - P2.2 77 - P2.2 TB1 CCI1B CCCCRR11 TTBB11 DVSS GND DVCC VCC 76 - P2.3 TB2 CCI2A 76 - P2.3 76 - P2.3 TB2 CCI2B CCCCRR22 TTBB22 DVSS GND DVCC VCC 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 comparator_A The primary function of the comparator_A module is to support precision slope A/D conversions, battery-voltage supervision, and monitoring of external analog signals. SD16_A The SD16_A module integrates three (in MSP430F47x3) or four (in MSP430F47x4) independent 16-bit sigma−delta A/D converters. Each channel is designed with a fully differential analog input pair and programmable-gain amplifier input stage. In addition to external analog inputs, an internal V sense and CC temperature sensor are also available. Basic Timer1 The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Basic Timer1 can be used to generate periodic interrupts and a clock for the LCD module. LCD driver with regulated charge pump The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral. The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump. Furthermore, it is possible to control the level of the LCD voltage and, thus, contrast in software. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 peripheral file map PERIPHERALS WITH WORD ACCESS Watchdog Watchdog timer control WDTCTL 0120h Flash_A Flash control 4 FCTL4 01BEh Flash control 3 FCTL3 012Ch Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h Timer__B3 Capture/compare register 2 TBCCR2 0196h Capture/compare register 1 TBCCR1 0194h Capture/compare register 0 TBCCR0 0192h Timer_B register TBR 0190h Capture/compare control 2 TBCCTL2 0186h Capture/compare control 1 TBCCTL1 0184h Capture/compare control 0 TBCCTL0 0182h Timer_B control TBCTL 0180h Timer_B interrupt vector TBIV 011Eh Timer__A3 Capture/compare register 2 TACCR2 0176h Capture/compare register 1 TACCR1 0174h Capture/compare register 0 TACCR0 0172h Timer_A register TAR 0170h Capture/compare control 2 TACCTL2 0166h Capture/compare control 1 TACCTL1 0164h Capture/compare control 0 TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interrupt vector TAIV 012Eh 32-bit Hardware MPY32 control 0 MPY32CTL0 015Ch MMullttiiplliier 64-bit result 3 − most significant word RES3 015Ah 64-bit result 2 RES2 0158h 64-bit result 1 RES1 0156h 64-bit result 0 − least significant word RES0 0154h Second 32-bit operand, high word OP2H 0152h Second 32-bit operand, low word OP2L 0150h Multiply signed + accumulate/ MACS32H 014Eh 32-bit operand1, high word Multiply signed + accumulate/ MACS32L 014Ch 32-bit operand1, low word Multiply + accumulate/ MAC32H 014Ah 32-bit operand1, high word Multiply + accumulate/ MAC32L 0148h 32-bit operand1, low word Multiply signed/32-bit operand1, high word MPYS32H 0146h Multiply signed/32-bit operand1, low word MPYS32L 0144h Multiply unsigned/32-bit operand1, high word MPY32H 0142h Multiply unsigned/32-bit operand1, low word MPY32L 0140h 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 peripheral file map (continued) PERIPHERALS WITH WORD ACCESS (CONTINUED) 32-bit Hardware Sum extend SUMEXT 013Eh Multiplier Result high word RESHI 013Ch Result low word RESLO 013Ah Second operand OP2 0138h Multiply signed + accumulate/operand1 MACS 0136h Multiply + accumulate/operand1 MAC 0134h Multiply signed/operand1 MPYS 0132h Multiply unsigned/operand1 MPY 0130h USCI_B0 USCI_B0 I2C own address UCB0I2COA 016Ch ((sseeee aallssoo:: Peripherals with USCI_B0 I2C slave address UCB0I2CSA 016Eh Byte Access) USCI_B1 USCI_B1 I2C own address UCB1I2COA 017Ch ((sseeee aallssoo:: Peripherals with USCI_B1 I2C slave address UCB1I2CSA 017Eh Byte Access) SD16__A General control SD16CTL 0100h ((see allso: Channel 0 control SD16CCTL0 0102h PPeerriipphheerraallss wwiitthh Byyte Access)) Channel 1 control SD16CCTL1 0104h Channel 2 control SD16CCTL2 0106h Channel 3 control SD16CCTL3 0108h Interrupt vector word register SD16IV 0110h Channel 0 conversion memory SD16MEM0 0112h Channel 1 conversion memory SD16MEM1 0114h Channel 2 conversion memory SD16MEM2 0116h Channel 3 conversion memory SD16MEM3 0118h Port PA Port PA resistor enable PAREN 014h Port PA selection PASEL 03Eh Port PA direction PADIR 03Ch Port PA output PAOUT 03Ah Port PA input PAIN 038h Port PB Port PB resistor enable PBREN 016h Port PB selection PBSEL 00Eh Port PB direction PBDIR 00Ch Port PB output PBOUT 00Ah Port PB input PBIN 008h POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS SD16_A Channel 0 input control SD16INCTL0 0B0h (see also: Channel 1 input control SD16INCTL1 0B1h Peripherals with Channel 2 input control SD16INCTL2 0B2h Word Access) Channel 3 input control SD16INCTL3 0B3h Channel 0 preload SD16PRE0 0B8h Channel 1 preload SD16PRE1 0B9h Channel 2 preload SD16PRE2 0BAh Channel 3 preload SD16PRE3 0BBh Reserved (internal SD16 Configuration 1) SD16CONF1 0BFh LCD_A LCD voltage control 1 LCDAVCTL1 0AFh LCD voltage control 0 LCDAVCTL0 0AEh LCD voltage port control 1 LCDAPCTL1 0ADh LCD voltage port control 0 LCDAPCTL0 0ACh LCD memory 20 LCDM20 0A4h : : : LCD memory 16 LCDM16 0A0h LCD memory 15 LCDM15 09Fh : : : LCD memory 1 LCDM1 091h LCD control and mode LCDACTL 090h USCI_A0 USCI_A0 transmit buffer UCA0TXBUF 067h USCI_A0 receive buffer UCA0RXBUF 066h USCI_A0 status UCA0STAT 065h USCI_A0 modulation control UCA0MCTL 064h USCI_A0 baud rate control 1 UCA0BR1 063h USCI_A0 baud rate control 0 UCA0BR0 062h USCI_A0 control 1 UCA0CTL1 061h USCI_A0 control 0 UCA0CTL0 060h USCI_A0 IrDA receive control UCA0IRRCTL 05Fh USCI_A0 IrDA transmit control UCA0IRTCTL 05Eh USCI_A0 auto baud rate control UCA0ABCTL 05Dh USCI_B0 USCI_B0 transmit buffer UCB0TXBUF 06Fh USCI_B0 receive buffer UCB0RXBUF 06Eh USCI_B0 status UCB0STAT 06Dh USCI_B1 I2C interrupt enable UCB0I2CIE 06Ch USCI_B0 bit rate control 1 UCB0BR1 06Bh USCI_B0 bit rate control 0 UCB0BR0 06Ah USCI_B0 control 1 UCB0CTL1 069h USCI_B0 control 0 UCB0CTL0 068h USCI_A1 USCI_A1 transmit buffer UCA1TXBUF 0D7h USCI_A1 receive buffer UCA1RXBUF 0D6h USCI_A1 status UCA1STAT 0D5h USCI_A1 modulation control UCA1MCTL 0D4h USCI_A1 baud rate control 1 UCA1BR1 0D3h USCI_A1 baud rate control 0 UCA1BR0 0D2h USCI_A1 control 1 UCA1CTL1 0D1h USCI_A1 control 0 UCA1CTL0 0D0h USCI_A1 IrDA receive control UCA1IRRCTL 0CFh USCI_A1 IrDA transmit control UCA1IRTCTL 0CEh USCI_A1 auto baud rate control UCA1ABCTL 0CDh USCI_A1 interrupt flag UC1IFG 007h USCI_A1 interrupt enable UC1IE 006h 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS (CONTINUED) USCI_B1 USCI_B1 transmit buffer UCB1TXBUF 0DFh USCI_B1 receive buffer UCB1RXBUF 0DEh USCI_B1 status UCB1STAT 0DDh USCI_B1 I2C interrupt enable UCB1I2CIE 0DCh USCI_B1 bit rate control 1 UCB1BR1 0DBh USCI_B1 bit rate control 0 UCB1BR0 0DAh USCI_B1 control 1 UCB1CTL1 0D9h USCI_B1 control 0 UCB1CTL0 0D8h USCI_A1 interrupt flag UC1IFG 007h USCI_A1 interrupt enable UC1IE 006h Compparator__A Comparator_A port disable CAPD 05Bh Comparator_A control2 CACTL2 05Ah Comparator_A control1 CACTL1 059h BrownOUT, SVS SVS control register (reset by brownout signal) SVSCTL 056h FLL+ Clock FLL+ control 2 FLL_CTL2 055h FLL+ control 1 FLL_CTL1 054h FLL+ control 0 FLL_CTL0 053h System clock frequency control SCFQCTL 052h System clock frequency integrator SCFI1 051h System clock frequency integrator SCFI0 050h Basic Timer1 BT counter 2 BTCNT2 047h BT counter 1 BTCNT1 046h BT control BTCTL 040h Port P10 Port P10 resistor enable P10REN 017h Port P10 selection P10SEL 00Fh Port P10 direction P10DIR 00Dh Port P10 output P10OUT 00Bh Port P10 input P10IN 009h Port P9 Port P9 resistor enable P9REN 016h Port P9 selection P9SEL 00Eh Port P9 direction P9DIR 00Ch Port P9 output P9OUT 00Ah Port P9 input P9IN 008h Port P8 Port P8 resistor enable P8REN 015h Port P8 selection P8SEL 03Fh Port P8 direction P8DIR 03Dh Port P8 output P8OUT 03Bh Port P8 input P8IN 039h Port P7 Port P7 resistor enable P7REN 014h Port P7 selection P7SEL 03Eh Port P7 direction P7DIR 03Ch Port P7 output P7OUT 03Ah Port P7 input P7IN 038h POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS (CONTINUED) Port P5 Port P5 resistor enable P5REN 012h Port P5 selection P5SEL 033h Port P5 direction P5DIR 032h Port P5 output P5OUT 031h Port P5 input P5IN 030h Port P4 Port P4 resistor enable P4REN 011h Port P4 selection P4SEL 01Fh Port P4 direction P4DIR 01Eh Port P4 output P4OUT 01Dh Port P4 input P4IN 01Ch Port P3 Port P3 resistor enable P3REN 010h Port P3 selection P3SEL 01Bh Port P3 direction P3DIR 01Ah Port P3 output P3OUT 019h Port P3 input P3IN 018h Port P2 Port P2 resistor enable P2REN 02Fh Port P2 selection P2SEL 02Eh Port P2 interrupt enable P2IE 02Dh Port P2 interrupt-edge select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h Port P1 Port P1 resistor enable P1REN 027h Port P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt-edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h Sppecial functions SFR interrupt flag2 IFG2 003h SFR interrupt flag1 IFG1 002h SFR interrupt enable2 IE2 001h SFR interrupt enable1 IE1 000h 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 absolute maximum ratings (see Note 1) Voltage applied at V to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V CC SS Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA Storage temperature, T : (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C stg (programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TDI/TCLK pin when blowing the JTAG fuse. 3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 recommended operating conditions MIN NOM MAX UNIT Supply voltage during program execution, 1.8 3.6 V VCC (AVCC = DVCC = VCC) (see Note 1) Supply voltage during program execution, SVS enabled, PORON = 1, 2.0 3.6 V VCC (AVCC = DVCC = VCC) (see Notes 1, 2) Supply voltage during program/erase flash memory, 2.2 3.6 V VCC (AVCC = DVCC = VCC) (see Note 1) Supply voltage, VSS 0 V Operating free-air temperature range, TA −40 85 °C VCC = 1.8 V, dc 4.15 MHz Duty Cycle = 50% ±10% VCC = 2.2 V, dc 7.5 MHz PPrroocceessssoorr ffrreeqquueennccyy ffSSYYSSTTEEMM ((MMaaxxiimmuumm MMCCLLKK ffrreeqquueennccyy)) Duty Cycle = 50% ±10% (see Notes 3, 4 and Figure 1) VCC = 2.7 V, dc 12 Duty Cycle = 50% ±10% MMHHzz VCC ≥ 3.3 V, dc 16 Duty Cycle = 50% ±10% NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3V between AVCC and DVCC can be tolerated during power up and operation. 2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage. POR is going inactive when the supply voltage is raised abve minimum supply voltage plus the hysteresis of the SVS circuitry. 3. The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. 4. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this datasheet. Legend: 16MHz ÏÏÏÏÏÏÏÏÏ ÏÏ Supply voltage range, ÏÏÏÏÏÏÏÏÏ ÏÏ during flash memory z MH ÏÏÏÏÏÏÏÏÏ ÏÏ programming − 12MHz y ÏÏÏÏÏÏÏÏÏ ÏÏ c n e Supply voltage range, u ÏÏÏÏÏÏÏÏÏ ÏÏ q during program execution e Fr 7.5MHz ÏÏÏÏÏÏÏÏÏ ÏÏ m e ÏÏÏÏÏÏÏÏÏ st y S 4.15MHz ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏ 1.8V 2.2V 2.7V 3.3V 3.6V Supply Voltage−V NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V. Figure 1. Operating Area 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) supply current into AV + DV excluding external current CC CC PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Active mode, (see Note 1) f((MCLK)) = f((SMCLK)) = 1 MHz, VCC = 2.2 V 280 350 II(AM) ff(ACLK) = 3322, 776688 HHzz TTA = −4400°°CC ttoo 8855°°CC μAA XTS_FLL = 0, SELM = (0, 1) VCC = 3 V 420 560 (Program executes from flash) LLooww-ppoowweerr mmooddee,, ((LLPPMM00)) VCC = 2.2 V 45 70 II(LPM0) (see Notes 1, 4) TTA = −4400°°CC ttoo 8855°°CC VCC = 3 V 75 110 μAA Low-power mode, (LPM2), VCC = 2.2 V 11 14 II(LPM2) ff(MCLK) = ff (SMCLK) = 00 MMHHzz, TTA = −4400°°CC ttoo 8855°°CC μAA f(ACLK) = 32, 768 Hz, SCG0 = 0 (see Notes 2, 4) VCC = 3 V 17 22 TA = −40°C 1.0 2.0 LLooww-ppoowweerr mmooddee, ((LLPPMM33)) ffff((((AMMACCCCLLLLKKKK)))) === 33ff((22SS,,MM 77CC66LL88KK ))HH ==zz ,,00 SS MMCCHHGGzz00,, = 11 TTAA == 2650°°CC VVCC = 22.22 VV 12..10 23..00 μAA Basic Timer1 enabled, ACLK selected TA = 85°C 3.0 6.0 II(LPM3) LL((ssCCttaaDDttii_ccAA mm eeoonnddaaeebb,, lleeffLLddCC,DD LL CC== DDff((AACCCCPPLLEEKKNN)) // 33=22 00)), TA = −40°C 1.2 3.0 ((sseeee NNootteess 22,, 33,, 44)) TA = 25°C 1.3 3.0 TA = 60°C VVCC = 33 VV 2.5 3.5 μAA TA = 85°C 3.5 7.5 TA = −40°C 3.5 5.5 LLooww-ppoowweerr mmooddee, ((LLPPMM33)) ffff((((AMMACCCCLLLLKKKK)))) === 33ff((22SS,,MM 77CC66LL88KK ))HH ==zz ,,00 SS MMCCHHGGzz00,, = 11 TTAA == 2650°°CC VVCC = 22.22 VV 35..55 57..50 μAA Basic Timer1 enabled, ACLK selected TA = 85°C 11.0 17.0 II(LPM3) LL((44CC−−DDmm_uuAAxx eemmnnooaaddbbeellee,, ddffLL, CCLLDDCC ==DD CCff((AAPPCCEELLNNKK )) =//33 0022,)) TA = −40°C 4.0 8.0 ((sseeee NNootteess 22,, 33,, 44)) TA = 25°C 4.0 6.5 TA = 60°C VVCC = 33 VV 6.0 8.0 μAA TA = 85°C 13.0 20.0 TA = −40°C 0.1 1.0 TA = 25°C 0.2 1.0 LLooww--ppoowweerr mmooddee, ((LLPPMM44)) TA = 60°C VVCC = 22.22 VV 1.0 2.0 μAA II(LPM4) fff((((MMAACCCCLLLLKKKK)))) === 000 HMMzHH, zzS,,C ff((GSSMM0 CC=LL KK1)) == 00 MMHHzz,, TTAA == −854°0C°C 10..81 52..00 ((see NNottes 22, 44)) TA = 25°C 0.2 2.0 TA = 60°C VVCC = 33 VV 1.5 2.5 μAA TA = 85°C 2.0 6.0 NOTES: 1. Timer_A is clocked by f(DCOCLK) = f(DCO) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. 2. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. 3. The LPM3 currents are characterized with a Micro Crystal CC4V−T1A (9 pF) crystal and OSCCAPx = 1h. 4. Current for brownout included. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 typical characteristics − active mode supply current (into V ) CC 10.0 9.0 5.0 TA = 85 °C fDCO = 16 MHz 8.0 TA = 25 °C A A m m 4.0 Current − 67..00 fDCO = 12 MHz Current − 3.0 Mode 45..00 fDCO = 8 MHz Mode VCC = 3 V TA = 85 °C Active 3.0 Active 2.0 TA = 25 °C 2.0 1.0 VCC = 2.2 V 1.0 fDCO = 1 MHz 0.0 0.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 4.0 8.0 12.0 16.0 VCC − Supply Voltage − V fDCO − DCO Frequency − MHz Figure 2. Active mode current vs V , T = 25°C Figure 3. Active mode current vs DCO frequency CC A 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs − Ports P1 through P5, P7 through P10, RST/NMI, JTAG: TCK, TMS, TDI/TCLK, TDO/TDI PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 0.45 0.75 VCC PPosiittiive-goiing iinputt tthhreshholldd VVIITT++ vvoollttaaggee 2.2 V 1.00 1.65 VV 3 V 1.35 2.25 0.25 0.55 VCC NNegattiive-goiing iinputt tthhreshholldd VVIITT−− vvoollttaaggee 2.2 V 0.55 1.20 VV 3 V 0.75 1.65 VVhys IIVnnIppTuu−)tt vvoollttaaggee hhyysstteerreessiiss ((VVIITT++ − 23.2 V V 00..23 11..00 VV RPull P(nuollt− RuSp/Tp/uNllM−dI oawndn JreTsAisGto prins) FFoorr ppuullll−−udpo:w VnI:N V =IN V =S SV,C C 20 35 50 k(cid:2) CI Input Capacitance VIN = VSS or VCC 5 pF inputs − Ports P1, P2 PARAMETER TEST CONDITIONS VCC MIN MAX UNIT Port P1, P2: P1.x to P2.x, External t(int) External interrupt timing trigger puls width to set interrupt flag, 2.2 V/3 V 20 ns (see Note 1) NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t(int) is met. It may be set even with trigger signals shorter than t(int). leakage current − Ports P1 through P5, P7 through P10 PARAMETER TEST CONDITIONS VCC MIN MAX UNIT Ilkg(Px.x) High-impedance leakage current see Notes 1 and 2 2.2 V/3 V ±50 nA NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1 through P5, P7 through P10 PARAMETER TEST CONDITIONS VCC MIN MAX UNIT I(OHmax) = −1.5 mA (see Notes 1) 2.2 V VCC−0.25 VCC I(OHmax) = −6 mA (see Notes 2) 2.2 V VCC−0.6 VCC VVOH HHiigghh-lleevveell oouuttppuutt vvoollttaaggee I(OHmax) = −1.5 mA (see Notes 1) 3 V VCC−0.25 VCC VV I(OHmax) = −6 mA (see Notes 2) 3 V VCC−0.6 VCC I(OLmax) = 1.5 mA (see Notes 1) 2.2 V VSS VSS+0.25 I(OLmax) = 6 mA (see Notes 2) 2.2 V VSS VSS+0.6 VVOL LLooww-lleevveell oouuttppuutt vvoollttaaggee I(OLmax) = 1.5 mA (see Notes 1) 3 V VSS VSS+0.25 VV I(OLmax) = 6 mA (see Notes 2) 3 V VSS VSS+0.6 NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop specified. 2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified. output frequency − Ports P1 through P5, P7 through P10 PARAMETER TEST CONDITIONS VCC MIN MAX UNIT P1.4/TBCLK/SMCLK, 2.2 V 10 MHz PPoorrtt oouuttppuutt ffrreeqquueennccyy ((wwiitthh ffPx.y load) CC(sLe e= N2200o tppeFF 1, RRanL d= 211) kk(cid:2)(cid:2) aaggaaiinnsstt VVCC//22 3 V 12 MHz P1.1/TA0/MCLK, P1.5/TACLK/ACLK, 2.2 V 12 MHz ffPort_CLK CClloocckk oouuttppuutt ffrreeqquueennccyy PP11.44//TTBBCCLLKK//SSMMCCLLKK, CL = 20 pF (see Note 2) 3 V 16 MHz NOTES: 1. Alternatively a resistive divider with 2 times 2 k(cid:2) between VCC and VSS is used as load. The output is connected to the center tap of the divider. 2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics − outputs TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT vs vs LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE 30.0 55.0 − mA VPC2.C4 = 2.2 V TA = 25°C − mA 50.0 VPC2.C4 = 3 V ent 25.0 ent 45.0 TA = 25°C urr urr 40.0 put C 20.0 TA = 85°C put C 35.0 TA = 85°C ut ut O O 30.0 el 15.0 el v v e e 25.0 L L w- w- o o 20.0 L 10.0 L cal cal 15.0 pi pi − Ty 5.0 − Ty 10.0 OL OL 5.0 I I 0.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOL − Low-Level Output Voltage − V VOL − Low-Level Output Voltage − V Figure 4 Figure 5 TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT vs vs HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE 0.0 0.0 ent − mA −5.0 VPC2.C4 = 2.2 V nt − mA −−150..00 VPC2.C4 = 3 V urr rre C u −15.0 Output −10.0 utput C −20.0 vel −15.0 el O −25.0 e v L e −30.0 gh- h-L cal Hi −20.0 al Hig −−4305..00 − TypiH −25.0 TA = 85°C − Typic −45.0 TA = 85°C IO −30.0 TA = 25°C IOH −50.0 TA = 25°C −55.0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH − High-Level Output Voltage − V VOH − High-Level Output Voltage − V Figure 6 Figure 7 NOTE: One output loaded at a time. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) POR/brownout reset (BOR) (see Notes 1 and 2) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(start) (see Figure 8) dVCC/dt ≤ 3 V/s 0.7 × V(B_IT−) V V(B_IT−) (see Figure 8 through Figure 10) dVCC/dt ≤ 3 V/s 1.71 V Vhys(B_IT−) (see Figure 8) dVCC/dt ≤ 3 V/s 70 130 180 mV td(BOR) (see Figure 8) 2000 μs Pulse length needed at RST/NMI pin t(reset) to accepted reset internally 2.2 V/3 V 2 μs NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT−) + Vhys(B_IT−) is ≤ 1.8V. 2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−). The default FLL+ settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit. V CC V hys(B_IT−) V (B_IT−) VCC(start) 1 0 td(BOR) Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics − POR/brownout reset (BOR) 2 VCC tpw 3 V VCC = 3 V Typical Conditions V 1.5 − p) o r 1 d C( C VCC(drop) V 0.5 0 0.001 1 1000 1 ns 1 ns tpw − Pulse Width − μs tpw − Pulse Width − μs Figure 9. V Level With a Square Voltage Drop to Generate a POR/Brownout Signal CC(drop) VCC tpw 2 3 V VCC = 3 V V 1.5 Typical Conditions − p) o dr 1 C( C VCC(drop) V 0.5 tf = tr 0 0.001 1 1000 tf tr tpw − Pulse Width − μs tpw − Pulse Width − μs Figure 10. V Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal CC(drop) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) SVS (supply voltage supervisor/monitor) (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tt(SVSR) ddVVCCCC//ddtt >≤ 3300 VV//mmss (see Figure 11) 5 2105000 μμss td(SVSon) SVSon, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V 150 300 μs tsettle VLD ≠ 0 (see Note 2) 12 μs V(SVSstart) VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 11) 1.55 1.7 V VLD = 1 70 120 155 mV VCC/dt ≤ 3 V/s (see Figure 11) VLD = 2 .. 14 V(SVS_IT−) V(SVS_IT−) VVhhyyss((SSVVSS__IITT−−)) x 0.001 x 0.016 VCC/dt ≤ 3 V/s (see Figure 11), external voltage applied VLD = 15 4.4 10.4 mV onA7 VLD = 1 1.8 1.9 2.05 VLD = 2 1.94 2.1 2.25 VLD = 3 2.05 2.2 2.37 VLD = 4 2.14 2.3 2.48 VLD = 5 2.24 2.4 2.6 VLD = 6 2.33 2.5 2.71 VLD = 7 2.46 2.65 2.86 VVCCCC//ddtt ≤≤ 33 VV//ss ((sseeee FFiigguurree 1111)) VLD = 8 2.58 2.8 3 VV((SSVVSS_IITT−)) VV VLD = 9 2.69 2.9 3.13 VLD = 10 2.83 3.05 3.29 VLD = 11 2.94 3.2 3.42 VLD = 12 3.11 3.35 3.61† VLD = 13 3.24 3.5 3.76† VLD = 14 3.43 3.7† 3.99† VCC/dt ≤ 3 V/s (see Figure 11), external voltage applied VLD = 15 1.1 1.2 1.3 onA7 I(CseCe(S NVSo)te 1) VLD ≠ 0, VCC = 2.2 V/3 V 10 15 μA †The recommended operating voltage range is limited to 3.6 V. NOTES: 1. The current consumption of the SVS module is not included in the ICC current consumption data. 2. tsettle is the settling time that the comparator output needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere between 2 and 15. The overdrive is assumed to be > 50 mV. 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 typical characteristics Software Sets VLD>0: SVS is Active V CC V hys(SVS_IT−) V (SVS_IT−) V (SVSstart) Vhys(B_IT−) V(B_IT−) V CC(start) Brown- Brownout Out Region Brownout Region 1 0 SVSOut td(BOR) td(BOR) SVS Circuit is Active From VLD > to VCC < V(B_IT−) 1 0 td(SVSon) td(SVSR) Set POR 1 undefined 0 Figure 11. SVS Reset (SVSR) vs Supply Voltage V CC t pw 3 V 2 Rectangular Drop V CC(min) 1.5 V Triangular Drop − n) mi 1 C( C 1 ns 1 ns V V 0.5 CC tpw 3 V 0 1 10 100 1000 tpw − Pulse Width − μs V CC(min) tf = tr tf tr t − Pulse Width − μs Figure 12. V With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal CC(min) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) DCO PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT f(DCOCLK) N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0 2.2 V/3 V 1 MHz 2.2 V 0.3 0.65 1.25 ff(DCO = 2) FFNN_88 = FFNN_44 = FFNN_33 = FFNN_22 = 00, DDCCOOPPLLUUSS = 11 3 V 0.3 0.7 1.3 MMHHzz 2.2 V 2.5 5.6 10.5 ff(DCO = 27) FFNN_88 = FFNN_44 = FFNN_33 = FFNN_22 = 00, DDCCOOPPLLUUSS = 11 3 V 2.7 6.1 11.3 MMHHzz FFNN__88 == FFNN__44 == FFNN__33 == 00,, FFNN__22 == 11,, DDCCOOPPLLUUSS == 11 2.2 V 0.7 1.3 2.3 ff(DCO = 2) 3 V 0.8 1.5 2.5 MMHHzz 2.2 V 5.7 10.8 18 ff(DCO = 27) FFNN_88 = FFNN_44 = FFNN_33 = 00, FFNN_22 = 11, DDOOPPLLUUSS = 11 3 V 6.5 12.1 20 MMHHzz 2.2 V 1.2 2 3 ff(DCO = 2) FFNN_88 = FFNN_44 = 00, FFNN_33 = 11, FFNN_22 = xx, DDCCOOPPLLUUSS = 11 3 V 1.3 2.2 3.5 MMHHzz 2.2 V 9 15.5 25 ff(DCO = 27) FFNN_88 = FFNN_44 = 00, FFNN_33 = 11, FFNN_22 = xx, DDCCOOPPLLUUSS = 11 3 V 10.3 17.9 28.5 MMHHzz 2.2 V 1.8 2.8 4.2 ff(DCO = 2) FFNN_88 = 00, FFNN_44 = 11, FFNN_33 = FFNN_22 = xx, DDCCOOPPLLUUSS = 11 3 V 2.1 3.4 5.2 MMHHzz 2.2 V 13.5 21.5 33 ff(DCO = 27) FFNN_88 = 00, FFNN_44 = 11, FFNN_33 = FFNN_22 = xx, DDCCOOPPLLUUSS = 11 3 V 16 26.6 41 MMHHzz 2.2 V 2.8 4.2 6.2 ff(DCO = 2) FFNN_88 = 11, FFNN_44 = FFNN_33 = FFNN_22 = xx, DDCCOOPPLLUUSS = 11 3 V 4.2 6.3 9.2 MMHHzz 2.2 V 21 32 46 ff(DCO = 27) FFNN_88 = 11, FFNN_44 = FFNN_33 = FFNN_22 = xx, DDCCOOPPLLUUSS = 11 3 V 30 46 70 MMHHzz Step size between adjacent DCO taps: 1 < TAP ≤ 20 1.06 1.11 SSn SSn = ffDCO(Tap n+1) // ffDCO(Tap n) (see Figure 14 for taps 21 to 27) TAP = 27 1.07 1.17 DDtt TTeemmppeerraattuurree ddrriifftt,, NN((DDCCOO)) == 0011EEhh,, FFNN__88 == FFNN__44 == FFNN__33 == FFNN__22 == 00,, 2.2 V –0.2 –0.3 –0.4 %%//(cid:3)(cid:3)CC D = 2, DCOPLUS = 0 3 V –0.2 –0.3 –0.4 Drift with VCC variation, N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, 2.2 V/3 V 0 5 15 %/V DV D = 2, DCOPLUS = 0 f f (DCO) (DCO) f(DCO3V) f(DCO20(cid:2)C) 1.0 1.0 0 1.8 2.4 3.0 3.6 −40 −20 0 20 40 60 85 VCC − V TA − °C Figure 13. DCO Frequency vs Supply Voltage V and vs Ambient Temperature CC 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) s ÎÎÎÎÎÎÎÎÎÎÎÎÎ p a 1.17 O T ÎÎÎÎÎÎÎÎÎÎÎÎÎ C D ÎÎÎÎÎÎÎÎÎÎÎÎÎ n e ÎÎÎÎÎÎÎÎÎÎÎÎÎ e w et ÎÎÎÎÎÎÎÎÎÎÎÎÎ b atio 1.11 ÎÎÎÎÎÎÎÎMaÎx ÎÎÎÎ R e ÎÎÎÎÎÎÎÎÎÎÎÎÎ z si ÎÎÎÎÎÎÎÎÎÎÎÎÎ p e St ÎÎÎÎÎÎÎÎÎÎÎÎÎ S - n 11..0076 ÎÎÎÎÎÎÎÎÎÎÎÎÎ Min 1 20 27 DCO Tap Figure 14. DCO Tap Step Size Legend O) C f(D Tolerance at Tap 27 DCO Frequency Adjusted by Bits 9 5 2 to 2 in SCFI1 {N } (DCO) Tolerance at Tap 2 Overlapping DCO Ranges: uninterrupted frequency range FN_2=0 FN_2=1 FN_2=x FN_2=x FN_2=x FN_3=0 FN_3=0 FN_3=1 FN_3=x FN_3=x FN_4=0 FN_4=0 FN_4=0 FN_4=1 FN_4=x FN_8=0 FN_8=0 FN_8=0 FN_8=0 FN_8=1 Figure 15. Five Overlapping DCO Ranges Controlled by FN_x Bits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) crystal oscillator, LFXT1, low-frequency modes (see Note 4) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT LFXT1 oscillator crystal fLFXT1, LF frequency, LF mode XTS_FLL = 0, LFXT1DIG = 0 1.8 V−3.6 V 32, 768 Hz LFXT1 oscillator logic level XTS_FLL = 0, LFXT1DIG = 1, fLFXT1, LF, logic square-wave input frequency, XCAPx = 0 1.8 V−3.6 V 10, 000 32, 768 Hz LF mode XTS_FLL = 0, LFXT1DIG = 0, fLFXT1, LF = 32,768 kHz, 500 OOsscciillllaattiioonn aalllloowwaannccee ffoorr LLFF CL, eff = 6 pF OOAALF crystals XTS_FLL = 0, LFXT1DIG = 0, kk(cid:2)(cid:2) fLFXT1, LF = 32,768 kHz, 200 CL, eff = 12 pF XTS_FLL = 0, XCAPx = 0 1 Integrated effective load XTS_FLL = 0, XCAPx = 1 5.5 CCL, eff ccaappaacciittaannccee, LLFF mmooddee XTS_FLL = 0, XCAPx = 2 8.5 ppFF ((sseeee NNoottee 11)) XTS_FLL = 0, XCAPx = 3 11 XTS_FLL = 0, Duty Cycle LF mode Measured at P1.4/ACLK, 2.2 V/3 V 30 50 70 % fLFXT1, LF = 32, 768 Hz Oscillator fault frequency, fFault, LF LF mode (see Note 3) XTS_FLL = 0 (see Note 2) 2.2 V/3 V 10 10, 000 Hz NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal. 2. Measured with logic level input frequency but also applies to operation with crystals. 3. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag. Frequencies in between might set the flag. 4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed. − Keep as short of a trace as possible between the device and the crystal. − Design a good ground plane around the oscillator pins. − Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. − Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. − Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. − If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. − Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. crystal oscillator, LFXT1, high-frequency mode PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 1.8 V−3.6 V 0.45 4 ffXT1 XXTT11 oosscciillllaattoorr ccrryyssttaall ffrreeqquueennccyy XXTTSS_FFLLLL = 11, CCeerraammiicc rreessoonnaattoorr 2.7 V−3.6 V 0.45 8 MMHHzz 1.8 V−3.6 V 1 4 ffXT1 XXTT11 oosscciillllaattoorr ccrryyssttaall ffrreeqquueennccyy XXTTSS_FFLLLL = 11, CCrryyssttaall 2.7 V−3.6 V 1 8 MMHHzz Integrated effective Load XTS_FLL = 1, XCAPx = 0 CL, eff Capacitance (see Note 1) (see Note 2) 1 pF Duty Cycle Measured at P1.4/ACLK 2.2 V/3 V 40 50 60 % NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal. 2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) crystal oscillator, XT2 oscillator (see Note 5) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT XT2 oscillator crystal frequency, fXT2, 0 mode 0 XT2Sx = 0 1.8 V − 3.6 V 0.4 1 MHz XT2 oscillator crystal frequency, fXT2, 1 mode 1 XT2Sx = 1 1.8 V − 3.6 V 1 4 MHz 1.8 V − 3.6 V 2 10 XXTT22 osciillllattor crysttall ffrequency, ffXXTT22,, 22 mmooddee 22 XXTT22SSxx = 22 2.2 V − 3.6 V 2 12 MMHHzz 3.0 V − 3.6 V 2 16 1.8 V − 3.6 V 0.4 10 XXTT22 osciillllattor llogiic llevell ffXXTT22,, llooggiicc ssqquuaarree--wwaavvee iinnppuutt ffrreeqquueennccyy XXTT22SSxx = 33 2.2 V − 3.6 V 0.4 12 MMHHzz 3.0 V − 3.6 V 0.4 16 XT2Sx = 0, 2700 fXT2 = 1 MHz, CL, eff = 15 pF XT2Sx = 1 OAXT2 Occrrsyycssittlaalallssti o((ssnee aeel loFFwiiggauunrreec e11 66fo))r HF fCLLF,X eTf1f ,= H 1F5 = p 4F MHz, 800 (cid:2) XT2Sx = 2 fLFXT1, HF = 16 MHz, 300 CL, eff = 15 pF Integrated effective load CL, eff capacitance (see Note 1) (see Note 2) 1 pF Measured at P1.4/ACLK, 2.2 V/3 V 40 50 60 fXT2 = 10 MHz DDuuttyy ccyyccllee %% Measured at P1.4/ACLK, 3 V 40 50 60 fXT2 = 16 MHz Oscillator fault frequency fFault, XT2 (see Note 4) XT2Sx = 3 (see Note 3) 2.2 V/3 V 30 300 kHz NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal. 2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. 3. Measured with logic level input frequency but also applies to operation with crystals. 4. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag. Frequencies in between might set the flag. 5. To improve EMI on the XT2 oscillator the following guidelines should be observed. − Keep traces as short as possible between the device and the crystal. − Design a good ground plane around the oscillator pins. − Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. − Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. − Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. − If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. − Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics − XT2 oscillator 100000.00 s m 10000.00 h O − e c n a w o 1000.00 All n o ati XT2Sx = 2 cill s 100.00 O XT2Sx = 0 XT2Sx = 1 10.00 0.10 1.00 10.00 100.00 Crystal Frequency − MHz Figure 16. Oscillation Allowance vs Crystal Frequency, CL, eff = 15 pF, TA = 25°C 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) wake-up LPM3 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f = 1 MHz 6 ttdd((LLPPMM33)) DDeellaayy ttiimmee f = 2 MHz VVCCCC == 22..22 VV//33 VV 6 μμss f = 3 MHz 6 LCD_A PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Charge pump enabled VCC(LCD) Supply voltage range (LCDCPEN = 1, VLCDx > 0000) 2.2 3.6 V CLCD C(saepea Nciototer o1n) LCDCAP C(LhCaDrgCeP pEuNm =p 1e,n VabLlCeDd x > 0000) 4.7 μF VLCD(typ) = 3V, LCDCPEN = 1, VLCDx = 1000, ICC(LCD) Supply current All segments on, fLCD = fACLK/32, 2.2 V 3.8 μA No LCD connected (see Note 2), TA = 25°C fLCD LCD frequency 1.1 kHz VLCDx = 0000 VCC VLCDx = 0001 2.60 VLCDx = 0010 2.66 VLCDx = 0011 2.72 VLCDx = 0100 2.78 VLCDx = 0101 2.84 VLCDx = 0110 2.90 VLCDx = 0111 2.96 VVLCD LLCCDD vvoollttaaggee VLCDx = 1000 3.02 VV VLCDx = 1001 3.08 VLCDx = 1010 3.14 VLCDx = 1011 3.20 VLCDx = 1100 3.26 VLCDx = 1101 3.32 VLCDx = 1110 3.38 VLCDx = 1111 3.44 3.60 RLCD LimCpDe ddarinvceer output VVLLCCDD =x 3=V 1, 0L0C0D, CILPOEAND == ± 11,0 μA 2.2 V 10 kΩ NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device. 2. Connecting an actual display will increase the current consumption depending on the size of the LCD. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Comparator_A (see Note 1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 2.2 V 25 40 II(CC) CCAAOONN = 11, CCAARRSSEELL = 00, CCAARREEFF = 00 3 V 45 60 μAA CAON = 1, CARSEL = 0, CAREF = 2.2 V 30 50 II(Refladder/RefDiode) 11//22//33, μAA No load at P1.6/CA0 and P1.7/CA1 3 V 45 80 Voltage@0.25VCCnode PCA0 = 1, CARSEL = 1, CAREF = 1, V(Ref025) V No load at P1.6/CA0 and P1.7/CA1 2.2 V/3 V 0.23 0.24 0.25 CC Voltage@0.5VCCnode PCA0 = 1, CARSEL = 1, CAREF = 2, V(Ref050) V No load at P1.6/CA0 and P1.7/CA1 2.2 V/3 V 0.47 0.48 0.5 CC PCA0 = 1, CARSEL = 1, CAREF = 3, 2.2 V 390 480 540 SSeeee FFiigguurree 1177 aanndd VV(RefVT) Figure 18 NNoo llooaadd aatt PP11.66//CCAA00 aanndd PP11.77//CCAA11, mmVV TA = 85°C 3 V 400 490 550 Common-mode input VIC voltage range CAON = 1 2.2 V/3 V 0 VCC−1 V Vp−VS Offset voltage See Note 2 2.2 V/3 V −30 30 mV Vhys Input hysteresis CAON = 1 2.2 V/3 V 0 0.7 1.4 mV TTAA == 2255°CC,, 2.2 V 80 165 300 nnss Overdrive 10 mV, without filter: CAF = 0 3 V 70 120 240 tt(response LH and HL), sseeee NNoottee 33 TTAA == 2255°CC 2.2 V 1.4 1.9 2.8 μss Overdrive 10 mV, with filter: CAF = 1 3 V 0.9 1.5 2.2 NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together. 3. The response time is measured at P1.6/CA0 with an input voltage step and the Comparator_A already enabled (CAON = 1). If CAON is set at the same time, a settling time of up to 300 ns is added to the response time. 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) typical characteristics REFERENCE VOLTAGE REFERENCE VOLTAGE vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 650 650 VCC = 3 V VCC = 2.2 V V 600 V 600 m m ge − Typical ge − Typical Volta 550 Volta 550 nce nce Refere 500 Refere 500 − − F F E E VR 450 VR 450 400 400 −45 −25 −5 15 35 55 75 95 −45 −25 −5 15 35 55 75 95 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 17. V vs Temperature Figure 18. V vs Temperature (RefVT) (RefVT) 0 V VCC CAF 0 1 CAON Low-Pass Filter To Internal Modules 0 0 V+ + _ V− 1 1 CAOUT Set CAIFG Flag τ ≈ 2 μs Figure 19. Block Diagram of Comparator_A Module Overdrive VCAOUT V− 400 mV V+ t(response) Figure 20. Overdrive Definition POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 41

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Timer_A PARAMETER TEST CONDITIONS VCC MIN MAX UNIT Internal: SMCLK, ACLK, 2.2 V 10 ffTA TTiimmeerr_AA cclloocckk ffrreeqquueennccyy EExxtteerrnnaall:: TTAACCLLKK, IINNCCLLKK, MMHHzz Duty Cycle = 50% ±10% 3 V 16 tTA, cap Timer_A, capture timing TA0, TA1, TA2 2.2 V/3 V 20 ns Timer_B PARAMETER TEST CONDITIONS VCC MIN MAX UNIT Internal: SMCLK, ACLK, 2.2 V 10 ffTB TTiimmeerr_BB cclloocckk ffrreeqquueennccyy EExxtteerrnnaall:: TTBBCCLLKK, MMHHzz Duty Cycle = 50% ±10% 3 V 16 tTB, cap Timer_B, capture timing TB0, TB1, TB2 2.2 V/3 V 20 ns 42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) USCI (UART mode) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Internal: SMCLK, ACLK fUSCI USCI input clock frequency External: UCLK fSYSTEM MHz Duty Cycle = 50% ± 10% BITCLK clock frequency fBITCLK (equals Baudrate in MBaud) 2.2V /3 V 1 MHz UUAARRTT rreecceeiivvee ddeegglliittcchh ttiimmee 2.2 V 50 150 600 ns ttτ (see Note 1) 3 V 50 100 600 ns NOTES: 1. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglich time are suppressed. To ensure that pulses are correctly recognized their width should exceed the maximum specification of the deglitch time. USCI (SPI master mode) (see Figure 21 and Figure 22) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT SMCLK, ACLK fUSCI USCI input clock frequency Duty Cycle = 50% ± 10% fSYSTEM MHz 2.2 V 110 ns ttSU, MI SSOOMMII iinnppuutt ddaattaa sseettuupp ttiimmee 3 V 75 ns 2.2 V 0 ns ttHD, MI SSOOMMII iinnppuutt ddaattaa hhoolldd ttiimmee 3 V 0 ns UUCCLLKK eeddggee ttoo SSIIMMOO vvaalliidd,, 2.2 V 30 ns ttVALID, MO SSIIMMOO oouuttppuutt ddaattaa vvaalliidd ttiimmee CL = 20 pF 3 V 20 ns NOTE: fUCxCLK(cid:2)2t1 with tLO(cid:3)HI(cid:4)max(tVALID,MO(USCI)(cid:5)tSU,SI(Slave),tSU,MI(USCI)(cid:5)tVALID,SO(Slave)). LO(cid:3)HI For the slave’s parameters tSU, SI(Slave) and tVALID, SO(Slave) see the SPI parameters of the attached slave. USCI (SPI slave mode) (see Figure 23 and Figure 24) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT STE lead time tSTE, LEAD STE low to clock 2.2 V/3 V 50 ns STE lag time tSTE, LAG Last clock to STE high 2.2 V/3 V 10 ns STE access time tSTE, ACC STE low to SOMI data out 2.2 V/3 V 50 ns STE disable time tSTE, DIS STE high to SOMI high impedance 2.2 V/3 V 50 ns 2.2 V 20 ns ttSU, SI SSIIMMOO iinnppuutt ddaattaa sseettuupp ttiimmee 3 V 15 ns 2.2 V 10 ns ttHD, SI SSIIMMOO iinnppuutt ddaattaa hhoolldd ttiimmee 3 V 10 ns UUCCLLKK eeddggee ttoo SSOOMMII vvaalliidd,, 2.2 V 75 110 ns ttVALID, SO SSOOMMII oouuttppuutt ddaattaa vvaalliidd ttiimmee CL = 20 pF 3 V 50 75 ns NOTE: fUCxCLK(cid:2)2t1 with tLO(cid:3)HI(cid:4)max(tVALID,MO(Master)(cid:5)tSU,SI(USCI),tSU,MI(Master)(cid:5)tVALID,SO(USCI)). LO(cid:3)HI For the master’s parameters tSU, MI(Master) and tVALID, MO(Master) see the SPI parameters of the attached master. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 43

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 21. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tHD,MI tSU,MI SOMI tVALID,MO SIMO Figure 22. SPI Master Mode, CKPH = 1 44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,SI tHD,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 23. SPI Slave Mode, CKPH = 0 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 24. SPI Slave Mode, CKPH = 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 45

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) USCI (I2C mode) (see Figure 25) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Internal: SMCLK, ACLK fUSCI USCI input clock frequency External: UCLK fSYSTEM MHz Duty cycle = 50% ± 10% fSCL SCL clock frequency 2.2 V/3 V 0 400 kHz fSCL ≤ 100 kHz 2.2 V/3 V 4.0 ttHD, STA HHoolldd ttiimmee ((rreeppeeaatteedd)) SSTTAARRTT fSCL > 100 kHz 2.2 V/3 V 0.6 uuss fSCL ≤ 100 kHz 2.2 V/3 V 4.7 ttSU, STA SSeettuupp ttiimmee ffoorr aa rreeppeeaatteedd SSTTAARRTT fSCL > 100 kHz 2.2 V/3 V 0.6 uuss tHD, DAT Data hold time 2.2 V/3 V 0 ns tSU, DAT Data setup time 2.2 V/3 V 250 ns tSU, STO Setup time for STOP 2.2 V/3 V 4.0 us 2.2 V 50 150 600 ttSP PPuullssee wwiiddtthh ooff ssppiikkeess ssuupppprreesssseedd bbyy iinnppuutt ffiilltteerr 3 V 50 100 600 nnss tHD,STA tSU,STA tHD,STA SDA 1/fSCL tSP SCL tSU,DAT tSU,STO tHD,DAT Figure 25. I2C Mode Timing 46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SD16_A, power supply and recommended operating conditions PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT AVCC Avonlatalogge supply AAVVCSSC == DDVVSCSC = 0V 2.5 3.6 V GAIN: 1, 2 3 V 730 1050 SSDD1166LLPP == 00,, Analog supply ffSSDD1166 = 11 MMHHzz,, GAIN: 4, 8, 16 3 V 810 1150 currentt: 11 acttiive SD16OSR = 256 GAIN: 32 3 V 1160 1700 IISSDD1166 SSDD1166_AA cchhaannnneell μμAA including internal SD16LP = 1, GAIN: 1 3 V 720 1030 rreeffeerreennccee ffSD16 = 00.55 MMHHzz, SD16OSR = 256 GAIN: 32 3 V 810 1150 Analog front-end SD16LP = 0 (Low power mode disabled) 3 V 0.03 1 1.1 ffSD16 iinnppuutt cclloocckk MMHHzz frequency SD16LP = 1 (Low power mode enabled) 3 V 0.03 0.5 SD16_A, input range (see Note 1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT DDiiffffeerreennttiiaall ffuullll ssccaallee Bipolar mode, SD16UNI = 0 −VREF/2GAIN +VREF/2GAIN VVID, FSR input voltage range Unipolar mode, SD16UNI = 1 0 +VREF/2GAIN mmVV SD16GAINx = 1 ±500 DDiiffffeerreennttiiaall iinnppuutt SD16GAINx = 2 ±250 voltage range for SD16GAINx = 4 ±125 VVID ssppeecciiffiieedd SSDD1166RREEFFOONN = 11 SD16GAINx = 8 ±62 mmVV ppeerrffoorrmmaannccee ((sseeee NNoottee 22)) SD16GAINx = 16 ±31 SD16GAINx = 32 ±15 Input impedance SD16GAINx = 1 3 V 200 ZZI ((oonnee iinnppuutt ppiinn ttoo ffSD16 = 11 MMHHzz kkΩΩ AVSS) SD16GAINx = 32 3 V 75 Differential input SD16GAINx = 1 3 V 300 400 ZZID iimmppeeddaannccee ffSD16 = 11 MMHHzz kkΩΩ (IN+ to IN−) SD16GAINx = 32 3 V 100 150 Absolute input VI voltage range AVSS -1V AVCC V Common-mode VIC input voltage range AVSS -1V AVCC V NOTES: 1. All parameters pertain to each SD16_A channel. 2. The analog input range depends on the reference voltage applied to VREF. If VREF is sourced externally, the full-scale range is defined by VFSR+ = +(VREF/2)/GAIN and VFSR− = −(VREF/2)/GAIN. The analog input range should not exceed 80% of VFSR+ or VFSR−. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 47

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SD16_A, performance (f = 1MHz, SD16OSRx = 256, SD16REFON = 1) SD16 PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT SD16GAINx = 1, 3 V 83 85 Signal Amplitude VPP = 500 mV SD16GAINx = 2, 3 V 81 84 Signal Amplitude VPP = 250 mV SD16GAINx = 4, 3 V 76 79 SSIINNAADD SSiiggnnaall-ttoo-nnooiissee ++ Signal Amplitude VPP = 125 mV ffIINN == 5500 HHzz,, 110000 HHzz ddBB distortion ratio SD16GAINx = 8, (see Notes 1 and 2) 3 V 70 75 Signal Amplitude VPP = 62 mV SD16GAINx = 16, 3 V 66 70 Signal Amplitude VPP = 31 mV SD16GAINx = 32, 3 V 62 65 Signal Amplitude VPP = 15 mV SD16GAINx = 1 3 V 0.97 1.00 1.02 SD16GAINx = 2 3 V 1.90 1.96 2.02 SD16GAINx = 4 3 V 3.76 3.86 3.96 GG Nominal gain SD16GAINx = 8 3 V 7.36 7.62 7.84 SD16GAINx = 16 3 V 14.56 15.04 15.52 SD16GAINx = 32 3 V 27.20 28.35 29.76 SD16GAINx = 1 3 V ±0.2 EEOS OOffffsseett eerrrroorr SD16GAINx = 32 3 V ±1.5 %%FFSSRR OOffffsseett eerrrroorr tteemmppeerraattuurree SD16GAINx = 1 3 V ±4 ±20 ppppmm ddEEOS//ddTT coefficient SD16GAINx = 32 3 V ±20 ±100 FSR/(cid:3)C SD16GAINx = 1, Common-mode input signal: 3 V >90 CCoommmmoonn-mmooddee rreejjeeccttiioonn VID = 500 mV, fIN = 50 Hz, 100 Hz CCMMRRRR ddBB ratio SD16GAINx = 32, Common-mode input signal: 3 V >75 VID = 16 mV, fIN = 50 Hz, 100 Hz AC power supply AC PSRR rejection ratio SD16GAINx = 1, VCC = 3V ± 100mV, fVcc = 50 Hz 3 V >80 dB XT Crosstalk SD16GAINx = 1, VID = 500 mV, fIN = 50 Hz, 100 Hz 3 V <−100 dB NOTES: 1. The following voltages were applied to the SD16 inputs: VIN, A+(t) = 1.2V + VPP/2 × sin(2π × fIN × t) VIN, A−(t) = 1.2V − VPP/2 × sin(2π × fIN × t) resulting in a differential voltage of Vdiff = VIN, A+(t) − VIN, A−(t) = VPP × sin(2π × fIN × t) 2. The SINAD performance of the SD16_A maybe degraded. See errata sheet. 48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) typical characteristics − SD16_A SNR/SINAD performance over OSR 100.0 95.0 SNR 90.0 B 85.0 SINAD d − D 80.0 A N SI 75.0 R/ N 70.0 S 65.0 60.0 55.0 50.0 10.00 100.00 1000.00 OSR Figure 26. SNR/SINAD performance over OSR, f = 1MHz, SD16REFON = 1, SD16GAINx = 1 SD16 V (t) = 1.2V + 500mV (cid:3) sin(2(cid:2) (cid:3) 50Hz (cid:3) t) IN SD16_A, temperature sensor and built-in V sense CC PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Sensor temperature TCSensor coefficient 1.18 1.32 1.46 mV/K VOffset, sensor Sensor offset voltage −100 100 mV Temperature sensor voltage at TA = 85°C 3 V 435 475 515 SSensor outtputt vollttage VVSSeennssoorr ((sseeee NNoottee 22)) Temperature sensor voltage at TA = 25°C 3 V 355 395 435 mmVV Temperature sensor voltage at TA = 0°C 3 V 320 360 400 VCC, Sense VCC divider at input 5 fSD16 = 32kHz, SD16OSRx = 256, SD16REFON = 1 0.08 1/11 0.10 VCC Source resistance of RSource, VCC VCC divider at input 5 500 kΩ NOTES: 1. The following formula can be used to calculate the temperature sensor output voltage: VSensor, typ = TCSensor ( 273 + T [°C] ) + VOffset, sensor [mV] 2. Results based on characterization and/or production test, not TCSensor or VOffset, sensor. Measured with fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 49

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SD16_A, built-in voltage reference PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Internal reference VREF voltage SD16REFON = 1, SD16VMIDON = 0 3 V 1.14 1.20 1.26 V Reference supply IREF current SD16REFON = 1, SD16VMIDON = 0 3 V 175 260 μA TC Temperature coefficient SD16REFON = 1, SD16VMIDON = 0 (see Note 1) 3 V 18 50 ppm/K CREF VREF load capacitance SD16REFON = 1, SD16VMIDON = 0 (see Note 2) 100 nF ILOAD VcuRrEreFn(I)t maximum load SD16REFON = 1, SD16VMIDON = 0 3 V ±200 nA SD16REFON = 0−>1, SD16VMIDON = 0, tON Turn on time CREF = 100nF 3 V 5 ms DC Power Supply SD16REFON = 1, SD16VMIDON = 0, DC PSR 100 uV/V Rejection ΔVREF/ΔVCC VCC = 2.5V - 3.6V NOTES: 1. Calculated using the box method: (MAX(-40...85°C) − MIN(-40...85°C)) / MIN(−40...85°C) / (85°C − (-40°C)) 2. There is no capacitance required on VREF. However, a capacitance of at least 100nF is recommended to reduce any reference voltage noise. SD16_A, reference output buffer PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Reference buffer output VREF, BUF voltage SD16REFON = 1, SD16VMIDON = 1 3 V 1.2 V Reference Supply + IREF, BUF Reference output buffer SD16REFON = 1, SD16VMIDON = 1 3 V 385 600 μA quiescent current Required load CREF(O) capacitance on VREF SD16REFON = 1, SD16VMIDON = 1 470 nF Maximum load current ILOAD, Max on VREF SD16REFON = 1, SD16VMIDON = 1 3 V ±1 mA Maximum voltage variation vs. load current |ILOAD| = 0 to 1mA 3 V −15 +15 mV SD16REFON = 0−>1, SD16VMIDON = 0−>1, tON Turn on time CREF = 470nF 3 V 100 μs SD16_A, external reference input PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VREF(I) Input voltage range SD16REFON = 0 3 V 1.0 1.25 1.5 V IREF(I) Input current SD16REFON = 0 3 V 50 nA 50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) flash memory PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(PGM/ Program and Erase supply voltage 2.2 3.6 V ERASE) fFTG Flash Timing Generator frequency 257 476 kHz IPGM Supply current from VCC during program 2.2 V/3.6 V 3 5 mA IERASE Supply current from VCC during erase 2.2 V/3.6 V 3 7 mA tCPT Cumulative program time (see Note 1) 2.2 V/3.6 V 10 ms tCMErase Cumulative mass erase time 2.2 V/3.6 V 20 ms Program/Erase endurance 104 105 cycles tRetention Data retention duration TJ = 25°C 100 years tWord Word or byte program time 30 tBlock, 0 Block program time for 1st byte or word 25 tBlock, 1-63 Block program time for each additional byte or word 18 tBlock, End Block program end-sequence wait time sseeee NNoottee 22 6 ttFTG tMass Erase Mass erase time 10593 tSeg Erase Segment erase time 4819 NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. 2. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG). RAM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(RAMh) RAM retention supply voltage (see Note 1) CPU halted 1.6 V NOTE 1: This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition. JTAG interface TEST PARAMETER CONDITIONS VCC MIN NOM MAX UNIT 2.2 V 0 5 MHz ffTCK TTCCKK iinnppuutt ffrreeqquueennccyy sseeee NNoottee 11 3 V 0 10 MHz RInternal Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2 2.2 V/ 3 V 20 35 50 kΩ NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected. 2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions. JTAG fuse (see Note 1) TEST PARAMETER CONDITIONS VCC MIN MAX UNIT VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V VFB Voltage level on TDI/TCLK for fuse-blow: F versions 6 7 V IFB Supply current into TDI/TCLK during fuse blow 100 mA tFB Time to blow fuse 1 ms NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 51

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 APPLICATION INFORMATION Port P1, P1.0 to P1.5, input/output with Schmitt trigger Pad Logic DVSS DVSS CAPD.x P1REN.x DVSS 0 DVCC 1 1 P1DIR.x 0 Direction 1 0:Input 1:Output P1OUT.x 0 Module X OUT 1 P1.0/TA0 P1.1/TA0/MCLK P1SEL.x Bus P1.2/TA1 Keeper P1.3/TBOUTH/SVSOUT P1IN.x EN P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK EN Module X IN D P1IE.x EN P1IRQ.x Q Set P1IFG.x P1SEL.x Interrupt Edge P1IES.x Select 52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 Port P1 (P1.0 to P1.5) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP11.XX)) XX FFUUNNCCTTIIOONN P1DIR.x P1SEL.x CAPD.x P1.0/TA0 0 P1.0 (I/O) I: 0, O: 1 0 0 Timer_A3.CCI0A 0 1 0 Timer_A3.TA0 1 1 0 Input buffer disabled (see Note 2) X X 1 P1.1/TA0/MCLK 1 P1.1 (I/O) I: 0, O: 1 0 0 Timer_A3.CCI0B 0 1 0 MCLK 1 1 0 Input buffer disabled (see Note 2) X X 1 P1.2/TA1 2 P1.2 (I/O) I: 0, O: 1 0 0 Timer_A3.CCI1A 0 1 0 Timer_A3.TA1 1 1 0 Input buffer disabled (see Note 2) X X 1 P1.3/ 3 P1.3 (I/O) I: 0, O: 1 0 0 TBOUTH/SVSOUT Timer_B7.TBOUTH 0 1 0 SVSOUT 1 1 0 Input buffer disabled (see Note 2) X X 1 P1.4/TBCLK/SMCLK 4 P1.4 (I/O) I: 0, O: 1 0 0 Timer_B7.TBCLK 0 1 0 SMCLK 1 1 0 Input buffer disabled (see Note 2) X X 1 P1.5/TACLK/ACLK 5 P1.5 (I/O) I: 0, O: 1 0 0 Timer_A3.TACLK 0 1 0 ACLK 1 1 0 Input buffer disabled (see Note 2) X X 1 NOTES: 1. X: Don’t care. 2. Setting the CAPD.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 53

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 Port P1, P1.6, P1.7, input/output with Schmitt trigger Pad Logic To Comparator_A From Comparator_A CAPD.x P1REN.x DVSS 0 DVCC 1 1 P1DIR.x 0 Direction 1 0:Input 1:Output P1OUT.x 0 Module X OUT 1 P1.6/CA0 P1.7/CA1 P1SEL.x Bus Keeper P1IN.x EN EN Module X IN D P1IE.x EN P1IRQ.x Q Set P1IFG.x P1SEL.x Interrupt Edge P1IES.x Select Port P1 (P1.6 and P1.7) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP11.XX)) XX FFUUNNCCTTIIOONN P1DIR.x P1SEL.x CAPD.x P1.6/CA0 6 P1.6 (I/O) I: 0, O: 1 0 0 CA0 (see Note 2) X X 1 P1.7/CA1 7 P1.7 (I/O) I: 0, O: 1 0 0 CA1 (see Note 2) X X 1 NOTES: 1. X: Don’t care. 2. Setting the CAPD.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 port P2, P2.0, P2.6 to P2.7, input/output with Schmitt trigger DVSS P2REN.x DVSS 0 DVCC 1 1 P2DIR.x 0 Direction 1 0:Input 1:Output P2OUT.x 0 Module X OUT 1 P2.0/TA2 P2.6/CAOUT P2SEL.x Bus P2.7 Keeper P2IN.x EN EN Module X IN D P2IE.x EN P2IRQ.x Q Set P2IFG.x P2SEL.x Interrupt Edge P2IES.x Select Port P2 (P2.0, P2.6 and P2.7) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP22.XX)) XX FFUUNNCCTTIIOONN P2DIR.x P2SEL.x P2.0/TA2 0 P2.0 (I/O) I: 0, O: 1 0 Timer_A3.CCI2A 0 1 Timer_A3.TA2 1 1 P2.6/CAOUT 6 P2.6 (I/O) I: 0, O: 1 0 N/A 0 1 CAOUT 1 1 P2.7 7 P2.7 (I/O) I: 0, O: 1 0 N/A 0 1 DVSS 1 1 NOTES: 1. N/A: Not available or not applicable 2. Setting TBOUTH causes all Timer_B outputs to be set to high impedance. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 55

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 port P2, P2.1 to P2.3, input/output with Schmitt trigger Timer_B Output Tristate Logic P1.3/TBOUTH/SVSOUT P1SEL.3 P1DIR.3 P2REN.x DVSS 0 DVCC 1 1 P2DIR.x 0 Direction 1 0:Input 1:Output P2OUT.x 0 Module X OUT 1 P2.1/TB0 P2.2/TB1 P2SEL.x Bus P2.3/TB2 Keeper P2IN.x EN EN Module X IN D P2IE.x EN P2IRQ.x Q Set P2IFG.x P2SEL.x Interrupt Edge P2IES.x Select Port P2 (P2.1 to P2.3) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP22.XX)) XX FFUUNNCCTTIIOONN P2DIR.x P2SEL.x P2.1/TB0 1 P2.1 (I/O) I: 0, O: 1 0 Timer_B7.CCI0A and Timer_B7.CCI0B 0 1 Timer_B7.TB0 (see Note 2) 1 1 P2.2/TB1 2 P2.2 (I/O) I: 0, O: 1 0 Timer_B7.CCI1A and Timer_B7.CCI1B 0 1 Timer_B7.TB1 (see Note 2) 1 1 P2.3/TB3 3 P2.3 (I/O) I: 0, O: 1 0 Timer_B7.CCI2A and Timer_B7.CCI2B 0 1 Timer_B7.TB3 (see Note 2) 1 1 NOTES: 1. N/A: Not available or not applicable 2. Setting TBOUTH causes all Timer_B outputs to be set to high impedance. 56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 port P2, P2.4 to P2.5, input/output with Schmitt trigger DVSS P2REN.x DVSS 0 DVCC 1 1 P2DIR.x 0 Direction USCI Direction 1 0:Input Control 1:Output P2OUT.x 0 Module X OUT 1 P2.4/UCA0TXD/UCA0SIMO P2.5/UCA0RXD/UCA0SOMI P2SEL.x Bus Keeper P2IN.x EN EN Module X IN D P2IE.x EN P2IRQ.x Q Set P2IFG.x P2SEL.x Interrupt Edge P2IES.x Select Port P2 (P2.4 and P2.5) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP22.XX)) XX FFUUNNCCTTIIOONN P2DIR.x P2SEL.x P2.4/ 4 P2.4 (I/O) I: 0, O: 1 0 UCA0TXD/UCA0SIMO UCA0TXD/UCA0SIMO (see Note 1, 2) X 1 P2.5/ 5 P2.5 (I/O) I: 0, O: 1 0 UCA0RXD/UCA0SOMI UCA0RXD/UCA0SOMI (see Note 1, 2) X 1 NOTES: 1. X: Don’t care. 2. The pin direction is controlled by the USCI module. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 57

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 port P3, P3.0 to P3.3, input/output with Schmitt trigger DVSS Pad Logic P3REN.x DVSS 0 DVCC 1 1 P3DIR.x 0 Direction USCI Direction 1 0:Input Control 1:Output P3OUT.x 0 Module X OUT 1 P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3SEL.x Bus P3.2/UCB0SOMI/UCB0SCL Keeper P3.3/UCB0CLK/UCA0STE P3IN.x EN EN Module X IN D Port P3 (P3.0 to P3.3) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP33.XX)) XX FFUUNNCCTTIIOONN P3DIR.x P3SEL.x P3.0/ 0 P3.0 (I/O) I: 0, O: 1 0 UCA0CLK/UCB0STE UCA0CLK/UCB0STE (see Notes 1, 2, 3) X 1 P3.1/ 1 P3.1 (I/O) I: 0, O: 1 0 UUCCBB00SSIIMMOO// UCB0SDA UCB0SIMO/UCB0SDA (see Notes 1, 2, 4) X 1 P3.2/ 2 P3.2 (I/O) I: 0, O: 1 0 UUCCBB00SSOOMMII// UCB0SCL UCB0SOMI/UCB0SCL (see Notes 1, 2, 4) X 1 P3.3/ 3 P3.3 (I/O) I: 0, O: 1 0 UCB0CLK/UCA0STE UCB0CLK (see Notes 1, 2, 5) X 1 NOTES: 1. X: Don’t care. 2. The pin direction is controlled by the USCI module. 3. UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output USCI_B0 will be forced to 3-wire SPI mode even if 4-wire SPI mode is selected. 4. In case the I2C functionality is selected the output drives only the logical 0 to VSS level. 5. UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output USCI_A0 will be forced to 3-wire SPI mode even if 4-wire SPI mode is selected. 58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 port P3, P3.4 to P3.7, input/output with Schmitt trigger DVSS Pad Logic P3REN.x DVSS 0 DVCC 1 1 P3DIR.x 0 Direction 1 0:Input 1:Output P3OUT.x 0 Module X OUT 1 P3.4 P3.5 P3SEL.x Bus P3.6 Keeper P3.7 P3IN.x EN EN Module X IN D Port P3 (P3.4 to P3.7) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP33.XX)) XX FFUUNNCCTTIIOONN P3DIR.x P3SEL.x P3.4 4 P3.4 (I/O) I: 0, O: 1 0 N/A 0 1 DVSS 1 1 P3.5 5 P3.5 (I/O) I: 0, O: 1 0 N/A 0 1 DVSS 1 1 P3.6 6 P3.6 (I/O) I: 0, O: 1 0 N/A 0 1 DVSS 1 1 P3.7 7 P3.7 (I/O) I: 0, O: 1 0 N/A 0 1 DVSS 1 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 59

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 port P4, P4.0 to P4.1, input/output with Schmitt trigger DVSS Pad Logic P4REN.x DVSS 0 DVCC 1 1 P4DIR.x 0 Direction USCI Direction 1 0:Input Control 1:Output P4OUT.x 0 Module X OUT 1 P4.0/UCA1TXD/UCA1SIMO P4.1/UCA1RXD/UCA1SOMI P4SEL.x Bus Keeper P4IN.x EN EN Module X IN D Port P4 (P4.0 to P4.1) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP44.XX)) XX FFUUNNCCTTIIOONN P4DIR.x P4SEL.x P4.0/ 0 P4.0 (I/O) I: 0, O: 1 0 UCA1TXD/UCA1SIMO UCA1TXD/UCA1SIMO (see Notes 1, 2) X 1 P4.1/ 1 P4.1 (I/O) I: 0, O: 1 0 UCA1RXD/UCA1SOMI UCA1RXD/UCA1SOMI (see Notes 1, 2) X 1 NOTES: 1. X: Don’t care. 2. The pin direction is controlled by the USCI module. 60 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 port P4, P4.2 to P4.5, input/output with Schmitt trigger Pad Logic Segment Sz LCDS... P4REN.x DVSS 0 DVCC 1 1 P4DIR.x 0 Direction USCI Direction 1 0:Input Control 1:Output P4OUT.x 0 Module X OUT 1 P4.2/UCB1STE/UCA1CLK/S39 P4.3/UCB1SIMO/UCB1SDA/S38 P4SEL.x Bus P4.4/UCB1SOMI/UCB1SCL/S37 Keeper P4.5/UCB1CLK/UCA1STE/S36 P4IN.x EN EN Module X IN D Port P4 (P4.2 to P4.5) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP44.XX)) XX FFUUNNCCTTIIOONN P4DIR.x P4SEL.x LCDS36 P4.2/ 2 P4.2 (I/O) I: 0, O: 1 0 0 UCA1CLK/UCB1STE/ UCA1CLK/UCB1STE (see Notes 2, 3) X 1 0 SS3399 S39 X X 1 P4.3/ 3 P4.3 (I/O) I: 0, O: 1 0 0 UCB1SIMO/UCB1SDA/ UCB1SIMO/UCB1SDA (see Notes 2, 4) X 1 0 SS3388 S38 X X 1 P4.4/ 4 P4.4 (I/O) I: 0, O: 1 0 0 UCB1SOMI/UCB1SCL/ UCB1SOMI/UCB1SCL (see Notes 2, 4) X 1 0 SS3377 S37 X X 1 P4.5/ 5 P4.5 (I/O) I: 0, O: 1 0 0 UCB1CLK/UCA1STE/ UCB1CLK/UCA1STE (see Notes 2, 5) X 1 0 SS3366 S36 X X 1 NOTES: 1. X: Don’t care. 2. The pin direction is controlled by the USCI module. 3. UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output USCI_B1 will be forced to 3-wire SPI mode even if 4-wire SPI mode is selected. 4. In case the I2C functionality is selected the output drives only the logical 0 to VSS level. 5. UCB1CLK function takes precedence over UCA1STE function. If the pin is required as UCB1CLK input or output USCI_A1 will be forced to 3-wire SPI mode even if 4-wire SPI mode is selected. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 61

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 port P4, P4.6 to P4.7, input/output with Schmitt trigger Pad Logic Segment Sz LCDS... P4REN.x DVSS 0 DVCC 1 1 P4DIR.x 0 Direction 1 0:Input 1:Output P4OUT.x 0 Module X OUT 1 P4.6/S35 P4.7/S34 P4SEL.x Bus Keeper P4IN.x EN EN Module X IN D Port P4 (P4.6 to P4.7) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP44.XX)) XX FFUUNNCCTTIIOONN P4DIR.x P4SEL.x LCDS32 P4.6/S35 6 P4.6 (I/O) I: 0, O: 1 0 0 S35 X X 1 P4.7/S34 7 P4.7 (I/O) I: 0, O: 1 0 0 S34 X X 1 NOTES: 1. X: Don’t care. 62 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 port P5, P5.0, input/output with Schmitt trigger Pad Logic To SVS P5REN.x DVSS 0 DVCC 1 1 P5DIR.x 0 Direction 1 0:Input 1:Output P5OUT.x 0 DVSS 1 P5.0/SVSIN P5SEL.x Bus Keeper P5IN.x EN Port P5 (P5.0) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP55.XX)) XX FFUUNNCCTTIIOONN P5DIR.x P5SEL.x P5.0/SVSIN 0 P5.0 (I/O) (see Note 1) I: 0, O: 1 0 SVSIN (see Notes 1, 3) X 1 NOTES: 1. X: Don’t care. 2. N/A: Not available or not applicable. 3. Setting the P5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 63

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 port P5, P5.1, input/output with Schmitt trigger Pad Logic Segment S0 LCDS0 P5REN.1 DVSS 0 DVCC 1 1 P5DIR.1 0 Direction 1 0:Input 1:Output P5OUT.1 0 Module X OUT 1 P5.1/S0 P5SEL.1 Bus Keeper P5IN.1 EN EN Module X IN D Port P5 (P5.1) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP55.XX)) XX FFUUNNCCTTIIOONN P5DIR.x P5SEL.x LCDS0 P5.1/S0 1 P5.1 (I/O) I: 0, O: 1 0 0 N/A 0 1 0 DVSS 1 1 0 S0 X X 1 NOTES: 1. X: Don’t care. 2. N/A: Not available or not applicable. 64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 port P5, P5.2 to P5.7, input/output with Schmitt trigger Pad Logic LCD Signal P5REN.x DVSS 0 DVCC 1 1 P5DIR.x 0 Direction 1 0:Input 1:Output P5OUT.x 0 DVSS 1 P5.2/COM1 P5.3/COM2 P5SEL.x Bus P5.4/COM3 Keeper P5.5/R03 P5IN.x EN P5.6/LCDREF/R13 P5.7/R23 Port P5 (P5.2 to P5.4) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP55.XX)) XX FFUUNNCCTTIIOONN P5DIR.x P5SEL.x P5.2/COM1 2 P5.2 (I/O) I: 0, O: 1 0 COM1 (see Note 2) X 1 P5.3/COM2 3 P5.3 (I/O) I: 0, O: 1 0 COM2 (see Note 2) X 1 P5.4/COM3 4 P5.4 (I/O) I: 0, O: 1 0 COM3 (see Note 2) X 1 P5.5/R03 5 P5.5 (I/O) I: 0, O: 1 0 R03 (see Note 2) X 1 P5.6/LCDREF/R13 6 P5.6 (I/O) I: 0, O: 1 0 R13 or LCDREF (see Notes 2, 3) X 1 P5.7/R23 7 P5.7 (I/O) I: 0, O: 1 0 R23 (see Note 2) X 1 NOTES: 1. X: Don’t care. 2. Setting the P5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. 3. External reference for the LCD_A charge pump is applied when VLCDREFx = 01. Otherwise R13 is selected. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 65

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 port P7 to port P10, input/output with Schmitt trigger Pad Logic Segment Sz LCDS... PyREN.x DVSS 0 DVCC 1 1 PyDIR.x 0 Direction 1 0:Input 1:Output PyOUT.x 0 Module X OUT 1 Py.x/Sz PySEL.x Bus Keeper PyIN.x EN EN Module X IN D 66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 Port P7 (P7.0 to P7.1) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP77.XX)) XX FFUUNNCCTTIIOONN P7DIR.x P7SEL.x LCDS32 P7.0/S33 0 P7.0 (I/O) I: 0, O: 1 0 0 S33 X X 1 P7.1/S32 1 P7.1 (I/O) I: 0, O: 1 0 0 S32 X X 1 NOTES: 1. X: Don’t care. Port P7 (P7.4 to P7.5) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP77.XX)) XX FFUUNNCCTTIIOONN P7DIR.x P7SEL.x LCDS28 P7.2/S31 2 P7.2 (I/O) I: 0, O: 1 0 0 S31 X X 1 P7.3/S30 3 P7.3 (I/O) I: 0, O: 1 0 0 S30 X X 1 P7.4/S29 4 P7.4 (I/O) I: 0, O: 1 0 0 S29 X X 1 P7.5/S28 5 P7.5 (I/O) I: 0, O: 1 0 0 S28 X X 1 NOTES: 1. X: Don’t care. Port P7 (P7.6 to P7.7) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP77.XX)) XX FFUUNNCCTTIIOONN P7DIR.x P7SEL.x LCDS24 P7.6/S27 6 P7.6 (I/O) I: 0, O: 1 0 0 S27 X X 1 P7.7/S26 7 P7.7 (I/O) I: 0, O: 1 0 0 S26 X X 1 NOTES: 1. X: Don’t care. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 67

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 Port P8 (P8.0 to P8.1) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP88.XX)) XX FFUUNNCCTTIIOONN P8DIR.x P8SEL.x LCDS24 P8.0/S25 0 P8.0 (I/O) I: 0, O: 1 0 0 S25 X X 1 P8.1/S24 1 P8.0 (I/O) I: 0, O: 1 0 0 S24 X X 1 NOTES: 1. X: Don’t care. Port P8 (P8.2 to P8.5) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP88.XX)) XX FFUUNNCCTTIIOONN P8DIR.x P8SEL.x LCDS20 P8.2/S23 2 P8.2 (I/O) I: 0, O: 1 0 0 S23 X X 1 P8.3/S22 3 P8.3 (I/O) I: 0, O: 1 0 0 S22 X X 1 P8.4/S21 4 P8.4 (I/O) I: 0, O: 1 0 0 S21 X X 1 P8.5/S20 5 P8.5 (I/O) I: 0, O: 1 0 0 S23 X X 1 NOTES: 1. X: Don’t care. Port P8 (P8.6 to P8.7) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP88.XX)) XX FFUUNNCCTTIIOONN P8DIR.x P8SEL.x LCDS16 P8.6/S19 6 P8.6 (I/O) I: 0, O: 1 0 0 S19 X X 1 P8.7/S18 7 P8.7 (I/O) I: 0, O: 1 0 0 S18 X X 1 NOTES: 1. X: Don’t care. 68 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 Port P9 (P9.0 to P9.1) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP99.XX)) XX FFUUNNCCTTIIOONN P9DIR.x P9SEL.x LCDS16 P9.0/S17 0 P9.0 (I/O) I: 0, O: 1 0 0 S17 (see Note 1) X X 1 P9.1/S16 1 P9.1 (I/O) I: 0, O: 1 0 0 S16 (see Note 1) X X 1 NOTES: 1. X: Don’t care. Port P9 (P9.2 to P9.5) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP99.XX)) XX FFUUNNCCTTIIOONN P9DIR.x P9SEL.x LCDS12 P9.2/S15 2 P9.2 (I/O) I: 0, O: 1 0 0 S15 X X 1 P9.3/S14 3 P9.3 (I/O) I: 0, O: 1 0 0 S14 X X 1 P9.4/S13 4 P9.4 (I/O) I: 0, O: 1 0 0 S13 X X 1 P9.5/S12 5 P9.5 (I/O) I: 0, O: 1 0 0 S12 X X 1 NOTES: 1. X: Don’t care. Port P9 (P9.6 to P9.7) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP99.XX)) XX FFUUNNCCTTIIOONN P9DIR.x P9SEL.x LCDS8 P9.6/S11 6 P9.6 (I/O) I: 0, O: 1 0 0 S11 X X 1 P9.7/S10 7 P9.7 (I/O) I: 0, O: 1 0 0 S10 X X 1 NOTES: 1. X: Don’t care. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 69

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 Port P10 (P10.0 to P10.1) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP1100.XX)) XX FFUUNNCCTTIIOONN P10DIR.x P10SEL.x LCDS8 P10.0/S8 0 P10.0 (I/O) I: 0, O: 1 0 0 S8 X X 1 P10.1/S7 1 P10.1 (I/O) I: 0, O: 1 0 0 S7 X X 1 NOTES: 1. X: Don’t care. Port P10 (P10.2 to P10.5) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP1100.XX)) XX FFUUNNCCTTIIOONN P10DIR.x P10SEL.x LCDS4 P10.2/S7 2 P10.2 (I/O) I: 0, O: 1 0 0 S7 X X 1 P10.3/S6 3 P10.3 (I/O) I: 0, O: 1 0 0 S6 X X 1 P10.4/S5 4 P10.4 (I/O) I: 0, O: 1 0 0 S5 X X 1 P10.5/S4 5 P10.5 (I/O) I: 0, O: 1 0 0 S4 X X 1 NOTES: 1. X: Don’t care. Port P10 (P10.6 to P10.7) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP1100.XX)) XX FFUUNNCCTTIIOONN P10DIR.x P10SEL.x LCDS0 P10.6/S3 6 P10.6 (I/O) I: 0, O: 1 0 0 S3 X X 1 P10.7/S2 7 P10.7 (I/O) I: 0, O: 1 0 0 S2 X X 1 NOTES: 1. X: Don’t care. 70 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 JTAG pins (TMS, TCK, TDI/TCLK, TDO/TDI), input/output with Schmitt trigger or output TDO Controlled by JTAG Controlled by JTAG TDO/TDI JTAG Controlled DV by JTAG CC TDI Burn and Test Fuse TDI/TCLK Test DV and CC Emulation TMS Module TMS DV CC TCK TCK RST/NMI Tau ~ 50 ns D Brownout G U S D TCK U G S POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 71

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 JTAG fuse check mode Devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse-check current (I ) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be taken (TF) to avoid accidentally activating the fuse check mode and increasing overall system power consumption. Activation of the fuse-check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse-check mode. After deactivation, the fuse-check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see Figure 27). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). The JTAG pins are terminated internally and, therefore, do not require external termination. Time TMS Goes Low After POR TMS I(TF) ITDI/TCLK Figure 27. Fuse-Check Mode Current 72 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C − MAY 2007 − REVISED MARCH 2011 Data Sheet Revision History Literature Summary Number SLAS545 PRODUCT PREVIEW data sheet SLAS545A PRODUCTION DATA data sheet Section DEVELOPMENT TOOL SUPPORT added, page 2. SLAS545B Split XT1 frequency ranges depending on supply voltage range, page 36. Added parameter fLFXT1, LF, logic to LFXT1, low frequency modes characteristics, page 36. SLAS545C Changed limits on td(SVSon) parameter (page 32) NOTE: Page and figure numbers refer to the specified revision and may differ in other revisions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 73

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MSP430F4783IPZ ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F4783 & no Sb/Br) MSP430F4783IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F4783 & no Sb/Br) MSP430F4784IPZ ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F4784 & no Sb/Br) MSP430F4784IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F4784 & no Sb/Br) MSP430F4793IPZ ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F4793 & no Sb/Br) MSP430F4793IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F4793 & no Sb/Br) MSP430F4794IPZ ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F4794 & no Sb/Br) MSP430F4794IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F4794 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) MSP430F4783IPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2 MSP430F4784IPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2 MSP430F4793IPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2 MSP430F4794IPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) MSP430F4783IPZR LQFP PZ 100 1000 350.0 350.0 43.0 MSP430F4784IPZR LQFP PZ 100 1000 350.0 350.0 43.0 MSP430F4793IPZR LQFP PZ 100 1000 350.0 350.0 43.0 MSP430F4794IPZR LQFP PZ 100 1000 350.0 350.0 43.0 PackMaterials-Page2

MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 M 0,17 75 51 76 50 100 26 0,13 NOM 1 25 12,00 TYP Gage Plane 14,20 SQ 13,80 0,25 16,20 SQ 0,05 MIN 0°–7° 15,80 1,45 0,75 1,35 0,45 Seating Plane 1,60 MAX 0,08 4040149/B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

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