MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 (cid:2) (cid:2) Low Supply-Voltage Range, 1.8 V to 3.6 V Serial Onboard Programming, (cid:2) Ultralow-Power Consumption: No External Programming Voltage Needed Active Mode: 250 μ A at 1 MHz, 2.2 V Programmable Code Protection by Security Standby Mode: 1.1 μ A Fuse Off Mode (RAM Retention): 0.1 μ A (cid:2) Integrated LCD Driver With Contrast (cid:2) Five Power Saving Modes Control for Up to 56Segments (cid:2) (cid:2) MSP430x42x0 Family Members Include: Wake-Up From Standby Mode in Less Than 6 μ s MSP430F4250:16KB+256B Flash Memory (cid:2) 256B RAM 16-Bit RISC Architecture, MSP430F4260:24KB+256B Flash Memory 125-ns Instruction Cycle Time 256B RAM (cid:2) 16-Bit Sigma-Delta A/D Converter With MSP430F4270:32KB+256B Flash Memory Internal Reference and Five Differential 256B RAM Analog Inputs (cid:2) For Complete Module Descriptions, See (cid:2) 12-Bit D/A Converter The MSP430x4xx Family User’s Guide, (cid:2) 16-Bit Timer_A With Three Literature Number SLAU056 Capture/Compare Registers (cid:2) For Additional Device Information, See The (cid:2) Brownout Detector MSP430F42x0 Device Erratasheet, (cid:2) Bootstrap Loader Literature Number SLAZ022 description The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 μ s. The MSP430F42x0 is a microcontroller configuration with a 16-bit timer, a high performance 16-bit sigma-delta A/D converter, 12-bit D/A converter, 32 I/O pins, and a liquid crystal display driver. Typical applications for this device include analog and digital sensor systems, digital motor control, remote controls, thermostats, digital timers, hand-held meters, etc. AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC 48-PIN SSOP PLASTIC 48-PIN QFN (DL) (RGZ) MSP430F4250IDL MSP430F4250IRGZ −4400°CC ttoo 8855°CC MSP430F4260IDL MSP430F4260IRGZ MSP430F4270IDL MSP430F4270IRGZ This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2007, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 pin designation, MSP430F42x0 DL PACKAGE (TOP VIEW) TDO/TDI 1 48 P5.4/COM3 TDI/TCLK 2 47 P5.3/COM2 TMS 3 46 P5.2/COM1 TCK 4 45 COM0 RST/NMI 5 44 P2.0/S13 DV 6 43 P2.1/S12 CC DV 7 42 P2.2/S11 SS XIN 8 41 P2.3/S10 XOUT 9 MSP430F42x0IDL 40 P2.4/S9 AV 10 39 P2.5/S8 SS AV 11 38 P2.6/S7 CC V 12 37 P2.7/S6 REF P6.0/A0+ 13 36 S5 P6.1/A0− 14 35 P5.7/S4 P6.2/A1+ 15 34 P5.6/S3 P6.3/A1− 16 33 P5.5/S2 P6.4 17 32 P5.0/S1 P6.5 18 31 P5.1/S0 P6.6 19 30 LCDCAP/R23 P6.7 20 29 LCDREF/R13 P1.7/A2+ 21 28 P1.0/TA0 P1.6/A2− 22 27 P1.1/TA0/MCLK P1.5/TACLK/ACLK/A3+ 23 26 P1.2/TA1/A4− P1.4/A3−/DAC0 24 25 P1.3/TA2/A4+ 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 pin designation, MSP430F42x0 (continued) RGZ PACKAGE (TOP VIEW) 3 2 1 MI LK DI OM OM OM 13 12 N C T C C C 0 S S VCC ST/ CK MS DI/T DO/ 5.4/ 5.3/ 5.2/ OM 2.0/ 2.1/ D R T T T T P P P C P P 47 46 45 44 43 42 41 40 39 38 DV 1 36 P2.2/S11 SS XIN 2 35 P2.3/S10 XOUT 3 34 P2.4/S9 AVSS 4 33 P2.5/S8 AV 5 32 P2.6/S7 CC V 6 31 P2.7/S6 REF MSP430F42x0IRGZ P6.0/A0+ 7 30 S5 P6.1/A0− 8 29 P5.7/S4 P6.2/A1+ 9 28 P5.6/S3 P6.3/A1− 10 27 P5.5/S2 P6.4 11 26 P5.0/S1 P6.5 12 25 P5.1/S0 14 15 16 17 18 19 20 21 22 23 6 7 + − + 0 + − K 0 3 3 P6. P6. A2 A2 A3 AC A4 A4 CL TA R1 R2 7/ 6/ K/ D 2/ 1/ M 0/ F/ P/ P1. P1. ACL A3−/ 3/TA 2/TA TA0/ P1. DRE DCA K/ 4/ 1. 1. 1/ C C CL P1. P P P1. L L A T 5/ 1. P POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 MSP430F42x0 functional block diagram XIN XOUT DVCC DVSS AVCC AVSS P1 P2 P3 P4 P5 P6 8 8 8 8 8 8 ACLK Oscillator Flash RAM Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 FLL+ SMCLK 32KB 256B 8 I/O 8 I/O 8 I/O 8 I/O 8 I/O 8 I/O MCLK 24KB Interrupt Interrupt 16KB Capability Capability 8 MHz MAB CPU incl. 16 Registers MDB Emulation Module Watchdog Basic LCD_A DAC12 POR/ TWimDeTr++ Timer_A3 Timer 1 56 SD16_A 12 Bit Brownout 3 CC Reg 1 Interrupt Segments 16 Bit 1 Channel JTAG 15/16-Bit Vector 1,2,3,4 MUX Voltage Out Interface fLCD RST/NMI 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 MSP430F42x0 Terminal Functions TERMINAL NAME DL RGZ DESCRIPTION I/O NO. NO. TDO/TDI 1 43 I/O Test data output port. TDO/TDI data output or programming data input terminal TDI/TCLK 2 44 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TMS 3 45 I Test mode select. TMS is used as an input port for device programming and test. TCK 4 46 I Test clock. TCK is the clock input port for device programming and test. RST/NMI 5 47 I General-purpose digital I/O / reset input or nonmaskable interrupt input port DVCC 6 48 Digital supply voltage, positive terminal DVSS 7 1 Digital supply voltage, negative terminal XIN 8 2 I Input terminal of crystal oscillator XT1 XOUT 9 3 O Output terminal of crystal oscillator XT1 AVSS 10 4 Analog supply voltage, negative terminal AVCC 11 5 Analog supply voltage, positive terminal VREF 12 6 I/O Analog reference voltage P6.0/A0+ 13 7 I/O General-purpose digital I/O / analog input A0+ P6.1/A0− 14 8 I/O General-purpose digital I/O / analog input A0− P6.2/A1+ 15 9 I/O General-purpose digital I/O / analog input A1+ P6.3/A1− 16 10 I/O General-purpose digital I/O / analog input A1− P6.4 17 11 I/O General-purpose digital I/O P6.5 18 12 I/O General-purpose digital I/O P6.6 19 13 I/O General-purpose digital I/O P6.7 20 14 I/O General-purpose digital I/O P1.7/A2+ 21 15 I/O General-purpose digital I/O / analog input A2+ P1.6/A2− 22 16 I/O General-purpose digital I/O / analog input A2− General-purpose digital I/O / Timer_A, clock signal TACLK input / P1.5/TACLK/ACLK/A3+ 23 17 I/O ACLK output (divided by 1, 2, 4, or 8) / analog input A3+ P1.4/A3−/DAC0 24 18 I/O General-purpose digital I/O / analog input A3− / DAC12 output General-purpose digital I/O / Timer_A, Capture: CCI2A, compare: Out2 output / P1.3/TA2/A4+ 25 19 I/O analog input A4+ General-purpose digital I/O / Timer_A, Capture: CCI1A, compare: Out1 output / P1.2/TA1/A4− 26 20 I/O analog input A4− General-purpose digital I/O / Timer_A. Capture: CCI0B / MCLK output. Note: TA0 is only an P1.1/TA0/MCLK 27 21 I/O input on this pin / BSL Receive General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL P1.0/TA0 28 22 I/O Transmit LCDREF/R13 29 23 External LCD reference voltage input / input port of third most positive analog LCD level (V4 or V3) LCDCAP/R23 30 24 Capacitor connection for LCD charge pump / input port of second most positive analog LCD level (V2) P5.1/S0 31 25 I/O General-purpose digital I/O / LCD segment output 0 P5.0/S1 32 26 I/O General-purpose digital I/O / LCD segment output 1 P5.5/S2 33 27 I/O General-purpose digital I/O / LCD segment output 2 P5.6/S3 34 28 I/O General-purpose digital I/O / LCD segment output 3 P5.7/S4 35 29 I/O General-purpose digital I/O / LCD segment output 4 S5 36 30 O LCD segment output 5 P2.7/S6 37 31 I/O General-purpose digital I/O / LCD segment output 6 P2.6/S7 38 32 I/O General-purpose digital I/O / LCD segment output 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 MSP430F42x0 Terminal Functions (Continued) TERMINAL NAME DL RGZ DESCRIPTION I/O NO. NO. P2.5/S8 39 33 I/O General-purpose digital I/O / LCD segment output 8 P2.4/S9 40 34 I/O General-purpose digital I/O / LCD segment output 9 P2.3/S10 41 35 I/O General-purpose digital I/O / LCD segment output 10 P2.2/S11 42 36 I/O General-purpose digital I/O / LCD segment output 11 P2.1/S12 43 37 I/O General-purpose digital I/O / LCD segment output 12 P2.0/S13 44 38 I/O General-purpose digital I/O / LCD segment output 13 COM0 45 39 O Common output, COM0−3 are used for LCD backplanes. P5.2/COM1 46 40 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes. P5.3/COM2 47 41 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes. P5.4/COM3 48 42 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes. QFN Pad NA None NA QFN package pad connection to DVSS recommended. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture Program Counter PC/R0 that is highly transparent to the application. All operations, other than program-flow instructions, Stack Pointer SP/R1 are performed as register operations in Status Register SR/CG1/R2 conjunction with seven addressing modes for source operand and four addressing modes for Constant Generator CG2/R3 destination operand. General-Purpose Register R4 The CPU is integrated with 16 registers that provide reduced instruction execution time. The General-Purpose Register R5 register-to-register operation execution time is one cycle of the CPU clock. General-Purpose Register R6 Four of the registers, R0 to R3, are dedicated as General-Purpose Register R7 program counter, stack pointer, status register, and constant generator respectively. The General-Purpose Register R8 remaining registers are general-purpose registers. General-Purpose Register R9 Peripherals are connected to the CPU using data, General-Purpose Register R10 address, and control buses, and can be handled with all instructions. General-Purpose Register R11 instruction set General-Purpose Register R12 The instruction set consists of 51 instructions with three formats and seven address modes. Each General-Purpose Register R13 instruction can operate on word and byte data. Table1 shows examples of the three types of General-Purpose Register R14 instruction formats; the address modes are listed General-Purpose Register R15 in Table2. Table 1. Instruction Word Formats Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 −−−> R5 Single operands, destination only e.g. CALL R8 PC −−>(TOS), R8−−> PC Relative jump, un/conditional e.g. JNE Jump-on-equal bit = 0 Table 2. Address Mode Descriptions ADDRESS MODE S D SYNTAX EXAMPLE OPERATION Register (cid:3) (cid:3) MOV Rs,Rd MOV R10,R11 R10 —> R11 Indexed (cid:3) (cid:3) MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)—> M(6+R6) Symbolic (PC relative) (cid:3) (cid:3) MOV EDE,TONI M(EDE) —> M(TONI) Absolute (cid:3) (cid:3) MOV & MEM, & TCDAT M(MEM) —> M(TCDAT) Indirect (cid:3) MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) —> M(Tab+R6) Indirect M(R10) —> R11 (cid:3) MOV @Rn+,Rm MOV @R10+,R11 autoincrement R10 + 2—> R10 Immediate (cid:3) MOV #X,TONI MOV #45,TONI #45 —> M(TONI) NOTE: S = source D = destination POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: (cid:2) Active mode (AM) − All clocks are active (cid:2) Low-power mode 0 (LPM0) − CPU is disabled ACLK and SMCLK remain active, MCLK is available to modules FLL+ loop control remains active (cid:2) Low-power mode 1 (LPM1) − CPU is disabled ACLK and SMCLK remain active, MCLK is available to modules FLL+ loop control is disabled (cid:2) Low-power mode 2 (LPM2) − CPU is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO’s dc-generator remains enabled ACLK remains active (cid:2) Low-power mode 3 (LPM3) − CPU is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO’s dc-generator is disabled ACLK remains active (cid:2) Low-power mode 4 (LPM4); − CPU is disabled ACLK is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO’s dc-generator is disabled Crystal oscillator is stopped 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh−0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 3. Interrupt Sources, Flags, and Vectors of MSP430F42x0 Configuration WORD INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT PRIORITY ADDRESS Power-Up Reset 0FFFEh 15, highest External Reset Watchdog WDTIFG Flash Memory KEYV PC Out-of-Range (see Note 4) (see Note 1) NMI NMIIFG (see Notes 1 and 3) (Non)maskable Oscillator Fault OFIFG (see Notes 1 and 3) (Non)maskable 0FFFCh 14 Flash Memory Access Violation ACCVIFG (see Notes 1 and 3) (Non)maskable 0FFFAh 13 SD16CCTLx SD16OVIFG, SD16_A SD16CCTLx SD16IFG Maskable 0FFF8h 12 (see Notes 1 and 2) 0FFF6h 11 Watchdog Timer WDTIFG Maskable 0FFF4h 10 0FFF2h 9 0FFF0h 8 0FFEEh 7 Timer_A3 TACCR0 CCIFG0 (see Note 2) Maskable 0FFECh 6 TACCR1 CCIFG1 and TACCR2 CCIFG2, Timer_A3 Maskable 0FFEAh 5 TAIFG (see Notes 1 and 2) I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0FFE8h 4 DAC12 DAC12_0IFG Maskable 0FFE6h 3 (see Note 2) 0FFE4h 2 I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0FFE2h 1 Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest NOTES: 1. Multiple source flags 2. Interrupt flags are located in the module. 3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. 4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh) or from within unused address ranges (MSP430F4270, MSP430F4260: from 0300h to 0BFFh and from 01100h to 07FFFh, MSP430F4250: from 0300h to 0BFFh and from 01100h to 0BFFFh). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 special function registers The MSP430 special function registers(SFR) are located in the lowest address space, and are organized as byte mode registers. SFRs should be accessed with byte instructions. interrupt enable registers 1 and 2 Address 7 6 5 4 3 2 1 0 0h ACCVIE NMIIE OFIE WDTIE rw–0 rw–0 rw–0 rw–0 WDTIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured as a general-purpose timer. OFIE: Oscillator-fault-interrupt enable NMIIE: Nonmaskable-interrupt enable ACCVIE: Flash access violation interrupt enable Address 7 6 5 4 3 2 1 0 01h BTIE rw–0 BTIE: Basic timer interrupt enable interrupt flag registers 1 and 2 Address 7 6 5 4 3 2 1 0 02h NMIIFG OFIFG WDTIFG rw–0 rw–1 rw–(0) WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation Reset on V power-on or a reset condition at the RST/NMI pin in reset mode CC OFIFG: Flag set on oscillator fault NMIIFG: Set via RST/NMI pin Address 7 6 5 4 3 2 1 0 03h BTIFG rw–0 BTIFG: Basic timer flag 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 module enable registers 1 and 2 Address 7 6 5 4 3 2 1 0 04h Address 7 6 5 4 3 2 1 0 05h Legend: rw: Bit Can Be Read and Written rw–0,1: Bit Can Be Read and Written. It Is Reset or Set by PUC. rw–(0,1): Bit Can Be Read and Written. It Is Reset or Set by POR. SFR Bit Not Present in Device memory organization MSP430F4250 MSP430F4260 MSP430F4270 Memory Size 16KB 24KB 32KB Main: interrupt vector Flash 0FFFFh − 0FFE0h 0FFFFh − 0FFE0h 0FFFFh − 0FFE0h Main: code memory Flash 0FFFFh − 0C000h 0FFFFh − 0A000h 0FFFFh − 08000h Information memory Size 256 Byte 256 Byte 256 Byte Flash 010FFh − 01000h 010FFh − 01000h 010FFh − 01000h Boot memory Size 1KB 1KB 1KB ROM 0FFFh − 0C00h 0FFFh − 0C00h 0FFFh − 0C00h RAM Size 256 Byte 256 Byte 256 Byte 02FFh − 0200h 02FFh − 0200h 02FFh − 0200h Peripherals 16-bit 01FFh − 0100h 01FFh − 0100h 01FFh − 0100h 8-bit 0FFh − 010h 0FFh − 010h 0FFh − 010h 8-bit SFR 0Fh − 00h 0Fh − 00h 0Fh − 00h bootstrap loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089. BSL Function DL Package Pins RGZ Package Pins Data Transmit 28 − P1.0 22 − P1.0 Data Receive 27 − P1.1 21 − P1.1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: (cid:2) Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size. (cid:2) Segments 0 to n may be erased in one step, or each segment may be individually erased. (cid:2) Segments A and B can be erased individually, or as a group with segments 0−n. Segments A and B are also called information memory. (cid:2) New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use. 16KB 24KB 32KB 0FFFFh 0FFFFh 0FFFFh Segment 0 w/ Interrupt Vectors 0FE00h 0FE00h 0FE00h 0FDFFh 0FDFFh 0FDFFh Segment 1 0FC00h 0FC00h 0FC00h 0FBFFh 0FBFFh 0FBFFh Segment 2 0FA00h 0FA00h 0FA00h 0F9FFh 0F9FFh 0F9FFh Main Memory 0C400h 0A400h 08400h 0C3FFh 0A3FFh 083FFh Segment n-1 0C200h 0A200h 08200h 0C1FFh 0A1FFh 081FFh Segment n† 0C000h 0A000h 08000h 010FFh 010FFh 010FFh Segment A 01080h 01080h 01080h Information 0107Fh 0107Fh 0107Fh Memory Segment B 01000h 01000h 01000h 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, Literature Number SLAU056. oscillator and system clock The clock system in the MSP430F42x0 family of devices is supported by the FLL+ module that includes support for a 32768 Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low-power consumption. The FLL+ features digital frequency locked loop (FLL) hardware which in conjunction with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μ s. The FLL+ module provides the following clock signals: (cid:2) Auxiliary clock (ACLK), sourced from a 32768 Hz watch crystal or a high frequency crystal. (cid:2) Main clock (MCLK), the system clock used by the CPU. (cid:2) Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. (cid:2) ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8. brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and power-off. The CPU begins code execution after the brownout circuit releases the device reset. However, V may not have ramped to V at that time. The user must insure the default FLL+ settings are not CC CC(min) changed until V reaches V . CC CC(min) digital I/O There are four 8-bit I/O ports implemented—ports P1, P2, P5 and P6: (cid:2) All individual I/O bits are independently programmable. (cid:2) Any combination of input, output, and interrupt conditions is possible. (cid:2) Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. (cid:2) Read/write access to port-control registers is supported by all instructions. Basic Timer1 The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts. LCD driver with regulated charge pump The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2−MUX, 3−MUX, and 4−MUX LCDs are supported by this peripheral. The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump. Furthermore it is possible to control the level of the LCD voltage and thus contrast in software. watchdog timer The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_A3 Signal Connections Input Pin Number DDeevviiccee IInnppuutt MMoodduullee MMoodduullee MMoodduullee OOuuttppuutt Output Pin Number DDLL RRGGZZ SSiiggnnaall IInnppuutt NNaammee BBlloocckk SSiiggnnaall DDLL RRGGZZ 23 - P1.5 17 - P1.5 TACLK TACLK ACLK ACLK TTiimmeerr NNAA SMCLK SMCLK 23 - P1.5 17 - P1.5 TACLK INCLK 28 - P1.0 22 - P1.0 TA0 CCI0A 28 - P1.0 22 - P1.0 27 - P1.1 21 - P1.1 TA0 CCI0B CCCCRR00 TTAA00 DVSS GND DVCC VCC 26 - P1.2 20 - P1.2 TA1 CCI1A 26 - P1.2 20 - P1.2 26 - P1.2 20 - P1.2 TA1 CCI1B CCCCRR11 TTAA11 DVSS GND DVCC VCC 25 - P1.3 19 - P1.3 TA2 CCI2A 25 - P1.3 19 - P1.3 ACLK (internal) CCI2B CCCCRR22 TTAA22 DVSS GND DVCC VCC SD16_A The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit sigma-delta core and reference generator. In addition to external analog inputs, an internal V sense and CC temperature sensor are also available. DAC12 The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 peripheral file map PERIPHERALS WITH WORD ACCESS Watchdog Watchdog timer control WDTCTL 0120h Timer__A3 Capture/compare register 2 TACCR2 0176h Capture/compare register 1 TACCR1 0174h Capture/compare register 0 TACCR0 0172h Timer_A register TAR 0170h Capture/compare control 2 TACCTL2 0166h Capture/compare control 1 TACCTL1 0164h Capture/compare control 0 TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interrupt vector TAIV 012Eh Flash Flash control 3 FCTL3 012Ch Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h DAC12 DAC12_0 data DAC12_0DAT 01C8h DAC12_0 control DAC12_0CTL 01C0h SD16__A General Control SD16CTL 0100h (see also: Channel 0 Control SD16CCTL0 0102h PPeerriipphheerraallss wwiitthh BByyttee AAcccceessss)) Interrupt vector word register SD16IV 0110h Channel 0 conversion memory SD16MEM0 0112h PERIPHERALS WITH BYTE ACCESS SD16_A Channel 0 Input Control SD16INCTL0 0B0h ((sseeee aallssoo:: Peripherals with Analog Enable SD16AE 0B7h Word Access) LCD_A LCD Voltage Control 1 LCDAVCTL1 0AFh LCD Voltage Control 0 LCDAVCTL0 0AEh LCD Voltage Port Control 1 LCDAPCTL1 0ADh LCD Voltage Port Control 0 LCDAPCTL0 0ACh LCD memory 20 LCDM20 0A4h : : : LCD memory 16 LCDM16 0A0h LCD memory 15 LCDM15 09Fh : : : LCD memory 1 LCDM1 091h LCD control and mode LCDACTL 090h FLL+ Clock FLL+ Control 1 FLL_CTL1 054h FLL+ Control 0 FLL_CTL0 053h System clock frequency control SCFQCTL 052h System clock frequency integrator SCFI1 051h System clock frequency integrator SCFI0 050h Basic Timer1 BT counter 2 BTCNT2 047h BT counter 1 BTCNT1 046h BT control BTCTL 040h POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS (CONTINUED) Port P6 Port P6 selection P6SEL 037h Port P6 direction P6DIR 036h Port P6 output P6OUT 035h Port P6 input P6IN 034h Port P5 Port P5 selection P5SEL 033h Port P5 direction P5DIR 032h Port P5 output P5OUT 031h Port P5 input P5IN 030h Port P2 Port P2 selection P2SEL 02Eh Port P2 interrupt enable P2IE 02Dh Port P2 interrupt-edge select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h Port P1 Port P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt-edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h Sppecial functions SFR module enable 2 ME2 005h SFR module enable 1 ME1 004h SFR interrupt flag 2 IFG2 003h SFR interrupt flag 1 IFG1 002h SFR interrupt enable 2 IE2 001h SFR interrupt enable 1 IE1 000h 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Voltage applied at V to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V CC SS Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA Storage temperature, T : (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C stg (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TDI/TCLK pin when blowing the JTAG fuse. recommended operating conditions MIN NOM MAX UNITS Supply voltage during program execution (see Note 1), 1.8 3.6 V VCC (AVCC = DVCC = VCC) Supply voltage during flash memory programming (see Note 1), 2.5 3.6 V VCC (AVCC = DVCC = VCC) Supply voltage, VSS (AVSS = DVSS = VSS) 0 0 V Operating free-air temperature range, TA −40 85 °C LF selected, Watch crystal 32.768 kHz XTS_FLL=0 LFXT1 crystal frequency, f(LFXT1) XT1 selected, Ceramic resonator 450 8000 kHz ((sseeee NNoottee 22)) XTS_FLL=1 XT1 selected, Crystal 1000 8000 kHz XTS_FLL=1 VCC = 1.8 V DC 4.15 PPrroocceessssoorr ffrreeqquueennccyy ((ssiiggnnaall MMCCLLKK)), ff(System) VCC = 3.6 V DC 8 MMHHzz NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V betweeen AVCC and DVCC can be tolerated during power up and operation. 2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal. fSystem (MHz) ÎÎÎÎÎ 8 MHz ÎÎÎÎÎ Supply voltage range, Supply voltage range, MSP430F42x0, MSP430F42x0, duÎringÎÎÎÎduring flash memory programming program execution ÎÎÎÎÎ ÎÎÎÎÎ 4.15 MHz ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 1.8 2.5 3 3.6 Supply Voltage − V Figure 1. Frequency vs Supply Voltage, typical characteristic POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) supply current into AV + DV excluding external current CC CC PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Active mode, (see Note 1) VCC = 2.2 V 250 370 II(AM) fffX(((MMATCCCSLLL=KKK0))) , = == S 3ff((E2SS,LMM7MCC68LL=KK (H0)) ,==z1 )11 MMHHzz,, TTA = −4400°°CC ttoo 8855°°CC VCC = 3 V 400 520 μ AA LLooww-ppoowweerr mmooddee,, ((LLPPMM00)) VCC = 2.2 V 55 70 II(LPM0) (see Note 1 and Note 4) TTA = −4400°°CC ttoo 8855°°CC VCC = 3 V 95 110 μ AA Low-power mode, (LPM2), VCC = 2.2 V 11 14 ff((MMCCLLKK)) == ff ((SSMMCCLLKK)) == 00 MMHHzz,, II(LPM2) f(ACLK) = 32,768 Hz, SCG0 = 0 TTA = −4400°°CC ttoo 8855°°CC μ AA (see Note 2 and Note 4) VCC = 3 V 17 22 TA = −40°C 1.0 2.0 LLooww--ppoowweerr mmooddee,, ((LLPPMM33)) TA = 25°C 1.1 2.0 ff((MMCCLLKK)) = ff((SSMMCCLLKK)) = 00 MMHHzz,, TA = 60°C VVCC = 22.22 VV 2.0 3.0 f(ACLK) = 32,768 Hz, SCG0 = 1 TA = 85°C 3.5 6.0 II(LPM3) BBLLCCaassDDiicc_ AATT iieemmnneeaarrbb11ll eeeeddnn,,aa LLbbCClleeDDddCC , PPAAEECCNNLL KK== ss00ee::lleecctteedd TA = −40°C 1.8 2.8 μ AA ((static mode ;; fLLCCDD = f((AACCLLKK))/32)) TA = 25°C 1.6 2.7 (see Note 2, Note 3, and Note 4) TA = 60°C VVCC = 33 VV 2.5 3.5 TA = 85°C 4.2 7.5 LLooww--ppoowweerr mmooddee,, ((LLPPMM33)) TA = −40°C 2.5 3.5 ff((MMCCLLKK)) = ff((SSMMCCLLKK)) = 00 MMHHzz,, TA = 25°C VVCCCC = 22..22 VV 2.5 3.5 f(ACLK) = 32,768 Hz, SCG0 = 1 TA = 85°C 3.8 6.0 II(LPM3) BBLLCCaassDDiicc_ AATT iieemmnneeaarrbb11ll eeeeddnn,,aa LLbbCClleeDDddCC , PPAAEECCNNLL KK== ss00ee::lleecctteedd TA = −40°C 2.9 4.0 μ AA ((4-mux mode;; fLLCCDD = f((AACCLLKK))/32)) TA = 25°C VVCCCC = 33 VV 2.9 4.0 (see Note 2, Note 3, and Note 4) TA = 85°C 4.4 7.5 TA = −40°C 0.1 0.5 TA = 25°C 0.1 0.5 TA = 60°C VVCC = 22.22 VV 0.7 1.1 Low-power mode, (LPM4) TA = 85°C 1.7 3.0 II(LPM4) ffff(((MAACCCLLLKKK))) === 0000 HHMMzzHH,, zzSS,CC ff(GGSM00 C==L K11) ((=ss ee00ee MM NNHHoozzttee, 22 aanndd NNoottee 44)) TA = −40°C 0.1 0.8 μ AA TA = 25°C 0.1 0.8 TA = 60°C VVCC = 33 VV 0.8 1.2 TA = 85°C 1.9 3.5 NOTES: 1. Timer_A is clocked by f(DCOCLK) = f(DCO) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. 2. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. 3. The LPM3 currents are characterized with a Micro Crystal CC4V−T1A (9pF) crystal and OSCCAPx=01h. 4. Current for brownout included. Current consumption of active mode versus system frequency I(AM) = I(AM) [1 MHz] × f(System) [MHz] Current consumption of active mode versus supply voltage I(AM) = I(AM) [3 V] + 175 μ A/V × (VCC – 3 V) 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SCHMITT-trigger inputs − Ports P1, P2, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC = 2.2 V 1.1 1.55 VVIT+ PPoossiittiivvee-ggooiinngg iinnppuutt tthhrreesshhoolldd vvoollttaaggee VCC = 3 V 1.5 1.98 VV VCC = 2.2 V 0.4 0.9 VVIT− NNeeggaattiivvee-ggooiinngg iinnppuutt tthhrreesshhoolldd vvoollttaaggee VCC = 3 V 0.9 1.3 VV VCC = 2.2 V 0.3 1.1 VVhys IInnppuutt vvoollttaaggee hhyysstteerreessiiss ((VVIT+ − VVIT−)) VV VCC = 3 V 0.5 1 inputs Px.x, TAx PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT PPoorrtt PP11,, PP22:: PP11..xx ttoo PP22..xx,, eexxtteerrnnaall ttrriiggggeerr ssiiggnnaall 2.2 V 62 tt(int) EExxtteerrnnaall iinntteerrrruupptt ttiimmiinngg for the interrupt flag, (see Note 1) 3 V 50 nnss 2.2 V 62 tt(cap) TTiimmeerr_AA ccaappttuurree ttiimmiinngg TTAA00, TTAA11, TTAA22 nnss 3 V 50 TTiimmeerr__AA cclloocckk ffrreeqquueennccyy 2.2 V 8 ff(TAext) externally applied to pin TTAACCLLKK, IINNCCLLKK:: tt(H) == tt(L) 3 V 10 MMHHzz 2.2 V 8 ff(TAint) TTiimmeerr_AA, cclloocckk ffrreeqquueennccyy SSMMCCLLKK oorr AACCLLKK ssiiggnnaall sseelleecctteedd MMHHzz 3 V 10 NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals shorter than t(int). leakage current − Ports P1, P2, P5, and P6 (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Ilkg(Px.y) Lcuerarkeangte Port Px V(Px.y) (see Note 2) VCC = 2.2 V/3 V ±50 nA NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The port pin must be selected as input. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1, P2, P5, and P6 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOH(max) = −1.5 mA, VCC = 2.2 V, See Note 1 VCC−0.25 VCC IOH(max) = −6 mA, VCC = 2.2 V, See Note 2 VCC−0.6 VCC VVOH HHiigghh-lleevveell oouuttppuutt vvoollttaaggee IOH(max) = −1.5 mA, VCC = 3 V, See Note 1 VCC−0.25 VCC VV IOH(max) = −6 mA, VCC = 3 V, See Note 2 VCC−0.6 VCC IOL(max) = 1.5 mA, VCC = 2.2 V, See Note 1 VSS VSS+0.25 IOL(max) = 6 mA, VCC = 2.2 V, See Note 2 VSS VSS+0.6 VVOL LLooww-lleevveell oouuttppuutt vvoollttaaggee VV IOL(max) = 1.5 mA, VCC = 3 V, See Note 1 VSS VSS+0.25 IOL(max) = 6 mA, VCC = 3 V, See Note 2 VSS VSS+0.6 NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum specified voltage drop. 2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum specified voltage drop. output frequency PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f(Px.y) (x = 1, 2, 5, 6; 0 ≤ y ≤ 7) CILL = = ± 210.5 p mF,A VCC = 2.2 V / 3 V DC fSystem MHz f(MCLK) P1.1/TA0/MCLK CL = 20 pF fSystem MHz PP11..11//TTAA00//MMCCLLKK,, f(MCLK) = f(XT1) 40% 60% t(Xdc) Duty cycle of output frequency CL = 20 pF, 50%− 50%+ VCC = 2.2 V / 3 V f(MCLK) = f(DCOCLK) 15 ns 50% 15 ns 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1, P2, P5, and P6 (continued) TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT vs vs LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE 30 50 ent − mA 25 VPC1.C0 = 2.2 V TA =T 2A5 =°C −40°C nt − mA 4405 VPC1.C0 = 3 V TA T=A 2 =5 °−C40°C r e put Cur 20 TA = 85°C ut Curr 3305 TA = 85°C Out utp vel 15 el O 25 e v Low-l 10 ow-le 20 cal al L 15 ypi pic 10 T 5 y − L − T 5 O L O I 0 I 0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOL − Low-Level Output Voltage − V VOL − Low-Level Output Voltage − V Figure 2 Figure 3 TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT vs vs HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE 0 0 VCC = 2.2 V VCC = 3 V mA P1.0 mA −5 P1.0 Current − −5 Current − −−1150 High-level Output −−1150 High-level Output −−−−33225050 I− Typical OH −−2250 TA = 85°C TA = −40°C TA = 25°C I− Typical OH −−−544050 TA = 85°C TA = −40°CTA = 25°C 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH − High-Level Output Voltage − V VOH − High-Level Output Voltage − V Figure 4 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) wake-up LPM3 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f = 1 MHz 6 ttdd((LLPPMM33)) DDeellaayy ttiimmee f = 2 MHz VVCCCC = 22..22 VV//33 VV 6 μμ ss f = 3 MHz 6 RAM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRAMh CPU halted (see Note 1) 1.6 V NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution should take place during this supply voltage condition. LCD_A PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Charge pump enabled VCC(LCD) Supply Voltage Range (LCDCPEN = 1; VLCDx > 0000) 2.2 3.6 V CLCD Capacitor on LCDCAP (see Note 1) C(LhCaDrgCeP pEuNm =p 1e;n VabLlCeDdx > 0000) 4.7 μ F VLCD(typ)=3V; LCDCPEN = 1; VLCDx= 1000, all segments on ICC(LCD) Average Supply Current (see Note 2) fLCD= fACLK/32 2.2 V 3.8 μ A no LCD connected (see Note 3) TA = 25°C fLCD LCD frequency 1.1 kHz VLCD LCD voltage VLCDx = 0000 VCC V VLCD LCD voltage VLCDx = 0001 2.60 V VLCD LCD voltage VLCDx = 0010 2.66 V VLCD LCD voltage VLCDx = 0011 2.72 V VLCD LCD voltage VLCDx = 0100 2.78 V VLCD LCD voltage VLCDx = 0101 2.84 V VLCD LCD voltage VLCDx = 0110 2.90 V VLCD LCD voltage VLCDx = 0111 2.96 V VLCD LCD voltage VLCDx = 1000 3.02 V VLCD LCD voltage VLCDx = 1001 3.08 V VLCD LCD voltage VLCDx = 1010 3.14 V VLCD LCD voltage VLCDx = 1011 3.20 V VLCD LCD voltage VLCDx = 1100 3.26 V VLCD LCD voltage VLCDx = 1101 3.32 V VLCD LCD voltage VLCDx = 1110 3.38 V VLCD LCD voltage VLCDx = 1111 3.44 3.60 V RLCD LCD Driver Output impedance VVLLCCDD =x 3=V 1; 0L0C0D, ICLOPAEDN = = ± 11;0μ A 2.2 V 10 kΩ NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device. 2. Refer to the supply current specifications I(LPM3) for additional current specifications with the LCD_A module active. 3. Connecting an actual display will increase the current consumption depending on the size of the LCD. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) POR/brownout reset (BOR) (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(BOR) 2000 μ s VCC(start) dVCC/dt ≤ 3 V/s (see Figure 6) 0.7 × V(B_IT−) V V(B_IT−) Brownout dVCC/dt ≤ 3 V/s (see Figure 6 through Figure 8) 1.71 V Vhys(B_IT−) (see Note 2) dVCC/dt ≤ 3 V/s (see Figure 6) 70 130 180 mV Pulse length needed at RST/NMI pin to accepted reset internally, t(reset) VCC = 2.2 V/3 V 2 μ s NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT−) + Vhys(B_IT−) is ≤ 1.8V. 2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−). The default FLL+ settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout. typical characteristics V CC V hys(B_IT−) V (B_IT−) VCC(start) 1 0 td(BOR) Figure 6. POR/Brownout Reset (BOR) vs Supply Voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) typical characteristics (continued) 2 VCC tpw 3 V VCC = 3 V Typical Conditions 1.5 V − p) o r 1 d C( C VCC(drop) V 0.5 0 0.001 1 1000 1 ns 1 ns tpw − Pulse Width − μ s tpw − Pulse Width − μ s Figure 7. V Level With a Square Voltage Drop to Generate a POR/Brownout Signal (CC)min VCC tpw 2 3 V VCC = 3 V V 1.5 Typical Conditions − p) o dr 1 C( C VCC(drop) V 0.5 tf = tr 0 0.001 1 1000 tf tr tpw − Pulse Width − μ s tpw − Pulse Width − μ s Figure 8. V Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal CC(drop) 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) DCO PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT f(DCOCLK) NfC(rDysCtOal) ==0 312E.7h6, 8F NkH_8z=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0, 2.2 V/3 V 1 MHz 2.2 V 0.3 0.65 1.25 ff(DCO=2) FFNN_88=FFNN_44=FFNN_33=FFNN_22=00 ;; DDCCOOPPLLUUSS = 11 3 V 0.3 0.7 1.3 MMHHzz 2.2 V 2.5 5.6 10.5 ff(DCO=27) FFNN_88=FFNN_44=FFNN_33=FFNN_22=00;; DDCCOOPPLLUUSS = 11 3 V 2.7 6.1 11.3 MMHHzz 2.2 V 0.7 1.3 2.3 ff(DCO=2) FFNN_88=FFNN_44=FFNN_33=00, FFNN_22=11;; DDCCOOPPLLUUSS = 11 3 V 0.8 1.5 2.5 MMHHzz 2.2 V 5.7 10.8 18 ff(DCO=27) FFNN_88=FFNN_44=FFNN_33=00, FFNN_22=11;; DDCCOOPPLLUUSS = 11 3 V 6.5 12.1 20 MMHHzz 2.2 V 1.2 2 3 ff(DCO=2) FFNN_88=FFNN_44=00, FFNN_33= 11, FFNN_22=xx;; DDCCOOPPLLUUSS = 11 3 V 1.3 2.2 3.5 MMHHzz 2.2 V 9 15.5 25 ff(DCO=27) FFNN_88=FFNN_44=00, FFNN_33= 11, FFNN_22=xx;; DDCCOOPPLLUUSS = 11 3 V 10.3 17.9 28.5 MMHHzz 2.2 V 1.8 2.8 4.2 ff(DCO=2) FFNN_88=00, FFNN_44= 11, FFNN_33= FFNN_22=xx;; DDCCOOPPLLUUSS = 11 3 V 2.1 3.4 5.2 MMHHzz 2.2 V 13.5 21.5 33 ff(DCO=27) FFNN_88=00, FFNN_44=11, FFNN_33= FFNN_22=xx;; DDCCOOPPLLUUSS = 11 3 V 16 26.6 41 MMHHzz 2.2 V 2.8 4.2 6.2 ff(DCO=2) FFNN_88=11, FFNN_44=FFNN_33=FFNN_22=xx;; DDCCOOPPLLUUSS = 11 3 V 4.2 6.3 9.2 MMHHzz 2.2 V 21 32 46 ff(DCO=27) FFNN_88=11,FFNN_44=FFNN_33=FFNN_22=xx;; DDCCOOPPLLUUSS = 11 3 V 30 46 70 MMHHzz SStteepp ssiizzee bbeettwweeeenn aaddjjaacceenntt DDCCOO ttaappss:: 1 < TAP ≤ 20 1.06 1.11 SSn Sn = fDCO(Tap n+1) / fDCO(Tap n) (see Figure 10 for taps 21 to 27) TAP = 27 1.07 1.17 DDt TTDee =mm 2pp;ee DrraaCttuuOrreeP LddUrriiffStt,, =NN ((0DD,CC (OOse)) ==e N0011oEEtehh ,,2 FF)NN__88==FFNN__44==FFNN__33==FFNN__22==00 2.32 VV ––00..22 ––00..33 ––00..44 %%//(cid:4)(cid:4)CC DV DDr =ift 2w; iDthC VOCPCL vUaSri a=t i0on, N(DCO) = 01Eh, FN_8=FN_4=FN_3=FN_2=0 0 5 15 %/V f f (DCO) (DCO) f(DCO3V) f(DCO20(cid:2)C) 1.0 1.0 0 1.8 2.4 3.0 3.6 −40 −20 0 20 40 60 85 VCC − V TA − °C Figure 9. DCO Frequency vs Supply Voltage V and vs Ambient Temperature CC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) s ÎÎÎÎÎÎÎÎÎÎÎÎÎ p a 1.17 O T ÎÎÎÎÎÎÎÎÎÎÎÎÎ C D ÎÎÎÎÎÎÎÎÎÎÎÎÎ n e ÎÎÎÎÎÎÎÎÎÎÎÎÎ e w et ÎÎÎÎÎÎÎÎÎÎÎÎÎ b atio 1.11 ÎÎÎÎÎÎÎÎMaxÎÎÎÎÎ R e ÎÎÎÎÎÎÎÎÎÎÎÎÎ z si ÎÎÎÎÎÎÎÎÎÎÎÎÎ p e St ÎÎÎÎÎÎÎÎÎÎÎÎÎ S - n 11..0076 ÎÎÎÎÎÎÎÎÎÎÎÎÎ Min 1 20 27 DCO Tap Figure 10. DCO Tap Step Size Legend Tolerance at Tap 27 O) C D f( DCO Frequency Adjusted by Bits 29 to 25 in SCFI1 {N{DCO}} Tolerance at Tap 2 Overlapping DCO Ranges: Uninterrupted Frequency Range FN_2=0 FN_2=1 FN_2=x FN_2=x FN_2=x FN_3=0 FN_3=0 FN_3=1 FN_3=x FN_3=x FN_4=0 FN_4=0 FN_4=0 FN_4=1 FN_4=x FN_8=0 FN_8=0 FN_8=0 FN_8=0 FN_8=1 Figure 11. Five Overlapping DCO Ranges Controlled by FN_x Bits 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) crystal oscillator, LFXT1 oscillator (see Notes 1 and 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OSCCAPx = 0h, VCC = 2.2 V / 3 V 0 IInntteeggrraatteedd iinnppuutt ccaappaacciittaannccee OSCCAPx = 1h, VCC = 2.2 V / 3 V 10 CCXIN (see Note 4) OSCCAPx = 2h, VCC = 2.2 V / 3 V 14 ppFF OSCCAPx = 3h, VCC = 2.2 V / 3 V 18 OSCCAPx = 0h, VCC = 2.2 V / 3 V 0 IInntteeggrraatteedd oouuttppuutt ccaappaacciittaannccee OSCCAPx = 1h, VCC = 2.2 V / 3 V 10 CCXOUT (see Note 4) OSCCAPx = 2h, VCC = 2.2 V / 3 V 14 ppFF OSCCAPx = 3h, VCC = 2.2 V / 3 V 18 VIL VSS 0.2×VCC VIH IInnppuutt lleevveellss aatt XXIINN VVCC = 22.22 VV//33 VV ((sseeee NNoottee 33)) 0.8×VCC VCC VV NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is (CXINxCXOUT) / (CXIN + CXOUT). This is independent of XTS_FLL. 2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed. − Keep as short of a trace as possible between the ’F42x0 and the crystal. − Design a good ground plane around the oscillator pins. − Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. − Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. − Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. − If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. − Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. 3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator. 4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SD16_A, power supply and recommended operating conditions PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT AVCC Avonlatalogge supply AAVVCSSC == DDVVSCSC = 0V 2.5 3.6 V SD16BUFx = 00; GAIN: 1,2 3 V 650 950 SSDD1166LLPP == 00,, ffSSDD1166 = 11 MMHHzz,, SD16BUFx = 00; GAIN: 4,8,16 3 V 730 1100 SD16OSR = 256 SD16BUFx = 00; GAIN: 32 3 V 1050 1550 Analog supply SD16LP = 1, SD16BUFx = 00; GAIN: 1 3 V 620 930 IISD16 ccuurrrreenntt iinncclluuddiinngg ffSD16 = 00.55 MMHHzz, μ AA internal reference SD16OSR = 256 SD16BUFx = 00; GAIN: 32 3 V 700 1060 SD16BUFx = 01; GAIN: 1 3 V 850 SSDD1166LLPP == 00,, ffSSDD1166 = 11 MMHHzz,, SD16BUFx = 10; GAIN: 1 3 V 1130 SD16OSR = 256 SD16BUFx = 11; GAIN: 1 3 V 1130 Analog front-end SD16LP = 0 (Low power mode disabled) 3 V 0.03 1 1.1 ffSD16 iinnppuutt cclloocckk MMHHzz frequency SD16LP = 1 (Low power mode enabled) 3 V 0.03 0.5 SD16_A, input range PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT DDiiffffeerreennttiiaall ffuullll ssccaallee Bipolar Mode, SD16UNI = 0 −VREF/2GAIN +VREF/2GAIN mV VVID,FSR input voltage range Unipolar Mode, SD16UNI = 1 0 +VREF/2GAIN mV SD16GAINx = 1 ±500 DDiiffffeerreennttiiaall iinnppuutt SD16GAINx = 2 ±250 voltage range for SD16GAINx = 4 ±125 VVID ssppeecciiffiieedd SSDD1166RREEFFOONN=11 SD16GAINx = 8 ±62 mmVV ppeerrffoorrmmaannccee ((sseeee NNoottee 11)) SD16GAINx = 16 ±31 SD16GAINx = 32 ±15 Input impedance SffDSSDD111666B =U F11MMx =HH zz0,,0 SSDD1166GGAAIINNxx == 312 33 VV 27050 kkΩΩ ZZI ((oonnee iinnppuutt ppiinn to AVSS) fSD16 = 1MHz, SD16GAINx = 1 3 V >10 MΩ SD16BUFx = 01 Differential SffDSSDD111666B =U F11MMx =HH zz0,,0 SSDD1166GGAAININxx = = 3 12 33 VV 310000 410500 kkΩΩ ZZID IInnppuutt iimmppeeddaannccee (IN+ to IN−) fSD16 = 1MHz, SD16GAINx = 1 3 V >10 MΩ SD16BUFx > 00 AAbbssoolluuttee iinnppuutt SD16BUFx = 00 AVSS -0.1V AVCC VVI voltage range SD16BUFx > 00 AVSS AVCC −1.2V VV CCoommmmoonn-mmooddee SD16BUFx = 00 AVSS -0.1V AVCC VVIC input voltage range SD16BUFx > 00 AVSS AVCC −1.2V VV NOTES: 1. The analog input range depends on the reference voltage applied to VREF. If VREF is sourced externally, the full-scale range is defined by VFSR+ = +(VREF/2)/GAIN and VFSR− = −(VREF/2)/GAIN. The analog input range should not exceed 80% of VFSR+ or VFSR−. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SD16_A, performance (f = 30kHz, SD16REFON = 1, SD16BUFx = 01) SD16 PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT SD16GAINx = 1,Signal Amplitude = 500mV 3 V 84 SD16OSRx = 256 Signal-to-noise + SD16GAINx = 1,Signal Amplitude = 500mV SINAD ddiissttoorrttiioonn rraattiioo SD16OSRx = 512 fIN = 2.8Hz 3 V 84 dB SD16GAINx = 1,Signal Amplitude = 500mV 3 V 84 SD16OSRx = 1024 Nominal gain SD16GAINx = 1; SD16OSRx = 1024 3 V 0.97 1.00 1.02 Gain temperature dG/dT SD16GAINx = 1; SD16OSRx = 1024 (see Note 1) 3 V 15 ppm/(cid:4)C drift dG/dVCC Gdraifitn supply voltage S(sDee1 6NGoAteIN 2x) = 1; SD16OSRx = 1024; VCC = 2.5V - 3.6V 0.35 %/V NOTES: 1. Calculated using the box method: (MAX(−40...85(cid:4)C) − MIN(−40...85(cid:4)C))/MIN(−40...85(cid:4)C)/(85C − (−40(cid:4)C)) 2. Calculated using the box method: (MAX(2.5...3.6V) − MIN(2.5...3.6V))/MIN(2.5...3.6V)/(3.6V − 2.5V) SD16_A, performance (f = 1MHz, SD16OSRx = 256, SD16REFON = 1, SD16BUFx = 00) SD16 PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT SD16GAINx = 1,Signal Amplitude = 500mV 3 V 83.5 85 SD16GAINx = 2,Signal Amplitude = 250mV 3 V 81.5 84 SSIINNAADD SSiiggnnaall-ttoo-nnooiissee ++ SD16GAINx = 4,Signal Amplitude = 125mV ffIINN == 5500HHzz,, 3 V 76 79.5 ddBB distortion ratio SD16GAINx = 8,Signal Amplitude = 62mV 100Hz 3 V 73 76.5 SD16GAINx = 16,Signal Amplitude = 31mV 3 V 69 73 SD16GAINx = 32,Signal Amplitude = 15mV 3 V 62 69 SD16GAINx = 1 3 V 0.97 1.00 1.02 SD16GAINx = 2 3 V 1.90 1.96 2.02 SD16GAINx = 4 3 V 3.76 3.86 3.96 GG Nominal gain SD16GAINx = 8 3 V 7.36 7.62 7.84 SD16GAINx = 16 3 V 14.56 15.04 15.52 SD16GAINx = 32 3 V 27.20 28.35 29.76 SD16GAINx = 1 3 V ±0.2 EEOS OOffffsseett eerrrroorr SD16GAINx = 32 3 V ±1.5 %%FFSSRR Offset error SD16GAINx = 1 3 V ±4 ±20 ppppmm ddEEOS//ddTT ttceeommefppfieecrrieaanttuutrree SD16GAINx = 32 3 V ±20 ±100 FSR/(cid:4)C SD16GAINx = 1, Common-mode input signal: 3 V >90 CCoommmmoonn-mmooddee VID = 500 mV, fIN = 50 Hz, 100 Hz CCMMRRRR ddBB rejection ratio SD16GAINx = 32, Common-mode input signal: 3 V >75 VID = 16 mV, fIN = 50 Hz, 100 Hz AC power supply AC PSRR rejection ratio SD16GAINx = 1, VCC = 3 V ± 100 mV, fVCC = 50 Hz 3 V >80 dB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SD16_A, temperature sensor PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Sensor temperature TCSensor coefficient 1.18 1.32 1.46 mV/K VOffset,sensor Sensor offset voltage −100 100 mV Temperature sensor voltage at TA = 85°C 3 V 435 475 515 SSensor outtputt vollttage VVSSeennssoorr ((sseeee NNoottee 22)) Temperature sensor voltage at TA = 25°C 3 V 355 395 435 mmVV Temperature sensor voltage at TA = 0°C 3 V 320 360 400 NOTES: 1. The following formula can be used to calculate the temperature sensor output voltage: VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV] 2. Results based on characterization and/or production test, not TCSensor or VOffset,sensor. SD16_A, built-in voltage reference PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Internal reference VREF voltage SD16REFON = 1, SD16VMIDON = 0 3 V 1.14 1.20 1.26 V Reference supply IREF current SD16REFON = 1, SD16VMIDON = 0 3 V 175 260 μ A TC Temperature coefficient SD16REFON = 1, SD16VMIDON = 0 3 V 18 50 ppm/K CREF VREF load capacitance SD16REFON = 1, SD16VMIDON = 0 (see Note 1) 100 nF ILOAD VcuRrEreFn(I)t maximum load SD16REFON = 1, SD16VMIDON = 0 3 V ±200 nA SD16REFON = 0−>1, SD16VMIDON = 0, tON Turn on time CREF = 100nF 3 V 5 ms DC power supply DC PSR rejection, Δ VREF/Δ VCC SD16REFON = 1, SD16VMIDON = 0, VCC = 2.5 V to 3.6 V 100 uV/V NOTES: 1. There is no capacitance required on VREF. However, a capacitance of at least 100nF is recommended to reduce any reference voltage noise. SD16_A, reference output buffer PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Reference buffer output VREF,BUF voltage SD16REFON = 1, SD16VMIDON = 1 3 V 1.2 V Reference Supply + IREF,BUF Reference output buffer SD16REFON = 1, SD16VMIDON = 1 3 V 385 600 μ A quiescent current Required load CREF(O) capacitance on VREF SD16REFON = 1, SD16VMIDON = 1 470 nF Maximum load current ILOAD,Max on VREF SD16REFON = 1, SD16VMIDON = 1 3 V ±1 mA Maximum voltage varia- tion vs. load current |ILOAD| = 0 to 1mA 3 V −15 +15 mV SD16REFON = 0−>1; SD16VMIDON = 1; tON Turn on time CREF = 470nF 3 V 100 μ s 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 SD16_A, external reference input PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VREF(I) Input voltage range SD16REFON = 0 3 V 1.0 1.25 1.5 V IREF(I) Input current SD16REFON = 0 3 V 50 nA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, supply specifications PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT AVCC = DVCC, AVCC Analog supply voltage AVSS = DVSS =0 V 2.20 3.60 V DAC12AMPx=2, DAC12IR=0, 2.2V/3V 50 110 DAC12_xDAT=0800h DAC12AMPx=2, DAC12IR=1, 2.2V/3V 50 110 SSuuppppllyy CCuurrrreenntt DAC12_xDAT=0800h, VREF,DAC12 = AVCC IIDD (see Notes 1 and 2) DAC12AMPx=5, DAC12IR=1, μ AA 2.2V/3V 200 440 DAC12_xDAT=0800h, VREF,DAC12 = AVCC DAC12AMPx=7, DAC12IR=1, 2.2V/3V 700 1500 DAC12_xDAT=0800h, VREF,DAC12 = AVCC Power supply DAC12_xDAT = 800h, VREF,DAC12 = 1.2V PSRR rejection ratio 2.7V 70 dB Δ AVCC = 100mV (see Notes 3 and 4) NOTES: 1. No load at the output pin assuming that the control bits for the shared pins are set properly. 2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input specifications. 3. PSRR = 20*log{Δ AVCC/Δ VDAC12_xOUT}. 4. VREF is applied externally. The internal reference is not used. 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, linearity specifications (see Figure 12) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Resolution (12-bit Monotonic) 12 bits INL Integral nonlinearity VREF,DAC12 = 1.2V 2.7V ±2.0 ±8.0 LSB (see Note 1) DAC12AMPx = 7, DAC12IR = 1 DNL Differential nonlinearity VREF,DAC12 = 1.2V 2.7V ±0.4 ±1.0 LSB (see Note 1) DAC12AMPx = 7, DAC12IR = 1 Offset voltage w/o calibration VREF,DAC12 = 1.2V 2.7V ±20 DAC12AMPx = 7, DAC12IR = 1 EO (see Notes 1, 2) mmVV Offset voltage with calibration VREF,DAC12 = 1.2V 2.7V ±2.5 DAC12AMPx = 7, DAC12IR = 1 (see Notes 1, 2) dE(O)/dT Offset error temperature coefficient 2.7V ±30 μ V/C (see Note 1) EG Gain error (see Note 1) VREF,DAC12 = 1.2V 2.7V ±3.50 % FSR Gain temperature ppm of dE(G)/dT coefficient (see Note 1) 2.7V 10 FSR/°C DAC12AMPx=2 2.7V 100 TTiimmee ffoorr ooffffsseett ccaalliibbrraattiioonn ttOOffffsseett__CCaall ((sseeee NNoottee 33)) DAC12AMPx=3,5 2.7V 32 mmss DAC12AMPx=4,6,7 2.7V 6 NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and “b” of the first order equation: y = a + b*x. VDAC12_xOUT = EO + (1 + EG) * (VREF,DAC12/4095) * DAC12_xDAT, DAC12IR = 1. 2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON 3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx ={0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may effect accuracy and is not recommended. DAC VOUT DAC Output RLoad= VR+ Ideal transfer AVCC function 2 Offset Error Gain Error CLoad = 100pF Positive Negative DAC Code Figure 12. Linearity Test Load Conditions and Gain/Offset Definition POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, linearity specifications (continued) TYPICAL INL ERROR vs DIGITAL INPUT DATA 4 VCC = 2.2 V, VREF = 1.2V B 3 DAC12AMPx = 7 LS DAC12IR = 1 − r 2 o r r E y 1 rit a e nlin 0 o N al −1 r g e nt −2 − I L N I −3 −4 0 512 1024 1536 2048 2560 3072 3584 4095 DAC12_xDAT − Digital Code TYPICAL DNL ERROR vs DIGITAL INPUT DATA 2.0 B VCC = 2.2 V, VREF = 1.2V LS 1.5 DAC12AMPx = 7 − DAC12IR = 1 r o r 1.0 r E y arit 0.5 e n onli 0.0 N al nti −0.5 e r e Diff −1.0 − L N −1.5 D −2.0 0 512 1024 1536 2048 2560 3072 3584 4095 DAC12_xDAT − Digital Code 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, output specifications PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT No Load, VREF,DAC12 = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, 2.2V/3V 0 0.005 DAC12AMPx = 7 No Load, VREF,DAC12 = AVCC, Output voltage DAC12_xDAT = 0FFFh, DAC12IR = 1, 2.2V/3V AVCC−0.05 AVCC rraannggee DAC12AMPx = 7 VVO (see Note 1, RLoad= 3 kΩ , VREF,DAC12 = AVCC, VV Figure 15) DAC12_xDAT = 0h, DAC12IR = 1, 2.2V/3V 0 0.1 DAC12AMPx = 7 RLoad= 3 kΩ , VREF,DAC12 = AVCC, DAC12_xDAT = 0FFFh, DAC12IR = 1, 2.2V/3V AVCC−0.13 AVCC DAC12AMPx = 7 Max DAC12 CL(DAC12) load capacitance 2.2V/3V 100 pF MMaaxx DDAACC1122 2.2V −0.5 +0.5 IIL(DAC12) load current 3V −1.0 +1.0 mmAA RLoad= 3 kΩ , VO/P(DAC12) < 0.3 V, 2.2V/3V 150 250 DAC12AMPx = 2, DAC12_xDAT = 0h Output RLoad= 3 kΩ , RO/P(DAC12) Resistance VO/P(DAC12) > AVCC−0.3 V 2.2V/3V 150 250 Ω ((sseeee FFiigguurree 1155)) DAC12_xDAT = 0FFFh RLoad= 3 kΩ , 2.2V/3V 1 4 0.3V ≤ VO/P(DAC12) ≤ AVCC − 0.3V NOTES: 1. Data is valid after the offset calibration of the output amplifier. RO/P(DAC12_x) Max ILoad RLoad AVCC DAC12 2 O/P(DAC12_x) CLoad = 100pF Min 0.3 AVCC −0.3V VOUT AVCC Figure 15. DAC12_x Output Resistance Tests POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) 12-bit DAC, reference input specifications PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT RReeffeerreennccee iinnppuutt DAC12IR=0, (see Notes 1 and 2) 2.2V/3V AVCC/3 AVCC+0.2 VVREF voltage range DAC12IR=1, (see Notes 3 and 4) 2.2V/3V AVCC AVCC+0.2 VV RReeffeerreennccee iinnppuutt DAC12IR=0 2.2V/3V 20 MΩ RRii(VREF) resistance DAC12IR=1 2.2V/3V 40 48 56 kΩ NOTES: 1. For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC). 2. The maximum voltage applied at reference input voltage terminal VREF = [AVCC − VE(O)] / [3*(1 + EG)]. 3. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC). 4. The maximum voltage applied at reference input voltage terminal VREF = [AVCC − VE(O)] / (1 + EG). 12-bit DAC, dynamic specifications; V = AV , DAC12IR = 1 (see Figure 16 and Figure 17) REF,DAC12 CC PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT DDAACC1122__xxDDAATT == 880000hh,, DAC12AMPx=0 → {2, 3, 4} 2.2V/3V 60 120 DDAACC1122 oonn- ttOONN ttiimmee EErrrroorrVV((OO)) << ±±00..55 LLSSBB DAC12AMPx=0 → {5, 6} 2.2V/3V 15 30 μμ ss (see Note 1,Figure 16) DAC12AMPx=0 → 7 2.2V/3V 6 12 DAC12AMPx=2 2.2V/3V 100 200 SSeettttlliinngg DDAACC1122_xxDDAATT = ttSS((FFSS)) ttiimmee,ffuullll-ssccaallee 8800hh→→ FF77FFhh→→ 8800hh DAC12AMPx=3,5 2.2V/3V 40 80 μμ ss DAC12AMPx=4,6,7 2.2V/3V 15 30 DDAACC1122__xxDDAATT == DAC12AMPx=2 2.2V/3V 5 SSeettttlliinngg ttiimmee, ttSS((CC--CC)) ccooddee ttoo ccooddee 33FF88hh→→ 440088hh→→ 33FF88hh DAC12AMPx=3,5 2.2V/3V 2 μμ ss BF8h→ C08h→ BF8h DAC12AMPx=4,6,7 2.2V/3V 1 DAC12AMPx=2 2.2V/3V 0.05 0.12 DDAACC1122_xxDDAATT = SSRR SSlleeww RRaattee DAC12AMPx=3,5 2.2V/3V 0.35 0.7 VV//μμ ss 8800hh→→ FF77FFhh→→ 8800hh DAC12AMPx=4,6,7 2.2V/3V 1.5 2.7 DAC12AMPx=2 2.2V/3V 10 DDAACC1122_xxDDAATT = GGlliittcchh eenneerrggyy:: ffuullll-ssccaallee DAC12AMPx=3,5 2.2V/3V 10 nnVV-ss 8800hh→→ FF77FFhh→→ 8800hh DAC12AMPx=4,6,7 2.2V/3V 15 NOTES: 1. RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 16. 2. Slew rate applies to output voltage steps ≥ 200mV. Conversion 1 Conversion 2 Conversion 3 DAC Output VOUT Glitch +/− 1/2 LSB RLoad= 3 kΩ Energy ILoad AVCC 2 +/− 1/2 LSB CLoad = 100pF RO/P(DAC12.x) tsettleLH tsettleHL Figure 16. Settling Time and Glitch Energy Testing 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) Conversion 1 Conversion 2 Conversion 3 VOUT 90% 90% 10% 10% tSRLH tSRHL Figure 17. Slew Rate Testing 12-bit DAC, dynamic specifications continued (T = 25°C unless otherwise noted) A PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2, 2.2V/3V 40 DAC12IR = 1, DAC12_xDAT = 800h 33-ddBB bbanddwiiddtthh, DAC12AMPx = {5, 6}, DAC12SREFx = 2, BW−3dB VDC=1.5V, VAC=0.1VPP DAC12IR = 1, DAC12_xDAT = 800h 2.2V/3V 180 kHz ((sseeee FFiigguurree 1188)) DAC12AMPx = 7, DAC12SREFx = 2, 2.2V/3V 550 DAC12IR = 1, DAC12_xDAT = 800h NOTES: 1. RLOAD = 3 kΩ , CLOAD = 100 pF RLoad= 3 kΩ VeREF+ ILoad DAC12_x AVCC DACx 2 AC CLoad = 100pF DC Figure 18. Test Conditions for 3-dB Bandwidth Specification POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) Flash Memory TEST PARAMETER CONDITIONS VCC MIN NOM MAX UNIT VCC(PGM/ Program and Erase supply voltage 2.5 3.6 V ERASE) fFTG Flash Timing Generator frequency 257 476 kHz IPGM Supply current from DVCC during program 2.5V/3.6V 3 5 mA IERASE Supply current from DVCC during erase 2.5V/3.6V 3 7 mA tCPT Cumulative program time see Note 1 2.5V/3.6V 10 ms tCMErase Cumulative mass erase time see Note 2 2.5V/3.6V 200 ms Program/Erase endurance 104 105 cycles tRetention Data retention duration TJ = 25°C 100 years tWord Word or byte program time 35 tBlock, 0 Block program time for 1st byte or word 30 tBlock, 1-63 Block program time for each additional byte or word 21 tBlock, End Block program end-sequence wait time sseeee NNoottee 33 6 ttFTG tMass Erase Mass erase time 5297 tSeg Erase Segment erase time 4819 NOTES: 1. The cumulative program time must not be exceeded when writing to a 64−byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. 2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles are required). 3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG). JTAG Interface TEST PARAMETER CONDITIONS VCC MIN NOM MAX UNIT 2.2 V 0 5 MHz ffTCK TTCCKK iinnppuutt ffrreeqquueennccyy sseeee NNoottee 11 3 V 0 10 MHz RInternal Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2 2.2 V/ 3 V 25 60 90 kΩ NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected. 2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions. JTAG Fuse (see Note 1) TEST PARAMETER CONDITIONS VCC MIN NOM MAX UNIT VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V VFB Voltage level on TDI/TCLK for fuse-blow: F versions 6 7 V IFB Supply current into TDI/TCLK during fuse blow 100 mA tFB Time to blow fuse 1 ms NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode. 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 input/output schematics Port P1 pin schematic: P1.0, P1.1, input/output with Schmitt−trigger Pad Logic DVSS DVSS DVSS P1DIR.x 0 Direction 1 0: Input 1: Output P1OUT.x 0 Module X OUT 1 P1.0/TA0 P1.1/TA0/MCLK P1SEL.x Bus Keeper EN P1IN.x EN Module X IN D P1IE.x EN P1IRQ.x Q Set P1IFG.x P1SEL.x Interrupt Edge P1IES.x Select Note: x = 0,1 Port P1 (P1.0, P1.1) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP11.XX)) XX FFUUNNCCTTIIOONN P1DIR.x P1SEL.x P1.0/TA0 0 P1.0† Input/Output 0/1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 P1.1/TA0/MCLK 1 P1.1† Input/Output 0/1 0 Timer_A3.CCI0B 0 1 MCLK 1 1 †Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P1 pin schematic: P1.2, input/output with Schmitt−trigger and analog functions INCH=4 Pad Logic 0 AVSS A4− 1 SD16AE.x P1DIR.x 0 Direction 1 0: Input 1: Output P1OUT.x 0 Module X OUT 1 P1.2/TA1/A4− P1SEL.x Bus Keeper EN P1IN.x EN Module X IN D P1IE.x EN P1IRQ.x Q Set P1IFG.x P1SEL.x Interrupt Edge P1IES.x Select Note: x = 2 Port P1 (P1.2) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP11.XX)) XX FFUUNNCCTTIIOONN P1DIR.x P1SEL.x SD16AE.x P1.2/TA1/A4− 2 P1.2† Input/Output 0/1 0 0 Timer_A3.CCI1A 0 1 0 Timer_A3.TA1 1 1 0 A4− (see Notes 3, 4) X X 1 †Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. 4. Negative input to SD16_A (A4−) connected to VSS if corresponding SD16AE.x bit is cleared. 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P1 pin schematic: P1.3, P1.5, P1.7, input/output with Schmitt−trigger and analog functions INCH=y Pad Logic Ay+ SD16AE.x P1DIR.x 0 Direction 1 0: Input 1: Output P1OUT.x 0 Module X OUT 1 P1.3/TA2/A4+ P1.5/TACLK/ACLK/A3+ P1SEL.x Bus P1.7/A2+ Keeper EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q Set P1IFG.x P1SEL.x Interrupt Edge P1IES.x Select Note: x = 3,5,7 y = 4,3,2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 41

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P1 (P1.3, P1.5, P1.7) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP11.XX)) XX FFUUNNCCTTIIOONN P1DIR.x P1SEL.x SD16AE.x P1.3/TA2/A4+ 3 P1.3† Input/Output 0/1 0 0 Timer_A3.CCI2A 0 1 0 Timer_A3.TA2 1 1 0 A4+ (see Note 3) X X 1 P1.5/TACLK/ACLK/A3+ 5 P1.5† Input/Output 0/1 0 0 Timer_A3.TACLK/INCLK 0 1 0 ACLK 1 1 0 A3+ (see Note 3) X X 1 P1.7/A2+ 7 P1.5† Input/Output 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 A2+ (see Note 3) X X 1 †Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. 42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P1 pin schematic: P1.4, input/output with Schmitt−trigger and analog functions INCH=3 Pad Logic 0 AVSS A3− 1 SD16AE.x DAC12OPS ’1’ if DAC12AMPx>0 P1DIR.x 0 Direction 1 0: Input 1: Output P1OUT.x 0 DVSS 1 P1.4/A3−/DAC0 P1SEL.x Bus Keeper EN P1IN.x DAC12OPS P1IE.x EN DAC0 P1IRQ.x Q Set P1IFG.x P1SEL.x Interrupt Edge P1IES.x Select Note: x = 4 Port P1 (P1.4) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP11.XX)) XX FFUUNNCCTTIIOONN P1DIR.x P1SEL.x SD16AE.x DAC12OPS P1.4/A3−/DAC0 4 P1.4† Input/Output 0/1 0 0 0 N/A 0 1 0 0 DVSS 1 1 0 0 A3− (see Notes 3, 4) X X 1 0 DAC0 (see Note 5) X X X 1 †Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. 4. Negative input to SD16_A (A3−) connected to AVSS if corresponding SD16AE.x bit is cleared. 5. Setting the DAC12OPS bit also disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 43

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P1 pin schematic: P1.6, input/output with Schmitt−trigger and analog functions INCH=2 Pad Logic 0 AVSS A2− 1 SD16AE.x P1DIR.x 0 Direction 1 0: Input 1: Output P1OUT.x 0 DVSS 1 P1.6/A2− P1SEL.x Bus Keeper EN P1IN.x P1IE.x EN P1IRQ.x Q Set P1IFG.x P1SEL.x Interrupt Edge P1IES.x Select Note: x = 6 Port P1 (P1.6) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP11.XX)) XX FFUUNNCCTTIIOONN P1DIR.x P1SEL.x SD16AE.x P1.6/A2− 6 P1.6† Input/Output 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 A2− (see Notes 3, 4) X X 1 †Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. 4. Negative input to SD16_A (A2−) connected to AVSS if corresponding SD16AE.x bit is cleared. 44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P2 pin schematic: P2.0 to P2.7, input/output with Schmitt−trigger, LCD and analog functions Pad Logic LCDS4/8/12 Segment Sy DVSS P2DIR.x 0 Direction 1 0: Input 1: Output P2OUT.x 0 DVSS 1 P2.0/S13 P2SEL.x Bus P2.1/S12 Keeper P2.2/S11 EN P2.3/S10 P2.4/S9 P2.5/S8 P2IN.x P2.6/S7 P2.7/S6 P2IE.x EN P2IRQ.x Q Set P2IFG.x P2SEL.x Interrupt Edge P2IES.x Select Note: x = 0 to 7 y = 13 to 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 45

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P2 (P2.0 to P2.7) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP22.XX)) XX FFUUNNCCTTIIOONN P2DIR.x P2SEL.x LCDS12 P2.0/S13 0 P2.0† Input/Output 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 S13 X X 1 P2.1/S12 1 P2.1† Input/Output 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 S12 X X 1 P2.2/S11 2 P2.2† Input/Output 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 S11 X X 1 P2.3/S10 3 P2.3† Input/Output 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 S10 X X 1 P2.4/S9 4 P2.4† Input/Output 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 S9 X X 1 P2.5/S8 5 P2.5† Input/Output 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 S8 X X 1 P2.6/S7 6 P2.6† Input/Output 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 S7 X X 1 P2.7/S6 7 P2.7† Input/Output 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 S6 X X 1 †Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P5 pin schematic: P5.0, P5.1, P5.5 to P5.7, input/output with Schmitt−trigger and LCD functions Pad Logic LCDS0/4 Segment Sy DVSS P5DIR.x 0 Direction 1 0: Input 1: Output P5OUT.x 0 DVSS 1 P5.0/S1 P5.1/S0 P5SEL.x Bus P5.5/S2 Keeper P5.6/S3 EN P5.7/S4 P5IN.x Note: x = 0,1,5,6,7 y = 1,0,2,3,4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 47

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P5 (P5.0, P5.1, P5.5, P5.6) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP55.XX)) XX FFUUNNCCTTIIOONN P5DIR.x P5SEL.x LCDS0 P5.0/S1 0 P5.0† Input/Output 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 S1 X X 1 P5.1/S0 1 P5.1† Input/Output 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 S0 X X 1 P5.5/S2 5 P5.5† Input/Output 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 S2 X X 1 P5.6/S3 6 P5.6† Input/Output 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 S3 X X 1 †Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. Port P5 (P5.7) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP55.XX)) XX FFUUNNCCTTIIOONN P5DIR.x P5SEL.x LCDS4 P5.7/S4 7 P5.7† Input/Output 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 S4 X X 1 †Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P5 pin schematic: P5.2 to P5.4, input/output with Schmitt−trigger and LCD functions Pad Logic LCD Signal DVSS P5DIR.x 0 Direction 1 0: Input 1: Output P5OUT.x 0 DVSS 1 P5.2/COM1 P5.3/COM2 P5SEL.x Bus P5.4/COM3 Keeper EN P5IN.x Note: x = 2 to 4 Port P5 (P5.2 to P5.4) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP55.XX)) XX FFUUNNCCTTIIOONN P5DIR.x P5SEL.x P5.2/COM1 2 P5.2† Input/Output 0/1 0 COM1 X 1 P5.3/COM2 3 P5.3† Input/Output 0/1 0 COM2 X 1 P5.4/COM3 4 P5.4† Input/Output 0/1 0 COM3 X 1 †Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 49

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P6 pin schematic: P6.0, P6.2, input/output with Schmitt−trigger and analog functions INCH=0/1 # Pad Logic Ay+# P6DIR.x 0 Direction 1 0: Input 1: Output P6OUT.x 0 DVSS 1 P6.0/A0+ P6.2/A1+ P6SEL.x Bus Keeper EN P6IN.x Note: x = 0,2 y = 0,1 #Signal from or to SD16 Port P6 (P6.0, P6.2) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP66.XX)) XX FFUUNNCCTTIIOONN P6DIR.x P6SEL.x P6.0/A0+ 0 P6.0† Input/Output 0/1 0 A0+ (see Note 3) X 1 P6.2/A1+ 2 P6.2† Input/Output 0/1 0 A1+ (see Note 3) X 1 †Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. 50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P6 pin schematic: P6.1, P6.3, input/output with Schmitt−trigger and analog functions INCH=0/1 # Pad Logic Ay−# P6DIR.x 0 Direction 1 0: Input 1: Output P6OUT.x 0 DVSS 1 P6.1/A0− P6.3/A1− P6SEL.x Bus Keeper EN P6IN.x Note: x = 1,3 y = 0,1 #Signal from or to SD16 Port P6 (P6.1, P6.3) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP66.XX)) XX FFUUNNCCTTIIOONN P6DIR.x P6SEL.x P6.1/A0− 1 P6.1† Input/Output 0/1 0 A0− (see Note 3) X 1 P6.3/A1− 3 P6.3† Input/Output 0/1 0 A1− (see Note 3) X 1 †Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 51

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P6 pin schematic: P6.4 to P6.7, input/output with Schmitt−trigger and analog functions P6DIR.x 0 Direction Pad Logic 1 0: Input 1: Output P6OUT.x 0 DVSS 1 P6.4 P6.5 P6SEL.x Bus P6.6 Keeper P6.7 EN P6IN.x Note: x = 4 to 7 Port P6 (P6.4 to P6.7) pin functions CONTROL BITS / SIGNALS PPIINN NNAAMMEE ((PP66.XX)) XX FFUUNNCCTTIIOONN P6DIR.x P6SEL.x P6.4 4 P6.4† Input/Output 0/1 0 N/A 0 1 DVSS 1 1 P6.5 5 P6.5† Input/Output 0/1 0 N/A 0 1 DVSS 1 1 P6.6 6 P6.6† Input/Output 0/1 0 N/A 0 1 DVSS 1 1 P6.7 7 P6.7† Input/Output 0/1 0 N/A 0 1 DVSS 1 1 †Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output TDO Controlled by JTAG Controlled by JTAG TDO/TDI JTAG Controlled DV by JTAG CC TDI Burn and Test Fuse TDI/TCLK Test DV and CC Emulation TMS Module TMS DV CC TCK TCK RST/NMI Tau ~ 50 ns D Brownout G U S D TCK U G S POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 53

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 JTAG fuse check mode MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current (I ) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be (TF) taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see Figure 19). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). The JTAG pins are terminated internally and therefore do not require external termination. Time TMS Goes Low After POR TMS I(TF) ITDI/TCLK Figure 19. Fuse Check Mode Current 54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Data Sheet Revision History Literature Summary Number Updated functional block diagram (page 4) Clarified test conditions in recommended operating conditions table (page 17) Clarified test conditions in electrical characteristics table (page 18) SLAS455D Clarified test conditions in DCO table (page 25) Changed PSRR to AC PSRR in SD16_A, performance table (page 29) Changed PSRR to DC PSR in SD16_A, built-in voltage reference table; corrected typical value from 10 to 100 μ V/V (page 30) NOTE: Page and figure numbers refer to the respective document revision. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 55

Manual Update Sheet SLAZ557–December2013 Corrections to MSP430F42x0 Data Sheet (SLAS455D) DocumentBeingUpdated: MSP430F42x0MixedSignalMicrocontroller LiteratureNumberBeingUpdated:SLAS455D Page ChangeorAdd 46 ThetableincludesLCDS12inthe"CONTROLBITS/SIGNALS" column.Thisiscorrectfor P2.0/S13andP2.1/S12. ForP2.2/S11,P2.3/S10,P2.4/S9,andP2.5/S8,thecorrectcontrolbitis LCDS8. ForP2.6/S7andP2.7/S6,thecorrectcontrolbitis LCDS4. SLAZ557–December2013 CorrectionstoMSP430F42x0DataSheet(SLAS455D) 1 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MSP430F4250IDL ACTIVE SSOP DL 48 25 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F4250 & no Sb/Br) MSP430F4250IDLR ACTIVE SSOP DL 48 1000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F4250 & no Sb/Br) MSP430F4250IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 MSP430 & no Sb/Br) F4250 MSP430F4250IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 MSP430 & no Sb/Br) F4250 MSP430F4260IDL ACTIVE SSOP DL 48 25 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F4260 & no Sb/Br) MSP430F4260IDLR ACTIVE SSOP DL 48 1000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F4260 & no Sb/Br) MSP430F4260IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 MSP430 & no Sb/Br) F4260 MSP430F4260IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 MSP430 & no Sb/Br) F4260 MSP430F4270IDL ACTIVE SSOP DL 48 25 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F4270 & no Sb/Br) MSP430F4270IDLR ACTIVE SSOP DL 48 1000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F4270 & no Sb/Br) MSP430F4270IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 MSP430 & no Sb/Br) F4270 MSP430F4270IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 MSP430 & no Sb/Br) F4270 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Mar-2015 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) MSP430F4250IDLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 MSP430F4250IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 MSP430F4260IDLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 MSP430F4260IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 MSP430F4260IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 MSP430F4270IDLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 MSP430F4270IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Mar-2015 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) MSP430F4250IDLR SSOP DL 48 1000 367.0 367.0 55.0 MSP430F4250IRGZT VQFN RGZ 48 250 210.0 185.0 35.0 MSP430F4260IDLR SSOP DL 48 1000 367.0 367.0 55.0 MSP430F4260IRGZR VQFN RGZ 48 2500 367.0 367.0 38.0 MSP430F4260IRGZT VQFN RGZ 48 250 210.0 185.0 35.0 MSP430F4270IDLR SSOP DL 48 1000 367.0 367.0 55.0 MSP430F4270IRGZT VQFN RGZ 48 250 210.0 185.0 35.0 PackMaterials-Page2

GENERIC PACKAGE VIEW RGZ 48 VQFN - 1 mm max height 7 x 7, 0.5 mm pitch PLASTIC QUADFLAT PACK- NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224671/A www.ti.com

PACKAGE OUTLINE RGZ0048A VQFN - 1 mm max height PLASTIC QUADFLAT PACK- NO LEAD 7.1 A B 6.9 7.1 PIN 1 INDEX AREA 6.9 (0.1) TYP SIDE WALL DETAIL OPTIONAL METAL THICKNESS 1 MAX C SEATING PLANE 0.05 0.08 C 0.00 2X 5.5 5.15±0.1 (0.2) TYP 13 24 44X 0.5 12 25 SEE SIDE WALL DETAIL SYMM 2X 5.5 1 36 0.30 PIN1 ID 48X 0.18 (OPTIONAL) 48 37 SYMM 0.1 C A B 0.5 48X 0.3 0.05 C 4219044/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RGZ0048A VQFN - 1 mm max height PLASTIC QUADFLAT PACK- NO LEAD 2X (6.8) ( 5.15) SYMM 48X (0.6) 48 35 48X (0.24) 44X (0.5) 1 34 SYMM 2X 2X (5.5) (6.8) 2X (1.26) 2X (1.065) (R0.05) TYP 23 12 21X (Ø0.2) VIA TYP 13 22 2X (1.26) 2X (1.065) 2X (5.5) LAND PATTERN EXAMPLE SCALE: 15X 0.07 MAX 0.07 MIN SOLDER MASK ALL AROUND ALL AROUND OPENING EXPOSED METAL EXPOSED METAL METAL SOLDER MASK METAL UNDER OPENING NON SOLDER MASK SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4219044/B 08/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RGZ0048A VQFN - 1 mm max height PLASTIC QUADFLAT PACK- NO LEAD 2X (6.8) SYMM ( 1.06) 48X (0.6) 48X (0.24) 44X (0.5) SYMM 2X 2X (5.5) (6.8) 2X (0.63) 2X (1.26) (R0.05) TYP 2X 2X (0.63) (1.26) 2X (5.5) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 67% PRINTED COVERAGE BY AREA SCALE: 15X 4219044/B 08/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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