MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 (cid:2) (cid:2) Low Supply-Voltage Range, 1.8 V to 3.6 V Serial Onboard Programming, (cid:2) Ultralow Power Consumption No External Programming Voltage Needed, − Active Mode: 200 μA at 1 MHz, 2.2 V Programmable Code Protection by Security − Standby Mode: 0.7 μA Fuse − Off Mode (RAM Retention): 0.1 μA (cid:2) Bootstrap Loader in Flash Devices (cid:2) (cid:2) Five Power-Saving Modes Family Members Include: (cid:2) − MSP430C412: 4KB ROM, 256B RAM Wake-Up From Standby Mode in Less Than 6 μs − MSP430C413: 8KB ROM, 256B RAM (cid:2) − MSP430F412: 4KB + 256B Flash Frequency-Locked Loop (FLL+) 256B RAM (cid:2) 16-Bit RISC Architecture, 125-ns − MSP430F413: 8KB + 256B Flash Instruction Cycle Time 256B RAM (cid:2) 16-Bit Timer_A With Three or Five† − MSP430F415: 16KB + 256B Flash Capture/Compare Registers 512B RAM (cid:2) Integrated LCD Driver for 96 Segments − MSP430F417: 32KB + 256B Flash (cid:2) 1KB RAM On-Chip Comparator (cid:2) (cid:2) Available in 64-Pin QFP (PM) and Brownout Detector 64-Pin QFN (RTD/RGC) Packages (cid:2) Supply Voltage Supervisor/Monitor − (cid:2) For Complete Module Descriptions,See the Programmable Level Detection on MSP430x4xx Family User’s Guide, MSP430F415/417 Devices Only Literature Number SLAU056 † Timer_A5 in ’F415 and ’F417 devices only description The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 μs. The MSP430x41x series are microcontroller configurations with one or two built-in 16-bit timers, a comparator, 96 LCD segment drive capability, and 48 I/O pins. Typical applications include sensor systems that capture analog signals, convert them to digital values, and process the data and transmit them to a host system. The comparator and timer make the configurations ideal for industrial meters, counter applications, handheld meters, etc. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2008, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 AVAILABLE OPTIONS PACKAGED DEVICES TTA PLASTIC 64-PIN QFP (PM) PLASTIC 64-PIN QFN (RTD/RGC) MSP430C412IPM MSP430C412IRGC MSP430C413IPM MSP430C413IRGC MSP430F412IPM MSP430F412IRTD −40°C to 85°C MSP430F413IPM MSP430F413IRTD MSP430F415IPM MSP430F415IRTD MSP430F417IPM MSP430F417IRTD pin designation − MSP430x412, MSP430x413 K L T C U M O NMI CLK TDI TA0 TA0/ TA1 SVS VCCVSSVSS6.2 6.1 6.0 ST/ CK MS DI/T DO/ 1.0/ 1.1/ 1.2/ 1.3/ 1.4 A D A P P P R T T T T P P P P P 6463 6261 60 59 58 57 56 55 54 53 52 51 5049 DV 1 48 P1.5/TACLK/ACLK CC P6.3 2 47 P1.6/CA0 P6.4 3 46 P1.7/CA1 P6.5 4 45 P2.0/TA2 P6.6 5 44 P2.1 P6.7 6 43 P5.7/R33 NC 7 42 P5.6/R23 XIN 8 41 P5.5/R13 MSP430x412 XOUT 9 MSP430x413 40 R03 NC 10 39 P5.4/COM3 NC 11 38 P5.3/COM2 P5.1/S0 12 37 P5.2/COM1 P5.0/S1 13 36 COM0 P4.7/S2 14 35 P2.2/S23 P4.6/S3 15 34 P2.3/S22 P4.5/S4 16 33 P2.4/S21 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P4.4/S5 P4.3/S6 P4.2/S7 P4.1/S8 P4.0/S9 P3.7/S10 P3.6/S11 P3.5/S12 P3.4/S13 P3.3/S14 P3.2/S15 P3.1/S16 P3.0/S17 P2.7/S18 OUT/S19 P2.5/S20 A C 6/ 2. P NC − No internal connection. External connection to VSS recommended. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 pin designation − MSP430x415, MSP430x417 T U K O L S C V M S 0 0/ 1 0/ 0 VCCVSSVSS16.2 6.1 6.0 ST/NMI CK MS DI/TCLK DO/TDI 1.0/TA0. 1.1/TA0. 1.2/TA0. 1.3/TA1. 1.4/TA1. A D A P P P R T T T T P P P P P 6463 6261 60 59 58 57 56 55 54 53 52 51 5049 DV 1 48 P1.5/TA0CLK/ACLK CC P6.3 2 47 P1.6/CA0 P6.4 3 46 P1.7/CA1 P6.5 4 45 P2.0/TA0.2 P6.6 5 44 P2.1/TA1.1 P6.7 6 43 P5.7/R33 NC 7 42 P5.6/R23 XIN 8 41 P5.5/R13 MSP430x415 XOUT 9 MSP430x417 40 R03 AVSS2 10 39 P5.4/COM3 NC 11 38 P5.3/COM2 P5.1/S0 12 37 P5.2/COM1 P5.0/S1 13 36 COM0 P4.7/S2 14 35 P2.2/TA1.2/S23 P4.6/S3 15 34 P2.3/TA1.3/S22 P4.5/S4 16 33 P2.4/TA1.4/S21 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P4.4/S5 P4.3/S6 P4.2/S7 P4.1/S8 P4.0/S9 P3.7/S10 P3.6/S11 P3.5/S12 P3.4/S13 P3.3/S14 P3.2/S15 P3.1/S16 P3.0/S17 P2.7/S18 OUT/S19 CLK/S20 A 1 C A P2.6/ P2.5/T NC − No internal connection. External connection to VSS recommended. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 functional block diagram − MSP430x412, MSP430x413 XIN XOUT DVCC DVSS AVCC AVSS P1 P2 P3 P4 P5 P6 8 8 8 8 8 8 ACLK Oscillators Flash−F41x Port 1 Port 2 FLL+ SMCLK ROM−C41x RAM Port 3 Port 4 Port 5 Port 6 8 I/O 8 I/O MCLK 8KB 256B Interrupt Interrupt 8 I/O 8 I/O 8 I/O 6 I/O 4KB Capability Capability 8 MHz MAB CPU incl. 16 Registers MDB Emulation Module (F versions Watchdog Basic LCD only) POR/ WDT Timer_A3 Comparator_ Timer 1 96 SVS/ A Segments Brownout 15/16-Bit 3 CC Reg 1 Interrupt 1,2,3,4 MUX JTAG Vector Interface fLCD RST/NMI functional block diagram − MSP430x415, MSP430x417 XIN XOUT DVCC DVSS AVCC AVSS P1 P2 P3 P4 P5 P6 8 8 8 8 8 8 ACLK Oscillators Port 1 Port 2 FLL+ SMCLK Flash RAM Port 3 Port 4 Port 5 Port 6 8 I/O 8 I/O 32KB 1KB MCLK 16KB 512B Interrupt Interrupt 8 I/O 8 I/O 8 I/O 6 I/O Capability Capability 8 MHz MAB CPU incl. 16 Registers MDB Emulation Module Watchdog Basic (F versions POR/ WDT Timer0_A3 Timer1_A5 Timer 1 LCD only) SVS/ Comparator 96 _A Segments Brownout 15/16-Bit 3 CC Reg 5 CC Reg 1 Interrupt 1,2,3,4 MUX JTAG Vector Interface fLCD RST/NMI 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 Terminal Functions − MSP430x412, MSP430x413 TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. Positive terminal that supplies SVS, brownout, oscillator, comparator_A, port 1, and LCD resistive AVCC 64 divider circuitry; must not power up prior to DVCC. Negative terminal that supplies SVS, brownout, oscillator, comparator_A. Needs to be externally AVSS 62 connected to DVSS. DVCC 1 Digital supply voltage, positive terminal. Supplies all parts, except those which are supplied via AVCC. Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via DVSS 63 AVCC/AVSS. NC 7, 10, 11 Not internally connected. Connection to VSS recommended. P1.0/TA0 53 I/O General-purpose digital I/O / Timer_A, Capture: CCI0A input, compare: Out0 output/BSL transmit General-purpose digital I/O / Timer_A, Capture: CCI0B input/MCLK output. Note: TA0 is only an input P1.1/TA0/MCLK 52 I/O on this pin/BSL receive. P1.2/TA1 51 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output P1.3/SVSOUT 50 I/O General-purpose digital I/O / SVS: output of SVS comparator P1.4 49 I/O General-purpose digital I/O P1.5/TACLK/ ACLK 48 I/O General-purpose digital I/O / Input of Timer_A clock/output of ACLK P1.6/CA0 47 I/O General-purpose digital I/O / Comparator_A input P1.7/CA1 46 I/O General-purpose digital I/O / Comparator_A input P2.0/TA2 45 I/O General-purpose digital I/O / Timer_A capture: CCI2A input, compare: Out2 output P2.1 44 I/O General-purpose digital I/O P2.2/S23 35 I/O General-purpose digital I/O / LCD segment output 23 (see Note 1) P2.3/S22 34 I/O General-purpose digital I/O / LCD segment output 22 (see Note 1) P2.4/S21 33 I/O General-purpose digital I/O / LCD segment output 21 (see Note 1) P2.5/S20 32 I/O General-purpose digital I/O / LCD segment output 20 (see Note 1) P2.6/CAOUT/S19 31 I/O General-purpose digital I/O / Comparator_A output/LCD segment output 19 (see Note 1) P2.7/S18 30 I/O General-purpose digital I/O / LCD segment output 18 (see Note 1) P3.0/S17 29 I/O General-purpose digital I/O / LCD segment output 17 (see Note 1) P3.1/S16 28 I/O General-purpose digital I/O / LCD segment output 16 (see Note 1) P3.2/S15 27 I/O General-purpose digital I/O / LCD segment output 15 (see Note 1) P3.3/S14 26 I/O General-purpose digital I/O / LCD segment output 14 (see Note 1) P3.4/S13 25 I/O General-purpose digital I/O / LCD segment output 13 (see Note 1) P3.5/S12 24 I/O General-purpose digital I/O / LCD segment output 12 (see Note 1) P3.6/S11 23 I/O General-purpose digital I/O / LCD segment output 11 (see Note 1) P3.7/S10 22 I/O General-purpose digital I/O / LCD segment output 10 (see Note 1) NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 Terminal Functions − MSP430x412, MSP430x413 (Continued) TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. P4.0/S9 21 I/O General-purpose digital I/O / LCD segment output 9 (see Note 1) P4.1/S8 20 I/O General-purpose digital I/O / LCD segment output 8 (see Note 1) P4.2/S7 19 I/O General-purpose digital I/O / LCD segment output 7 (see Note 1) P4.3/S6 18 I/O General-purpose digital I/O / LCD segment output 6 (see Note 1) P4.4/S5 17 I/O General-purpose digital I/O / LCD segment output 5 (see Note 1) P4.5/S4 16 I/O General-purpose digital I/O / LCD segment output 4 (see Note 1) P4.6/S3 15 I/O General-purpose digital I/O / LCD segment output 3 (see Note 1) P4.7/S2 14 I/O General-purpose digital I/O / LCD segment output 2 (see Note 1) P5.0/S1 13 I/O General-purpose digital I/O / LCD segment output 1 (see Note 1) P5.1/S0 12 I/O General-purpose digital I/O / LCD segment output 0 (see Note 1) COM0 36 O Common output. COM0−3 are used for LCD backplanes P5.2/COM1 37 I/O General-purpose digital I/O / Common output. COM0−3 are used for LCD backplanes. P5.3/COM2 38 I/O General-purpose digital I/O / Common output. COM0−3 are used for LCD backplanes. P5.4/COM3 39 I/O General-purpose digital I/O / Common output. COM0−3 are used for LCD backplanes. R03 40 I Input port of fourth positive (lowest) analog LCD level (V5) P5.5/R13 41 I/O General-purpose digital I/O / Input port of third most positive analog LCD level (V4 or V3) P5.6/R23 42 I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2) P5.7/R33 43 I/O General-purpose digital I/O / Output port of most positive analog LCD level (V1) P6.0 59 I/O General-purpose digital I/O P6.1 60 I/O General-purpose digital I/O P6.2 61 I/O General-purpose digital I/O P6.3 2 I/O General-purpose digital I/O P6.4 3 I/O General-purpose digital I/O P6.5 4 I/O General-purpose digital I/O P6.6 5 I/O General-purpose digital I/O P6.7 6 I/O General-purpose digital I/O RST/NMI 58 I Reset input / Nonmaskable interrupt input TCK 57 I Test clock. TCK is the clock input port for device programming and test. TDI/TCLK 55 I Test data input / Test clock input. The device protection fuse is connected to TDI. TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal. TMS 56 I Test mode select. TMS is used as an input port for device programming and test. XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT 9 O Output terminal of crystal oscillator XT1. QFN Pad NA NA QFN package pad connection to VSS recommended. NOTE 2: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 Terminal Functions − MSP430x415, MSP430x417 TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. Positive terminal that supplies SVS, brownout, oscillator, comparator_A, port 1, and LCD resistive AVCC 64 divider circuitry; must not power up prior to DVCC. Negative terminal that supplies SVS, brownout, oscillator, comparator_A. Needs to be externally AVSS1 62 connected to DVSS. DVCC 1 Digital supply voltage, positive terminal. Supplies all parts, except those which are supplied via AVCC. Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via DVSS 63 AVCC/AVSS. Negative terminal that supplies SVS, brownout, oscillator, comparator_A. Needs to be externally AVSS2 10 connected to DVSS. NC 7, 11 Not internally connected. Connection to VSS recommended. P1.0/TA0.0 53 I/O General-purpose digital I/O / Timer0_A. Capture: CCI0A input, compare: Out0 output/BSL transmit General-purpose digital I/O / Timer0_A. Capture: CCI0B input/MCLK output. Note: TA0 is only an input P1.1/TA0.0/MCLK 52 I/O on this pin/BSL receive P1.2/TA0.1 51 I/O General-purpose digital I/O / Timer0_A, capture: CCI1A input, compare: Out1 output P1.3/TA1.0/ 50 I/O General-purpose digital I/O / Timer1_A, capture: CCI0B input/SVS: output of SVS comparator SVSOUT P1.4/TA1.0 49 I/O General-purpose digital I/O / Timer1_A, capture: CCI0A input, compare: Out0 output P1.5/TA0CLK/ 48 I/O General-purpose digital I/O / input of Timer0_A clock/output of ACLK ACLK P1.6/CA0 47 I/O General-purpose digital I/O / Comparator_A input P1.7/CA1 46 I/O General-purpose digital I/O / Comparator_A input P2.0/TA0.2 45 I/O General-purpose digital I/O / Timer0_A capture: CCI2A input, compare: Out2 output P2.1/TA1.1 44 I/O General-purpose digital I/O / Timer1_A, capture: CCI1A input, compare: Out1 output General-purpose digital I/O / Timer1_A, capture: CCI2A input, compare: Out2 output/LCD segment P2.2/TA1.2/S23 35 I/O output 23 (see Note 1) General-purpose digital I/O / Timer1_A, capture: CCI3A input, compare: Out3 output/LCD segment P2.3/TA1.3/S22 34 I/O output 22 (see Note 1) General-purpose digital I/O / Timer1_A, capture: CCI4A input, compare: Out4 output/LCD segment P2.4/TA1.4/S21 33 I/O output 21 (see Note 1) P2.5/TA1CLK/S20 32 I/O General-purpose digital I/O / input of Timer1_A clock/LCD segment output 20 (see Note 1) P2.6/CAOUT/S19 31 I/O General-purpose digital I/O / Comparator_A output/LCD segment output 19 (see Note 1) P2.7/S18 30 I/O General-purpose digital I/O / LCD segment output 18 (see Note 1) P3.0/S17 29 I/O General-purpose digital I/O / LCD segment output 17 (see Note 1) P3.1/S16 28 I/O General-purpose digital I/O / LCD segment output 16 (see Note 1) P3.2/S15 27 I/O General-purpose digital I/O / LCD segment output 15 (see Note 1) P3.3/S14 26 I/O General-purpose digital I/O / LCD segment output 14 (see Note 1) P3.4/S13 25 I/O General-purpose digital I/O / LCD segment output 13 (see Note 1) P3.5/S12 24 I/O General-purpose digital I/O / LCD segment output 12 (see Note 1) P3.6/S11 23 I/O General-purpose digital I/O / LCD segment output 11 (see Note 1) P3.7/S10 22 I/O General-purpose digital I/O / LCD segment output 10 (see Note 1) NOTE 3: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 Terminal Functions − MSP430x415, MSP430x417 (Continued) TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. P4.0/S9 21 I/O General-purpose digital I/O / LCD segment output 9 (see Note 1) P4.1/S8 20 I/O General-purpose digital I/O / LCD segment output 8 (see Note 1) P4.2/S7 19 I/O General-purpose digital I/O / LCD segment output 7 (see Note 1) P4.3/S6 18 I/O General-purpose digital I/O / LCD segment output 6 (see Note 1) P4.4/S5 17 I/O General-purpose digital I/O / LCD segment output 5 (see Note 1) P4.5/S4 16 I/O General-purpose digital I/O / LCD segment output 4 (see Note 1) P4.6/S3 15 I/O General-purpose digital I/O / LCD segment output 3 (see Note 1) P4.7/S2 14 I/O General-purpose digital I/O / LCD segment output 2 (see Note 1) P5.0/S1 13 I/O General-purpose digital I/O / LCD segment output 1 (see Note 1) P5.1/S0 12 I/O General-purpose digital I/O / LCD segment output 0 (see Note 1) COM0 36 O Common output. COM0−3 are used for LCD backplanes. P5.2/COM1 37 I/O General-purpose digital I/O / common output. COM0−3 are used for LCD backplanes. P5.3/COM2 38 I/O General-purpose digital I/O / common output. COM0−3 are used for LCD backplanes. P5.4/COM3 39 I/O General-purpose digital I/O / common output. COM0−3 are used for LCD backplanes. R03 40 I Input port of fourth positive (lowest) analog LCD level (V5) P5.5/R13 41 I/O General-purpose digital I/O / input port of third most positive analog LCD level (V4 or V3) P5.6/R23 42 I/O General-purpose digital I/O / input port of second most positive analog LCD level (V2) P5.7/R33 43 I/O General-purpose digital I/O / output port of most positive analog LCD level (V1) P6.0 59 I/O General-purpose digital I/O P6.1 60 I/O General-purpose digital I/O P6.2 61 I/O General-purpose digital I/O P6.3 2 I/O General-purpose digital I/O P6.4 3 I/O General-purpose digital I/O P6.5 4 I/O General-purpose digital I/O P6.6 5 I/O General-purpose digital I/O P6.7/SVSIN 6 I/O General-purpose digital I/O / SVS, analog input RST/NMI 58 I Reset input / Nonmaskable interrupt input port TCK 57 I Test clock. TCK is the clock input port for device programming and test. TDI/TCLK 55 I Test data input / Test clock input. The device protection fuse is connected to TDI. TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal. TMS 56 I Test mode select. TMS is used as an input port for device programming and test. XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT 9 O Output terminal of crystal oscillator XT1. QFN Pad NA NA QFN package pad connection to VSS recommended NOTE 4: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture Program Counter PC/R0 that is highly transparent to the application. All operations, other than program-flow instructions, Stack Pointer SP/R1 are performed as register operations in Status Register SR/CG1/R2 conjunction with seven addressing modes for source operand and four addressing modes for Constant Generator CG2/R3 destination operand. General-Purpose Register R4 The CPU is integrated with 16 registers that provide reduced instruction execution time. The General-Purpose Register R5 register-to-register operation execution time is one cycle of the CPU clock. General-Purpose Register R6 Four of the registers, R0 to R3, are dedicated as General-Purpose Register R7 program counter, stack pointer, status register, and constant generator, respectively. The General-Purpose Register R8 remaining registers are general-purpose registers. General-Purpose Register R9 Peripherals are connected to the CPU using data, General-Purpose Register R10 address, and control buses, and can be handled with all instructions. General-Purpose Register R11 instruction set General-Purpose Register R12 The instruction set consists of 51 instructions with three formats and seven address modes. Each General-Purpose Register R13 instruction can operate on word and byte data. Table1 shows examples of the three types of General-Purpose Register R14 instruction formats; the address modes are listed General-Purpose Register R15 in Table2. Table 1. Instruction Word Formats Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 −−−> R5 Single operands, destination only e.g. CALL R8 PC −−>(TOS), R8−−> PC Relative jump, un/conditional e.g. JNE Jump-on-equal bit = 0 Table 2. Address Mode Descriptions ADDRESS MODE S D SYNTAX EXAMPLE OPERATION (cid:2) (cid:2) Register MOV Rs,Rd MOV R10,R11 R10 −−> R11 (cid:2) (cid:2) Indexed MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)−−> M(6+R6) (cid:2) (cid:2) Symbolic (PC relative) MOV EDE,TONI M(EDE) −−> M(TONI) (cid:2) (cid:2) Absolute MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT) (cid:2) Indirect MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6) Indirect (cid:2) M(R10) −−> R11 MOV @Rn+,Rm MOV @R10+,R11 autoincrement R10 + 2−−> R10 (cid:2) Immediate MOV #X,TONI MOV #45,TONI #45 −−> M(TONI) NOTE: S = source D = destination POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: (cid:2) Active mode (AM) − All clocks are active. (cid:2) Low-power mode 0 (LPM0) − CPU is disabled. − ACLK and SMCLK remain active, MCLK is available to modules. − FLL+ loop control remains active. (cid:2) Low-power mode 1 (LPM1) − CPU is disabled. − ACLK and SMCLK remain active. MCLK is available to modules. − FLL+ loop control is disabled. (cid:2) Low-power mode 2 (LPM2) − CPU is disabled. − MCLK, FLL+ loop control, and DCOCLK are disabled. − DCO’s dc generator remains enabled. − ACLK remains active. (cid:2) Low-power mode 3 (LPM3) − CPU is disabled. − MCLK, FLL+ loop control, and DCOCLK are disabled. − DCO’s dc generator is disabled. − ACLK remains active. (cid:2) Low-power mode 4 (LPM4) − CPU is disabled. − ACLK is disabled. − MCLK, FLL+ loop control, and DCOCLK are disabled. − DCO’s dc generator is disabled. − Crystal oscillator is stopped. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up WDTIFG Reset 0FFFEh 15, highest External reset KEYV Watchdog (see Note 1) Flash memory NMI NMIIFG (see Notes 1 and 3) (Non)maskable Oscillator fault OFIFG (see Notes 1 and 3) (Non)maskable 0FFFCh 14 Flash memory access violation ACCVIFG (see Notes 1 and 3) (Non)maskable Timer1_A5 (see Note 4) TA1CCR0 CCIFG (see Note 2) Maskable 0FFFAh 13 TA1CCR1 to TA1CCR4 Timer1_A5 (see Note 4) CCIFGs and TA1CTL TAIFG Maskable 0FFF8h 12 (see Notes 1 and 2) Comparator_A CMPAIFG Maskable 0FFF6h 11 Watchdog timer WDTIFG Maskable 0FFF4h 10 0FFF2h 9 0FFF0h 8 0FFEEh 7 Timer_A3/Timer0_A3 TACCR0/TA0CCR0 CCIFG Maskable 0FFECh 6 (see Note 2) TACCR1/TA0CCR1, TACCR2/TA0CCR2 CCIFGs Timer_A3/Timer0_A3 Maskable 0FFEAh 5 and TACLT/TA0CTL TAIFG (see Notes 1 and 2) P1IFG.0 to P1IFG.7 I/O port P1 (eight flags) Maskable 0FFE8h 4 (see Notes 1 and 2) 0FFE6h 3 0FFE4h 2 P2IFG.0 to P2IFG.7 I/O port P2 (eight flags) Maskable 0FFE2h 1 (see Notes 1 and 2) Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest NOTES: 1. Multiple source flags 2. Interrupt flags are located in the module. 3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot. 4. Implemented in MSP430x415 and MSP430x417 devices only POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 and 2 Address 7 6 5 4 3 2 1 0 0h ACCVIE NMIIE OFIE WDTIE rw-0 rw-0 rw-0 rw-0 Address 7 6 5 4 3 2 1 0 1h BTIE rw-0 WDTIE: Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. OFIE: Oscillator fault interrupt enable NMIIE: Nonmaskable interrupt enable ACCVIE: Flash access violation interrupt enable BTIE: Basic Timer1 interrupt enable interrupt flag register 1 and 2 Address 7 6 5 4 3 2 1 0 02h NMIIFG OFIFG WDTIFG rw-0 rw-1 rw-(0) Address 7 6 5 4 3 2 1 0 3h BTIFG rw-0 WDTIFG: Set on watchdog-timer overflow (in watchdog mode) or security key violation. Reset with V power-up, CC or a reset condition at the RST/NMI pin in reset mode. OFIFG: Flag set on oscillator fault NMIIFG: Set via RST/NMI pin BTIFG: Basic Timer1 interrupt flag module enable registers 1 and 2 Address 7 6 5 4 3 2 1 0 04h/05h Legend: rw−0,1: Bit Can Be Read and Written. It Is Reset or Set by PUC. rw−(0,1): Bit Can Be Read and Written. It Is Reset or Set by POR. SFR Bit Not Present in Device. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 memory organization MSP430F412 MSP430F413 MSP430F415 MSP430F417 Memory Size 4KB 8KB 16KB 32KB Interrupt vector Flash 0FFFFh to 0FFE0h 0FFFFh to 0FFE0h 0FFFFh to 0FFE0h 0FFFFh to 0FFE0h Code memory Flash 0FFFFh to 0F000h 0FFFFh to 0E000h 0FFFFh to 0C000h 0FFFFh to 08000h Information memory Size 256 Byte 256 Byte 256 Byte 256 Byte Flash 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h Boot memory Size 1KB 1KB 1KB 1KB ROM 0FFFh to 0C00h 0FFFh to 0C00h 0FFFh to 0C00h 0FFFh to 0C00h RAM Size 256 Byte 256 Byte 512 Byte 1 KB 02FFh to 0200h 02FFh to 0200h 03FFh to 0200h 05FFh to 0200h Peripherals 16-bit 01FFh to 0100h 01FFh to 0100h 01FFh to 0100h 01FFh to 0100h 8-bit 0FFh to 010h 0FFh to 010h 0FFh to 010h 0FFh to 010h 8-bit SFR 0Fh to 00h 0Fh to 00h 0Fh to 00h 0Fh to 00h MSP430C412 MSP430C413 Memory Size 4KB 8KB Interrupt vector ROM 0FFFFh to 0FFE0h 0FFFFh to 0FFE0h Code memory ROM 0FFFFh to 0F000h 0FFFFh to 0E000h Information memory Size NA NA Boot memory Size NA NA RAM Size 256 Byte 256 Byte 02FFh to 0200h 02FFh to 0200h Peripherals 16-bit 01FFh to 0100h 01FFh to 0100h 8-bit 0FFh to 010h 0FFh to 010h 8-bit SFR 0Fh to 00h 0Fh to 00h bootstrap loader (BSL) The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader, literature number SLAA089. BSL FUNCTION PM, RTD, RGC PACKAGE PINS Data Transmit 53 - P1.0 Data Receive 52 - P1.1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: (cid:2) Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size. (cid:2) Segments 0 to n may be erased in one step, or each segment may be individually erased. (cid:2) Segments A and B can be erased individually, or as a group with segments 0 to n. Segments A and B are also called information memory. (cid:2) New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use. 4KB 8KB 16KB 32KB 0FFFFh 0FFFFh 0FFFFh 0FFFFh Segment 0 With Interrupt Vectors 0FE00h 0FE00h 0FE00h 0FE00h 0FDFFh 0FDFFh 0FDFFh 0FDFFh Segment 1 0FC00h 0FC00h 0FC00h 0FC00h 0FBFFh 0FBFFh 0FBFFh 0FBFFh Segment 2 0FA00h 0FA00h 0FA00h 0FA00h 0F9FFh 0F9FFh 0F9FFh 0F9FFh Main Memory 0F400h 0E400h 0C400h 08400h 0F3FFh 0E3FFh 0C3FFh 083FFh Segment n−1 0F200h 0E200h 0C200h 08200h 0F1FFh 0E1FFh 0C1FFh 081FFh Segment n 0F000h 0E000h 0C000h 08000h 010FFh 010FFh 010FFh 010FFh Segment A 01080h 01080h 01080h 01080h Information Memory 0107Fh 0107Fh 0107Fh 0107Fh Segment B 01000h 01000h 01000h 01000h 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number SLAU056. oscillator and system clock The clock system in the MSP430x41x family of devices is supported by the FLL+ module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware which in conjunction with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The FLL+ module provides the following clock signals: (cid:2) Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. (cid:2) Main clock (MCLK), the system clock used by the CPU. (cid:2) Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. (cid:2) ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8. brownout, supply voltage supervisor The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a fixed level or user selectable level (MSP430x415 & MSP430x417 only) and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, V may not CC have ramped to V at that time. The user must ensure the default FLL+ settings are not changed until V CC(min) CC reaches V . If desired, the SVS circuit can be used to determine when V reaches V . CC(min) CC CC(min) digital I/O There are six 8-bit I/O ports implemented—ports P1 through P6. (cid:2) All individual I/O bits are independently programmable. (cid:2) Any combination of input, output, and interrupt conditions is possible. (cid:2) Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. (cid:2) Read/write access to port-control registers is supported by all instructions. Basic Timer1 Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Basic Timer1 can be used to generate periodic interrupts and clock for the LCD module. LCD driver The LCD driver generates the segment and common signals required to drive an LCD display. The LCD controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 watchdog timer (WDT) The primary function of the WDT module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. comparator_A The primary function of the comparator_A module is to support precision slope analog-to-digital conversions, battery−voltage supervision, and monitoring of external analog signals. Timer_A3/Timer0_A3 Timer_A3/Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3/Timer0_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3/Timer0_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. TIMER_A3/TIMER0_A3 SIGNAL CONNECTIONS INPUT PIN DEVICE INPUT MODULE INPUT MODULE OUTPUT OUTPUT PIN MODULE BLOCK NUMBER SIGNAL NAME SIGNAL NUMBER 48 - P1.5 TACLK/TA0CLK TACLK ACLK ACLK TTiimmeerr NNAA SMCLK SMCLK 48 - P1.5 TACLK/TA0CLK INCLK 53 - P1.0 TA0/TA0.0 CCI0A 53 - P1.0 52 - P1.1 TA0/TA0.0 CCI0B CCCCRR00 TTAA00//TTAA00.00 DVSS GND DVCC VCC 51 - P1.2 TA1/TA0.1 CCI1A 51 - P1.2 CAOUT (internal) CCI1B CCCCRR11 TTAA11//TTAA00.11 DVSS GND DVCC VCC 45 - P2.0 TA2/TA0.2 CCI2A 45 - P2.0 ACLK (internal) CCI2B CCCCRR22 TTAA22//TTAA00.22 DVSS GND DVCC VCC 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 Timer1_A5 (MSP430x415 and MSP430x417 only) Timer1_A5 is a 16-bit timer/counter with five capture/compare registers. Timer1_A5 can support multiple capture/compares, PWM outputs, and interval timing. Timer1_A5 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. TIMER1_A5 SIGNAL CONNECTIONS INPUT PIN DEVICE INPUT MODULE INPUT MODULE OUTPUT OUTPUT PIN MODULE BLOCK NUMBER SIGNAL NAME SIGNAL NUMBER 32 - P2.5 TA1CLK TACLK ACLK ACLK TTiimmeerr NNAA SMCLK SMCLK 32 - P2.5 TA1CLK INCLK 49 - P1.4 TA1.0 CCI0A 49 - P1.4 50 - P1.3 TA1.0 CCI0B CCCCRR00 TTAA11.00 DVSS GND DVCC VCC 44 - P2.1 TA1.1 CCI1A 44 - P2.1 CAOUT (internal) CCI1B CCCCRR11 TTAA11.11 DVSS GND DVCC VCC 35 - P2.2 TA1.2 CCI2A 35 - P2.2 Not Connected CCI2B CCCCRR22 TTAA11.22 DVSS GND DVCC VCC 34 - P2.3 TA1.3 CCI3A 34 - P2.3 Not Connected CCI3B CCCCRR33 TTAA11.33 DVSS GND DVCC VCC 33 - P2.4 TA1.4 CCI4A 33 - P2.4 Not Connected CCI4B CCCCRR44 TTAA11.44 DVSS GND DVCC VCC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 peripheral file map PERIPHERALS WITH WORD ACCESS Watchdog Watchdog Timer control WDTCTL 0120h Timer1__A5 Timer1_A interrupt vector TA1IV 011Eh (MSP430x415 and Timer1_A control TA1CTL 0180h MMSSPP443300xx441177 oonnllyy)) Capture/compare control 0 TA1CCTL0 0182h Capture/compare control 1 TA1CCTL1 0184h Capture/compare control 2 TA1CCTL2 0186h Capture/compare control 3 TA1CCTL3 0188h Capture/compare control 4 TA1CCTL4 018Ah Reserved 018Ch Reserved 018Eh Timer1_A register TA1R 0190h Capture/compare register 0 TA1CCR0 0192h Capture/compare register 1 TA1CCR1 0194h Capture/compare register 2 TA1CCR2 0196h Capture/compare register 3 TA1CCR3 0198h Capture/compare register 4 TA1CCR4 019Ah Reserved 019Ch Reserved 019Eh Timer__A3/Timer0__A3 Timer_A/Timer0_A interrupt vector TAIV/TA0IV 012Eh Timer_A/Timer0_A control TACTL/TA0CTL 0160h Capture/compare control 0 TACCTL0/TA0CCTL0 0162h Capture/compare control 1 TACCTL1/TA0CCTL1 0164h Capture/compare control 2 TACCTL2/TA0CCTL2 0166h Reserved 0168h Reserved 016Ah Reserved 016Ch Reserved 016Eh Timer_A/Timer0_A register TAR/TA0R 0170h Capture/compare register 0 TACCR0/TA0CCR0 0172h Capture/compare register 1 TACCR1/TA0CCR1 0174h Capture/compare register 2 TACCR2/TA0CCR2 0176h Reserved 0178h Reserved 017Ah Reserved 017Ch Reserved 017Eh Flash Flash control 3 FCTL3 012Ch Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS LCD LCD memory 20 LCDM20 0A4h : : : LCD memory 16 LCDM16 0A0h LCD memory 15 LCDM15 09Fh : : : LCD memory 1 LCDM1 091h LCD control and mode LCDCTL 090h Compparator__A Comparator_A port disable CAPD 05Bh Comparator_A control2 CACTL2 05Ah Comparator_A control1 CACTL1 059h Brownout, SVS SVS control register SVSCTL 056h FLL+ Clock FLL+ Control1 FLL_CTL1 054h FLL+ Control0 FLL_CTL0 053h System clock frequency control SCFQCTL 052h System clock frequency integrator SCFI1 051h System clock frequency integrator SCFI0 050h Basic Timer1 BT counter2 BTCNT2 047h BT counter1 BTCNT1 046h BT control BTCTL 040h Port P6 Port P6 selection P6SEL 037h Port P6 direction P6DIR 036h Port P6 output P6OUT 035h Port P6 input P6IN 034h Port P5 Port P5 selection P5SEL 033h Port P5 direction P5DIR 032h Port P5 output P5OUT 031h Port P5 input P5IN 030h Port P4 Port P4 selection P4SEL 01Fh Port P4 direction P4DIR 01Eh Port P4 output P4OUT 01Dh Port P4 input P4IN 01Ch Port P3 Port P3 selection P3SEL 01Bh Port P3 direction P3DIR 01Ah Port P3 output P3OUT 019h Port P3 input P3IN 018h Port P2 Port P2 selection P2SEL 02Eh Port P2 interrupt enable P2IE 02Dh Port P2 interrupt-edge select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS (CONTINUED) Port P1 Port P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt-edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h Sppecial Functions SFR module enable 2 ME2 005h SFR module enable 1 ME1 004h SFR interrupt flag2 IFG2 003h SFR interrupt flag1 IFG1 002h SFR interrupt enable2 IE2 001h SFR interrupt enable1 IE1 000h absolute maximum ratings† Voltage applied at V to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 4.1 V CC SS Voltage applied to any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA Storage temperature: Unprogrammed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C Programmed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TDI/TCLK pin when blowing the JTAG fuse. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 recommended operating conditions PARAMETER MIN NOM MAX UNITS Supply voltage during program execution, MSP430x41x 1.8 3.6 V VCC (AVCC = DVCC = VCC) (see Note 1) SSuuppppllyy vvoollttaaggee dduurriinngg pprrooggrraamm eexxeeccuuttiioonn,, SSVVSS eennaabblleedd aanndd PPOORROONN == 11,, MSP430x412/413 2.2 3.6 VV VCC (AVCC = DVCC = VCC) (see Note 1 and Note 2) MSP430x415/417 2.0 3.6 Supply voltage during programming of flash memory, MSP430F41x 2.7 3.6 V VCC (AVCC = DVCC = VCC) Supply voltage, VSS (AVSS/1/2 = DVSS = VSS) 0 0 V Operating free-air temperature range, TA MSP430x41x −40 85 °C LF selected, XTS_FLL=0 Watch crystal 32768 Hz LLFFXXTT11 crysttall ffrequency, ff(LFXT1) XT1 selected, XTS_FLL=1 Ceramic resonator 450 8000 ((sseeee NNoottee 33)) kkHHzz XT1 selected, XTS_FLL=1 Crystal 1000 8000 VCC = 1.8 V DC 4.15 PPrroocceessssoorr ffrreeqquueennccyy ((ssiiggnnaall MMCCLLKK)), ff(System) VCC = 3.6 V DC 8 MMHHzz NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power up and operation. 2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage. POR is going inactive when the supply voltage is raised above minimum supply voltage plus the hysteresis of the SVS circuitry. 3. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal. z f (MHz) H Supply Voltage Range M − During Programming of y ÎÎthÎe FlÎash ÎMemÎory c n ue 8 MHz ÎÎÎÎÎÎ q e Supply Voltage Range, x41x r ÎÎÎÎÎÎ r F During Program Execution o ÎÎÎÎÎÎ s s ce ÎÎÎÎÎÎ o r P ÎÎÎÎÎÎ m 4.15 MHz mu ÎÎÎÎÎÎ xi a ÎÎÎÎÎÎ M − ÎÎÎÎÎÎ m) ste ÎÎÎÎÎÎ y S f( ÎÎÎÎÎÎ 1.8 V 2.7 V 3 V 3.6 V VCC − Supply Voltage − V Figure 1. Frequency vs Supply Voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) supply current into AV + DV excluding external current (see Note 1) CC CC PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 2.2 V 160 200 AAccttiivvee mmooddee,, CC4411xx II(AM) fff((((MMAACCCCLLLLKKKK)))) === 3ff((2SS,MM7CC68LLKK H)) ==z, ffX((DDTCCSOO_)) F==L 11L MM= HH0zz,, TTA = −4400°°CC ttoo 8855°°CC 23.2 V V 224000 320500 μAA (F41x: Program executes in flash) FF4411xx 3 V 300 350 Low-power mode (LPM0) 2.2 V 32 45 ff((MMCCLLKK)) == ff((SSMMCCLLKK)) == ff((DDCCOO)) == 00..55 MMHHzz,, f(ACLK) = 32,768 Hz, XTS_FLL = 0 3 V 55 70 FN_8=FN_4=FN_3=FN_2=0 (see Note 3) CC4411xx II(LPM0) Low-power mode (LPM0) F41x TTA = −4400°°CC ttoo 8855°°CC μAA 2.2 V 57 70 ff((MMCCLLKK)) == ff((SSMMCCLLKK)) == ff((DDCCOO)) == 11 MMHHzz,, f(ACLK) = 32,768 Hz, XTS_FLL = 0 3 V 92 100 FN_8=FN_4=FN_3=FN_2=0 (see Note 3) 2.2 V 11 14 II(LPM2) LLooww-ppoowweerr mmooddee ((LLPPMM22)) ((sseeee NNoottee 33)) TTA = −4400°°CC ttoo 8855°°CC 3 V 17 22 μAA TA = −40°C 0.95 1.4 TA = −10°C 0.8 1.3 TA = 25°C 22..22 VV 0.7 1.2 TA = 60°C 0.95 1.4 TA = 85°C 1.6 2.3 II(LPM3) LLooww-ppoowweerr mmooddee ((LLPPMM33)) ((sseeee NNoottee 22 aanndd NNoottee 33)) TA = −40°C 1.1 1.7 μAA TA = −10°C 1.0 1.6 TA = 25°C 33 VV 0.9 1.5 TA = 60°C 1.1 1.7 TA = 85°C 2.0 2.6 TA = −40°C 0.1 0.5 II((LLPPMM44)) LLooww-ppoowweerr mmooddee ((LLPPMM44)) ((sseeee NNoottee 33)) TA = 25°C 22..22 VV//33 VV 0.1 0.5 μμAA TA = 85°C 0.8 2.5 NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. The current consumption is measured with active Basic Timer1 and LCD (ACLK selected). The current consumption of the Comparator_A and the SVS module are specified in the respective sections. 2. The LPM3 currents are characterized with a KDS Daishinku DT−38 (6 pF) crystal. 3. Current for brownout included. current consumption of active mode versus system frequency I(AM) = I(AM) [1 MHz] × f(System) [MHz] current consumption of active mode versus supply voltage I(AM) = I(AM) [3 V] + 140 μA/V × (VCC – 3 V) 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs − ports P1, P2, P3, P4, P5, and P6 PARAMETER VCC MIN MAX UNIT 2.2 V 1.1 1.5 VVIT+ PPoossiittiivvee-ggooiinngg iinnppuutt tthhrreesshhoolldd vvoollttaaggee 3 V 1.5 1.9 VV 2.2 V 0.4 0.9 VVIT− NNeeggaattiivvee-ggooiinngg iinnppuutt tthhrreesshhoolldd vvoollttaaggee 3 V 0.9 1.3 VV 2.2 V 0.3 1.1 VVhys IInnppuutt vvoollttaaggee hhyysstteerreessiiss ((VVIT+ − VVIT−)) VV 3 V 0.45 1 standard inputs − RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI) PARAMETER VCC MIN MAX UNIT VIL Low-level input voltage VSS VSS+0.6 V 22.22 VV//33 VV VIH High-level input voltage 0.8×VCC VCC V inputs Px.x, TAx/TAx.x PARAMETER TEST CONDITIONS VCC MIN MAX UNIT 2.2 V/3 V 1.5 cycle PPoorrtt PP11,, PP22:: PP11..xx ttoo PP22..xx,, EExxtteerrnnaall t((iinntt)) External interruppt timingg trigggger siggnal for the interruppt flagg 2.2 V 62 ((see NNote 1)) nnss 3 V 50 2.2 V 62 tt((cap)) TTiimmeerr_AA, ccaappttuurree ttiimmiinngg TTAAxx//TTAAxx.yy nnss 3 V 50 TTiimmeerr__AA cclloocckk ffrreeqquueennccyy eexxtteerrnnaallllyy aapppplliieedd 2.2 V 8 ff(TAext) to pin TTAACCLLKK//TTAAxxCCLLKK, IINNCCLLKK tt(H) == tt(L) 3 V 10 MMHHzz 2.2 V 8 ff(TAint) TTiimmeerr_AA cclloocckk ffrreeqquueennccyy SSMMCCLLKK oorr AACCLLKK ssiiggnnaall sseelleecctteedd MMHHzz 3 V 10 NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in MCLK cycles. leakage current (see Note 1) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT Ilkg(P1.x) Port P1 V(P1.x) (see Note 2) ±50 Ilkg(P2.x) Port P2 V(P2.x) (see Note 2) ±50 Ilkg(P3.x) Port P3 V(P3.x) (see Note 2) ±50 LLeeaakkaaggee ccuurrrreenntt 22.22 VV//33 VV nnAA Ilkg(P4.x) Port P4 V(P4.x) (see Note 2) ±50 Ilkg(P5.x) Port P5 V(P5.x) (see Note 2) ±50 Ilkg(P6.x) Port P6 V(P6.x) (see Note 2) ±50 NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The port pin must be selected as an input. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs − ports P1, P2, P3, P4, P5, and P6 PARAMETER TEST CONDITIONS VCC MIN MAX UNIT IOH(max) = −1.5 mA, See Note 1 2.2 V VCC−0.25 VCC IOH(max) = −6 mA, See Note 2 2.2 V VCC−0.6 VCC VVOH HHiigghh-lleevveell oouuttppuutt vvoollttaaggee IOH(max) = −1.5 mA, See Note 1 3 V VCC−0.25 VCC VV IOH(max) = −6 mA, See Note 2 3 V VCC−0.6 VCC IOL(max) = 1.5 mA, See Note 1 2.2 V VSS VSS+0.25 IOL(max) = 6 mA, See Note 2 2.2 V VSS VSS+0.6 VVOL LLooww-lleevveell oouuttppuutt vvoollttaaggee VV IOL(max) = 1.5 mA, See Note 1 3 V VSS VSS+0.25 IOL(max) = 6 mA, See Note 2 3 V VSS VSS+0.6 NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum specified voltage drop. 2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±24 mA to satisfy the maximum specified voltage drop. output frequency PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ffPx.y ((11 ≤≤ xx ≤≤ 66, 00 ≤≤ yy ≤≤ 77)) CCILLL = == ± 22 100. 5ppmFF,,A VVCCCC == 23. 2V V DDCC 1102 MMHHzz fACLK, VCC = 2.2 V 8 ffMCLK, PP11.11//TTAA00//MMCCLLKK, PP11.55//TTAACCLLKK//AACCLLKK CCL = 2200 ppFF MMHHzz fSMCLK VCC = 3 V 12 PP11..55//TTAACCLLKK//AACCLLKK,, fACLK = fLFXT1 = fXT1 40% 60% CCLL = 2200 ppFF fACLK = fLFXT1 = fLF 30% 70% VCC = 2.2 V / 3 V fACLK = fLFXT1/n 50% tXdc Duty cycle of output frequency 50%− 50%+ P1.1/TA0/MCLK, fMCLK = fLFXT1/n 15 ns 50% 15 ns CCL = 2200 ppFF, 50%− 50%+ VCC = 2.2 V / 3 V fMCLK = fDCOCLK 15 ns 50% 15 ns 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) MSP430x412, MSP430x413 outputs − ports P1, P2, P3, P4, P5, and P6 (see Note A) TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT vs vs LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE 16 25 A VCC = 2.2 V TA = 25°C A VCC = 3 V − m 14 P1.0 − m P1.0 TA = 25°C nt nt 20 Curre 12 TA = 85°C Curre TA = 85°C ut 10 ut p p 15 ut ut O O el 8 el v v e e w-L 6 w-L 10 o o L L cal 4 cal pi pi 5 y y T T − 2 − L L O O I I 0 0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOL − Low-Level Output Voltage − V VOL − Low-Level Output Voltage − V Figure 2 Figure 3 TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT vs vs HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE 0 0 A VCC = 2.2 V A VCC = 3 V m P1.0 m P1.0 − −2 − nt nt −5 e e urr −4 urr C C ut ut −10 p p ut −6 ut O O el el −15 v v Le −8 Le h- h- Hig Hig −20 TA = 85°C pical −10 TA = 85°C pical − Ty −12 − Ty −25 TA = 25°C H H IO TA = 25°C IO −14 −30 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH − High-Level Output Voltage − V VOH − High-Level Output Voltage − V Figure 4 Figure 5 NOTE A: One output loaded at a time POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) MSP430x415, MSP430x417 outputs − ports P1, P2, P3, P4, P5, and P6 (see Note A) TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT vs vs LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE 25 40 mA VPC2.C4 = 2.2 V TA = 25°C mA 35 VPC2.C4 = 3 V TA = 25°C − − urrent 20 TA = 85°C urrent 30 TA = 85°C C C ut ut 25 p 15 p ut ut O O el el 20 v v e e w-L 10 w-L 15 o o L L cal cal 10 pi 5 pi y y T T − − 5 L L O O I I 0 0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOL − Low-Level Output Voltage − V VOL − Low-Level Output Voltage − V Figure 6 Figure 7 TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT vs vs HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE 0 0 A VCC = 2.2 V A VCC = 3 V m P2.4 m −5 P2.4 − − nt −5 nt −10 e e urr urr C C −15 ut ut utp −10 utp −20 O O el el −25 v v e e L L h- −15 h- −30 g g Hi Hi pical −20 TA = 85°C pical −−4305 TA = 85°C y y T T − − H H −45 IO TA = 25°C IO TA = 25°C −25 −50 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH − High-Level Output Voltage − V VOH − High-Level Output Voltage − V Figure 8 Figure 9 NOTE B: One output loaded at a time 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) wake-up LPM3 PARAMETER TEST CONDITIONS MIN MAX UNIT f = 1 MHz 6 ttdd((LLPPMM33)) DDeellaayy ttiimmee f = 2 MHz VVCCCC = 22..22 VV//33 VV 6 μμss f = 3 MHz 6 RAM (see Note 1) PARAMETER TEST CONDITIONS MIN MAX UNIT VRAMh CPU halted (see Note 1) 1.6 V NOTE 1: This parameter defines the minimum supply voltage when the data in the program memory RAM remain unchanged. No program execution should take place during this supply voltage condition. LCD PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(33) Voltage at P5.7/R33 2.5 VCC +0.2 V(23) Voltage at P5.6/R23 (V33−V03) × 2/3 + V03 V(13) AAnnaalloogg vvoollttaaggee Voltage at P5.5/R13 VVCC = 33 VV (V(33)−V(03)) × 1/3 + V(03) VV V(33) − V(03) Voltage at R33/R03 2.5 VCC + 0.2 I(R03) R03 = VSS No load at all ±20 I(R13) Inpput leakagge P5.5/R13 = VCC/3 segment and ±20 nA ccoommmmoonn lliinneess, I(R23) P5.6/R23 = 2 × VCC/3 VCC = 3 V ±20 V(Sxx0) V(03) V(03) − 0.1 V(Sxx1) SSeeggmmeenntt lliinnee V(13) V(13) − 0.1 V(Sxx2) voltage II(Sxx) = −33 μAA, VVCC = 33 VV V(23) V(23) − 0.1 VV V(Sxx3) V(33) V(33) + 0.1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Comparator_A (see Note 1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 2.2 V 25 40 II(CC) CCAAOONN = 11, CCAARRSSEELL = 00, CCAARREEFF = 00 3 V 45 60 μAA CAON = 1, CARSEL = 0, 2.2 V 30 50 II(Refladder/RefDiode) CCAARREEFF = 11//22//33, μAA No load at P1.6/CA0 and P1.7/CA1 3 V 45 71 Voltage@0.25V node PCA0 = 1, CARSEL = 1, CAREF = 1, V(Ref025) CC No load at P1.6/CA0 and P1.7/CA1 2.2 V / 3 V 0.23 0.24 0.25 V CC Voltage@0.5V node PCA0 = 1, CARSEL = 1, CAREF = 2, V(Ref050) CC No load at P1.6/CA0 and P1.7/CA1 2.2V / 3 V 0.47 0.48 0.50 V CC PCA0 = 1, CARSEL = 1, CAREF = 3, 2.2 V 390 480 540 SSeeee FFiigguurree 1100 aanndd VV(RefVT) Figure 11 NNoo llooaadd aatt PP11.66//CCAA00 aanndd PP11.77//CCAA11;; mmVV TA = 85°C 3 V 400 490 550 Common-mode input V(IC) voltage range CAON = 1 2. 2 V/3 V 0 VCC−1.0 V V(offset) Offset voltage See Note 2 2.2 V/3 V −30 30 mV Vhys Input hysteresis CAON = 1 2.2 V/3 V 0 0.7 1.4 mV TTAA == 2255°CC,, 2.2 V 160 210 300 nnss Overdrive 10 mV, Without filter: CAF = 0 3 V 80 150 240 tt(response LH) TTAA == 2255°CC 2.2 V 1.4 1.9 3.4 μss Overdrive 10 mV, With filter: CAF = 1 3 V 0.9 1.5 2.6 TTAA == 2255°CC 2.2 V 130 210 300 nnss Overdrive 10 mV, Without filter: CAF = 0 3 V 80 150 240 tt(response HL) TTAA == 2255°CC,, 2.2 V 1.4 1.9 3.4 μss Overdrive 10 mV, With filter: CAF = 1 3 V 0.9 1.5 2.6 NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) REFERENCE VOLTAGE REFERENCE VOLTAGE vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 650 650 VCC = 3 V VCC = 2.2 V mV 600 mV 600 − − e e g Typical g Typical a a olt 550 olt 550 V V e e c c n n e e er er ef 500 ef 500 R R − − T) T) V V ef ef R 450 R 450 V( V( 400 400 −45 −25 −5 15 35 55 75 95 −45 −25 −5 15 35 55 75 95 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 10 Figure 11 0 V VCC CAF 0 1 CAON Low Pass Filter To Internal Modules 0 0 V+ + _ V− 1 1 CAOUT Set CAIFG Flag τ ≈ 2 μs Figure 12. Comparator_A Module Block Diagram Overdrive VCAOUT V− 400 mV V+ t(response) Figure 13. Overdrive Definition POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) POR brownout, reset (see Notes 1 and 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(BOR) 2000 μs VCC(start) dVCC/dt ≤ 3 V/s (see Figure 14) 0.7 × V(B_IT−) V V(B_IT−) BBrroowwnnoouutt dVCC/dt ≤ 3 V/s (see Figure 14, Figure 15, Figure 16) 1.71 V Vhys(B_IT−) dVCC/dt ≤ 3 V/s (see Figure 14) 70 130 180 mV Pulse length needed at RST/NMI pin to accepted reset internally, t(reset) VCC = 2.2 V/3 V 2 μs NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT−) + Vhys(B_IT−) is ≤ 1.8 V. 2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−). The default FLL+ settings must not be changed until VCC ≥ VCC(min). See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit. VCC Vhys(B_IT−) V(B_IT−) VCC(start) 1 0 td(BOR) Figure 14. POR/Brownout Reset (BOR) vs Supply Voltage 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 2 VCC tpw 3 V V = 3 V cc Typical Conditions 1.5 V − p) o 1 r d (CC VCC(drop) V 0.5 0 0.001 1 1000 1 ns 1 ns tpw − Pulse Width − μs tpw − Pulse Width − μs Figure 15. V Level With a Square Voltage Drop to Generate a POR/Brownout Signal CC(drop) VCC tpw 2 3 V V = 3 V cc 1.5 Typical Conditions V − op) 1 r d (C VCC(drop) C 0.5 V tf = tr 0 0.001 1 1000 tf tr tpw − Pulse Width − μs tpw − Pulse Width − μs Figure 16. V Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal CC(drop) SVS (supply voltage supervisor/monitor) (MSP430x412, MSP430x413 only) (see Notes 1 and 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT dVCC/dt > 30 V/ms (see Note 2) 5 150 μs ttd(SVSR) dVCC/dt ≤ 30 V/ms (see Note 2) 2000 μs td(SVSon) SVSon, switch from 0 to 1, VCC = 3 V (see Note 2) 20 150 μs V(SVSstart) dVCC/dt ≤ 3 V/s (see Figure 17) 1.55 1.7 V SSVVSS V(SVS_IT−) dVCC/dt ≤ 3 V/s (see Figure 17) 1.8 1.95 2.2 V Vhys(SVS_IT−) dVCC/dt ≤ 3 V/s (see Figure 17) 70 100 155 mV I(CseCe(S NVSo)te 1) VLD ≠ 0 (VLD bits are in SVSCTL register), VCC = 2.2 V/3 V 10 15 μA NOTES: 1. The current consumption of the SVS module is not included in the ICC current consumption data. 2. The SVS is not active at power up. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SVS (supply voltage supervisor/monitor) (MSP430x415, MSP430x417 only) (see Notes 1 and 2) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT ttd(SVSR) ddVVCCCC//ddtt >≤ 3300 VV//mmss (see Figure 17) 5 2105000 μμss td(SVSon) SVSon, switch from VLD=0 to VLD ≠ 0, VCC = 3 V 20 150 μs tsettle VLD ≠ 0‡ 12 μs V(SVSstart) VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 17) 1.55 1.7 V VLD = 1 70 120 155 mV VCC/dt ≤ 3 V/s (see Figure 17) VLD = 2 to 14 V(SVS_IT−) V(SVS_IT−) VVhhyyss((SSVVSS__IITT−−)) × 0.004 × 0.008 VCC/dt ≤ 3 V/s (see Figure 17), VLD = 15 4.4 10.4 mV External voltage applied onSVSIN VLD = 1 1.8 1.9 2.05 VLD = 2 1.94 2.1 2.25 VLD = 3 2.05 2.2 2.37 VLD = 4 2.14 2.3 2.48 VLD = 5 2.24 2.4 2.6 VLD = 6 2.33 2.5 2.71 VLD = 7 2.46 2.65 2.86 VVCCCC//ddtt ≤≤ 33 VV//ss ((sseeee FFiigguurree 1177)) VLD = 8 2.58 2.8 3 VV((SSVVSS_IITT−)) VV VLD = 9 2.69 2.9 3.13 VLD = 10 2.83 3.05 3.29 VLD = 11 2.94 3.2 3.42 VLD = 12 3.11 3.35 3.61† VLD = 13 3.24 3.5 3.76† VLD = 14 3.43 3.7† 3.99† VCC/dt ≤ 3 V/s (see Figure 17), VLD = 15 1.1 1.2 1.3 External voltage applied onSVSIN I(CseCe(S NVSo)te 1) VLD ≠ 0, VCC = 2.2 V/3 V 10 15 μA †The recommended operating voltage range is limited to 3.6 V. ‡tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere between 2 and 15. The overdrive is assumed to be > 50 mV. NOTES: 1. The current consumption of the SVS module is not included in the ICC current consumption data. 2. The SVS is not active at power up. 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Software Sets VLD>0:SVS is Active V CC Vhys(SVS_IT−) V (SVS_IT−) V (SVSstart) Vhys(B_IT−) V(B_IT−) V CC(start) Brownout Brownout Region Brownout Region 1 0 SVS out td(BOR) td(BOR) SVS Circuit is Active From VLD > to VCC < V(B_IT−) 1 0 td(SVSon) Set POR td(SVSR) 1 Undefined 0 Figure 17. SVS Reset (SVSR) vs Supply Voltage VCC tpw 3 V 2 Rectangular Drop VCC(drop) 1.5 Triangular Drop V − p) o 1 dr C( 1 ns 1 ns C V 0.5 VCC tpw 3 V 0 1 10 100 1000 tpw − Pulse Width − μs VCC(drop) tf = tr tf tr t − Pulse Width − μs Figure 18. V With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal CC(drop) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) DCO PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT f(DCOCLK) NDC(DOCOP)L =U 0S1 =E h0,, FfCNry_s8ta l= = F 3N2_.746 =8 FkNH_z3 = FN_2 = 0, D = 2, 2.2 V/3 V 1 MHz 2.2 V 0.3 0.65 1.25 ff(DCO=2) FFNN_88 = FFNN_44 = FFNN_33 = FFNN_22 = 00, DDCCOOPPLLUUSS = 11 3 V 0.3 0.7 1.3 MMHHzz 2.2 V 2.5 5.6 10.5 ff(DCO=27) FFNN_88 = FFNN_44 = FFNN_33 = FFNN_22 = 00, DDCCOOPPLLUUSS = 11 3 V 2.7 6.1 11.3 MMHHzz 2.2 V 0.7 1.3 2.3 ff(DCO=2) FFNN_88 = FFNN_44 = FFNN_33 = 00, FFNN_22 = 11, DDCCOOPPLLUUSS = 11 3 V 0.8 1.5 2.5 MMHHzz 2.2 V 5.7 10.8 18 ff(DCO=27) FFNN_88 = FFNN_44 = FFNN_33 = 00, FFNN_22 = 11, DDCCOOPPLLUUSS = 11 3 V 6.5 12.1 20 MMHHzz 2.2 V 1.2 2 3 ff(DCO=2) FFNN_88 = FFNN_44 = 00, FFNN_33 = 11, FFNN_22 = xx, DDCCOOPPLLUUSS = 11 3 V 1.3 2.2 3.5 MMHHzz 2.2 V 9 15.5 25 ff(DCO=27) FFNN_88 = FFNN_44 = 00, FFNN_33 = 11, FFNN_22 = xx;; DDCCOOPPLLUUSS = 11 3 V 10.3 17.9 28.5 MMHHzz 2.2 V 1.8 2.8 4.2 ff(DCO=2) FFNN_88 = 00, FFNN_44 = 11, FFNN_33 = FFNN_22 = xx, DDCCOOPPLLUUSS = 11 3 V 2.1 3.4 5.2 MMHHzz 2.2 V 13.5 21.5 33 ff(DCO=27) FFNN_88 = 00, FFNN_44 = 11, FFNN_33 = FFNN_22 =xx, DDCCOOPPLLUUSS = 11 3 V 16 26.6 41 MMHHzz 2.2 V 2.8 4.2 6.2 ff(DCO=2) FFNN_88 = 11, FFNN_44 = FFNN_33 = FFNN_22=xx, DDCCOOPPLLUUSS = 11 3 V 4.2 6.3 9.2 MMHHzz 2.2 V 21 32 46 ff(DCO=27) FFNN_88 = 11,FFNN_44 = FFNN_33 = FFNN_22 = xx, DDCCOOPPLLUUSS = 11 3 V 30 46 70 MMHHzz Step size between adjacent DCO taps: 1 < TAP ≤ 20 1.06 1.11 SSn SSn = ffDCO(Tap n+1) // ffDCO(Tap n) (see Figure 20 for taps 21 to 27) TAP = 27 1.07 1.17 DDt TTDee =mm 2pp,ee DrraaCttuuOrreeP LddUrriiffStt,, =NN ((0DDCCOO)) == 0011EEhh,, FFNN__88 == FFNN__44 == FFNN__33 == FFNN__22 == 00,, 23.2 V V ––00..22 ––00..33 ––00..44 %%//(cid:3)(cid:3)CC DV DFNrif_t 8w =it hF VNC_C4 v=a FriNat_io3n =, NF(ND_C2O )= = 0 0, 1DE =h ,2 , DCOPLUS = 0 0 5 15 %/V f f (DCO) (DCO) f(DCO3V) f(DCO20(cid:2)C) 1.0 1.0 0 1.8 2.4 3.0 3.6 −40 −20 0 20 40 60 85 VCC − V TA − °C Figure 19. DCO Frequency vs Supply Voltage V and vs Ambient Temperature CC 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) s ÎÎÎÎÎÎÎÎÎÎÎÎÎ p a 1.17 O T ÎÎÎÎÎÎÎÎÎÎÎÎÎ C D ÎÎÎÎÎÎÎÎÎÎÎÎÎ n e ÎÎÎÎÎÎÎÎÎÎÎÎÎ e w et ÎÎÎÎÎÎÎÎÎÎÎÎÎ b atio 1.11 ÎÎÎÎÎÎÎÎMaÎx ÎÎÎÎ R e ÎÎÎÎÎÎÎÎÎÎÎÎÎ z si ÎÎÎÎÎÎÎÎÎÎÎÎÎ p e St ÎÎÎÎÎÎÎÎÎÎÎÎÎ S - n 11..0076 ÎÎÎÎÎÎÎÎÎÎÎÎÎ Min 1 20 27 DCO Tap Figure 20. DCO Tap Step Size Legend Tolerance at Tap 27 O) C D f( DCO Frequency Adjusted by Bits 29 to 25 in SCFI1 {N{DCO}} Tolerance at Tap 2 Overlapping DCO Ranges: Uninterrupted Frequency Range FN_2=0 FN_2=1 FN_2=x FN_2=x FN_2=x FN_3=0 FN_3=0 FN_3=1 FN_3=x FN_3=x FN_4=0 FN_4=0 FN_4=0 FN_4=1 FN_4=x FN_8=0 FN_8=0 FN_8=0 FN_8=0 FN_8=1 Figure 21. Five Overlapping DCO Ranges Controlled by FN_x Bits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) crystal oscillator, LFXT1 oscillator (see Notes 1 and 2) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT OSCCAPx = 0h 0 OSCCAPx = 1h 10 CCXIN IInntteeggrraatteedd llooaadd ccaappaacciittaannccee OSCCAPx = 2h 22.22 VV//33 VV 14 ppFF OSCCAPx = 3h 18 OSCCAPx = 0h 0 OSCCAPx = 1h 10 CCXOUT IInntteeggrraatteedd llooaadd ccaappaacciittaannccee OSCCAPx = 2h 22.22 VV//33 VV 14 ppFF OSCCAPx = 3h 18 VIL 2.2 V/3 V VSS 0.2×VCC IInnppuutt lleevveellss aatt XXIINN sseeee NNoottee 33 VV VIH 2.2 V/3 V 0.8×VCC VCC NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2pF. The effective load capacitor for the crystal is (CXIN × CXOUT) / (CXIN + CXOUT). It is independent of XTS_FLL. 2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines must be observed: • Keep the trace between the MSP430x41x and the crystal as short as possible. • Design a good ground plane around oscillator pins. • Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. • Avoid running PCB traces underneath or adjacent to XIN an XOUT pins. • Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. • If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. • Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. 3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator. 4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h. 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) flash memory TEST PARAMETER CONDITIONS VCC MIN TYP MAX UNIT VCC(PGM/ Program and erase supply voltage 2.7 3.6 V ERASE) fFTG Flash timing generator frequency 257 476 kHz IPGM Supply current from DVCC during program 2.7 V/ 3.6 V 3 5 mA IERASE Supply current from DVCC during erase 2.7 V/ 3.6 V 3 7 mA tCPT Cumulative program time See Note 1 2.7 V/ 3.6 V 10 ms tCMErase Cumulative mass erase time See Note 2 2.7 V/ 3.6 V 200 ms Program/erase endurance 104 105 cycles tRetention Data retention duration TJ = 25°C 100 years tWord Word or byte program time 35 tBlock, 0 Block program time for 1st byte or word 30 tBlock, 1-63 Block program time for each additional byte or word 21 tBlock, End Block program end-sequence wait time SSeeee NNoottee 33 6 ttFTG tMass Erase Mass erase time 5297 tSeg Erase Segment erase time 4819 NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. 2. The mass erase duration generated by the flash timing generator is at least 11.1 ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To achieve the required cumulative mass erase time the flash controller’s mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles are required). 3. These values are hardwired into the flash controller’s state machine (tFTG = 1/fFTG). JTAG interface TEST PARAMETER CONDITIONS VCC MIN TYP MAX UNIT 2.2 V 0 5 MHz ffTCK TTCCKK iinnppuutt ffrreeqquueennccyy sseeee NNoottee 11 3 V 0 10 MHz RInternal Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2 2.2 V/ 3 V 25 60 90 kΩ NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected. 2. TMS, TDI/TCLK, and TCK pullup resistors are implemented in all versions. JTAG fuse (see Note 1) TEST PARAMETER MIN MAX UNIT CONDITIONS VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V MSP430C41x 3.5 3.9 V VVFB VVoollttaaggee lleevveell oonn TTDDII//TTCCLLKK ffoorr ffuussee-bbllooww MSP430F41x 6 7 V IFB Supply current into TDI/TCLK during fuse blow 100 mA tFB Time to blow fuse 1 ms NOTES: 1. Once the fuse is blown, no further access to the MSP430 via JTAG/Test is possible. The JTAG block is switched to bypass mode. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 APPLICATION INFORMATION input/output schematics Port P1, P1.0 to P1.5, input/output with Schmitt trigger Pad Logic CAPD.x P1SEL.x 0: Input 0 P1DIR.x 1: Output Direction Control 1 From Module 0 P1.x P1OUT.x 1 Module X OUT Bus keeper MSP430x412, MSP430x413 only P1.0/TA0 P1IN.x P1.1/TA0/MCLK P1.2/TA1 EN P1.3/SVSOUT P1.4 Module X IN D P1.5/TACLK/ACLK MSP430x415, P1IE.x MSP430x417 only P1IRQ.x Q EN Interrupt P1.0/TA0.0 Edge P1IFG.x P1.1/TA0.0/MCLK Set Select P1.2/TA0.1 P1.3/TA1.0/SVSOUT P1.4/TA1.0 P1IES.x P1SEL.x P1.5/TA0CLK/ACLK NOTE: 0 ≤ x ≤ 5. Port Function is Active if CAPD.x = 0 Direction Module X PnSEL.x PnDIR.x Control PnOUT.x PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x OUT From Module P1SEL.0 P1DIR.0 P1DIR.0 P1OUT.0 Out0 Sig.† P1IN.0 CCI0A† P1IE.0 P1IFG.0 P1IES.0 P1SEL.1 P1DIR.1 P1DIR.1 P1OUT.1 MCLK P1IN.1 CCI0B† P1IE.1 P1IFG.1 P1IES.1 P1SEL.2 P1DIR.2 P1DIR.2 P1OUT.2 Out1 Sig.† P1IN.2 CCI1A† P1IE.2 P1IFG.2 P1IES.2 P1SEL.3 P1DIR.3 P1DIR.3 P1OUT.3 SVSOUT P1IN.3 Unused P1IE.3 P1IFG.3 P1IES.3 P1SEL.4 P1DIR.4 P1DIR.4 P1OUT.4 DVSS§ P1IN.4 Unused§ P1IE.4 P1IFG.4 P1IES.4 Out0 Sig.‡ CCI0A‡ P1SEL.5 P1DIR.5 P1DIR.5 P1OUT.5 ACLK P1IN.5 TACLK† P1IE.5 P1IFG.5 P1IES.5 †Timer_A3/Timer0_A3 ‡Timer1_A5 (MSP430x415, MSP430x417 only) §MSP430x412, MSP430x413 only 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 APPLICATION INFORMATION Port P1, P1.6, P1.7 input/output with Schmitt trigger Pad Logic Note: Port Function Is Active if CAPD.6 = 0 CAPD.6 P1SEL.6 0 0: Input P1DIR.6 1: Output 1 P1DIR.6 P1.6/ 0 CA0 P1OUT.6 1 DVSS Bus Keeper P1IN.6 EN unused D P1IE.7 P1IRQ.07 EN Interrupt P1IFG.7 Q Edge Set Select P1IES.x P1SEL.x Comparator_A P2CA AVcc CAREF CAEX CA0 CAF CCI1B + CA1 to Timer_Ax − 2 CAREF Reference Block Pad Logic Note: Port Function Is Active if CAPD.7 = 0 CAPD.7 P1SEL.7 0 0: Input P1DIR.7 1: Output 1 P1DIR.7 P1.7/ 0 CA1 P1OUT.7 1 DVSS Bus Keeper P1IN.7 EN unused D P1IE.7 P1IRQ.07 EN Interrupt P1IFG.7 Q Edge Set Select P1IES.7 P1SEL.7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 APPLICATION INFORMATION port P2, P2.0 to P2.7, input/output with Schmitt trigger P2.0, P2.1 LCDM.5 LCDM.6 P2.2 to P2.5 LCDM.7 P2.6, P2.7 0: Port Active 1: Segment xx Function Active Pad Logic Segment xx P2SEL.x 0: Input 0 P2DIR.x 1: Output Direction Control 1 From Module 0 P2.x P2OUT.x 1 Module X OUT Bus MSP430x412, keeper MSP430x413 only P2.0/TA2 P2.1 P2IN.x P2.2/S23 P2.3/S22 EN P2.4/S21 P2.5/S20 P2.6/CAOUT/S19 Module X IN D P2.7/S18 MSP430x415, P2IE.x MSP430x417 only P2IRQ.x EN Interrupt P2.0/TA0.2 Q P2IFG.x Edge P2.1/TA1.1 Set Select P2.2/TA1.2/S23 P2.3/TA1.3/S22 P2.4/TA1.4/S21 P2IES.x P2SEL.x P2.5/TA1CLK/S20 NOTE: 0 ≤ x ≤ 7 P2.6/CAOUT/S19 P2.7/S18 Direction Module X PnSEL.x PnDIR.x Control PnOUT.x PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x OUT From Module P2SEL.0 P2DIR.0 P2DIR.0 P2OUT.0 Out2 Sig.† P2IN.0 CCI2A† P2IE.0 P2IFG.0 P2IES.0 DVSS§ Unused§ P2SEL.1 P2DIR.1 P2DIR.1 P2OUT.1 Out1 Sig.‡ P2IN.1 CCI1A‡ P2IE.1 P2IFG.1 P2IES.1 DVSS§ Unused§ P2SEL.2 P2DIR.2 P2DIR.2 P2OUT.2 Out2 Sig.‡ P2IN.2 CCI2A‡ P2IE.2 P2IFG.2 P2IES.2 DVSS§ Unused§ P2SEL.3 P2DIR.3 P2DIR.3 P2OUT.3 Out3 Sig.‡ P2IN.3 CCI3A‡ P2IE.3 P2IFG.3 P2IES.3 DVSS§ Unused§ P2SEL.4 P2DIR.4 P2DIR.4 P2OUT.4 Out4 Sig.‡ P2IN.4 CCI4A‡ P2IE.4 P2IFG.4 P2IES.4 Unused§ P2SEL.5 P2DIR.5 P2DIR.5 P2OUT.5 DVSS P2IN.5 TA1CLK‡ P2IE.5 P2IFG.5 P2IES.5 P2SEL.6 P2DIR.6 P2DIR.6 P2OUT.6 CAOUT P2IN.6 Unused P2IE.6 P2IFG.6 P2IES.6 P2SEL.7 P2DIR.7 P2DIR.7 P2OUT.7 DVSS P2IN.7 Unused P2IE.7 P2IFG.7 P2IES.7 †Timer_A3/Timer0_A3 ‡Timer1_A5 (MSP430x415, MSP430x417 only) §MSP430x412, MSP430x413 only 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 APPLICATION INFORMATION port P3, P3.0 to P3.7, input/output with Schmitt trigger LCDM.5 P3.2 to P3.7 LCDM.6 LCDM.7 P3.0, P3.1 0: Port Active 1: Segment xx Function Active Pad Logic Segment xx P3SEL.x 0: Input 0 P3DIR.x 1: Output Direction Control 1 From Module 0 P3.x P3OUT.x 1 Module X OUT Bus keeper P3.0/S17 P3.1/S16 P3.2/S15 P3IN.x P3.3/S14 P3.4/S13 EN P3.5/S12 P3.6/S11 Module X IN D P3.7/S10 NOTE: 0 ≤ x ≤ 7 Direction Module X PnSEL.x PnDIR.x Control PnOUT.x PnIN.x Module X IN OUT From Module P3SEL.0 P3DIR.0 P3DIR.0 P3OUT.0 DVSS P3IN.0 Unused P3SEL.1 P3DIR.1 P3DIR.1 P3OUT.1 DVSS P3IN.1 Unused P3SEL.2 P3DIR.2 P3DIR.2 P3OUT.2 DVSS P3IN.2 Unused P3SEL.3 P3DIR.3 P3DIR.3 P3OUT.3 DVSS P3IN.3 Unused P3SEL.4 P3DIR.4 P3DIR.4 P3OUT.4 DVSS P3IN.4 Unused P3SEL.5 P3DIR.5 P3DIR.5 P3OUT.5 DVSS P3IN.5 Unused P3SEL.6 P3DIR.6 P3DIR.6 P3OUT.6 DVSS P3IN.6 Unused P3SEL.7 P3DIR.7 P3DIR.7 P3OUT.7 DVSS P3IN.7 Unused POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 41

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 APPLICATION INFORMATION port P4, P4.0 to P4.7, input/output with Schmitt trigger LCDM.5 0: Port Active LCDM.6 1: Segment xx LCDM.7 Function Active Pad Logic Segment xx P4SEL.x 0: Input 0 P4DIR.x 1: Output Direction Control 1 From Module 0 P4.x P4OUT.x 1 Module X OUT Bus keeper P4.0/S9 P4.1/S8 P4.2/S7 P4IN.x P4.3/S6 P4.4/S5 EN P4.5/S4 P4.6/S3 Module X IN D P4.7/S2 NOTE: 0 ≤ x ≤ 7 Direction Module X PnSEL.x PnDIR.x Control PnOUT.x PnIN.x Module X IN OUT From Module P4SEL.0 P4DIR.0 P4DIR.0 P4OUT.0 DVSS P4IN.0 Unused P4SEL.1 P4DIR.1 P4DIR.1 P4OUT.1 DVSS P4IN.1 Unused P4SEL.2 P4DIR.2 P4DIR.2 P4OUT.2 DVSS P4IN.2 Unused P4SEL.3 P4DIR.3 P4DIR.3 P4OUT.3 DVSS P4IN.3 Unused P4SEL.4 P4DIR.4 P4DIR.4 P4OUT.4 DVSS P4IN.4 Unused P4SEL.5 P4DIR.5 P4DIR.5 P4OUT.5 DVSS P4IN.5 Unused P4SEL.6 P4DIR.6 P4DIR.6 P4OUT.6 DVSS P4IN.6 Unused P4SEL.7 P4DIR.7 P4DIR.7 P4OUT.7 DVSS P4IN.7 Unused 42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 APPLICATION INFORMATION port P5, P5.0, P5.1, input/output with Schmitt trigger LCDM.5 0: Port Active LCDM.6 1: Segment LCDM.7 Function Active Pad Logic Segment xx or COMx or Rxx P5SEL.x 0: Input 0 P5DIR.x 1: Output Direction Control 1 From Module 0 P5.x P5OUT.x 1 Module X OUT Bus keeper P5.0/S1 P5.1/S0 P5IN.x EN Module X IN D NOTE: x = 0, 1 Direction Module X PnSEL.x PnDIR.x Control PnOUT.x PnIN.x Module X IN Segment OUT From Module P5SEL.0 P5DIR.0 P5DIR.0 P5OUT.0 DVSS P5IN.0 Unused S1 P5SEL.1 P5DIR.1 P5DIR.1 P5OUT.1 DDVVSSSS P5IN.1 UUnnuusseedd S0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 43

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 APPLICATION INFORMATION port P5, P5.2 to P5.4, input/output with Schmitt trigger 0: Port Active 1: COMx Function Active Pad Logic COMx P5SEL.x 0: Input 0 P5DIR.x 1: Output Direction Control 1 From Module 0 P5.x P5OUT.x 1 Module X OUT Bus keeper P5.2/COM1 P5.3/COM2 P5.4/COM3 P5IN.x EN Module X IN D NOTE: 2 ≤ x ≤ 4 Direction Module X PnSEL.x PnDIR.x Control PnOUT.x PnIN.x Module X IN COMx OUT From Module P5SEL.2 P5DIR.2 P5DIR.2 P5OUT.2 DVSS P5IN.2 Unused COM1 P5SEL.3 P5DIR.3 P5DIR.3 P5OUT.3 DDVVSSSS P5IN.3 UUnnuusseedd COM2 P5SEL.4 P5DIR.4 P5DIR.4 P5OUT.4 DDVVSSSS P5IN.4 UUnnuusseedd COM3 NOTE: The direction control bits P5SEL.2, P5SEL.3, and P5SEL.4 are used to distinguish between port and common functions. Note that a 4MUX LCD requires all common signals COM3 to COM0, a 3MUX LCD requires COM2 to COM0, 2MUX LCD requires COM1 to COM0, and a static LCD requires only COM0. 44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 APPLICATION INFORMATION port P5, P5.5 to P5.7, input/output with Schmitt trigger 0: Port Active 1: Rxx Function Active Pad Logic Rxx P5SEL.x 0: Input 0 P5DIR.x 1: Output Direction Control 1 From Module 0 P5.x P5OUT.x 1 Module X OUT Bus keeper P5.5/R13 P5.6/R23 P5.7/R33 P5IN.x EN Module X IN D NOTE: 5 ≤ x ≤ 7 Direction Module X PnSEL.x PnDIR.x Control PnOUT.x PnIN.x Module X IN Rxx OUT From Module P5SEL.5 P5DIR.5 P5DIR.5 P5OUT.5 DVSS P5IN.5 Unused R13 P5SEL.6 P5DIR.6 P5DIR.6 P5OUT.6 DDVVSSSS P5IN.6 UUnnuusseedd R23 P5SEL.7 P5DIR.7 P5DIR.7 P5OUT.7 DDVVSSSS P5IN.7 UUnnuusseedd R33 NOTE: The direction control bits P5SEL.5, P5SEL.6, and P5SEL.7 are used to distinguish between port and LCD analog level functions. Note that 4MUX and 3MUX LCDs require all Rxx signals R33 to R03, a 2MUX LCD requires R33, R13, and R03, and a static LCD requires only R33 and R03. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 45

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 APPLICATION INFORMATION port P6, P6.0 to P6.6, input/output with Schmitt trigger P6SEL.x 0: Input P6DIR.x 0 1: Output Direction Control 1 From Module 0 P6.x P6OUT.x 1 Module X OUT PP66..0 PP66..1 P6.2 P6IN.x P6.3 PP66..4 EN PP66..5 PP66..6 Module X IN D NOTE: 0 ≤ x ≤ 6 Direction Module X PnSEL.x PnDIR.x Control PnOUT.x PnIN.x Module X IN OUT From Module P6SEL.0 P6DIR.0 P6DIR.0 P6OUT.0 DVSS P6IN.0 Unused P6SEL.1 P6DIR.1 P6DIR.1 P6OUT.1 DVSS P6IN.1 Unused P6SEL.2 P6DIR.2 P6DIR.2 P6OUT.2 DVSS P6IN.2 Unused P6SEL.3 P6DIR.3 P6DIR.3 P6OUT.3 DVSS P6IN.3 Unused P6SEL.4 P6DIR.4 P6DIR.4 P6OUT.4 DVSS P6IN.4 Unused P6SEL.5 P6DIR.5 P6DIR.5 P6OUT.5 DVSS P6IN.5 Unused P6SEL.6 P6DIR.6 P6DIR.6 P6OUT.6 DVSS P6IN.6 Unused 46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 APPLICATION INFORMATION port P6, P6.7 input/output with Schmitt trigger (MSP430x412/413 only) P6SEL.7 0: Input P6DIR.7 0 1: Output Direction Control 1 From Module 0 P6.x P6OUT.7 1 Module X OUT P6.7 P6IN.7 EN Module X IN D Direction Module X PnSEL.x PnDIR.x Control PnOUT.x PnIN.x Module X IN OUT From Module P6SEL.7 P6DIR.7 P6DIR.7 P6OUT.7 DVSS P6IN.7 Unused POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 47

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 APPLICATION INFORMATION port P6, P6.7 input/output with Schmitt trigger (MSP430F415/417 only) SVS VLDx=15 P6SEL.7 0 P6DIR.7 0: Input 1: Output 1 Pad Logic P6.7/SVSIN 0 P6OUT.7 DVss 1 Bus Keeper P6IN.7 EN Module X IN D SVS VLDx=15 1 To SVS NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if the analog signal is in the range of transitions 0→1 or 1→0. The value of the throughput current depends on the driving capability of the gate. For MSP430, it is approximately 100 μA. Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, if an analog signal is applied to the pin. SVS VLDx = 15 P6SEL.7 P6DIR.7 Port Function 0 0 0 P6.7 Input 0 0 1 P6.7 Output 0 1 X Undefined 1 X X SVSIN 48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 APPLICATION INFORMATION JTAG pins (TMS, TCK, TDI/TCLK, TDO/TDI), input/output with Schmitt trigger or output TDO Controlled by JTAG Controlled by JTAG TDO/TDI JTAG Controlled DV by JTAG CC TDI Burn and Test Fuse TDI/TCLK DV CC TMS Test and TMS Emulation Module (F versions only) DV CC TCK TCK RST/NMI Tau ~ 50 ns D Brownout G U S D TCK U G S POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 49

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 APPLICATION INFORMATION JTAG fuse check mode MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, I , of 1.8 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be TF taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see Figure 22). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). The JTAG pins are terminated internally, and therefore do not require external termination. Time TMS Goes Low After POR TMS ITF ITDI/TCLK Figure 22. Fuse Check Mode Current, MSP430C41x, MSP430F41x 50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 Data Sheet Revision History Literature Summary Number Updated functional block diagrams (page 4) Clarified test conditions in recommended operating conditions table (page 21) Split Supply voltage during program execution for MSP430x412/413 and MSP430x415/417 (page 21) SLAS340H Clarified test conditions for I(LPM0) in supply current into AVCC + DVCC table (page 22) Added P2−P5 to leakage current table (page 23) Changed tCPT maximum value from 4 ms to 10 ms in Flash memory table (page 37) SLAS340I Changed all RTD package options for MSP430C41x to RGC package. NOTE: Page and figure numbers refer to the respective document revision. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 51

Manual Update Sheet SLAZ554–December2013 Corrections to MSP430x41x Data Sheet (SLAS340J) DocumentBeingUpdated: MSP430x41xMixedSignalMicrocontroller LiteratureNumberBeingUpdated:SLAS340J Page ChangeorAdd 40 Intopleftofthefigure: LCDM.5shouldbechangedtobit0ofLCDPx,whichisbit5oftheLCDCTLregister. LCDM.6shouldbechangedtobit1ofLCDPx,whichisbit6oftheLCDCTLregister. LCDM.7shouldbechangedtobit2ofLCDPx,whichisbit7oftheLCDCTLregister. 41 Intopleftofthefigure: LCDM.5shouldbechangedtobit0ofLCDPx,whichisbit5oftheLCDCTLregister. LCDM.6shouldbechangedtobit1ofLCDPx,whichisbit6oftheLCDCTLregister. LCDM.7shouldbechangedtobit2ofLCDPx,whichisbit7oftheLCDCTLregister. 42 Intopleftofthefigure: LCDM.5shouldbechangedtobit0ofLCDPx,whichisbit5oftheLCDCTLregister. LCDM.6shouldbechangedtobit1ofLCDPx,whichisbit6oftheLCDCTLregister. LCDM.7shouldbechangedtobit2ofLCDPx,whichisbit7oftheLCDCTLregister. 43 Intopleftofthefigure: LCDM.5shouldbechangedtobit0ofLCDPx,whichisbit5oftheLCDCTLregister. LCDM.6shouldbechangedtobit1ofLCDPx,whichisbit6oftheLCDCTLregister. LCDM.7shouldbechangedtobit2ofLCDPx,whichisbit7oftheLCDCTLregister. SLAZ554–December2013 CorrectionstoMSP430x41xDataSheet(SLAS340J) 1 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MSP430F412IPM ACTIVE LQFP PM 64 160 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F412 & no Sb/Br) REV # MSP430F412IPMR ACTIVE LQFP PM 64 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F412 & no Sb/Br) REV # MSP430F412IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS SN Level-3-260C-168 HR -40 to 85 M430F412 & no Sb/Br) MSP430F412IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS SN Level-3-260C-168 HR -40 to 85 M430F412 & no Sb/Br) MSP430F413IPM ACTIVE LQFP PM 64 160 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F413 & no Sb/Br) REV # MSP430F413IPMR ACTIVE LQFP PM 64 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F413 & no Sb/Br) REV # MSP430F413IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS SN Level-3-260C-168 HR -40 to 85 M430F413 & no Sb/Br) MSP430F413IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS SN Level-3-260C-168 HR -40 to 85 M430F413 & no Sb/Br) MSP430F415IPM ACTIVE LQFP PM 64 160 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F415 & no Sb/Br) MSP430F415IPMR ACTIVE LQFP PM 64 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F415 & no Sb/Br) MSP430F415IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS SN Level-3-260C-168 HR -40 to 85 M430F415 & no Sb/Br) MSP430F415IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS SN Level-3-260C-168 HR -40 to 85 M430F415 & no Sb/Br) MSP430F417IPM ACTIVE LQFP PM 64 160 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F417 & no Sb/Br) MSP430F417IPMR ACTIVE LQFP PM 64 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430F417 & no Sb/Br) MSP430F417IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS SN Level-3-260C-168 HR -40 to 85 M430F417 & no Sb/Br) MSP430F417IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS SN Level-3-260C-168 HR -40 to 85 M430F417 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) MSP430F412IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F412IRTDR VQFN RTD 64 2500 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 MSP430F412IRTDT VQFN RTD 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 MSP430F413IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F413IRTDR VQFN RTD 64 2500 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 MSP430F413IRTDT VQFN RTD 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 MSP430F415IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F415IRTDR VQFN RTD 64 2500 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 MSP430F415IRTDT VQFN RTD 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 MSP430F417IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F417IRTDR VQFN RTD 64 2500 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 MSP430F417IRTDT VQFN RTD 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) MSP430F412IPMR LQFP PM 64 1000 336.6 336.6 41.3 MSP430F412IRTDR VQFN RTD 64 2500 367.0 367.0 38.0 MSP430F412IRTDT VQFN RTD 64 250 210.0 185.0 35.0 MSP430F413IPMR LQFP PM 64 1000 336.6 336.6 41.3 MSP430F413IRTDR VQFN RTD 64 2500 367.0 367.0 38.0 MSP430F413IRTDT VQFN RTD 64 250 210.0 185.0 35.0 MSP430F415IPMR LQFP PM 64 1000 336.6 336.6 41.3 MSP430F415IRTDR VQFN RTD 64 2500 367.0 367.0 38.0 MSP430F415IRTDT VQFN RTD 64 250 210.0 185.0 35.0 MSP430F417IPMR LQFP PM 64 1000 336.6 336.6 41.3 MSP430F417IRTDR VQFN RTD 64 2500 367.0 367.0 38.0 MSP430F417IRTDT VQFN RTD 64 250 210.0 185.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PM0064A LQFP - 1.6 mm max height SCALE 1.400 PPLLAASSTTIICC QQUUAADD FFLLAATTPPAACCKK 10.2 B 9.8 NOTE 3 64 49 PIN 1 ID 1 48 10.2 12.2 TYP 9.8 11.8 NOTE 3 16 33 A 17 32 0.27 64X 60X 0.5 0.17 4X 7.5 0.08 C A B C (0.13) TYP SEATING PLANE 00..0088 SEE DETAIL A 0.25 (1.4) 1.6 MAX GAGE PLANE 0 -7 0.75 0.05 MIN 0.45 DETSDCEATLAEIL: 1A4AIL A TYPICAL 4215162/A 03/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MS-026. www.ti.com

EXAMPLE BOARD LAYOUT PM0064A LQFP - 1.6 mm max height PLASTIC QUAD FLATPACK SYMM 64 49 64X (1.5) 1 48 64X (0.3) SYMM 60X (0.5) (11.4) (R0.05) TYP 16 33 17 32 (11.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X 0.05 MAX EXPOSED METAL ALL AROUND EXPOSED METAL 0.05 MIN ALL AROUND METAL SOLDER MASK SOLDER MASK METAL UNDER OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4215162/A 03/2017 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004). www.ti.com

EXAMPLE STENCIL DESIGN PM0064A LQFP - 1.6 mm max height PLASTIC QUAD FLATPACK SYMM 64 49 64X (1.5) 1 48 64X (0.3) SYMM 60X (0.5) (11.4) (R0.05) TYP 16 33 17 32 (11.4) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X 4215162/A 03/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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