MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • LowSupplyVoltageRange:1.8Vto3.6V • UniversalSerialCommunicationInterface 2 • Ultra-LowPowerConsumption – EnhancedUARTSupportingAutoBaudrate – ActiveMode:270µAat1MHz,2.2V Detection(LIN) – StandbyMode:0.7 µA – IrDAEncoderandDecoder – OffMode(RAMRetention):0.1µA – SynchronousSPI • Ultra-FastWake-UpFromStandbyModein – I2C™ LessThan1µs • BrownoutDetector • 16-BitRISCArchitecture,62.5-nsInstruction • SerialOnboardProgramming,NoExternal CycleTime ProgrammingVoltageNeeded,Programmable • BasicClockModuleConfigurations CodeProtectionbySecurityFuse – InternalFrequenciesupto16MHzWith • BootstrapLoader FourCalibratedFrequenciesto±1% • On-ChipEmulationModule – InternalVery-Low-PowerLow-Frequency • FamilyMembersInclude: (LF)Oscillator – MSP430F2330 – 32-kHzCrystal – 8KB+256BFlashMemory – High-Frequency(HF)Crystalupto16MHz – 1KBRAM – Resonator – MSP430F2350 – ExternalDigitalClockSource – 16KB+256BFlashMemory – ExternalResistor – 2KBRAM • 16-BitTimer_AWithThreeCapture/Compare – MSP430F2370 Registers – 32KB+256BFlashMemory • 16-BitTimer_BWithThreeCapture/Compare – 2KBRAM Registers • Availablein40-PinQFNPackageand49-Pin • On-ChipComparatorforAnalogSignal Die-SizedBGAPackage(SeeTable1) CompareFunctionorSlopeAnalog-to-Digital • ForCompleteModuleDescriptions,Seethe (A/D)Conversion MSP430x2xxFamilyUser'sGuide(SLAU144) DESCRIPTION TheTexasInstrumentsMSP430™familyofultra-low-powermicrocontrollersconsistsofseveraldevicesfeaturing different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes,isoptimizedtoachieveextendedbatterylifeinportablemeasurementapplications.Thedevicefeaturesa powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. Thedigitallycontrolledoscillator(DCO)allowswake-upfromlow-powermodestoactivemodeinlessthan1µs. TheMSP430F23x0seriesisanultra-low-powermicrocontrollerwithtwobuilt-in16-bittimers,oneuniversalserial communicationinterface(USCI),aversatileanalogcomparator,and32I/Opins. 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. MSP430isatrademarkofTexasInstruments. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2006–2011,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. Table1.AvailableOptions PACKAGEDDEVICES(1)(2) TA PLASTIC49-PINDSBGA PLASTIC40-PINQFN (YFF) (RHA) MSP430F2330IYFF MSP430F2330IRHA -40°Cto85°C MSP430F2350IYFF MSP430F2350IRHA MSP430F2370IYFF MSP430F2370IRHA - MSP430F2330TRHA -40°Cto105°C - MSP430F2350TRHA - MSP430F2370TRHA (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) Packagedrawings,thermaldata,andsymbolizationareavailableatwww.ti.com/packaging. Development Tool Support All MSP430 microcontrollers include an Embedded Emulation Module (EEM) that allows advanced debugging andprogrammingthrougheasy-to-usedevelopmenttools.Recommendedhardwareoptionsinclude: • DebuggingandProgrammingInterfacewithTargetBoard – MSP-FET430U23X0(RHApackage) • DebuggingandProgrammingInterface – MSP-FET430UIF(USB) – MSP-FET430PIF(ParallelPort) • TargetBoard – MSP-TS430QFN23X0(RHApackage) • ProductionProgrammer – MSP-GANG430 2 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Device Pinout, RHA Package RHAPACKAGE (TOPVIEW) K L C A H/ KT LU MI LKDIBCBOB2 SN CTTTT AVCCD/AVSRST/TCKTMSTDI/TTDO/P4.7/P4.6/P4.5/ 0 9 8 7 6 5 4 3 2 1 4 3 3 3 3 3 3 3 3 3 DV 1 30 P4.4/TB1 CC XIN/P2.6/CA6 2 29 P4.3/TB0 XOUT/P2.7/CA7 3 28 P4.2/TB2 P1.0/TACLK 4 27 P4.1/TB1 P1.1/TA0 5 26 P4.0/TB0 ExposedThermal Pad P1.2/TA1 6 25 P3.7 P1.3/TA2 7 24 P3.6 P1.4/SMCLK 8 23 P3.5/UCA0RXD/UCA0SOMI P1.5/TA0 9 22 P3.4/UCA0TXD/UCA0SIMO P1.6/TA1 10 21 P3.3/UCB0CLK/UCA0STE 1 2 3 4 5 6 7 8 9 0 1 1 1 1 1 1 1 1 1 2 2234125KAL AAAAAAALDC TCCCTTCCSS P1.7/CLK/CLK/TA0/CA0/CA1/R/OSCCA0CB0CB0 0/AAINUT/2.3/2.4/2.5/E/UO/UMI/U P2.P2.1/T2/CAOPPPCB0STB0SIMB0SO 2. UCC P P3.0/3.1/U3.2/U PP Copyright©2006–2011,TexasInstrumentsIncorporated 3

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Device Pinout, YFF Package YFFPACKAGE (TOPVIEW) A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 C1 C2 C3 C4 C5 C6 C7 D1 D2 D3 D4 D5 D6 D7 E1 E2 E3 E4 E5 E6 E7 F1 F2 F3 F4 F5 F6 F7 G1 G2 G3 G4 G5 G6 G7 Package Dimensions The package dimensions for this YFF package are shown in the following table. See the package drawing at the endofthisdatasheetformoredetails. Table2.YFFPackageDimensions PACKAGEDDEVICES D E MSP430F2370IYFF MSP430F2350IYFF 3.20±0.05mm 3.20±0.05mm MSP430F2330IYFF 4 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Functional Block Diagram XIN XOUT DVCC D/AVSS AVCC 1.x/P2.x P P3.x/P4.x 2x8 2x8 ACLK BasicClock Ports Flash RAM Ports System+ SMCLK P1/P2 P3/P4 32kB 2kB 2x8I/O 16kB 2kB 2x8I/O MCLK Interrupt 8kB 1kB capability 16MHz MAB CPU incl.16 Registers MDB Hardware Emulation Multiplier USCIA0: Watchdog Timer_A3 Timer_B3 Comp_A+ UART Brownout WDT+ IrDA,SPI MPY, InJteTrAfaGce Protection MMPAYCS,, 15-Bit Re3g CisCters Re3gCisCters Cha8nnels USSPCI,II2BC0: MACS RST/NMI Copyright©2006–2011,TexasInstrumentsIncorporated 5

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Table3.TerminalFunctions TERMINAL DESCRIPTION NAME YFF RHA I/O DV B3 1 Digitalsupplyvoltage,positiveterminal.Suppliesalldigitalparts. CC XIN/P2.6/CA6 A2 2 I/O Inputterminalofcrystaloscillator/general-purposedigitalI/Opin/Comparator_Ainput XOUT/P2.7/CA7 A3 3 I/O Outputterminalofcrystaloscillator/general-purposedigitalI/Opin/Comparator_Ainput P1.0/TACLK B4 4 I/O General-purposedigitalI/Opin/Timer_A,clocksignalTACLKinput P1.1/TA0 C4 5 I/O General-purposedigitalI/Opin/Timer_A,capture:CCI0Ainput,compare:Out0output P1.2/TA1 A5 6 I/O General-purposedigitalI/Opin/Timer_A,capture:CCI1Ainput,compare:Out1output P1.3/TA2 B5 7 I/O General-purposedigitalI/Opin/Timer_A,capture:CCI2Ainput,compare:Out2output P1.4/SMCLK A6 8 I/O General-purposedigitalI/Opin/SMCLKsignaloutput P1.5/TA0 B6 9 I/O General-purposedigitalI/Opin/Timer_A,compare:Out0output P1.6/TA1 A7 10 I/O General-purposedigitalI/Opin/Timer_A,compare:Out1output P1.7/TA2 B7 11 I/O General-purposedigitalI/Opin/Timer_A,compare:Out2output P2.0/ACLK/CA2 C5 12 I/O General-purposedigitalI/Opin/ACLKoutput/Comparator_Ainput P2.1/TAINCLK/CA3 C7 13 I/O General-purposedigitalI/Opin/Timer_A,clocksignalatINCLK/Comparator_Ainput General-purposedigitalI/Opin/Comparator_Aoutput/Timer_A,capture:CCI0B P2.2/CAOUT/TA0/CA4 C6 14 I/O input/Comparator_Ainput P2.3/CA0/TA1 D7 15 I/O General-purposedigitalI/Opin/Comparator_Ainput/Timer_A,compare:Out1output P2.4/CA1/TA2 D6 16 I/O General-purposedigitalI/Opin/Comparator_Ainput/Timer_A,compare:Out2output General-purposedigitalI/Opin/inputforexternalresistordefiningtheDCOnominal P2.5/R /CA5 E7 17 I/O OSC frequency/Comparator_Ainput P3.0/UCB0STE/ E6 18 I/O General-purposedigitalI/Opin/USCIB0slavetransmitenable/USCIAclockinput/output UCA0CLK P3.1/UCB0SIMO/ General-purposedigitalI/Opin/USCIB0slavein/masteroutinSPImode,SDAI2Cdata F7 19 I/O UCB0SDA inI2Cmode P3.2/UCB0SOMI/ General-purposedigitalI/Opin/USCIB0slaveout/masterininSPImode,SCLI2C F6 20 I/O UCB0SCL clockinI2Cmode P3.3/UCB0CLK/ G7 21 I/O General-purposedigitalI/O/USCIB0clockinput/output,USCIA0slavetransmitenable UCA0STE P3.4/UCA0TXD/ General-purposedigitalI/Opin/USCIA0transmitdataoutputinUARTmode,slavedata G6 22 I/O UCA0SIMO in/masteroutinSPImode P3.5/UCA0RXD/ General-purposedigitalI/Opin/USCIA0receivedatainputinUARTmode,slavedata G5 23 I/O UCA0SOMI out/masterininSPImode P3.6 F5 24 I/O General-purposedigitalI/Opin P3.7 G4 25 I/O General-purposedigitalI/Opin P4.0/TB0 F4 26 I/O General-purposedigitalI/Opin/Timer_B,capture:CCI0Ainput,compare:Out0output P4.1/TB1 G3 27 I/O General-purposedigitalI/Opin/Timer_B,capture:CCI1Ainput,compare:Out1output P4.2/TB2 G2 28 I/O General-purposedigitalI/Opin/Timer_B,capture:CCI2Ainput,compare:Out2output P4.3/TB0 F3 29 I/O General-purposedigitalI/Opin/Timer_B,capture:CCI0Binput,compare:Out0output P4.4/TB1 G1 30 I/O General-purposedigitalI/Opin/Timer_B,capture:CCI1Binput,compare:Out1output P4.5/TB2 F1 31 I/O General-purposedigitalI/Opin/Timer_B,compare:Out2output General-purposedigitalI/Opin/switchallPWMdigitaloutputstohighimpedance- P4.6/TBOUTH/ACLK F2 32 I/O Timer_B3:TB0toTB2/ACLKoutput P4.7/TBCLK E2 33 I/O General-purposedigitalI/Opin/inputclockTBCLK-Timer_B3 TDO/TDI E1 34 I/O Testdataoutputport.TDO/TDIdataoutputorprogrammingdatainputterminal Testdatainputortestclockinput.Thedeviceprotectionfuseisconnectedto TDI/TCLK D1 35 I TDI/TCLK. TMS D2 36 I Testmodeselect.TMSisusedasaninputportfordeviceprogrammingandtest. TCK C1 37 I Testclock.TCKistheclockinputportfordeviceprogrammingandtest. RST/NMI C2 38 I Resetinput,nonmaskableinterruptinputport. D/AV B1 39 Digital/analogsupplyvoltage,negativeterminal SS 6 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Table3.TerminalFunctions(continued) TERMINAL DESCRIPTION NAME YFF RHA I/O AV A1 40 Analogsupplyvoltage,positiveterminal CC QFNPad - NA NA QFNpackagepad.ConnectiontoD/AV recommended. SS A4, B2, C3, D3, Reserved - NA BGApackageGNDballs.ConnectiontoDV /AV isrecommended. D4, SS SS D5, E3, E4,E5 Copyright©2006–2011,TexasInstrumentsIncorporated 7

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com SHORT-FORM DESCRIPTION CPU Program Counter PC/R0 The MSP430™ CPU has a 16-bit RISC architecture Stack Pointer SP/R1 that is highly transparent to the application. All operations, other than program-flow instructions, are Status Register SR/CG1/R2 performed as register operations in conjunction with seven addressing modes for source operand and four Constant Generator CG2/R3 addressingmodesfordestinationoperand. General-Purpose Register R4 The CPU is integrated with 16 registers that provide reduced instruction execution time. The General-Purpose Register R5 register-to-register operation execution time is one cycleoftheCPUclock. General-Purpose Register R6 Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and General-Purpose Register R7 constant generator respectively. The remaining registersaregeneral-purposeregisters. General-Purpose Register R8 Peripherals are connected to the CPU using data, General-Purpose Register R9 address, and control buses and can be handled with allinstructions. General-Purpose Register R10 Instruction Set General-Purpose Register R11 The instruction set consists of 51 instructions with General-Purpose Register R12 three formats and seven address modes. Each instruction can operate on word and byte data. General-Purpose Register R13 Table 4 shows examples of the three types of instruction formats; Table 5 shows the address General-Purpose Register R14 modes. General-Purpose Register R15 Table4.InstructionWordFormats INSTRUCTIONFORMAT EXAMPLE OPERATION Dualoperands,source-destination ADDR4,R5 R4+R5→R5 Singleoperands,destinationonly CALLR8 PC→(TOS),R8→PC Relativejump,unconditional/conditional JNE Jump-on-equalbit=0 Table5.AddressModeDescriptions ADDRESSMODE S(1) D(2) SYNTAX EXAMPLE OPERATION Register ✓ ✓ MOVRs,Rd MOVR10,R11 R10→R11 Indexed ✓ ✓ MOVX(Rn),Y(Rm) MOV2(R5),6(R6) M(2+R5)→M(6+R6) Symbolic(PCrelative) ✓ ✓ MOVEDE,TONI M(EDE)→M(TONI) Absolute ✓ ✓ MOV&MEM,&TCDAT M(MEM)→M(TCDAT) Indirect ✓ MOV@Rn,Y(Rm) MOV@R10,Tab(R6) M(R10)→M(Tab+R6) M(R10)→R11 Indirectautoincrement ✓ MOV@Rn+,Rm MOV@R10+,R11 R10+2→R10 Immediate ✓ MOV#X,TONI MOV#45,TONI #45→M(TONI) (1) S=source (2) D=destination 8 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Operating Modes The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restorebacktothelow-powermodeonreturnfromtheinterruptprogram. Thefollowingsixoperatingmodescanbeconfiguredbysoftware: • Activemode(AM) – Allclocksareactive. • Low-powermode0(LPM0) – CPUisdisabled. – ACLKandSMCLKremainactive.MCLKisdisabled. • Low-powermode1(LPM1) – CPUisdisabledACLKandSMCLKremainactive.MCLKisdisabled. – DCOdc-generatorisdisabledifDCOnotusedinactivemode. • Low-powermode2(LPM2) – CPUisdisabled. – MCLKandSMCLKaredisabled. – DCOdc-generatorremainsenabled. – ACLKremainsactive. • Low-powermode3(LPM3) – CPUisdisabled. – MCLKandSMCLKaredisabled. – DCOdc-generatorisdisabled. – ACLKremainsactive. • Low-powermode4(LPM4) – CPUisdisabled. – ACLKisdisabled. – MCLKandSMCLKaredisabled. – DCOdc-generatorisdisabled. – Crystaloscillatorisstopped. Copyright©2006–2011,TexasInstrumentsIncorporated 9

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range of 0xFFFF to 0xFFC0. Thevectorcontainsthe16-bitaddressoftheappropriateinterrupthandlerinstructionsequence. If the reset vector (located at address 0xFFFE) contains 0xFFFF (for example, if flash is not programmed), the CPUgoesintoLPM4immediatelyafterpowerup. Table6.InterruptVectorAddresses SYSTEM INTERRUPTSOURCE INTERRUPTFLAG WORDADDRESS PRIORITY INTERRUPT Power-up PORIFG ExternalReset RSTIFG Watchdog WDTIFG Reset 0xFFFE 31,highest Flashkeyviolation KEYV PCoutofrange(1) (2) NMI NMIIFG (non)–maskable OscillatorFault OFIFG (non)–maskable 0xFFFC 30 Flashmemoryaccessviolation ACCVIFG(2)(3) (non)–maskable Timer_B3 TBCCR0CCIFG(4) maskable 0xFFFA 29 TBCCR1andTBCCR2, Timer_B3 CCIFGs,TBIFG(2)(4) maskable 0xFFF8 28 Comparator_A+ CAIFG maskable 0xFFF6 27 Watchdogtimer WDTIFG maskable 0xFFF4 26 Timer_A3 TACCR0CCIFG(4) maskable 0xFFF2 25 TACCR1CCIFG, Timer_A3 TACCR2CCIFG, maskable 0xFFF0 24 TAIFG(2)(4) USCI_A0/USCI_B0Receive UCA0RXIFG, USCI_B0I2CStatus UCB0RXIFG(2)(5) maskable 0xFFEE 23 USCI_A0/USCI_B0Transmit UCA0TXIFG, USCI_B0I2CReceive/Transmit UCB0TXIFG(2)(6) maskable 0xFFEC 22 0xFFEA 21 0xFFE8 20 I/OportP2(eightflags) P2IFG.0toP2IFG.7(2)(3) maskable 0xFFE6 19 I/OportP1(eightflags) P1IFG.0toP1IFG.7(2)(3) maskable 0xFFE4 18 0xFFE2 17 0xFFE0 16 See (7) 0xFFDE 15 See (8) 0xFFDCto0xFFC0 14to0,lowest (1) AresetisgeneratediftheCPUtriestofetchinstructionsfromwithinthemoduleregistermemoryaddressrange(0x0000to0x01FF)or fromwithinunusedaddressrange. (2) Multiplesourceflags (3) (non)-maskable:theindividualinterrupt-enablebitcandisableaninterruptevent,butthegeneralinterruptenablecannot. Nonmaskable:neithertheindividualnorthegeneralinterrupt-enablebitwilldisableaninterruptevent. (4) Interruptflagsarelocatedinthemodule. (5) InSPImode:UCB0RXIFG.InI2Cmode:UCALIFG,UCNACKIFG,ICSTTIFG,UCSTPIFG (6) InUART/SPImode:UCB0TXIFG.InI2Cmode:UCB0RXIFG,UCB0TXIFG (7) Thislocationisusedasbootstraploadersecuritykey(BSLSKEY). A0xAA55atthislocationdisablestheBSLcompletely. Azero(0x0)disablestheerasureoftheflashifaninvalidpasswordissupplied. (8) Theinterruptvectorsataddresses0xFFDCto0xFFC0arenotusedinthisdeviceandcanbeusedforregularprogramcodeif necessary. 10 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Special Function Registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided withthisarrangement. Legend rw Bitcanbereadandwritten. rw-0,1 Bitcanbereadandwritten.ItisResetorSetbyPUC. rw-(0),(1) Bitcanbereadandwritten.ItisResetorSetbyPOR. SFRbitisnotpresentindevice. Table7.InterruptEnable1 Address 7 6 5 4 3 2 1 0 00h ACCVIE NMIIE OFIE WDTIE rw-0 rw-0 rw-0 rw-0 WDTIE Watchdogtimerinterruptenable.Inactiveifwatchdogmodeisselected.Activeifwatchdogtimerisconfiguredininterval timermode. OFIE Oscillatorfaultinterruptenable NMIIE (Non)maskableinterruptenable ACCVIE Flashaccessviolationinterruptenable Table8.InterruptEnable2 Address 7 6 5 4 3 2 1 0 01h UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw-0 rw-0 rw-0 rw-0 UCA0RXIE USCI_A0receive-interruptenable UCA0TXIE USCI_A0transmit-interruptenable UCB0RXIE USCI_B0receive-interruptenable UCB0TXIE USCI_B0transmit-interruptenable Table9.InterruptFlagRegister1 Address 7 6 5 4 3 2 1 0 02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw-0 rw-(0) rw-(1) rw-1 rw-(0) WDTIFG Setonwatchdogtimeroverflow(inwatchdogmode)orsecuritykeyviolation. ResetonV power-uporaresetconditionatRST/NMIpininresetmode. CC OFIFG Flagsetonoscillatorfault RSTIFG Externalresetinterruptflag.SetonaresetconditionatRST/NMIpininresetmode.ResetonV powerup. CC PORIFG Power-onresetinterruptflag.SetonV powerup. CC NMIIFG SetviaRST/NMIpin Table10.InterruptFlagRegister2 Address 7 6 5 4 3 2 1 0 03h UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG rw-0 rw-0 rw-0 rw-0 UCA0RXIFG USCI_A0receive-interruptflag UCA0TXIFG USCI_A0transmit-interruptflag UCB0RXIFG USCI_B0receive-interruptflag UCB0TXIFG USCI_B0transmit-interruptflag Copyright©2006–2011,TexasInstrumentsIncorporated 11

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Memory Organization Table11.MemoryOrganization MSP430F2330 MSP430F2350 MSP430F2370 Memory Size 8KBFlash 16KBFlash 32KB Main:interruptvector Flash 0xFFFF-0xFFC0 0xFFFF-0xFFC0 0xFFFF-0xFFC0 Main:codememory Flash 0xFFFF-0xE000 0xFFFF-0xC000 0xFFFF-0x8000 Informationmemory Size 256Byte 256Byte 256Byte Flash 0x10FF-0x1000 0x10FF-0x1000 0x10FF-0x1000 Bootmemory Size 1KB 1KB 1KB ROM 0x0FFF-0x0C00 0x0FFF-0x0C00 0x0FFF-0x0C00 RAM Size 1KB 2KB 2KB 0x5FF-0x0200 0x9FF-0x0200 0x09FF-0x0200 Peripherals 16–bit 0x01FF-0x0100 0x01FF-0x0100 0x01FF-0x0100 8–bit 0x00FF-0x0010 0x00FF-0x0010 0x00FF-0x0010 8–bitSFR 0x000F-0x0000 0x000F-0x0000 0x000F-0x0000 Bootstrap Loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap LoaderUser’sGuide,literaturenumberSLAU319. Table12.BSLFunctionPins BSLFUNCTION YFFPACKAGEPINS RHAPACKAGEPINS Datatransmit C4-P1.1 5-P1.1 Datareceive C6-P2.2 14-P2.2 Flash Memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPUcanperformsingle-byteandsingle-wordwritestotheflashmemory.Featuresoftheflashmemoryinclude: • Flash memory has n segments of main memory and four segments of information memory (A to D) of 64byteseach.Eachsegmentinmainmemoryis512bytesinsize. • Segments0tonmaybeerasedinonestep,oreachsegmentmaybeindividuallyerased. • SegmentsAtoDcanbeerasedindividually,orasagroupwithsegments0ton. SegmentsAtoDarealsocalledinformationmemory. • Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is required. 12 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions.Forcompletemoduledescriptions,seetheMSP430x2xxFamilyUser'sGuide(SLAU144). Oscillator and System Clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator,aninternalvery-low-powerlow-frequencyoscillator,aninternaldigitally-controlledoscillator(DCO),and a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in lessthan1µs.Thebasicclockmoduleprovidesthefollowingclocksignals: • Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or the internal very-low-powerLFoscillator. • Mainclock(MCLK),thesystemclockusedbytheCPU. • Sub-Mainclock(SMCLK),thesub-systemclockusedbytheperipheralmodules. TheDCOsettingstocalibratetheDCOoutputfrequencyarestoredintheinformationmemorysegmentA. Table13.DCOCalibrationData,ProvidedFromFactoryInFlashInfoMemory SegmentA DCOFREQUENCY CALIBRATIONREGISTER SIZE ADDRESS CALBC1_1MHZ byte 0x10FF 1MHz CALBC0_1MHZ byte 0x10FE CALBC1_8MHZ byte 0x10FD 8MHz CALBC0_8MHZ byte 0x10FC CALBC1_12MHZ byte 0x10FB 12MHz CALBC0_12MHZ byte 0x10FA CALBC1_16MHZ byte 0x10F9 16MHz CALBC0_16MHZ byte 0x10F8 Brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and poweroff. Digital I/O Therearefour8-bitI/Oportsimplemented—portsP1,P2,P3,andP4: • AllindividualI/Obitsareindependentlyprogrammable. • Anycombinationofinput,output,andinterruptconditionispossible. • Edge-selectableinterruptinputcapabilityforalleightbitsofportP1andP2. • Read/writeaccesstoport-controlregistersissupportedbyallinstructions. • EachI/Ohasanindividuallyprogrammablepullup/pulldownresistor. The MSP430F23x0 devices provide 32 total port I/O pins available externally. See the device pinout for more information. Watchdog Timer (WDT+) The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selectedtimeintervals. Copyright©2006–2011,TexasInstrumentsIncorporated 13

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Hardware Multiplier The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16, 16×8, 8×16, and 8×8 bit operations. The module is capable of supporting signed and unsignedmultiplication as well as signed and unsignedmultiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required. Comparator_A+ The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions, battery-voltagesupervision,andmonitoringofexternalanalogsignals. Timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table14.Timer_A3SignalConnections INPUTPINNUMBER MODULE OUTPUTPINNUMBER DEVICEINPUT MODULE MODULE OUTPUT YFF RHA SIGNAL INPUTNAME BLOCK SIGNAL YFF RHA B4–P1.0 4–P1.0 TACLK TACLK ACLK ACLK Timer NA SMCLK SMCLK C7–P2.1 13–P2.1 TAINCLK INCLK C4–P1.1 5–P1.1 TA0 CCI0A C4–P1.1 5–P1.1 C6–P2.2 14–P2.2 TA0 CCI0B B6–P1.5 9-P1.5 CCR0 TA0 V GND SS V V CC CC A5–P1.2 6–P1.2 TA1 CCI1A A5–P1.2 6–P1.2 CAOUT CCI1B A7–P1.6 10–P1.6 (internal) CCR1 TA1 V GND D7–P2.3 15–P2.3 SS V V CC CC B5–P1.3 7–P1.3 TA2 CCI2A B5–P1.3 7–P1.3 ACLK(internal) CCI2B B7–P1.7 11–P1.7 CCR2 TA2 V GND D6–P2.4 16–P2.4 SS V V CC CC 14 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Timer_B3 Timer_B3 is a 16–bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table15.Timer_B3SignalConnections INPUTPINNUMBER MODULE OUTPUTPINNUMBER DEVICEINPUT MODULE MODULE OUTPUT YFF RHA SIGNAL INPUTNAME BLOCK SIGNAL YFF RHA E2–P4.7 33–P4.7 TBCLK TACLK ACLK ACLK Timer NA SMCLK SMCLK TBCLK INCLK F4–P4.0 26–P4.0 TB0 CCI0A F4–P4.0 26–P4.0 F3–P4.3 29–P4.3 TB0 CCI0B F3–P4.3 29–P4.3 CCR0 TB0 V GND SS V V CC CC G3–P4.1 27–P4.1 TA1 CCI1A G3–P4.1 27–P4.1 G1-P4.4 30-P4.4 TB1 CCI1B G1–P4.4 30–P4.4 CCR1 TB1 V GND SS V V CC CC G2–P4.2 28–P4.2 TB2 CCI2A G2–P4.2 28–P4.2 ACLK(internal) CCI2B F1–P4.5 31–P4.5 CCR2 TB2 V GND SS V V CC CC Universal Serial Communications Interface (USCI) The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols such as UART, enhancedUARTwithautomaticbaudratedetection(LIN),andIrDA. USCI_A0providessupportforSPI(3or4pin),UART,enhancedUART,andIrDA. USCI_B0providessupportforSPI(3or4pin)andI2C. Copyright©2006–2011,TexasInstrumentsIncorporated 15

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Peripheral File Map Table16.PeripheralsWithWordAccess ADDRESS MODULE REGISTERNAME SHORTNAME OFFSET Timer_B3 Capture/compareregister TBCCR2 0x0196 Capture/compareregister TBCCR1 0x0194 Capture/compareregister TBCCR0 0x0192 Timer_Bregister TBR 0x0190 Capture/comparecontrol TBCCTL2 0x0186 Capture/comparecontrol TBCCTL1 0x0184 Capture/comparecontrol TBCCTL0 0x0182 Timer_Bcontrol TBCTL 0x0180 Timer_Binterruptvector TBIV 0x011E Timer_A3 Capture/compareregister TACCR2 0x0176 Capture/compareregister TACCR1 0x0174 Capture/compareregister TACCR0 0x0172 Timer_Aregister TAR 0x0170 Capture/comparecontrol TACCTL2 0x0166 Capture/comparecontrol TACCTL1 0x0164 Capture/comparecontrol TACCTL0 0x0162 Timer_Acontrol TACTL 0x0160 Timer_Ainterruptvector TAIV 0x012E FlashMemory Flashcontrol3 FCTL3 0x012C Flashcontrol2 FCTL2 0x012A Flashcontrol1 FCTL1 0x0128 HardwareMultiplier Sumextend SUMEXT 0x013E Resulthighword RESHI 0x013C Resultlowword RESLO 0x013A Secondoperand OP2 0x0138 Multiplysigned+accumulate/operand1 MACS 0x0136 Multiply+accumulate/operand1 MAC 0x0134 Multiplysigned/operand1 MPYS 0x0132 Multiplyunsigned/operand1 MPY 0x0130 WatchdogTimer+ Watchdog/timercontrol WDTCTL 0x0120 Table17.PeripheralsWithByteAccess ADDRESS MODULE REGISTERNAME SHORTNAME OFFSET USCI_B0 USCI_B0transmitbuffer UCB0TXBUF 0x06F USCI_B0receivebuffer UCB0RXBUF 0x06E USCI_B0status UCB0STAT 0x06D USCI_B0bitratecontrol1 UCB0BR1 0x06B USCI_B0bitratecontrol0 UCB0BR0 0x06A USCI_B0control1 UCB0CTL1 0x069 USCI_B0control0 UCB0CTL0 0x068 USCI_B0I2Cslaveaddress UCB0SA 0x011A USCI_B0I2Cownaddress UCB0OA 0x0118 16 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Table17.PeripheralsWithByteAccess(continued) ADDRESS MODULE REGISTERNAME SHORTNAME OFFSET USCI_A0 USCI_A0transmitbuffer UCA0TXBUF 0x0067 USCI_A0receivebuffer UCA0RXBUF 0x0066 USCI_A0status UCA0STAT 0x0065 USCI_A0modulationcontrol UCA0MCTL 0x0064 USCI_A0baudratecontrol1 UCA0BR1 0x0063 USCI_A0baudratecontrol0 UCA0BR0 0x0062 USCI_A0control1 UCA0CTL1 0x0061 USCI_A0control0 UCA0CTL0 0x0060 USCI_A0IrDAreceivecontrol UCA0IRRCTL 0x005F USCI_A0IrDAtransmitcontrol UCA0IRTCTL 0x005E USCI_A0autobaudratecontrol UCA0ABCTL 0x005D BasicClockSystem+ Basicclocksystemcontrol3 BCSCTL3 0x0053 Basicclocksystemcontrol2 BCSCTL2 0x0058 Basicclocksystemcontrol1 BCSCTL1 0x0057 DCOclockfrequencycontrol DCOCTL 0x0056 PortP4 PortP4resistorenable P4REN 0x0011 PortP4selection P4SEL 0x001F PortP4direction P4DIR 0x001E PortP4output P4OUT 0x001D PortP4input P4IN 0x001C PortP3 PortP3resistorenable P3REN 0x0010 PortP3selection P3SEL 0x001B PortP3direction P3DIR 0x001A PortP3output P3OUT 0x0019 PortP3input P3IN 0x0018 PortP2 PortP2resistorenable P2REN 0x002F PortP2selection P2SEL 0x002E PortP2interruptenable P2IE 0x002D PortP2interruptedgeselect P2IES 0x002C PortP2interruptflag P2IFG 0x002B PortP2direction P2DIR 0x002A PortP2output P2OUT 0x0029 PortP2input P2IN 0x0028 PortP1 PortP1resistorenable P1REN 0x0027 PortP1selection P1SEL 0x0026 PortP1interruptenable P1IE 0x0025 PortP1interruptedgeselect P1IES 0x0024 PortP1interruptflag P1IFG 0x0023 PortP1direction P1DIR 0x0022 PortP1output P1OUT 0x0021 PortP1input P1IN 0x0020 SpecialFunction SFRinterruptflag2 IFG2 0x0003 SFRinterruptflag1 IFG1 0x0002 SFRinterruptenable2 IE2 0x0001 SFRinterruptenable1 IE1 0x0000 Copyright©2006–2011,TexasInstrumentsIncorporated 17

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Absolute Maximum Ratings(1) VoltageappliedatV toV -0.3Vto4.1V CC SS Voltageappliedtoanypin (2) -0.3Vto(V +0.3V) CC Diodecurrentatanydeviceterminal ±2mA Unprogrammeddevice -55°Cto150°C Storagetemperature,T (3) stg Programmeddevice -55°Cto150°C (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesreferencedtoV .TheJTAGfuse-blowvoltage,V ,isallowedtoexceedtheabsolutemaximumrating.Thevoltageis SS FB appliedtotheTESTpinwhenblowingtheJTAGfuse. (3) HighertemperaturemaybeappliedduringboardsolderingprocessaccordingtothecurrentJEDECJ-STD-020specificationwithpeak reflowtemperaturesnothigherthanclassifiedonthedevicelabelontheshippingboxesorreels. Recommended Operating Conditions(1) MIN MAX UNIT Duringprogramexecution 1.8 3.6 V Supplyvoltage(2),AV =DV =V V CC CC CC CC Duringflashmemoryprogramming 2.2 3.6 V Supplyvoltage,AV =DV =V 0 0 V SS SS SS SS Iversion -40 85 T Operatingfree-airtemperature °C A Tversion -40 105 V =1.8V,Dutycycle=50%±10% dc 4.15 CC Processorfrequency(maximumMCLKfrequency)(1)(3) f V =2.7V,Dutycycle=50%±10% dc 12 MHz SYSTEM (seeFigure1) CC V ≥3.3V,Dutycycle=50%±10% dc 16 CC (1) Modulesmighthaveadifferentmaximuminputclockspecification.Seethespecificationoftherespectivemoduleinthisdatasheet. (2) ItisrecommendedtopowerAV andDV fromthesamesource.Amaximumdifferenceof0.3VbetweenAV andDV canbe CC CC CC CC toleratedduringpower-up. (3) TheMSP430CPUisclockeddirectlywithMCLK.BoththehighandlowphaseofMCLKmustnotexceedthepulsewidthofthe specifiedmaximumfrequency. Legend: 16MHz Supply voltage range during flash memory z H programming M − 12MHz y c n Supply voltage range e u during program execution q e Fr 7.5MHz m e st y S 4.15MHz 1.8V 2.2V 2.7V 3.3V 3.6V Supply Voltage−V NOTE: Minimumprocessorfrequencyisdefinedbysystemclock.FlashprogramoreraseoperationsrequireaminimumV CC of2.2V. Figure1. OperatingArea 18 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Active Mode Supply Current (Into DV + AV ) Excluding External Current CC CC overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1)(2) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC f =f =f =1MHz, 2.2V 270 370 DCO MCLK SMCLK f =32768Hz, ACLK Programexecutesinflash, Activemode(AM) I BCSCTL1=CALBC1_1MHZ, µA AM,1MHz current(1MHz) DCOCTL=CALDCO_1MHZ, 3V 390 550 CPUOFF=0,SCG0=0,SCG1=0, OSCOFF=0 f =f =f =1MHz, 2.2V 226 DCO MCLK SMCLK f =32768Hz, ACLK ProgramexecutesinRAM, Activemode(AM) I BCSCTL1=CALBC1_1MHZ, µA AM,1MHz current(1MHz) DCOCTL=CALDCO_1MHZ, 3V 318 CPUOFF=0,SCG0=0,SCG1=0, OSCOFF=0 f =f =f =32768Hz/8 -40°Cto85°C 2 6 MCLK SMCLK ACLK =4096Hz, 2.2V 105°C 14 f =0Hz, DCO Activemode(AM) Programexecutesinflash, -40°Cto85°C 3 9 I µA AM,4kHz current(4kHz) SELMx=11,SELS=1, DIVMx=DIVSx=DIVAx=11, 3V CPUOFF=0,SCG0=1,SCG1=0, 105°C 17 OSCOFF=0 f =f =f ≈100kHz, -40°Cto85°C 60 85 MCLK SMCLK DCO(0,0) 2.2V Activemode(AM) fACLK=0Hz, 105°C 95 I Programexecutesinflash, µA AM,100kHz current(100kHz) RSELx=0,DCOx=0,CPUOFF=0, -40°Cto85°C 72 95 3V SCG0=0,SCG1=0,OSCOFF=1 105°C 105 (1) Allinputsaretiedto0VorV .Outputsdonotsourceorsinkanycurrent. CC (2) ThecurrentsarecharacterizedwithaMicroCrystalCC4V-T1ASMDcrystalwithaloadcapacitanceof9pF.Theinternalandexternal loadcapacitanceischosentocloselymatchtherequired9pF. Typical Characteristics - Active-Mode Supply Current (Into DV + AV ) CC CC ACTIVE-MODECURRENT vs ACTIVE-MODECURRENT SUPPLYVOLTAGE vs T =25°C DCOFREQUENCY A 8.0 5.0 fDCO= 16 MHz 7.0 TA= 85°C 4.0 A 6.0 A TA= 25°C −m fDCO= 12 MHz −m Mode Current 45..00 fDCO= 8 MHz Mode Current 23..00 VCC= 3 V TA= 85°C Active 23..00 Active TA= 25°C 1.0 1.0 fDCO= 1 MHz VCC= 2.2 V 0.0 0.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 4.0 8.0 12.0 16.0 VCC−Supply Voltage−V fDCO−DCO Frequency−MHz Figure2. Figure3. Copyright©2006–2011,TexasInstrumentsIncorporated 19

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Low-Power-Mode Supply Currents (Into V ) Excluding External Current (1)(2) CC overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC f =0MHz, -40°Cto85°C 68 84 MCLK f =f =1MHz, 2.2V SMCLK DCO 105°C 90 f =32768Hz, Low-powermode0 ACLK ILPM0,1MHz (LPM0)current(3) BCSCTL1=CALBC1_1MHZ, -40°Cto85°C 88 110 µA DCOCTL=CALDCO_1MHZ, 3V CPUOFF=1,SCG0=0,SCG1=0, 105°C 115 OSCOFF=0 f =0MHz, -40°Cto85°C 36 45 MCLK f =f (0,0)≈100kHz, 2.2V SMCLK DCO 105°C 50 Low-powermode0 f =0Hz, ILPM0,100kHz (LPM0)current(3) RASCLEKLx=0,DCOx=0, -40°Cto85°C 40 50 µA CPUOFF=1,SCG0=0,SCG1=0, 3V OSCOFF=1 105°C 54 f =f =0MHz, -40°Cto85°C 20 28 MCLK SMCLK f =1MHz, 2.2V DCO 105°C 32 f =32768Hz, Low-powermode2 ACLK ILPM2 (LPM2)current(4) BCSCTL1=CALBC1_1MHZ, -40°Cto85°C 23 32 µA DCOCTL=CALDCO_1MHZ, 3V CPUOFF=1,SCG0=0,SCG1=1, 105°C 37 OSCOFF=0 -40°Cto25°C 0.7 1 85°C 2.2V 3.3 f =f =f =0MHz, DCO MCLK SMCLK Low-powermode3 f =32768Hz, 105°C 10 ILPM3,LFXT1 (LPM3)current(4) CAPCLUKOFF=1,SCG0=1,SCG1=1, -40°Cto25°C 0.85 1.2 µA OSCOFF=0 85°C 3V 3.8 105°C 12 -40°Cto25°C 0.25 0.8 f =f =f =0MHz, 85°C 2.2V 2.9 DCO MCLK SMCLK Low-powermode3 fACLKfrominternalLFoscillator 105°C 9 ILPM3,VLO current,(LPM3)(4) (CVPLUOO),FF=1,SCG0=1,SCG1=1, -40°Cto25°C 0.35 1 µA OSCOFF=0 85°C 3V 3.5 105°C 11 -40°C 0.5 25°C 0.5 2.2V 85°C 1.7 2.7 f =f =f =0MHz, DCO MCLK SMCLK Low-powermode4 f =0Hz, 105°C 8.6 ILPM4 (LPM4)current(5) CAPCLUKOFF=1,SCG0=1,SCG1=1, -40°C 0.5 µA OSCOFF=1 25°C 0.5 3V 85°C 1.9 3 105°C 9 (1) Allinputsaretiedto0VorV .Outputsdonotsourceorsinkanycurrent. CC (2) ThecurrentsarecharacterizedwithaMicroCrystalCC4V-T1ASMDcrystalwithaloadcapacitanceof9pF.Theinternalandexternal loadcapacitanceischosentocloselymatchtherequired9pF. (3) CurrentforbrownoutandWDTclockedbySMCLKincluded. (4) CurrentforbrownoutandWDTclockedbyACLKincluded. (5) Currentforbrownoutincluded. 20 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, JTAG, RST/NMI, XIN(1)) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 0.45V 0.75V CC CC V Positive-goinginputthresholdvoltage 2.2V 1 1.65 V IT+ 3V 1.35 2.25 0.25V 0.55V CC CC V Negative-goinginputthresholdvoltage 2.2V 0.55 1.20 V IT- 3V 0.75 1.65 2.2V 0.2 1 V Inputvoltagehysteresis(V -V ) V hys IT+ IT- 3V 0.3 1 Forpullup:V =V , R Pullup/pulldownresistor IN SS 20 35 50 kΩ Pull Forpulldown:V =V IN CC C Inputcapacitance V =V orV 5 pF I IN SS CC (1) XINonlyinbypassmode Inputs (Ports P1, P2) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC PortP1,P2:P1.xtoP2.x,Externaltrigger t(int) Externalinterrupttiming pulsewidthtosetinterruptflag(1) 2.2V/3V 20 ns (1) Anexternalsignalsetstheinterruptflageverytimetheminimuminterruptpulsewidtht ismet.Itmaybesetwithtriggersignals (int) shorterthant . (int) Leakage Current (Ports P1, P2, P3, P4) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC I High-impedanceleakagecurrent (1) (2) 2.2V/3V ±50 nA lkg(Px.y) (1) TheleakagecurrentismeasuredwithV orV appliedtothecorrespondingpin(s),unlessotherwisenoted. SS CC (2) Theleakageofthedigitalportpinsismeasuredindividually.Theportpinisselectedforinputandthepullup/pulldownresistoris disabled. Copyright©2006–2011,TexasInstrumentsIncorporated 21

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Outputs (Ports P1, P2, P3, P4) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC I =-1.5mA (1) V -0.25 V OH(max) CC CC 2.2V I =-6mA (2) V -0.6 V OH(max) CC CC V High-leveloutputvoltage V OH I =-1.5mA(1) V -0.25 V OH(max) CC CC 3V I =-6mA(2) V -0.6 V OH(max) CC CC I =1.5mA(1) V V +0.25 OL(max) SS SS 2.2V I =6mA(2) V V +0.6 OL(max) SS SS V Low-leveloutputvoltage V OL I =1.5mA(1) V V +0.25 OL(max) SS SS 3V I =6mA(2) V V +0.6 OL(max) SS SS (1) Themaximumtotalcurrent,I andI ,foralloutputscombined,shouldnotexceed±12mAtoholdthemaximumvoltagedrop OH(max) OL(max) specified. (2) Themaximumtotalcurrent,I andI ,foralloutputscombined,shouldnotexceed±48mAtoholdthemaximumvoltagedrop OH(max) OL(max) specified. Output Frequency (Ports P1, P2, P3, P4) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 2.2V 7.5 f Portoutputfrequency(withload) P1.4/SMCLK,C =20pF,R =1kΩ(1)(2) MHz Px.y L L 3V 12 2.2V 7.5 f Clockoutputfrequency P2.0/ACLK,P1.4/SMCLK,C =20pF(2) MHz Port°CLK L 3V 16 (1) Aresistivedividerwithtwo0.5-kΩresistorsbetweenV andV isusedasload.Theoutputisconnectedtothecentertapofthe CC SS divider. (2) Theoutputvoltagereachesatleast10%and90%V atthespecifiedtogglefrequency. CC 22 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Typical Characteristics - Outputs Oneoutputloadedatatime. TYPICALLOW-LEVELOUTPUTCURRENT TYPICALLOW-LEVELOUTPUTCURRENT vs vs LOW-LEVELOUTPUTVOLTAGE LOW-LEVELOUTPUTVOLTAGE 25.0 50.0 VCC= 2.2 V TA= 25°C VCC= 3 V mA P2.4 mA P2.4 TA= 25°C nt− 20.0 TA= 85°C nt− 40.0 e e Curr Curr TA= 85°C put 15.0 put 30.0 ut ut O O el el ev ev w-L 10.0 w-L 20.0 o o L L al al Typic 5.0 Typic 10.0 − − OL OL I I 0.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOL−Low-Level Output Voltage−V VOL−Low-Level Output Voltage−V Figure4. Figure5. TYPICALHIGH-LEVELOUTPUTCURRENT TYPICALHIGH-LEVELOUTPUTCURRENT vs vs HIGH-LEVELOUTPUTVOLTAGE HIGH-LEVELOUTPUTVOLTAGE 0.0 0.0 A VCC= 2.2 V A VCC= 3 V m P2.4 m P2.4 − − Current −5.0 Current −10.0 Output −10.0 Output −20.0 High-Level −15.0 High-Level −30.0 Typical −20.0 Typical −40.0 TA= 85°C −H TA= 85°C −H O O I −25.0 TA= 25°C I −50.0 TA= 25°C 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH−High-Level Output Voltage−V VOH−High-Level Output Voltage−V Figure6. Figure7. Copyright©2006–2011,TexasInstrumentsIncorporated 23

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com POR/Brownout Reset (BOR)(1)(2) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 0.7× V SeeFigure8 dV /dt≤3V/s V CC(start) CC V (B_IT-) V SeeFigure8throughFigure10 dV /dt≤3V/s 1.71 V (B_IT-) CC V SeeFigure8 dV /dt≤3V/s 70 130 210 mV hys(B_IT-) CC t SeeFigure8 2000 µs d(BOR) PulselengthneededatRST/NMIpin t 2.2V/3V 2 µs (reset) toacceptedresetinternally (1) ThecurrentconsumptionofthebrownoutmoduleisalreadyincludedintheI currentconsumptiondata.Thevoltagelevel CC V +V is≤1.8V. (B_IT-) hys(B_IT-) (2) Duringpowerup,theCPUbeginscodeexecutionfollowingaperiodoft afterV =V +V .ThedefaultDCOsettings d(BOR) CC (B_IT-) hys(B_IT-) mustnotbechangeduntilV ≥V ,whereV istheminimumsupplyvoltageforthedesiredoperatingfrequency. CC CC(min) CC(min) V CC V hys(B_IT−) V (B_IT−) VCC(start) 1 0 td(BOR) Figure8. POR/BrownoutReset(BOR)vsSupplyVoltage 24 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Typical Characteristics - POR/Brownout Reset (BOR) 2 VCC tpw 3 V VCC= 3 V Typical Conditions V 1.5 − p) dro 1 C( C VCC(drop) V 0.5 0 0.001 1 1000 1 ns 1 ns tpw−Pulse Width− µs tpw−Pulse Width− µs Figure9.V LevelWithaSquareVoltageDroptoGenerateaPOR/BrownoutSignal CC(drop) VCC tpw 2 3 V VCC= 3 V V 1.5 Typical Conditions − p) o dr 1 C( C VCC(drop) V 0.5 tf=tr 0 0.001 1 1000 tf tr tpw−Pulse Width− µs tpw−Pulse Width− µs Figure10.V LevelWithaTriangleVoltageDroptoGenerateaPOR/BrownoutSignal CC(drop) Copyright©2006–2011,TexasInstrumentsIncorporated 25

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Main DCO Characteristics • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlapsRSELx=15. • DCOcontrolbitsDCOxhaveastepsizeasdefinedbyparameterS . DCO • Modulation control bits MODx select how often f is used within the period of 32 DCOCLK DCO(RSEL,DCO+1) cycles.Thefrequencyf isusedfortheremainingcycles.Thefrequencyisanaverageequalto: DCO(RSEL,DCO) 32×fDCO(RSEL,DCO) ×fDCO(RSEL,DCO+1) faverage = MOD×fDCO(RSEL,DCO) +(32–MOD)×fDCO(RSEL,DCO+1) DCO Frequency overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC RSELx<14 1.8 3.6 V Supplyvoltagerange RSELx=14 2.2 3.6 V CC RSELx=15 3.0 3.6 f DCOfrequency(0,0) RSELx=0,DCOx=0,MODx=0 2.2V/3V 0.06 0.14 MHz DCO(0,0) f DCOfrequency(0,3) RSELx=0,DCOx=3,MODx=0 2.2V/3V 0.07 0.17 MHz DCO(0,3) f DCOfrequency(1,3) RSELx=1,DCOx=3,MODx=0 2.2V/3V 0.10 0.20 MHz DCO(1,3) f DCOfrequency(2,3) RSELx=2,DCOx=3,MODx=0 2.2V/3V 0.14 0.28 MHz DCO(2,3) f DCOfrequency(3,3) RSELx=3,DCOx=3,MODx=0 2.2V/3V 0.20 0.40 MHz DCO(3,3) f DCOfrequency(4,3) RSELx=4,DCOx=3,MODx=0 2.2V/3V 0.28 0.54 MHz DCO(4,3) f DCOfrequency(5,3) RSELx=5,DCOx=3,MODx=0 2.2V/3V 0.39 0.77 MHz DCO(5,3) f DCOfrequency(6,3) RSELx=6,DCOx=3,MODx=0 2.2V/3V 0.54 1.06 MHz DCO(6,3) f DCOfrequency(7,3) RSELx=7,DCOx=3,MODx=0 2.2V/3V 0.80 1.50 MHz DCO(7,3) f DCOfrequency(8,3) RSELx=8,DCOx=3,MODx=0 2.2V/3V 1.10 2.10 MHz DCO(8,3) f DCOfrequency(9,3) RSELx=9,DCOx=3,MODx=0 2.2V/3V 1.60 3.00 MHz DCO(9,3) f DCOfrequency(10,3) RSELx=10,DCOx=3,MODx=0 2.2V/3V 2.50 4.30 MHz DCO(10,3) f DCOfrequency(11,3) RSELx=11,DCOx=3,MODx=0 2.2V/3V 3.00 5.50 MHz DCO(11,3) f DCOfrequency(12,3) RSELx=12,DCOx=3,MODx=0 2.2V/3V 4.30 7.30 MHz DCO(12,3) f DCOfrequency(13,3) RSELx=13,DCOx=3,MODx=0 2.2V/3V 6.00 9.60 MHz DCO(13,3) f DCOfrequency(14,3) RSELx=14,DCOx=3,MODx=0 2.2V/3V 8.60 13.9 MHz DCO(14,3) f DCOfrequency(15,3) RSELx=15,DCOx=3,MODx=0 3V 12.0 18.5 MHz DCO(15,3) f DCOfrequency(15,7) RSELx=15,DCOx=7,MODx=0 3V 16.0 26.0 MHz DCO(15,7) Frequencystepbetween S S =f /f 2.2V/3V 1.55 ratio RSEL rangeRSELandRSEL+1 RSEL DCO(RSEL+1,DCO) DCO(RSEL,DCO) Frequencystepbetweentap S S =f /f 2.2V/3V 1.05 1.08 1.12 ratio DCO DCOandDCO+1 DCO DCO(RSEL,DCO+1) DCO(RSEL,DCO) Dutycycle MeasuredatP1.4/SMCLK 2.2V/3V 40 50 60 % 26 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Calibrated DCO Frequencies - Tolerance at Calibration overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC Frequencytoleranceatcalibration 25°C 3V -1 ±0.2 +1 % BCSCTL1=CALBC1_1MHZ, f 1-MHzcalibrationvalue DCOCTL=CALDCO_1MHZ, 25°C 3V 0.990 1 1.010 MHz CAL(1MHz) Gatingtime:5ms BCSCTL1=CALBC1_8MHZ, f 8-MHzcalibrationvalue DCOCTL=CALDCO_8MHZ, 25°C 3V 7.920 8 8.080 MHz CAL(8MHz) Gatingtime:5ms BCSCTL1=CALBC1_12MHZ, f 12-MHzcalibrationvalue DCOCTL=CALDCO_12MHZ, 25°C 3V 11.88 12 12.12 MHz CAL(12MHz) Gatingtime:5ms BCSCTL1=CALBC1_16MHZ, f 16-MHzcalibrationvalue DCOCTL=CALDCO_16MHZ, 25°C 3V 15.84 16 16.16 MHz CAL(16MHz) Gatingtime:2ms Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC 1-MHztoleranceover 0°Cto85°C 3V -2.5 ±0.5 +2.5 % temperature 8-MHztoleranceover 0°Cto85°C 3V -2.5 ±1 +2.5 % temperature 12-MHztoleranceover 0°Cto85°C 3V -2.5 ±1 +2.5 % temperature 16-MHztoleranceover 0°Cto85°C 3V -3 ±2 +3 % temperature 2.2V 0.97 1 1.03 BCSCTL1=CALBC1_1MHZ, f 1-MHzcalibrationvalue DCOCTL=CALDCO_1MHZ, 0°Cto85°C 3V 0.975 1 1.025 MHz CAL(1MHz) Gatingtime:5ms 3.6V 0.97 1 1.03 2.2V 7.76 8 8.4 BCSCTL1=CALBC1_8MHZ, f 8-MHzcalibrationvalue DCOCTL=CALDCO_8MHZ, 0°Cto85°C 3V 7.8 8 8.2 MHz CAL(8MHz) Gatingtime:5ms 3.6V 7.6 8 8.24 2.2V 11.64 12 12.36 BCSCTL1=CALBC1_12MHZ, f 12-MHzcalibrationvalue DCOCTL=CALDCO_12MHZ, 0°Cto85°C 3V 11.64 12 12.36 MHz CAL(12MHz) Gatingtime:5ms 3.6V 11.64 12 12.36 BCSCTL1=CALBC1_16MHZ, 3V 15.52 16 16.48 f 16-MHzcalibrationvalue DCOCTL=CALDCO_16MHZ, 0°Cto85°C MHz CAL(16MHz) Gatingtime:2ms 3.6V 15 16 16.48 Copyright©2006–2011,TexasInstrumentsIncorporated 27

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Calibrated DCO Frequencies - Tolerance Over Supply Voltage V CC overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC 1-MHztoleranceoverV 25°C 1.8Vto3.6V -3 ±2 +3 % CC 8-MHztoleranceoverV 25°C 1.8Vto3.6V -3 ±2 +3 % CC 12-MHztoleranceoverV 25°C 2.2Vto3.6V -3 ±2 +3 % CC 16-MHztoleranceoverV 25°C 3Vto3.6V -6 ±2 +3 % CC BCSCTL1=CALBC1_1MHZ, f 1-MHzcalibrationvalue DCOCTL=CALDCO_1MHZ, 25°C 1.8Vto3.6V 0.97 1 1.03 MHz CAL(1MHz) Gatingtime:5ms BCSCTL1=CALBC1_8MHZ, f 8-MHzcalibrationvalue DCOCTL=CALDCO_8MHZ, 25°C 1.8Vto3.6V 7.76 8 8.24 MHz CAL(8MHz) Gatingtime:5ms BCSCTL1=CALBC1_12MHZ, f 12-MHzcalibrationvalue DCOCTL=CALDCO_12MHZ, 25°C 2.2Vto3.6V 11.64 12 12.36 MHz CAL(12MHz) Gatingtime:5ms BCSCTL1=CALBC1_16MHZ, f 16-MHzcalibrationvalue DCOCTL=CALDCO_16MHZ, 25°C 3Vto3.6V 15 16 16.48 MHz CAL(16MHz) Gatingtime:2ms Calibrated DCO Frequencies - Overall Tolerance overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC 1-MHztolerance -40°Cto105°C 1.8Vto3.6V -5 ±2 +5 % overall 8-MHztolerance -40°Cto105°C 1.8Vto3.6V -5 ±2 +5 % overall 12-MHztolerance -40°Cto105°C 2.2Vto3.6V -5 ±2 +5 % overall 16-MHztolerance -40°Cto105°C 3Vto3.6V -6 ±3 +6 % overall BCSCTL1=CALBC1_1MHZ, 1-MHzcalibration f DCOCTL=CALDCO_1MHZ, -40°Cto105°C 1.8Vto3.6V 0.95 1 1.05 MHz CAL(1MHz) value Gatingtime:5ms BCSCTL1=CALBC1_8MHZ, 8-MHzcalibration f DCOCTL=CALDCO_8MHZ, -40°Cto105°C 1.8Vto3.6V 7.6 8 8.4 MHz CAL(8MHz) value Gatingtime:5ms BCSCTL1=CALBC1_12MHZ, 12-MHzcalibration f DCOCTL=CALDCO_12MHZ, -40°Cto105°C 2.2Vto3.6V 11.4 12 12.6 MHz CAL(12MHz) value Gatingtime:5ms BCSCTL1=CALBC1_16MHZ, 16-MHzcalibration f DCOCTL=CALDCO_16MHZ, -40°Cto105°C 3Vto3.6V 15 16 17 MHz CAL(16MHz) value Gatingtime:2ms 28 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Typical Characteristics - Calibrated 1-MHz DCO Frequency CALIBRATED1-MHzFREQUENCY vs SUPPLYVOLTAGE 1.03 1.02 z 1.01 TA= 105°C H M cy− 1.00 TA= 85°C n e qu TA= 25°C e Fr 0.99 TA=−40°C 0.98 0.97 1.5 2.0 2.5 3.0 3.5 4.0 VCC−Supply Voltage−V Figure11. Copyright©2006–2011,TexasInstrumentsIncorporated 29

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Wake-Up From Lower-Power Modes (LPM3/4) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC BCSCTL1=CALBC1_1MHZ, 2 DCOCTL=CALDCO_1MHZ BCSCTL1=CALBC1_8MHZ, 2.2V/3V 1.5 DCOclockwake-uptime DCOCTL=CALDCO_8MHZ tDCO,LPM3/4 fromLPM3/4(1) BCSCTL1=CALBC1_12MHZ, µs 1 DCOCTL=CALDCO_12MHZ BCSCTL1=CALBC1_16MHZ, 3V 1 DCOCTL=CALDCO_16MHZ CPUwake-uptimefrom 1/f + tCPU,LPM3/4 LPM3/4(2) t MCLK Clock,LPM3/4 (1) TheDCOclockwake-uptimeismeasuredfromtheedgeofanexternalwake-upsignal(forexample,aportinterrupt)tothefirstclock edgeobservableexternallyonaclockpin(MCLKorSMCLK). (2) ParameterapplicableonlyifDCOCLKisusedforMCLK. Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4 CLOCKWAKE-UPTIMEFROMLPM3 vs DCOFREQUENCY 10.00 s µ − e m Ti e ak RSELx = 0 to 11 W 1.00 RSELx = 12 to 15 O C D 0.10 0.10 1.00 10.00 DCO Frequency−MHz Figure12. 30 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 DCO With External Resistor R (1) OSC overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC DCOR=1, 2.2V 1.8 f DCOoutputfrequencywithR RSELx=4,DCOx=3,MODx=0, MHz DCO,ROSC OSC T =25°C 3V 1.95 A DCOR=1, D Temperaturedrift 2.2V/3V ±0.1 %/°C T RSELx=4,DCOx=3,MODx=0 DCOR=1, D DriftwithV 2.2V/3V 10 %/V V CC RSELx=4,DCOx=3,MODx=0 (1) R =100kΩ.Metalfilmresistor,type0257,0.6Wwith1%toleranceandT =±50ppm/°C. OSC K Typical Characteristics - DCO With External Resistor R OSC DCOFREQUENCY DCOFREQUENCY vs vs R R OSC OSC V =2.2V,T =25°C V =3V,T =25°C CC A CC A 10.00 10.00 z z H H M M − 1.00 − 1.00 y y c c n n e e u u q q Fre RSELx = 4 Fre RSELx = 4 O O C 0.10 C 0.10 D D 0.01 0.01 10.00 100.00 1000.00 10000.00 10.00 100.00 1000.00 10000.00 ROSC−External Resistor−kW ROSC−External Resistor−kW Figure13. Figure14. DCOFREQUENCY DCOFREQUENCY vs vs TEMPERATURE SUPPLYVOLTAGE V =3V T =25°C CC A 2.50 2.50 2.25 2.25 ROSC= 100k ROSC= 100k 2.00 2.00 z z MH 1.75 MH 1.75 − − 1.50 1.50 y y c c n n e 1.25 e 1.25 u u q q O Fre 01..7050 ROSC= 270k O Fre 01..7050 ROSC= 270k C C D D 0.50 0.50 ROSC= 1M ROSC= 1M 0.25 0.25 0.00 0.00 −50 −25 0 25 50 75 100 2.0 2.5 3.0 3.5 4.0 TA−Temperature−°C VCC−Supply Voltage−V Figure15. Figure16. Copyright©2006–2011,TexasInstrumentsIncorporated 31

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Crystal Oscillator LFXT1, Low-Frequency Mode(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC LFXT1oscillatorcrystal f XTS=0,LFXT1Sx=0or1 1.8Vto3.6V 32768 Hz LFXT1,LF frequency,LFmode0,1 LFXT1oscillatorlogiclevel f squarewaveinputfrequency, XTS=0,XCAPx=0,LFXT1Sx=3 1.8Vto3.6V 10000 32768 50000 Hz LFXT1,LF,logic LFmode XTS=0,LFXT1Sx=0, 500 Oscillationallowancefor fLFXT1,LF=32768Hz,CL,eff=6pF OA kΩ LF LFcrystals XTS=0,LFXT1Sx=0, 200 f =32768Hz,C =12pF LFXT1,LF L,eff XTS=0,XCAPx=0 1 Integratedeffectiveload XTS=0,XCAPx=1 5.5 CL,eff capacitance,LFmode(2) XTS=0,XCAPx=2 8.5 pF XTS=0,XCAPx=3 11 XTS=0,MeasuredatP2.0/ACLK, Dutycycle,LFmode 2.2V/3V 30 50 70 % f =32768Hz LFXT1,LF fFault,LF OLFscmilloadtoer(3f)aultfrequency, XTS=0,XCAPx=0,LFXT1Sx=3(4) 2.2V/3V 10 10000 Hz (1) ToimproveEMIontheXT1oscillator,thefollowingguidelinesshouldbeobserved. (a)Keepthetracebetweenthedeviceandthecrystalasshortaspossible. (b)Designagoodgroundplanearoundtheoscillatorpins. (c)PreventcrosstalkfromotherclockordatalinesintooscillatorpinsXINandXOUT. (d)AvoidrunningPCBtracesunderneathoradjacenttotheXINandXOUTpins. (e)UseassemblymaterialsandpraxistoavoidanyparasiticloadontheoscillatorXINandXOUTpins. (f)Ifconformalcoatingisused,ensurethatitdoesnotinducecapacitive/resistiveleakagebetweentheoscillatorpins. (g)DonotroutetheXOUTlinetotheJTAGheadertosupporttheserialprogrammingadapterasshowninotherdocumentation.This signalisnolongerrequiredfortheserialprogrammingadapter. (2) Includesparasiticbondandpackagecapacitance(approximately2pFperpin). BecausethePCBaddsadditionalcapacitance,itisrecommendedtoverifythecorrectloadbymeasuringtheACLKfrequency.Fora correctsetup,theeffectiveloadcapacitanceshouldalwaysmatchthespecificationofthecrystalthatisused. (3) FrequenciesbelowtheMINspecificationsetthefaultflag.FrequenciesabovetheMAXspecificationdonotsetthefaultflag. Frequenciesinbetweenmightsettheflag. (4) Measuredwithlogic-levelinputfrequencybutalsoappliestooperationwithcrystals. Internal Very-Low-Power Low-Frequency Oscillator (VLO) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER V MIN TYP MAX UNIT CC f VLOfrequency 2.2V/3V 4 12 20 kHz VLO df /dT VLOfrequencytemperaturedrift(1) 2.2V/3V 0.5 %/°C VLO df /dV VLOfrequencysupplyvoltagedrift(2) 1.8Vto3.6V 4 %/V VLO CC (1) Calculatedusingtheboxmethod: Iversion:[MAX(-40...85°C)-MIN(-40...85°C)]/MIN(-40...85°C)/[85°C-(-40°C)] Tversion:[MAX(-40...105°C)-MIN(-40...105°C)]/MIN(-40...105°C)/[105°C-(-40°C)] (2) Calculatedusingtheboxmethod:[MAX(1.8...3.6V)-MIN(1.8...3.6V)]/MIN(1.8...3.6V)/(3.6V-1.8V) 32 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Crystal Oscillator LFXT1, High-Frequency Mode(1) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC LFXT1oscillatorcrystal f XTS=1,XCAPx=0,LFXT1Sx=0 1.8Vto3.6V 0.4 1 MHz LFXT1,HF0 frequency,HFmode0 LFXT1oscillatorcrystal f XTS=1,XCAPx=0,LFXT1Sx=1 1.8Vto3.6V 1 4 MHz LFXT1,HF1 frequency,HFmode1 1.8Vto3.6V 2 10 LFXT1oscillatorcrystal f XTS=1,XCAPx=0,LFXT1Sx=2 2.2Vto3.6V 2 12 MHz LFXT1,HF2 frequency,HFmode2 3Vto3.6V 2 16 1.8Vto3.6V 0.4 10 LFXT1oscillatorlogic-level f square-waveinput XTS=1,XCAPx=0,LFXT1Sx=3 2.2Vto3.6V 0.4 12 MHz LFXT1,HF,logic frequency,HFmode 3Vto3.6V 0.4 16 XTS=1,XCAPx=0,LFXT1Sx=0, 2700 f =1MHz,C =15pF LFXT1,HF L,eff OscillationallowanceforHF XTS=1,XCAPx=0,LFXT1Sx=1, OA crystals(seeFigure17and 800 Ω HF f =4MHz,C =15pF Figure18) LFXT1,HF L,eff XTS=1,XCAPx=0,LFXT1Sx=2, 300 f =16MHz,C =15pF LFXT1,HF L,eff CL,eff Icnatpeagcraittaendcee,ffHecFtivmeoldoea(d2) XTS=1,XCAPx=0(3) 1 pF XTS=1,XCAPx=0, MeasuredatP2.0/ACLK, 40 50 60 f =10MHz LFXT1,HF Dutycycle,HFmode 2.2V/3V % XTS=1,XCAPx=0, MeasuredatP2.0/ACLK, 40 50 60 f =16MHz LFXT1,HF f Oscillatorfaultfrequency (4) XTS=1,XCAPx=0,LFXT1Sx=3(5) 2.2V/3V 30 300 kHz Fault,HF (1) ToimproveEMIontheXT2oscillatorthefollowingguidelinesshouldbeobserved: (a)Keepthetracebetweenthedeviceandthecrystalasshortaspossible. (b)Designagoodgroundplanearoundtheoscillatorpins. (c)PreventcrosstalkfromotherclockordatalinesintooscillatorpinsXINandXOUT. (d)AvoidrunningPCBtracesunderneathoradjacenttotheXINandXOUTpins. (e)UseassemblymaterialsandpraxistoavoidanyparasiticloadontheoscillatorXINandXOUTpins. (f)Ifconformalcoatingisused,ensurethatitdoesnotinducecapacitive/resistiveleakagebetweentheoscillatorpins. (g)DonotroutetheXOUTlinetotheJTAGheadertosupporttheserialprogrammingadapterasshowninotherdocumentation.This signalisnolongerrequiredfortheserialprogrammingadapter. (2) Includesparasiticbondandpackagecapacitance(approximately2pFperpin).BecausethePCBaddsadditionalcapacitance,itis recommendedtoverifythecorrectloadbymeasuringtheACLKfrequency.Foracorrectsetup,theeffectiveloadcapacitanceshould alwaysmatchthespecificationoftheusedcrystal. (3) Requiresexternalcapacitorsatbothterminals.Valuesarespecifiedbycrystalmanufacturers. (4) FrequenciesbelowtheMINspecificationsetthefaultflag,frequenciesabovetheMAXspecificationdonotsetthefaultflag,and frequenciesinbetweenmightsettheflag. (5) Measuredwithlogic-levelinputfrequency,butalsoappliestooperationwithcrystals. Copyright©2006–2011,TexasInstrumentsIncorporated 33

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1) OSCILLATIONALLOWANCE OSCILLATORSUPPLYCURRENT vs vs CRYSTALFREQUENCY CRYSTALFREQUENCY C =15pF,T =25°C C =15pF,T =25°C L,eff A L,eff A 100000 800 LFXT1Sx = 2 700 A 10000 µ 600 W – – nt e ance Curr 500 w y Allo 1000 uppl 400 n S scillatio LFXT1Sx = 2 cillator 300 O s LFXT1Sx = 1 100 O 200 LFXT1Sx = 0 LFXT1Sx = 1 XT 100 LFXT1Sx = 0 10 0 0.1 1 10 100 0 4 8 12 16 20 CrystalFrequency–MHz Crystal Frequency–MHz Figure17. Figure18. 34 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Timer_A overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC Internal:SMCLK,ACLK 2.2V 10 f Timer_Aclockfrequency External:TACLK,INCLK MHz TA Dutycycle=50%±10% 3V 16 t Timer_Acapturetiming TA0,TA1,TA2 2.2V/3V 20 ns TA,cap Timer_B overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC Internal:SMCLK,ACLK 2.2V 10 f Timer_Bclockfrequency External:TACLK,INCLK MHz TB Dutycycle=50%±10% 3V 16 t Timer_Bcapturetiming TB0,TB1,TB2 2.2V/3V 20 ns TB,cap Copyright©2006–2011,TexasInstrumentsIncorporated 35

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com USCI (UART Mode) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER CONDITIONS V MIN TYP MAX UNIT CC Internal:SMCLK,ACLK f USCIinputclockfrequency External:UCLK f MHz USCI SYSTEM Dutycycle=50%±10% MaximumBITCLKclockfrequency fmax,BITCLK (equalsbaudrateinMBaud)(1) 2.2V/3V 2 MHz 2.2V 50 150 t UARTreceivedeglitchtime(2) ns τ 3V 50 100 (1) TheDCOwake-uptimemustbeconsideredinLPM3/4forbaudratesabove1MHz. (2) PulsesontheUARTreceiveinput(UCxRX)shorterthantheUARTreceivedeglitchtimearesuppressed.Toensurethatpulsesare correctlyrecognizedtheirwidthshouldexceedthemaximumspecificationofthedeglitchtime. USCI (SPI Master Mode)(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) (seeFigure19andFigure20) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC SMCLK,ACLK f USCIinputclockfrequency f MHz USCI Dutycycle=50%±10% SYSTEM 2.2V 110 t SOMIinputdatasetuptime ns SU,MI 3V 75 2.2V 0 t SOMIinputdataholdtime ns HD,MI 3V 0 UCLKedgetoSIMOvalid, 2.2V 30 t SIMOoutputdatavalidtime ns VALID,MO CL=20pF 3V 20 (1) f =1/2t witht ≥max(t +t ,t +t ). UCxCLK LO/HI LO/HI VALID,MO(USCI) SU,SI(Slave) SU,MI(USCI) VALID,SO(Slave) Fortheslave'sparameterst andt ,seetheSPIparametersoftheattachedslave. SU,SI(Slave) VALID,SO(Slave) USCI (SPI Slave Mode)(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) (seeFigure21andFigure22) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC t STEleadtime,STElowtoclock 2.2V/3V 50 ns STE,LEAD t STElagtime,LastclocktoSTEhigh 2.2V/3V 10 ns STE,LAG t STEaccesstime,STElowtoSOMIdataout 2.2V/3V 50 ns STE,ACC STEdisabletime,STEhightoSOMIhigh t 2.2V/3V 50 ns STE,DIS impedance 2.2V 20 t SIMOinputdatasetuptime ns SU,SI 3V 15 2.2V 10 t SIMOinputdataholdtime ns HD,SI 3V 10 UCLKedgetoSOMIvalid, 2.2V 75 110 t SOMIoutputdatavalidtime ns VALID,SO CL=20pF 3V 50 75 (1) f =1/2t witht ≥max(t +t ,t +t ). UCxCLK LO/HI LO/HI VALID,MO(Master) SU,SI(USCI) SU,MI(Master) VALID,SO(USCI) Forthemaster'sparameterst andt refertotheSPIparametersoftheattachedslave. SU,MI(Master) VALID,MO(Master) 36 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure19. SPIMasterMode,CKPH=0 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tHD,MI tSU,MI SOMI tVALID,MO SIMO Figure20. SPIMasterMode,CKPH=1 Copyright©2006–2011,TexasInstrumentsIncorporated 37

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,SI tHD,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure21. SPISlaveMode,CKPH=0 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure22. SPISlaveMode,CKPH=1 38 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 USCI (I2C Mode) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(seeFigure23) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC Internal:SMCLK,ACLK f USCIinputclockfrequency External:UCLK f MHz USCI SYSTEM Dutycycle=50%±10% f SCLclockfrequency 2.2V/3V 0 400 kHz SCL f ≤100kHz 4 SCL t Holdtime(repeated)START 2.2V/3V µs HD,STA f >100kHz 0.6 SCL f ≤100kHz 4.7 SCL t SetuptimeforarepeatedSTART 2.2V/3V µs SU,STA f >100kHz 0.6 SCL t Dataholdtime 2.2V/3V 0 ns HD,DAT t Datasetuptime 2.2V/3V 250 ns SU,DAT t SetuptimeforSTOP 2.2V/3V 4 µs SU,STO 2.2V 50 150 600 t Pulsewidthofspikessuppressedbyinputfilter ns SP 3V 50 100 600 tHD,STA tSU,STA tHD,STA SDA 1/fSCL tSP SCL tSU,DAT tSU,STO tHD,DAT Figure23. I2CModeTiming Copyright©2006–2011,TexasInstrumentsIncorporated 39

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Comparator_A+(1) overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 2.2V 25 40 I CAON=1,CARSEL=0,CAREF=0 µA (DD) 3V 45 60 CAON=1,CARSEL=0,CAREF=1/2/3, 2.2V 30 50 I µA (Refladder/RefDiode) NoloadatP2.3/CA0andP2.4/CA1 3V 45 71 Common-modeinputvoltage V CAON=1 2.2V/3V 0 V -1 V IC range CC Voltageat0.25V node/ PCA0=1,CARSEL=1,CAREF=1, V CC 2.2V/3V 0.23 0.24 0.25 (Ref025) V NoloadatP2.3/CA0andP2.4/CA1 CC Voltageat0.5V node/ PCA0=1,CARSEL=1,CAREF=2, V CC 2.2V/3V 0.47 0.48 0.5 (Ref050) V NoloadatP2.3/CA0andP2.4/CA1 CC PCA0=1,CARSEL=1,CAREF=3, 2.2V 390 480 540 V SeeFigure27andFigure28 NoloadatP2.3/CA0andP2.4/CA1, mV (RefVT) T =85°C 3V 400 490 550 A V Offsetvoltage(2) 2.2V/3V -30 30 mV (offset) V Inputhysteresis CAON=1 2.2V/3V 0 0.7 1.4 mV hys T =25°C,Overdrive10mV, 2.2V 80 165 300 A Withoutfilter:CAF=0(3) ns Responsetime (seeFigure24andFigure25) 3V 70 120 240 t (response) (low-highandhigh-low) T =25°C,Overdrive10mV, 2.2V 1.4 1.9 2.8 A Withfilter:CAF=1(3) µs (seeFigure24andFigure25) 3V 0.9 1.5 2.2 (1) TheleakagecurrentfortheComparator_A+terminalsisidenticaltoI specification. lkg(Px.y) (2) TheinputoffsetvoltagecanbecancelledbyusingtheCAEXbittoinverttheComparator_A+inputsonsuccessivemeasurements.The twosuccessivemeasurementsarethensummedtogether. (3) ResponsetimemeasuredatP2.2/CAOUT/TA0/CA4. 40 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 0 V VCC 0 1 CAF CAON Low-Pass Filter To Internal Modules 0 0 V+ + V− _ 1 1 CAOUT Set CAIFG Flag τ≈2.0µs Figure24. Comparator_A+ModuleBlockDiagram Overdrive VCAOUT V− 400 mV V+ t(response) Figure25. OverdriveDefinition CASHORT CA0 CA1 1 + VIN Comparator_A+ IOUT= 10µA − CASHORT=1 Figure26. Comparator_A+ShortResistanceTestCondition Copyright©2006–2011,TexasInstrumentsIncorporated 41

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Typical Characteristics - Comparator_A+ V V (RefVT) (RefVT) vs vs TEMPERATURE TEMPERATURE V =2.2V V =2.2V CC CC 650 650 V = 3 V V = 2.2 V CC CC 600 600 V V m m – Typical – s s Typical Volt 550 Volt 550 e e c c n n e e er er ef 500 ef 500 R R – – V(REFVT) V(REFVT) 450 450 400 400 -45 -25 -5 15 35 55 75 95 -45 -25 -5 15 35 55 75 95 T –Free-AirTemperature–°C T –Free-AirTemperature–°C A A Figure27. Figure28. SHORTRESISTANCE vs V /V IN CC 100 V = 1.8 V W CC k V = 2.2 V – CC e c n V = 3 V a CC st 10 si e R ort h S V = 3.6 V CC 1 0 0.2 0.4 0.6 0.8 1.0 V /V –Normalized Input Voltage–V/V IN CC Figure29. 42 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Flash Memory overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC V Programanderasesupplyvoltage 2.2 3.6 V CC(PGM/ERASE) f Flashtiminggeneratorfrequency 257 476 kHz FTG I SupplycurrentfromV duringprogram 2.2V/3.6V 1 5 mA PGM CC I SupplycurrentfromV duringerase 2.2V/3.6V 1 7 mA ERASE CC t Cumulativeprogramtime(1) 2.2V/3.6V 10 ms CPT t Cumulativemasserasetime 2.2V/3.6V 20 ms CMErase Program/eraseendurance 104 105 cycles t Dataretentionduration T =25°C 100 years Retention J t Wordorbyteprogramtime See (2) 30 t Word FTG t Blockprogramtimeforfirstbyteorword See (2) 25 t Block,0 FTG t Blockprogramtimeforeachadditional See (2) 18 t Block,1-63 byteorword FTG t Blockprogramend-sequencewaittime See (2) 6 t Block,End FTG t Masserasetime See (2) 10593 t MassErase FTG t Segmenterasetime See (2) 4819 t SegErase FTG (1) Thecumulativeprogramtimemustnotbeexceededwhenwritingtoa64-byteflashblock.Thisparameterappliestoallprogramming methods:individualword/bytewriteandblockwritemodes. (2) Thesevaluesarehardwiredintotheflashcontroller'sstatemachine(t =1/f ). FTG FTG RAM overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT V RAMretentionsupplyvoltage (1) CPUhalted 1.6 V (RAMh) (1) ThisparameterdefinestheminimumsupplyvoltageV whenthedatainRAMremainsunchanged.Noprogramexecutionshould CC happenduringthissupplyvoltagecondition. JTAG Interface overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER V MIN TYP MAX UNIT CC 2.2V 0 5 MHz f TCKinputfrequency(1) TCK 3V 0 10 MHz R InternalpulldownresistanceonTEST(2) 2.2V/3V 25 35 55 kΩ Internal (1) f mayberestrictedtomeetthetimingrequirementsofthemoduleselected. TCK (2) TMS,TDI/TCLK,andTCKpullupresistorsareimplementedinallversions. JTAG Fuse(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT V Supplyvoltageduringfuse-blowcondition T =25°C 2.5 V CC(FB) A V VoltagelevelonTESTforfuseblow 6 7 V FB I SupplycurrentintoTESTduringfuseblow 100 mA FB t Timetoblowfuse 1 ms FB (1) Afterthefuseisblown,nofurtheraccesstotheJTAG/Testandemulationfeaturesispossible,andtheJTAGblockisswitchedto bypassmode. Copyright©2006–2011,TexasInstrumentsIncorporated 43

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com APPLICATION INFORMATION Port P1 Pin Schematic: P1.0 to P1.7, Input/Output With Schmitt Trigger P1REN.x PadLogic DVSS 0 DVCC 1 1 P1DIR.x 0 Direction 0:Input 1 1:Output P1OUT.x 0 ModuleXOUT 1 P1.0/TACLK P1.1/TA0 P1SEL.x P1.2/TA1 P1.3/TA2 P1IN.x P1.4/SMCLK P1.5/TA0 EN P1.6/TA1 P1.7/TA2 ModuleXIN D P1IE.x EN P1IRQ.x Q Set P1IFG.x P1SEL.x Interrupt EdgeSelect P1IES.x 44 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Table18.PortP1(P1.0toP1.7)PinFunctions CONTROLBITS/SIGNALS PINNAME(P1.x) x FUNCTION P1DIR.x P1SEL.x P1.0(I/O) I:0,O:1 0 P1.0/TACLK 0 Timer_A3.TACLK 0 1 DVSS 1 1 P1.1(I/O) I:0,O:1 0 P1.1/TA0 1 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 P1.2(I/O) I:0,O:1 0 P1.2/TA1 2 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 P1.3(I/O) I:0,O:1 0 P1.3/TA2 3 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 P1.4(I/O) I:0,O:1 0 P1.4/SMCLK 4 SMCLK 1 1 P1.5(I/O) I:0,O:1 0 P1.5/TA0 5 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 P1.6(I/O) I:0,O:1 0 P1.6/TA1 6 Timer_A3.CCI0A 0 1 Timer_A3.TA1 1 1 P1.7(I/O) I:0,O:1 0 P1.7/TA2 7 Timer_A3.CCI0A 0 1 Timer_A3.TA2 1 1 Copyright©2006–2011,TexasInstrumentsIncorporated 45

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Port P2 Pin Schematic: P2.0 to P2.4, Input/Output With Schmitt Trigger PadLogic To Comparator_A From Comparator_A CAPD.x P2REN.x DVSS 0 DVCC 1 1 P2DIR.x 0 Direction 0:Input 1 1:Output P2OUT.x 0 ModuleXOUT 1 P2.0/ACLK/CA2 Bus P2.1/TAINCLK/CA3 P2SEL.x Keeper P2.2/CAOUT/TA0/CA4 P2IN.x EN P2.3/CA0/TA1 P2.4/CA1/TA2 EN ModuleXIN D P2IE.x EN P2IRQ.x Q Set P2IFG.x P2SEL.x Interrupt EdgeSelect P2IES.x 46 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Table19.PortP2(P2.0toP2.4)PinFunctions CONTROLBITS/SIGNALS(1) PINNAME(P2.x) x FUNCTION CAPD.x P2DIR.x P2SEL.x P2.0(I/O) 0 I:0,O:1 0 P2.0/ACLK/CA2 0 ACLK 0 1 1 CA2(2) 1 X X P2.1(I/O) 0 I:0,O:1 0 Timer_A3.TAINCLK 0 0 1 P2.1/TAINCLK/CA3 1 DVSS 0 1 1 CA3(2) 1 X X P2.2(I/O) 0 I:0,O:1 0 CAOUT 0 1 1 P2.2/CAOUT/TA0/CA4 2 TA0 0 0 1 CA4(2) 1 X X P2.3(I/O) 0 I:0,O:1 0 P2.3/CA0/TA1 3 CA0(2) 1 X X Timer_A3.TA1 0 1 1 P2.4(I/O) 0 I:0,O:1 0 P2.4/CA1/TA2 4 CA1(2) 1 X X Timer_A3.TA2 0 1 1 (1) X=Don'tcare (2) SettingtheCAPD.xbitdisablestheoutputdriveraswellastheinputtopreventparasiticcrosscurrentswhenapplyinganalogsignals. SelectingtheCAxinputtothecomparatormultiplexerwiththeP2CAxbitsautomaticallydisablestheinputbufferforthatpin,regardless ofthestateoftheassociatedCAPD.xbit. Copyright©2006–2011,TexasInstrumentsIncorporated 47

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger PadLogic ToComparator FromComparator CAPD.5 ToDCO inDCO DCOR P2REN.5 DVSS 0 DVCC 1 1 P2DIR.5 0 Direction 0:Input 1 1:Output P2OUT.5 0 ModuleXOUT 1 P2.5/ROSC/CA5 Bus P2SEL.x Keeper P2IN.5 EN EN ModuleXIN D P2IE.5 EN P2IRQ.5 Q Set P2IFG.5 P2SEL.5 Interrupt EdgeSelect P2IES.5 Table20.PortP2(P2.5)PinFunctions CONTROLBITS/SIGNALS(1) PINNAME(P2.x) x FUNCTION CAPD.5 DCOR P2DIR.5 P2SEL.5 P2.5(I/O) 0 0 I:0,O:1 0 R 0 1 X X OSC P2.5/R /CA5 5 OSC DV 0 0 1 1 SS CA5(2) 1 0 X X (1) X=Don'tcare (2) SettingtheCAPD.xbitdisablestheoutputdriveraswellastheinputtopreventparasiticcrosscurrentswhenapplyinganalogsignals. SelectingtheCAxinputtothecomparatormultiplexerwiththeP2CAxbitsautomaticallydisablestheinputbufferforthatpin,regardless ofthestateoftheassociatedCAPD.xbit. 48 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger BCSCTL3.LFXT1Sx=11 LFXT1off P2.7/XOUT/CA7 0 LFXT1CLK 1 PadLogic ToComparator From Comparator CAPD.6 P2SEL.7 P2REN.6 DVSS 0 DVCC 1 1 P2DIR.6 0 Direction 0:Input 1 1:Output P2OUT.6 0 ModuleXOUT 1 P2.6/XIN/CA6 Bus P2SEL.6 Keeper P2IN.6 EN EN ModuleXIN D P2IE.6 EN P2IRQ.6 Q Set P2IFG.6 P2SEL.6 Interrupt P2IES.6 EdgeSelect Copyright©2006–2011,TexasInstrumentsIncorporated 49

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Table21.PortP2(P2.6)PinFunctions CONTROLBITS/SIGNALS(1) PINNAME(P2.x) x FUNCTION CAPD.6 P2DIR.6 P2SEL.6 P2.6(I/O) 0 I:0,O:1 0 P2.6/XIN/CA6 6 XIN(default) X 1 1 CA6(2) 1 X 0 (1) X=Don'tcare (2) SettingtheCAPD.xbitdisablestheoutputdriveraswellastheinputtopreventparasiticcrosscurrentswhenapplyinganalogsignals. SelectingtheCAxinputtothecomparatormultiplexerwiththeP2CAxbitsautomaticallydisablestheinputbufferforthatpin,regardless ofthestateoftheassociatedCAPD.xbit. 50 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger BCSCTL3.LFXT1Sx=11 P2.6/XIN/TA1 LFXT1off 0 LFXT1CLK FromP2.6/XIN 1 PadLogic ToComparator From Comparator CAPD.7 P2SEL.6 P2REN.7 DVSS 0 DVCC 1 1 P2DIR.7 0 Direction 0:Input 1 1:Output P2OUT.7 0 ModuleXOUT 1 P2.7/XOUT Bus P2SEL.7 Keeper P2IN.7 EN EN ModuleXIN D P2IE.7 EN P2IRQ.7 Q Set P2IFG.7 P2SEL.7 Interrupt P2IES.7 EdgeSelect Copyright©2006–2011,TexasInstrumentsIncorporated 51

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Table22.PortP2(P2.7)PinFunctions CONTROLBITS/SIGNALS(1) PINNAME(P2.x) x FUNCTION CAPD.7 P2DIR.7 P2SEL.7 P2.7(I/O) 0 I:0,O:1 0 P2.7/XOUT/CA7 7 XOUT(default) X 1 1 CA7(2) 1 X 0 (1) X=Don'tcare (2) SettingtheCAPD.xbitdisablestheoutputdriveraswellastheinputtopreventparasiticcrosscurrentswhenapplyinganalogsignals. SelectingtheCAxinputtothecomparatormultiplexerwiththeP2CAxbitsautomaticallydisablestheinputbufferforthatpin,regardless ofthestateoftheassociatedCAPD.xbit. 52 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Port P3 Pin Schematic: P3.0 to P3.5, Input/Output With Schmitt Trigger PadLogic P3REN.x DVSS 0 DVCC 1 1 P3DIR.x 0 Direction Module 0:Input 1 direction 1:Output P3OUT.x 0 ModuleXOUT 1 P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3SEL.x P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3IN.x P3.4/UCA0TXD/UCA0SIMO P3.5/UCA0RXD/UCA0SOMI EN ModuleXIN D Table23.PortP3(P3.0toP3.5)PinFunctions CONTROLBITS/SIGNALS(1) PINNAME(P3.x) x FUNCTION P3DIR.x P3SEL.x P3.0/UCB0STE/ P3.0(I/O) I:0,O:1 0 0 UCA0CLK UCB0STE/UCA0CLK(2) X 1 P3.1/UCB0SIMO/ P3.1(I/O) I:0,O:1 0 1 UCB0SDA UCB0SIMO/UCB0SDA(2)(3) X 1 P3.2/UCB0SOMI/ P3.2(I/O) I:0,O:1 0 2 UCB0SCL UCB0SOMI/UCB0SCL(2)(3) X 1 P3.3/UCB0CLK/ P3.3(I/O) I:0,O:1 0 3 UCA0STE UCB0CLK/UCA0STE(2) X 1 P3.4/UCA0TXD/ P3.4(I/O) I:0,O:1 0 4 UCA0SIMO UCA0TXD/UCA0SIMO(2) X 1 P3.5/UCA0RXD/ P3.5(I/O) I:0,O:1 0 5 UCA0SOMI UCA0RXD/UCA0SOMI(2) X 1 (1) X=Don'tcare (2) ThepindirectioniscontrolledbytheUSCImodule. (3) IftheI2Cfunctionalityisselected,theoutputdrivesonlythelogical0toV level. SS Copyright©2006–2011,TexasInstrumentsIncorporated 53

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com Port P3 Pin Schematic: P3.6 and P3.7, Input/Output With Schmitt Trigger PadLogic P3REN.x DVSS 0 DVCC 1 1 P3DIR.x 0 Direction 0:Input 0 1 1:Output P3OUT.x 0 ModuleXOUT 1 P3.6 P3.7 P3SEL.x P3IN.x EN ModuleXIN D Table24.PortP3(P3.6andP3.7)PinFunctions CONTROLBITS/SIGNALS PINNAME(P3.x) x FUNCTION P3DIR.x P3SEL.x P3.6 6 P3.6(I/O) I:0,O:1 0 P3.7 7 P3.7(I/O) I:0,O:1 0 54 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 Port P4 Pin Schematic: P4.0 to P4.7, Input/Output With Schmitt Trigger PadLogic P4REN.x DVSS 0 DVCC 1 1 P4DIR.x 0 Direction 0:Input 1 1:Output P4OUT.x 0 ModuleXOUT 1 P4.0/TB0 P4.1/TB1 P4SEL.x P4.2/TB2 P4.3/TB0 P4IN.x P4.4/TB1 P4.5/TB2 EN P4.6/TBOUTH/ACLK P4.7/TBCLK/ TBINCLK ModuleXIN D Table25.PortP4(P4.0toP4.7)PinFunctions CONTROLBITS/SIGNALS PINNAME(P4.x) x FUNCTION P4DIR.x P4SEL.x P4.0(I/O) I:0,O:1 0 P4.0/TB0 0 Timer_B3.CCI0A 0 1 Timer_B3.OUT0 1 1 P4.1(I/O) I:0,O:1 0 P4.1/TB1 1 Timer_B3.CCI1A 0 1 Timer_B3.OUT1 1 1 P4.2(I/O) I:0,O:1 0 P4.2/TB2 2 Timer_B3.CCI2A 0 1 Timer_B3.OUT2 1 1 P4.3(I/O) I:0,O:1 0 P4.3/TB0 3 Timer_B3.CCI0B 0 1 Timer_B3.OUT0 1 1 P4.4(I/O) I:0,O:1 0 P4.4/TB1 4 Timer_B3.CCI1B 0 1 Timer_B3.OUT1 1 1 P4.5(I/O) I:0,O:1 0 P4.5/TB2 5 N/A 0 1 Timer_B3.OUT2 1 1 P4.6(I/O) I:0,O:1 0 P4.6/TBOUTH/ACLK 6 Timer_B3.TBOUTH 0 1 ACLK 1 1 P4.7(I/O) I:0,O:1 0 P4.7/TBCLK 7 Timer_B3.TBCLK 0 1 Copyright©2006–2011,TexasInstrumentsIncorporated 55

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger TDO Controlled by JTAG Controlled by JTAG JTAG TDO/TDI Controlled by JTAG DVCC DVCC TDI Fuse Burn &Test Fuse Test TDI/TCLK and Emulation Module DVCC TMS TMS DVCC During ProgrammingActivity and During Blowing of the Fuse, Pin TCK TDO/TDI Is Used toApply theT est Input Data for JTAG Circuitry TCK 56 Copyright©2006–2011,TexasInstrumentsIncorporated

MSP430F23x0 www.ti.com SLAS518E–AUGUST2006–REVISEDAUGUST2011 JTAG Fuse Check Mode MSP430devicesthathavethefuseontheTESTterminalhaveafusecheckmodethatteststhecontinuityofthe fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, I , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care TF must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse checkmodehasthepotentialtobeactivated. The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see Figure 30). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). TimeTMS Goes LowAfter POR TMS I TF I TEST Figure30. FuseCheckModeCurrent Copyright©2006–2011,TexasInstrumentsIncorporated 57

MSP430F23x0 SLAS518E–AUGUST2006–REVISEDAUGUST2011 www.ti.com REVISION HISTORY LITERATURE SUMMARY NUMBER SLAS518 PRODUCTPREVIEWdatasheetrelease SLAS518A PRODUCTIONDATAdatasheetrelease TheUSCIparametersectionwasrevised,pages36to39. CorrectedtheportschematicsofportP2.6andP2.7 AddedintheDSBGApackageversion. SLAS518B CorrectedWDTIFGdescriptioninIFG1register. CorrectedlabelsinFigure17and18. CorrectedtestconditionsofComparator_A+fromP1.0,P1.1toP2.3andP2.4. CorrectedtheUARTparameters. SLAS518C ReleaseofMSP430F2330IYFFandMSP430F2350IYFF SLAS518D ChangedT ,Programmeddevice,to-40°Cto150°CinAbsoluteMaximumRatings. stg SLAS518E ChangedT ,Programmeddevice,to-55°Cto150°CinAbsoluteMaximumRatings. stg 58 Copyright©2006–2011,TexasInstrumentsIncorporated

PACKAGE OPTION ADDENDUM www.ti.com 21-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MSP430F2330IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430 & no Sb/Br) F2330 MSP430F2330IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430 & no Sb/Br) F2330 MSP430F2330TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 105 M430 & no Sb/Br) F2330T MSP430F2330TRHAT ACTIVE VQFN RHA 40 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 105 M430 & no Sb/Br) F2330T MSP430F2350IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430 & no Sb/Br) F2350 MSP430F2350IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430 & no Sb/Br) F2350 MSP430F2350IYFFT ACTIVE DSBGA YFF 49 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 M430F2350 & no Sb/Br) MSP430F2350TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 105 M430 & no Sb/Br) F2350T MSP430F2350TRHAT ACTIVE VQFN RHA 40 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 105 M430 & no Sb/Br) F2350T MSP430F2370IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430 & no Sb/Br) F2370 MSP430F2370IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 M430 & no Sb/Br) F2370 MSP430F2370IYFFT ACTIVE DSBGA YFF 49 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 M430F2370 & no Sb/Br) MSP430F2370TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 105 M430 & no Sb/Br) F2370T MSP430F2370TRHAT ACTIVE VQFN RHA 40 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 105 M430 & no Sb/Br) F2370T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 21-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) MSP430F2330IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2330IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2330TRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2330TRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2350IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2350IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2350TRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2350TRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2370IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2370IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2370TRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2370TRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) MSP430F2330IRHAR VQFN RHA 40 2500 367.0 367.0 35.0 MSP430F2330IRHAT VQFN RHA 40 250 210.0 185.0 35.0 MSP430F2330TRHAR VQFN RHA 40 2500 367.0 367.0 35.0 MSP430F2330TRHAT VQFN RHA 40 250 210.0 185.0 35.0 MSP430F2350IRHAR VQFN RHA 40 2500 367.0 367.0 35.0 MSP430F2350IRHAT VQFN RHA 40 250 210.0 185.0 35.0 MSP430F2350TRHAR VQFN RHA 40 2500 367.0 367.0 35.0 MSP430F2350TRHAT VQFN RHA 40 250 210.0 185.0 35.0 MSP430F2370IRHAR VQFN RHA 40 2500 367.0 367.0 35.0 MSP430F2370IRHAT VQFN RHA 40 250 210.0 185.0 35.0 MSP430F2370TRHAR VQFN RHA 40 2500 367.0 367.0 35.0 MSP430F2370TRHAT VQFN RHA 40 250 210.0 185.0 35.0 PackMaterials-Page2

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None

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D: Max = 3.232 mm, Min =3 .172 mm E: Max = 3.232 mm, Min =3 .172 mm

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