MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • LowSupplyVoltageRange1.8Vto3.6V • SerialOnboardProgramming,NoExternal • Ultra-LowPowerConsumption ProgrammingVoltageNeeded,Programmable CodeProtectionbySecurityFuse – ActiveMode:220µAat1MHz,2.2V • On-ChipEmulationLogicWithSpy-Bi-Wire – StandbyMode:0.5 µA Interface – OffMode(RAMRetention):0.1µA • FamilyMembers: • FivePower-SavingModes – MSP430F2001 • Ultra-FastWake-UpFromStandbyModein – 1KB+256BFlashMemory LessThan1µs – 128BRAM • 16-BitRISCArchitecture,62.5-nsInstruction CycleTime – MSP430F2011 • BasicClockModuleConfigurations: – 2KB+256BFlashMemory – InternalFrequenciesupto16MHzWith – 128BRAM FourCalibratedFrequenciesto±1% – MSP430F2002 – InternalVeryLow-PowerLow-Frequency – 1KB+256BFlashMemory Oscillator – 128BRAM – 32-kHzCrystal – MSP430F2012 – ExternalDigitalClockSource – 2KB+256BFlashMemory • 16-BitTimer_AWithTwoCapture/Compare – 128BRAM Registers – MSP430F2003 • On-ChipComparatorforAnalogSignal – 1KB+256BFlashMemory CompareFunctionorSlopeA/D – 128BRAM (MSP430F20x1) – MSP430F2013 • 10-Bit200-kspsA/DConverterWithInternal Reference,Sample-and-Hold,andAutoscan – 2KB+256BFlashMemory (MSP430F20x2) – 128BRAM • 16-BitSigma-DeltaA/DConverterWith • Availablein14-PinPlasticSmall-OutlineThin DifferentialPGAInputsandInternalReference Package(TSSOP),14-PinPlasticDualInline (MSP430F20x3) Package(PDIP),and16-PinQFN • UniversalSerialInterface(USI)SupportingSPI • ForCompleteModuleDescriptions,Seethe andI2C(MSP430F20x2andMSP430F20x3) MSP430x2xxFamilyUser'sGuide(SLAU144) • BrownoutDetector DESCRIPTION The Texas Instruments MSP430 family of ultra-low-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. Thedigitallycontrolledoscillator(DCO)allowswake-upfromlow-powermodestoactivemodeinlessthan1µs. The MSP430F20xx series is an ultra-low-power mixed signal microcontroller with a built-in 16-bit timer and ten I/O pins. In addition, the MSP430F20x1 has a versatile analog comparator. The MSP430F20x2 and MSP430F20x3 have built-in communication capability using synchronous protocols (SPI or I2C) and a 10-bit A/D converter(MSP430F20x2)ora16-bitsigma-deltaA/Dconverter(MSP430F20x3). 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2005–2012,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. Stand alone RF sensor front end is another areaofapplication. Table1.AvailableOptions(1) PACKAGEDDEVICES(2) T A PLASTIC14-PINTSSOP(PW) PLASTIC14-PINDIP(N) PLASTIC16-PINQFN(RSA) MSP430F2001IPW MSP430F2001IN MSP430F2001IRSA MSP430F2011IPW MSP430F2011IN MSP430F2011IRSA MSP430F2002IPW MSP430F2002IN MSP430F2002IRSA -40°Cto85°C MSP430F2012IPW MSP430F2012IN MSP430F2012IRSA MSP430F2003IPW MSP430F2003IN MSP430F2003IRSA MSP430F2013IPW MSP430F2013IN MSP430F2013IRSA MSP430F2001TPW MSP430F2001TN MSP430F2001TRSA MSP430F2011TPW MSP430F2011TN MSP430F2011TRSA MSP430F2002TPW MSP430F2002TN MSP430F2002TRSA -40°Cto105°C MSP430F2012TPW MSP430F2012TN MSP430F2012TRSA MSP430F2003TPW MSP430F2003TN MSP430F2003TRSA MSP430F2013TPW MSP430F2013TN MSP430F2013TRSA (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) Packagedrawings,thermaldata,andsymbolizationareavailableatwww.ti.com/packaging. 2 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Device Pinout, MSP430F20x1 SeeportschematicssectionfordetailedI/Oinformation. PW or N PACKAGE (TOPVIEW) VCC 1 14 VSS P1.0/TACLK/ACLK/CA0 2 13 XIN/P2.6/TA1 P1.1/TA0/CA1 3 12 XOUT/P2.7 P1.2/TA1/CA2 4 11 TEST/SBWTCK P1.3/CAOUT/CA3 5 10 RST/NMI/SBWTDIO P1.4/SMCLK/CA4/TCK 6 9 P1.7/CAOUT/CA7/TDO/TDI P1.5/TA0/CA5/TMS 7 8 P1.6/TA1/CA6/TDI/TCLK RSAPACKAGE (TOPVIEW) CC C SS C V N V N 15 14 P1.0/TACLK/ACLK/CA0 1 12 XIN/P2.6/TA1 P1.1/TA0/CA1 2 11 XOUT/P2.7 P1.2/TA1/CA2 3 10 TEST/SBWTCK P1.3/CAOUT/CA3 4 9 RST/NMI/SBWTDIO 6 7 A4/TCK A5/TMS DI/TCLK DO/TDI C C T T CLK/ TA0/ CA6/ CA7/ SM 1.5/ A1/ UT/ P1.4/ P P1.6/T 7/CAO 1. P Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Device Pinout, MSP430F20x2 SeeportschematicssectionfordetailedI/Oinformation. PW or N PACKAGE (TOPVIEW) VCC 1 14 VSS P1.0/TACLK/ACLK/A0 2 13 XIN/P2.6/TA1 P1.1/TA0/A1 3 12 XOUT/P2.7 P1.2/TA1/A2 4 11 TEST/SBWTCK P1.3/ADC10CLK/A3/VREF−/VeREF− 5 10 RST/NMI/SBWTDIO P1.4/SMCLK/A4/VREF+/VeREF+/TCK 6 9 P1.7/A7/SDI/SDA/TDO/TDI P1.5/TA0/A5/SCLK/TMS 7 8 P1.6/TA1/A6/SDO/SCL/TDI/TCLK RSAPACKAGE (TOPVIEW) C C S S C C S S V V V V D A D A 15 14 P1.0/TACLK/ACLK/A0 1 12 XIN/P2.6/TA1 P1.1/TA0/A1 2 11 XOUT/P2.7 P1.2/TA1/A2 3 10 TEST/SBWTCK P1.3/ADC10CLK/A3/VREF−/VeREF− 4 9 RST/NMI/SBWTDIO 6 7 S K M K DI C T L T MCLK/A4/VREF+/VeREF+/T P1.5/TA0/A5/SCLK/ 6/TA1/A6/SDO/SCL/TDI/TC P1.7/A7/SDI/SDA/TDO/ S 1. 4/ P 1. P 4 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Device Pinout, MSP430F20x3 SeeportschematicssectionfordetailedI/Oinformation. PW or N PACKAGE (TOPVIEW) VCC 1 14 VSS P1.0/TACLK/ACLK/A0+ 2 13 XIN/P2.6/TA1 P1.1/TA0/A0−/A4+ 3 12 XOUT/P2.7 P1.2/TA1/A1+/A4− 4 11 TEST/SBWTCK P1.3/VREF/A1− 5 10 RST/NMI/SBWTDIO P1.4/SMCLK/A2+/TCK 6 9 P1.7/A3−/SDI/SDA/TDO/TDI P1.5/TA0/A2−/SCLK/TMS 7 8 P1.6/TA1/A3+/SDO/SCL/TDI/TCLK RSAPACKAGE (TOPVIEW) C C S S C C S S V V V V D A D A 15 14 P1.0/TACLK/ACLK/A0+ 1 12 XIN/P2.6/TA1 P1.1/TA0/A0−/A4+ 2 11 XOUT/P2.7 P1.2/TA1/A1+/A4− 3 10 TEST/SBWTCK P1.3/VREF/A1− 4 9 RST/NMI/SBWTDIO 6 7 K S K DI C M L T CLK/A2+/T 2−/SCLK/T CL/TDI/TC SDA/TDO/ SM 0/A O/S SDI/ P1.4/ P1.5/TA A1/A3+/SD P1.7/A3−/ T 6/ 1. P Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com FunctionalBlockDiagram,MSP430F20x1 P2.x& VCC VSS P1.x&JTAG XIN/XOUT 8 2 XIN XOUT Port P1 Port P2 ACLK Basic Clock Flash RAM Comparator System+ _A+ 8I/O 2I/O SMCLK Interrupt Interrupt 2kB 128B 8channel capability, capability, 1kB 128B MCLK input mux pull−up/down pull−up/down resistors resistors 16MHz MAB CPU incl.16 Registers MDB Emulation (2BP) Watchdog Timer_A2 JTAG Brownout WDT+ Interface Protection 2CC 15/16−Bit Registers Spy−Bi Wire RST/NMI NOTE: SeeportschematicssectionfordetailedI/Oinformation. FunctionalBlockDiagram,MSP430F20x2 P2.x& VCC VSS P1.x&JTAG XIN/XOUT 8 2 XIN XOUT Port P1 Port P2 ACLK ADC10 Basic Clock Flash RAM System+ 10−bit 8I/O 2I/O SMCLK Interrupt Interrupt 2kB 128B 8Channels capability, capability, 1kB 128B Autoscan MCLK DTC pull−up/down pull−up/down resistors resistors 16MHz MAB CPU incl.16 Registers MDB Emulation (2BP) USI Watchdog Timer_A2 JTAG Brownout WDT+ Universal Interface Protection 2CC Serial 15/16−Bit Registers Interface SPI,I2C Spy−Bi Wire RST/NMI NOTE: SeeportschematicssectionfordetailedI/Oinformation. 6 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 FunctionalBlockDiagram,MSP430F20x3 P2.x& VCC VSS P1.x&JTAG XIN/XOUT 8 2 XIN XOUT Port P1 Port P2 ACLK SD16_A Basic Clock Flash RAM System+ 16−bit 8I/O 2I/O SMCLK Interrupt Interrupt 2kB 128B Sigma− capability, capability, 1kB 128B DeltaA/D MCLK Converter pull−up/down pull−up/down resistors resistors 16MHz MAB CPU incl.16 Registers MDB Emulation (2BP) USI Watchdog Timer_A2 JTAG Brownout WDT+ Universal Interface Protection 2CC Serial 15/16−Bit Registers Interface SPI,I2C Spy−Bi Wire RST/NMI NOTE: SeeportschematicssectionfordetailedI/Oinformation. Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Table2.TerminalFunctions,MSP430F20x1 TERMINAL NO. DESCRIPTION NAME I/O PW,N RSA General-purposedigitalI/Opin Timer_A,clocksignalTACLKinput P1.0/TACLK/ACLK/CA0 2 1 I/O ACLKsignaloutput Comparator_A+,CA0input General-purposedigitalI/Opin P1.1/TA0/CA1 3 2 I/O Timer_A,capture:CCI0Ainput,compare:Out0output Comparator_A+,CA1input General-purposedigitalI/Opin P1.2/TA1/CA2 4 3 I/O Timer_A,capture:CCI1Ainput,compare:Out1output Comparator_A+,CA2input General-purposedigitalI/Opin P1.3/CAOUT/CA3 5 4 I/O Comparator_A+,output/CA3input General-purposedigitalI/Opin SMCLKsignaloutput P1.4/SMCLK/C4/TCK 6 5 I/O Comparator_A+,CA4input JTAGtestclock,inputterminalfordeviceprogrammingandtest General-purposedigitalI/Opin Timer_A,compare:Out0output P1.5/TA0/CA5/TMS 7 6 I/O Comparator_A+,CA5input JTAGtestmodeselect,inputterminalfordeviceprogrammingandtest General-purposedigitalI/Opin Timer_A,compare:Out1output P1.6/TA1/CA6/TDI/TCLK 8 7 I/O Comparator_A+,CA6input JTAGtestdatainputortestclockinputduringprogrammingandtest General-purposedigitalI/Opin P1.7/CAOUT/CA7/TDO/TDI(1) 9 8 I/O Comparator_A+,output/CA7input JTAGtestdataoutputterminalortestdatainputduringprogrammingandtest Inputterminalofcrystaloscillator XIN/P2.6/TA1 13 12 I/O General-purposedigitalI/Opin Timer_A,compare:Out1output Outputterminalofcrystaloscillator XOUT/P2.7 12 11 I/O General-purposedigitalI/Opin(2) Resetornonmaskableinterruptinput RST/NMI/SBWTDIO 10 9 I Spy-Bi-Wiretestdatainput/outputduringprogrammingandtest SelectstestmodeforJTAGpinsonPort1.Thedeviceprotectionfuseis TEST/SBWTCK 11 10 I connectedtoTEST. Spy-Bi-Wiretestclockinputduringprogrammingandtest V 1 16 Supplyvoltage CC V 14 14 Groundreference SS NC NA 13,15 Notconnected QFNPad NA Pad NA QFNpackagepad.ConnectiontoVSSisrecommended. (1) TDOorTDIisselectedviaJTAGinstruction. (2) IfXOUT/P2.7isusedasaninput,excesscurrentflowsuntilP2SEL.7iscleared.Thisisduetotheoscillatoroutputdriverconnectionto thispadafterreset. 8 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Table3.TerminalFunctions,MSP430F20x2 TERMINAL NO. DESCRIPTION NAME I/O PW,N RSA General-purposedigitalI/Opin Timer_A,clocksignalTACLKinput P1.0/TACLK/ACLK/A0 2 1 I/O ACLKsignaloutput ADC10analoginputA0 General-purposedigitalI/Opin P1.1/TA0/A1 3 2 I/O Timer_A,capture:CCI0Ainput,compare:Out0output ADC10analoginputA1 General-purposedigitalI/Opin P1.2/TA1/A2 4 3 I/O Timer_A,capture:CCI1Ainput,compare:Out1output ADC10analoginputA2 General-purposedigitalI/Opin ADC10conversionclockoutput P1.3/ADC10CLK/A3/ 5 4 I/O ADC10analoginputA3 VREF-/VeREF- Inputfornegativeexternalreferencevoltage/negativeinternalreferencevoltage output General-purposedigitalI/Opin SMCLKsignaloutput P1.4/SMCLK/A4/VREF+/ ADC10analoginputA4 6 5 I/O VeREF+/TCK Inputforpositiveexternalreferencevoltage/positiveinternalreferencevoltage output JTAGtestclock,inputterminalfordeviceprogrammingandtest General-purposedigitalI/Opin Timer_A,compare:Out0output P1.5/TA0/A5/SCLK/TMS 7 6 I/O ADC10analoginputA5 USI:externalclockinputinSPIorI2Cmode;clockoutputinSPImode JTAGtestmodeselect,inputterminalfordeviceprogrammingandtest General-purposedigitalI/Opin Timer_A,capture:CCI1Binput,compare:Out1output P1.6/TA1/A6/SDO/SCL/ 8 7 I/O ADC10analoginputA6 TDI/TCLK USI:DataoutputinSPImode;I2CclockinI2Cmode JTAGtestdatainputortestclockinputduringprogrammingandtest General-purposedigitalI/Opin P1.7/A7/SDI/SDA/ ADC10analoginputA7 TDO/TDI(1) 9 8 I/O USI:DatainputinSPImode;I2CdatainI2Cmode JTAGtestdataoutputterminalortestdatainputduringprogrammingandtest Inputterminalofcrystaloscillator XIN/P2.6/TA1 13 12 I/O General-purposedigitalI/Opin Timer_A,compare:Out1output Outputterminalofcrystaloscillator XOUT/P2.7 12 11 I/O General-purposedigitalI/Opin(2) Resetornonmaskableinterruptinput RST/NMI/SBWTDIO 10 9 I Spy-Bi-Wiretestdatainput/outputduringprogrammingandtest SelectstestmodeforJTAGpinsonPort1.Thedeviceprotectionfuseis TEST/SBWTCK 11 10 I connectedtoTEST. Spy-Bi-Wiretestclockinputduringprogrammingandtest V 1 NA Supplyvoltage CC V 14 NA Groundreference SS DV NA 16 Digitalsupplyvoltage CC AV NA 15 Analogsupplyvoltage CC DV NA 14 Digitalgroundreference SS AV NA 13 Analoggroundreference SS QFNPad NA Pad NA QFNpackagepad.ConnectiontoVSSisrecommended. (1) TDOorTDIisselectedviaJTAGinstruction. (2) IfXOUT/P2.7isusedasaninput,excesscurrentflowsuntilP2SEL.7iscleared.Thisisduetotheoscillatoroutputdriverconnectionto thispadafterreset. Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Table4.TerminalFunctions,MSP430F20x3 TERMINAL NO. DESCRIPTION NAME I/O PW,N RSA General-purposedigitalI/Opin Timer_A,clocksignalTACLKinput P1.0/TACLK/ACLK/A0+ 2 1 I/O ACLKsignaloutput SD16_ApositiveanaloginputA0 General-purposedigitalI/Opin Timer_A,capture:CCI0Ainput,compare:Out0output P1.1/TA0/A0-/A4+ 3 2 I/O SD16_AnegativeanaloginputA0 SD16_ApositiveanaloginputA4 General-purposedigitalI/Opin Timer_A,capture:CCI1Ainput,compare:Out1output P1.2/TA1/A1+/A4- 4 3 I/O SD16_ApositiveanaloginputA1 SD16_AnegativeanaloginputA4 General-purposedigitalI/Opin Inputforanexternalreferencevoltage/internalreferencevoltageoutput(canbe P1.3/VREF/A1- 5 4 I/O usedasmid-voltage) SD16_AnegativeanaloginputA1 General-purposedigitalI/Opin SMCLKsignaloutput P1.4/SMCLK/A2+/TCK 6 5 I/O SD16_ApositiveanaloginputA2 JTAGtestclock,inputterminalfordeviceprogrammingandtest General-purposedigitalI/Opin Timer_A,compare:Out0output P1.5/TA0/A2-/SCLK/TMS 7 6 I/O SD16_AnegativeanaloginputA2 USI:externalclockinputinSPIorI2Cmode;clockoutputinSPImode JTAGtestmodeselect,inputterminalfordeviceprogrammingandtest General-purposedigitalI/Opin Timer_A,capture:CCI1Binput,compare:Out1output P1.6/TA1/A3+/SDO/SCL/ 8 7 I/O SD16_ApositiveanaloginputA3 TDI/TCLK USI:DataoutputinSPImode;I2CclockinI2Cmode JTAGtestdatainputortestclockinputduringprogrammingandtest General-purposedigitalI/Opin P1.7/A3-/SDI/SDA/ SD16_AnegativeanaloginputA3 TDO/TDI(1) 9 8 I/O USI:DatainputinSPImode;I2CdatainI2Cmode JTAGtestdataoutputterminalortestdatainputduringprogrammingandtest Inputterminalofcrystaloscillator XIN/P2.6/TA1 13 12 I/O General-purposedigitalI/Opin Timer_A,compare:Out1output Outputterminalofcrystaloscillator XOUT/P2.7 12 11 I/O General-purposedigitalI/Opin(2) Resetornonmaskableinterruptinput RST/NMI/SBWTDIO 10 9 I Spy-Bi-Wiretestdatainput/outputduringprogrammingandtest SelectstestmodeforJTAGpinsonPort1.Thedeviceprotectionfuseis TEST/SBWTCK 11 10 I connectedtoTEST. Spy-Bi-Wiretestclockinputduringprogrammingandtest V 1 NA Supplyvoltage CC V 14 NA Groundreference SS DV NA 16 Digitalsupplyvoltage CC AV NA 15 Analogsupplyvoltage CC DV NA 14 Digitalgroundreference SS AV NA 13 Analoggroundreference SS QFNPad NA Pad NA QFNpackagepad.ConnectiontoVSSisrecommended. (1) TDOorTDIisselectedviaJTAGinstruction. (2) IfXOUT/P2.7isusedasaninput,excesscurrentflowsuntilP2SEL.7iscleared.Thisisduetotheoscillatoroutputdriverconnectionto thispadafterreset. 10 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 SHORT-FORM DESCRIPTION CPU Program Counter PC/R0 The MSP430 CPU has a 16-bit RISC architecture Stack Pointer SP/R1 that is highly transparent to the application. All operations, other than program-flow instructions, are Status Register SR/CG1/R2 performed as register operations in conjunction with seven addressing modes for source operand and four Constant Generator CG2/R3 addressingmodesfordestinationoperand. General-Purpose Register R4 The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to- General-Purpose Register R5 register operation execution time is one cycle of the CPUclock. General-Purpose Register R6 Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and General-Purpose Register R7 constant generator respectively. The remaining registersaregeneral-purposeregisters. General-Purpose Register R8 Peripherals are connected to the CPU using data, General-Purpose Register R9 address, and control buses, and can be handled with allinstructions. General-Purpose Register R10 Instruction Set General-Purpose Register R11 The instruction set consists of 51 instructions with General-Purpose Register R12 three formats and seven address modes. Each instruction can operate on word and byte data. General-Purpose Register R13 Table 5 shows examples of the three types of instruction formats; Table 6 shows the address General-Purpose Register R14 modes. General-Purpose Register R15 Table5.InstructionWordFormats INSTRUCTIONFORMAT EXAMPLE OPERATION Dualoperands,source-destination ADDR4,R5 R4+R5--->R5 Singleoperands,destinationonly CALLR8 PC-->(TOS),R8-->PC Relativejump,un/conditional JNE Jump-on-equalbit=0 Table6.AddressModeDescriptions ADDRESSMODE S(1) D(1) SYNTAX EXAMPLE OPERATION Register ✓ ✓ MOVRs,Rd MOVR10,R11 R10-->R11 Indexed ✓ ✓ MOVX(Rn),Y(Rm) MOV2(R5),6(R6) M(2+R5)-->M(6+R6) Symbolic(PCrelative) ✓ ✓ MOVEDE,TONI M(EDE)-->M(TONI) Absolute ✓ ✓ MOV&MEM,&TCDAT M(MEM)-->M(TCDAT) Indirect ✓ MOV@Rn,Y(Rm) MOV@R10,Tab(R6) M(R10)-->M(Tab+R6) M(R10)-->R11 Indirectautoincrement ✓ MOV@Rn+,Rm MOV@R10+,R11 R10+2-->R10 Immediate ✓ MOV#X,TONI MOV#45,TONI #45-->M(TONI) (1) S=source,D=destination Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Operating Modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake the device from any of the five low-power modes, service the request, and restore back to the low-powermodeonreturnfromtheinterruptprogram. Thefollowingsixoperatingmodescanbeconfiguredbysoftware: • Activemode(AM) – Allclocksareactive • Low-powermode0(LPM0) – CPUisdisabled – ACLKandSMCLKremainactive – MCLKisdisabled • Low-powermode1(LPM1) – CPUisdisabled – ACLKandSMCLKremainactive.MCLKisdisabled – DCO'sdc-generatorisdisabledifDCOnotusedinactivemode • Low-powermode2(LPM2) – CPUisdisabled – MCLKandSMCLKaredisabled – DCO'sdc-generatorremainsenabled – ACLKremainsactive • Low-powermode3(LPM3) – CPUisdisabled – MCLKandSMCLKaredisabled – DCO'sdc-generatorisdisabled – ACLKremainsactive • Low-powermode4(LPM4) – CPUisdisabled – ACLKisdisabled – MCLKandSMCLKaredisabled – DCO'sdc-generatorisdisabled – Crystaloscillatorisstopped 12 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h. Thevectorcontainsthe16-bitaddressoftheappropriateinterrupthandlerinstructionsequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the CPUgoesintoLPM4immediatelyafterpower-up. Table7.InterruptSources SYSTEM INTERRUPTSOURCE INTERRUPTFLAG WORDADDRESS PRIORITY INTERRUPT Power-up PORIFG Externalreset RSTIFG WatchdogTimer+ WDTIFG Reset 0FFFEh 31,highest Flashkeyviolation KEYV PCout-of-range(1) See (2) NMI NMIIFG (non)-maskable, Oscillatorfault OFIFG (non)-maskable, 0FFFCh 30 Flashmemoryaccessviolation ACCVIFG(2)(3) (non)-maskable 0FFFAh 29 0FFF8h 28 Comparator_A+(MSP430F20x1) CAIFG(4) maskable 0FFF6h 27 WatchdogTimer+ WDTIFG maskable 0FFF4h 26 Timer_A2 TACCR0CCIFG(4) maskable 0FFF2h 25 Timer_A2 TACCR1CCIFG.TAIFG(2)(4) maskable 0FFF0h 24 0FFEEh 23 0FFECh 22 ADC10(MSP430F20x2) ADC10IFG(4) maskable 0FFEAh 21 SD16CCTL0SD16OVIFG, SD16_A(MSP430F20x3) SD16CCTL0SD16IFG(2)(4) maskable USI USIIFG,USISTTIFG(2)(4) maskable 0FFE8h 20 (MSP430F20x2,MSP430F20x3) I/OPortP2(twoflags) P2IFG.6toP2IFG.7(2)(4) maskable 0FFE6h 19 I/OPortP1(eightflags) P1IFG.0toP1IFG.7(2)(4) maskable 0FFE4h 18 0FFE2h 17 0FFE0h 16 See (5) 0FFDEhto0FFC0h 15to0,lowest (1) AresetisgeneratediftheCPUtriestofetchinstructionsfromwithinthemoduleregistermemoryaddressrange(0hto01FFh)orfrom withinunusedaddressranges. (2) Multiplesourceflags (3) (non)-maskable:theindividualinterrupt-enablebitcandisableaninterruptevent,butthegeneralinterruptenablecannot. (4) Interruptflagsarelocatedinthemodule. (5) Theinterruptvectorsataddresses0FFDEhto0FFC0harenotusedinthisdeviceandcanbeusedforregularprogramcodeif necessary. Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Special Function Registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided withthisarrangement. Legend rw: Bitcanbereadandwritten. rw-0,1: Bitcanbereadandwritten.ItisresetorsetbyPUC. rw-(0,1): Bitcanbereadandwritten.ItisresetorsetbyPOR. SFRbitisnotpresentindevice. Table8.InterruptEnableRegister1and2 Address 7 6 5 4 3 2 1 0 00h ACCVIE NMIIE OFIE WDTIE rw-0 rw-0 rw-0 rw-0 WDTIE WatchdogTimerinterruptenable.Inactiveifwatchdogmodeisselected.ActiveifWatchdogTimerisconfiguredin intervaltimermode. OFIE Oscillatorfaultinterruptenable NMIIE (Non)maskableinterruptenable ACCVIE Flashaccessviolationinterruptenable Address 7 6 5 4 3 2 1 0 01h Table9.InterruptFlagRegister1and2 Address 7 6 5 4 3 2 1 0 02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw-0 rw-(0) rw-(1) rw-1 rw-(0) WDTIFG Setonwatchdogtimeroverflow(inwatchdogmode)orsecuritykeyviolation. ResetonV power-onoraresetconditionattheRST/NMIpininresetmode. CC OFIFG Flagsetonoscillatorfault. PORIFG Power-OnResetinterruptflag.SetonV power-up. CC RSTIFG Externalresetinterruptflag.SetonaresetconditionatRST/NMIpininresetmode.ResetonV power-up. CC NMIIFG SetviaRST/NMIpin Address 7 6 5 4 3 2 1 0 03h 14 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Memory Organization Table10.MemoryOrganization MSP430F200x MSP430F201x Memory Size 1KBFlash 2KBFlash Main:interruptvector Flash 0FFFFh-0FFC0h 0FFFFh-0FFC0h Main:codememory Flash 0FFFFh-0FC00h 0FFFFh-0F800h Size 256Byte 256Byte Informationmemory Flash 010FFh-01000h 010FFh-01000h 128Byte 128Byte RAM Size 027Fh-0200h 027Fh-0200h 16-bit 01FFh-0100h 01FFh-0100h Peripherals 8-bit 0FFh-010h 0FFh-010h 8-bitSFR 0Fh-00h 0Fh-00h Flash Memory The flash memory can be programmed via the Spy-Bi-Wire/JTAG port, or in-system by the CPU. The CPU can performsingle-byteandsingle-wordwritestotheflashmemory.Featuresoftheflashmemoryinclude: • Flash memory has n segments of main memory and four segments of information memory (A to D) of 64byteseach.Eachsegmentinmainmemoryis512bytesinsize. • Segments0tonmaybeerasedinonestep,oreachsegmentmaybeindividuallyerased. • Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also calledinformationmemory. • Segment A contains calibration data. After reset segment A is protected against programming and erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required. Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions.Forcompletemoduledescriptions,refertotheMSP430F2xxFamilyUser'sGuide. OscillatorandSystemClock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator and an internal digitally-controlled oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic clockmoduleprovidesthefollowingclocksignals: • Auxiliaryclock(ACLK),sourcedeitherfroma32768-HzwatchcrystalortheinternalLFoscillator. • Mainclock(MCLK),thesystemclockusedbytheCPU. • Sub-Mainclock(SMCLK),thesub-systemclockusedbytheperipheralmodules. Table11.DCOCalibrationData(ProvidedFromFactoryinFlashInformation MemorySegmentA) DCOFREQUENCY CALIBRATIONREGISTER SIZE ADDRESS CALBC1_1MHZ byte 010FFh 1MHz CALDCO_1MHZ byte 010FEh CALBC1_8MHZ byte 010FDh 8MHz CALDCO_8MHZ byte 010FCh CALBC1_12MHZ byte 010FBh 12MHz CALDCO_12MHZ byte 010FAh CALBC1_16MHZ byte 010F9h 16MHz CALDCO_16MHZ byte 010F8h Brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and poweroff. DigitalI/O Thereisone8-bitI/Oportimplemented—portP1—andtwobitsofI/OportP2: • AllindividualI/Obitsareindependentlyprogrammable. • Anycombinationofinput,output,andinterruptconditionispossible. • Edge-selectableinterruptinputcapabilityforalltheeightbitsofportP1andthetwobitsofportP2. • Readandwriteaccesstoport-controlregistersissupportedbyallinstructions. • EachI/Ohasanindividuallyprogrammablepulluporpulldownresistor. WatchdogTimer(WDT+) The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generateinterruptsatselectedtimeintervals. 16 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Timer_A2 Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table12.Timer_A2SignalConnections(MSP430F20x1) INPUTPINNUMBER MODULE OUTPUTPINNUMBER DEVICEINPUT MODULE MODULE OUTPUT PW,N RSA SIGNAL INPUTNAME BLOCK SIGNAL PW,N RSA 2-P1.0 1-P1.0 TACLK TACLK ACLK ACLK Timer NA SMCLK SMCLK 2-P1.0 1-P1.0 TACLK INCLK 3-P1.1 2-P1.1 TA0 CCI0A 3-P1.1 2-P1.1 ACLK(internal) CCI0B 7-P1.5 6-P1.5 CCR0 TA0 V GND SS V V CC CC 4-P1.2 3-P1.2 TA1 CCI1A 4-P1.2 3-P1.2 CAOUT CCI1B 8-P1.6 7-P1.6 (internal) CCR1 TA1 V GND 13-P2.6 12-P2.6 SS V V CC CC Table13.Timer_A2SignalConnections(MSP430F20x2,MSP430F20x3) INPUTPINNUMBER MODULE OUTPUTPINNUMBER DEVICEINPUT MODULE MODULE OUTPUT PW,N RSA SIGNAL INPUTNAME BLOCK SIGNAL PW,N RSA 2-P1.0 1-P1.0 TACLK TACLK Timer NA ACLK ACLK SMCLK SMCLK 2-P1.0 1-P1.0 TACLK INCLK 3-P1.1 2-P1.1 TA0 CCI0A CCR0 TA0 3-P1.1 2-P1.1 7-P1.5 6-P1.5 ACLK(internal) CCI0B 7-P1.5 6-P1.5 V GND SS V V CC CC 4-P1.2 3-P1.2 TA1 CCI1A CCR1 TA1 4-P1.2 3-P1.2 8-P1.6 7-P1.6 TA1 CCI1B 8-P1.6 7-P1.6 V GND 13-P2.6 12-P2.6 SS V V CC CC Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Comparator_A+(MSP430F20x1) The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions, battery-voltagesupervision,andmonitoringofexternalanalogsignals. USI(MSP430F20x2andMSP430F20x3) The universal serial interface (USI) module is used for serial data communication and provides the basic hardwareforsynchronouscommunicationprotocolslikeSPIandI2C. ADC10(MSP430F20x2) The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion resulthandling,allowingADCsamplestobeconvertedandstoredwithoutanyCPUintervention. SD16_A(MSP430F20x3) The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit sigma-delta core and reference generator. In addition to external analog inputs, internal V sense and temperature sensors CC arealsoavailable. 18 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 PeripheralFileMap Table14.PeripheralsWithWordAccess ADC10 ADCcontrol0 ADC10CTL0 01B0h (MSP430F20x2) ADCcontrol1 ADC10CTL1 01B2h ADCmemory ADC10MEM 01B4h ADCdatatransferstartaddress ADC10SA 01BCh SD16_A GeneralControl SD16CTL 0100h (MSP430F20x3) Channel0Control SD16CCTL0 0102h Interruptvectorwordregister SD16IV 0110h Channel0conversionmemory SD16MEM0 0112h Timer_A Capture/compareregister TACCR1 0174h Capture/compareregister TACCR0 0172h Timer_Aregister TAR 0170h Capture/comparecontrol TACCTL1 0164h Capture/comparecontrol TACCTL0 0162h Timer_Acontrol TACTL 0160h Timer_Ainterruptvector TAIV 012Eh FlashMemory Flashcontrol3 FCTL3 012Ch Flashcontrol2 FCTL2 012Ah Flashcontrol1 FCTL1 0128h WatchdogTimer+ Watchdog/timercontrol WDTCTL 0120h Table15.PeripheralsWithByteAccess ADC10 Analogenable ADC10AE 04Ah (MSP430F20x2) ADCdatatransfercontrolregister1 ADC10DTC1 049h ADCdatatransfercontrolregister0 ADC10DTC0 048h SD16_A Channel0InputControl SD16INCTL0 0B0h (MSP430F20x3) AnalogEnable SD16AE 0B7h USI USIcontrol0 USICTL0 078h (MSP430F20x2andMSP430F20x3) USIcontrol1 USICTL1 079h USIclockcontrol USICKCTL 07Ah USIbitcounter USICNT 07Bh USIshiftregister USISR 07Ch Comparator_A+ Comparator_A+portdisable CAPD 05Bh (MSP430F20x1) Comparator_A+control2 CACTL2 05Ah Comparator_A+control1 CACTL1 059h BasicClockSystem+ Basicclocksystemcontrol3 BCSCTL3 053h Basicclocksystemcontrol2 BCSCTL2 058h Basicclocksystemcontrol1 BCSCTL1 057h DCOclockfrequencycontrol DCOCTL 056h PortP2 PortP2resistorenable P2REN 02Fh PortP2selection P2SEL 02Eh PortP2interruptenable P2IE 02Dh PortP2interruptedgeselect P2IES 02Ch PortP2interruptflag P2IFG 02Bh PortP2direction P2DIR 02Ah PortP2output P2OUT 029h PortP2input P2IN 028h PortP1 PortP1resistorenable P1REN 027h PortP1selection P1SEL 026h PortP1interruptenable P1IE 025h PortP1interruptedgeselect P1IES 024h PortP1interruptflag P1IFG 023h PortP1direction P1DIR 022h PortP1output P1OUT 021h PortP1input P1IN 020h SpecialFunction SFRinterruptflag2 IFG2 003h SFRinterruptflag1 IFG1 002h SFRinterruptenable2 IE2 001h SFRinterruptenable1 IE1 000h Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Absolute Maximum Ratings(1) VoltageappliedatV toV -0.3Vto4.1V CC SS Voltageappliedtoanypin(2) -0.3VtoV +0.3V CC Diodecurrentatanydeviceterminal ±2mA Unprogrammeddevice -55°Cto150°C T Storagetemperature(3) stg Programmeddevice -55°Cto150°C (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesreferencedtoV .TheJTAGfuse-blowvoltage,V ,isallowedtoexceedtheabsolutemaximumrating.Thevoltageis SS FB appliedtotheTESTpinwhenblowingtheJTAGfuse. (3) HighertemperaturemaybeappliedduringboardsolderingaccordingtothecurrentJEDECJ-STD-020specificationwithpeakreflow temperaturesnothigherthanclassifiedonthedevicelabelontheshippingboxesorreels. Recommended Operating Conditions TypicalvaluesarespecifiedatV =3.3VandT =25°C(unlessotherwisenoted) CC A MIN NOM MAX UNIT Duringprogramexecution 1.8 3.6 V Supplyvoltage V CC Duringflashprogram/erase 2.2 3.6 V Supplyvoltage 0 V SS Iversion -40 85 T Operatingfree-airtemperature °C A Tversion -40 105 V =1.8V, CC dc 6 Dutycycle=50%±10% fSYSTE Processorfrequency(maximumMCLKfrequency)(1)(2) VCC=2.7V, dc 12 MHz Dutycycle=50%±10% M V ≥3.3V, CC dc 16 Dutycycle=50%±10% (1) TheMSP430CPUisclockeddirectlywithMCLK.BoththehighandlowphaseofMCLKmustnotexceedthepulsewidthofthe specifiedmaximumfrequency. (2) Modulesmighthaveadifferentmaximuminputclockspecification.Seethespecificationoftherespectivemoduleinthisdatasheet. Legend: 16MHz Supply voltage range, during flash memory z H programming M − 12MHz y c n e Supply voltage range, u q during program execution e Fr m e 6MHz st y S 1.8V 2.2V 2.7V 3.3V 3.6V Supply Voltage −V Note: Minimumprocessorfrequencyisdefinedbysystemclock.FlashprogramoreraseoperationsrequireaminimumV CC of2.2V. Figure1. SafeOperatingArea 20 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Electrical Characteristics Active Mode Supply Current Into V Excluding External Current CC overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1)(2) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC f =f =f =1MHz, 2.2V 220 270 DCO MCLK SMCLK f =32768Hz, ACLK Programexecutesinflash, Activemode(AM) I BCSCTL1=CALBC1_1MHZ, µA AM,1MHz current(1MHz) DCOCTL=CALDCO_1MHZ, 3V 300 370 CPUOFF=0,SCG0=0, SCG1=0,OSCOFF=0 f =f =f =1MHz, 2.2V 190 DCO MCLK SMCLK f =32768Hz, ACLK ProgramexecutesinRAM, Activemode(AM) I BCSCTL1=CALBC1_1MHZ, µA AM,1MHz current(1MHz) DCOCTL=CALDCO_1MHZ, 3V 260 CPUOFF=0,SCG0=0, SCG1=0,OSCOFF=0 f =f =f =32768Hz/8 -40°Cto85°C 2.2V 1.2 3 MCLK SMCLK ACLK =4096Hz, 105°C 2.2V 6 f =0Hz, DCO Activemode(AM) Programexecutesinflash, -40°Cto85°C 3V 1.6 4 I µA AM,4kHz current(4kHz) SELMx=11,SELS=1, DIVMx=DIVSx=DIVAx=11, CPUOFF=0,SCG0=1, 105°C 3V 7 SCG1=0,OSCOFF=0 f =f =f ≈100kHz, -40°Cto85°C 2.2V 37 50 MCLK SMCLK DCO(0,0) f =0Hz, ACLK 105°C 2.2V 60 Activemode(AM) Programexecutesinflash, I µA AM,100kHz current(100kHz) RSELx=0,DCOx=0, -40°Cto85°C 3V 40 55 CPUOFF=0,SCG0=0, SCG1=0,OSCOFF=1 105°C 3V 65 (1) Allinputsaretiedto0VortoV .Outputsdonotsourceorsinkanycurrent. CC (2) ThecurrentsarecharacterizedwithaMicroCrystalCC4V-T1ASMDcrystalwithaloadcapacitanceof9pF.Theinternalandexternal loadcapacitanceischosentocloselymatchtherequired9pF. Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Typical Characteristics - Active Mode Supply Current (Into V ) CC ACTIVEMODECURRENT vs ACTIVEMODECURRENT V vs CC (T =25°C) DCOFREQUENCY A 5.0 4.0 4.0 fDCO= 16 MHz T = 85°C A mA mA 3.0 − − Active Mode Current 123...000 fDCO= 8 MfHDzCO= 12 MHz Active Mode Current 12..00 VCC= 3 V TA= 8T5A°=C 25°C TA= 25°C V = 2.2 V fDCO= 1 MHz CC 0.0 0.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 4.0 8.0 12.0 16.0 VCC−Supply Voltage−V fDCO−DCO Frequency−MHz Figure2. Figure3. 22 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Low-Power Mode Supply Currents (Into V ) Excluding External Current CC overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) (2) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC f =0MHz, 2.2V 65 80 MCLK f =f =1MHz, SMCLK DCO f =32,768Hz, Low-powermode0 ACLK ILPM0,1MHz (LPM0)current(3) BDCCSOCCTTLL1==CCAALLDBCCO1__11MMHHZZ,, 3V 85 100 µA CPUOFF=1,SCG0=0, SCG1=0,OSCOFF=0 f =0MHz, 2.2V 37 48 MCLK f =f ≈100kHz, SMCLK DCO(0,0) Low-powermode0 f =0Hz, ILPM0,100kHz (LPM0)current(3) RASCLEKLx=0,DCOx=0, 3V 41 52 µA CPUOFF=1,SCG0=0, SCG1=0,OSCOFF=1 f =f =0MHz,f =1 -40°Cto85°C 22 29 MCLK SMCLK DCO MHz, 2.2V 105°C 31 f =32,768Hz, Low-powermode2 ACLK ILPM2 (LPM2)current(4) BCSCTL1=CALBC1_1MHZ, -40°Cto85°C 25 32 µA DCOCTL=CALDCO_1MHZ, 3V CPUOFF=1,SCG0=0, 105°C 34 SCG1=1,OSCOFF=0 -40°C 0.7 1.2 25°C 0.7 1 2.2V 85°C 1.4 2.3 f =f =f =0MHz, DCO MCLK SMCLK Low-powermode3 f =32,768Hz, 105°C 3 6 ILPM3,LFXT1 (LPM3)current(3) CAPCLUKOFF=1,SCG0=1, -40°C 0.9 1.2 µA SCG1=1,OSCOFF=0 25°C 0.9 1.2 3V 85°C 1.6 2.8 105°C 3 7 -40°C 0.4 0.7 25°C 0.5 0.7 2.2V f =f =f =0MHz, 85°C 1 1.6 DCO MCLK SMCLK Low-powermode3 fACLKfrominternalLFoscillator 105°C 2 5 ILPM3,VLO (LPM3)current(4) (CVPLUOO),FF=1,SCG0=1, -40°C 0.5 0.9 µA SCG1=1,OSCOFF=0 25°C 0.6 0.9 3V 85°C 1.3 1.8 105°C 2.5 6 -40°C 0.1 0.5 f =f =f =0MHz, DCO MCLK SMCLK Low-powermode4 f =0Hz, 25°C 0.1 0.5 ILPM4 (LPM4)current(5) CAPCLUKOFF=1,SCG0=1, 85°C 2.2V,3V 0.8 1.5 µA SCG1=1,OSCOFF=1 105°C 2 4 (1) Allinputsaretiedto0VortoV .Outputsdonotsourceorsinkanycurrent. CC (2) ThecurrentsarecharacterizedwithaMicroCrystalCC4V-T1ASMDcrystalwithaloadcapacitanceof9pF. (3) CurrentforbrownoutandWDTclockedbySMCLKincluded. (4) CurrentforbrownoutandWDTclockedbyACLKincluded. (5) Currentforbrownoutincluded. Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Schmitt-Trigger Inputs (Ports P1 and P2) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 0.45V 0.75V CC CC V Positive-goinginputthresholdvoltage 2.2V 1.00 1.65 V IT+ 3V 1.35 2.25 0.25V 0.55V CC CC V Negative-goinginputthresholdvoltage 2.2V 0.55 1.20 V IT- 3V 0.75 1.65 2.2V 0.2 1.0 V Inputvoltagehysteresis(V -V ) V hys IT+ IT- 3V 0.3 1.0 Forpullup:V =V , R Pullup/pulldownresistor IN SS 20 35 50 kΩ Pull Forpulldown:V =V IN CC C Inputcapacitance V =V orV 5 pF I IN SS CC Inputs (Ports P1 and P2) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC PortP1,P2:P1.xtoP2.x,Externaltriggerpulse t(int) Externalinterrupttiming widthtosetinterruptflag(1) 2.2V,3V 20 ns (1) Anexternalsignalsetstheinterruptflageverytimetheminimuminterruptpulsewidtht ismet.Itmaybesetevenwithtriggersignals (int) shorterthant . (int) Leakage Current (Ports P1 and P2) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC I High-impedanceleakagecurrent (1) (2) 2.2V,3V ±50 nA lkg(Px.y) (1) TheleakagecurrentismeasuredwithV orV appliedtothecorrespondingpins,unlessotherwisenoted. SS CC (2) Theleakageofthedigitalportpinsismeasuredindividually.Theportpinisselectedforinputandthepulluporpulldownresistoris disabled. 24 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Outputs (Ports P1 and P2) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC I =-1.5mA(1) 2.2V V -0.25 V (OHmax) CC CC I =-6mA (2) 2.2V V -0.6 V (OHmax) CC CC V High-leveloutputvoltage V OH I =-1.5mA(1) 3V V -0.25 V (OHmax) CC CC I =-6mA(2) 3V V -0.6 V (OHmax) CC CC I =1.5mA(1) 2.2V V V +0.25 (OLmax) SS SS I =6mA(2) 2.2V V V +0.6 (OLmax) SS SS V Low-leveloutputvoltage V OL I =1.5mA(1) 3V V V +0.25 (OLmax) SS SS I =6mA(2) 3V V V +0.6 (OLmax) SS SS (1) Themaximumtotalcurrent,I andI ,foralloutputscombinedshouldnotexceed±12mAtoholdthemaximumvoltagedrop (OHmax) (OLmax) specified. (2) Themaximumtotalcurrent,I andI ,foralloutputscombinedshouldnotexceed±48mAtoholdthemaximumvoltagedrop (OHmax) (OLmax) specified. Output Frequency (Ports P1 and P2) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC f Portoutputfrequency P1.4/SMCLK,C =20pF,R =1kΩ(1) (2) 2.2V 10 MHz Px.y (withload) L L 3V 12 2.2V 12 f Clockoutputfrequency P2.0/ACLK,P1.4/SMCLK,C =20pF(2) MHz Port°CLK L 3V 16 (1) Aresistivedividerwith2×0.5kΩ betweenV andV isusedasload.Theoutputisconnectedtothecentertapofthedivider. CC SS (2) Theoutputvoltagereachesatleast10%and90%V atthespecifiedtogglefrequency. CC Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Typical Characteristics - Outputs overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) LOW-LEVELOUTPUTCURRENT LOW-LEVELOUTPUTCURRENT vs vs LOW-LEVELOUTPUTVOLTAGE LOW-LEVELOUTPUTVOLTAGE 30.0 50.0 VCC= 2.2 V VCC= 3 V mA P1.7 TA= 25°C mA P1.7 TA= 25°C − 25.0 − 40.0 nt nt e e Curr 20.0 TA= 85°C Curr TA= 85°C put put 30.0 ut ut O O el 15.0 el ev ev w-L w-L 20.0 Lo 10.0 Lo al al Typic 5.0 Typic 10.0 − − OL OL I I 0.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOL−Low-Level Output Voltage−V VOL−Low-Level Output Voltage−V Figure4. Figure5. HIGH-LEVELOUTPUTCURRENT HIGH-LEVELOUTPUTCURRENT vs vs HIGH-LEVELOUTPUTVOLTAGE HIGH-LEVELOUTPUTVOLTAGE 0.0 0.0 VCC= 2.2 V VCC= 3 V A P1.7 A P1.7 m m − − nt −5.0 nt −10.0 e e urr urr C C ut ut p −10.0 p −20.0 ut ut O O el el v v e e h-L −15.0 h-L −30.0 g g cal Hi TA= 85°C cal Hi TA= 85°C ypi −20.0 ypi −40.0 T T − − H H O O TA= 25°C I TA= 25°C I −25.0 −50.0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH−High-Level Output Voltage−V VOH−High-Level Output Voltage−V Figure6. Figure7. 26 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 POR and Brownout Reset (BOR)(1)(2) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 0.7× V SeeFigure8 dV /dt≤3V/s V CC(start) CC V (B_IT-) V SeeFigure8throughFigure10 dV /dt≤3V/s 1.71 V (B_IT-) CC V SeeFigure8 dV /dt≤3V/s 70 130 210 mV hys(B_IT-) CC t SeeFigure8 2000 µs d(BOR) PulsedurationneededatRST/NMIpinto 2.2V, t 2 µs (reset) acceptresetinternally 3V (1) ThecurrentconsumptionofthebrownoutmoduleisalreadyincludedintheI currentconsumptiondata.ThevoltagelevelV + CC (B_IT-) V is≤1.8V. hys(B_IT-) (2) Duringpowerup,theCPUbeginscodeexecutionfollowingaperiodoft afterV =V +V .ThedefaultDCOsettings d(BOR) CC (B_IT-) hys(B_IT-) mustnotbechangeduntilV ≥V ,whereV istheminimumsupplyvoltageforthedesiredoperatingfrequency. CC CC(min) CC(min) V CC V hys(B_IT−) V (B_IT−) VCC(start) 1 0 td(BOR) Figure8. POR/BrownoutReset(BOR)vsSupplyVoltage Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Typical Characteristics - POR/Brownout Reset (BOR) 2 VCC tpw 3 V VCC= 3 V Typical Conditions V 1.5 − p) dro 1 C( C VCC(drop) V 0.5 0 0.001 1 1000 1 ns 1 ns tpw−Pulse Width− µs tpw−Pulse Width− µs Figure9.V LevelWithaSquareVoltageDroptoGenerateaPOR/BrownoutSignal CC(drop) VCC tpw 2 3 V VCC= 3 V V 1.5 Typical Conditions − p) o dr 1 C( C VCC(drop) V 0.5 tf= tr 0 0.001 1 1000 tf tr tpw−Pulse Width− µs tpw−Pulse Width− µs Figure10.V LevelWithaTriangleVoltageDroptoGenerateaPOR/BrownoutSignal CC(drop) 28 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Main DCO Characteristics • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlapsRSELx=15. • DCOcontrolbitsDCOxhaveastepsizeasdefinedbyparameterS . DCO • Modulation control bits MODx select how often f is used within the period of 32 DCOCLK DCO(RSEL,DCO+1) cycles. The frequency f is used for the remaining cycles. The frequency is an average equal to: DCO(RSEL,DCO) 32×fDCO(RSEL,DCO) ×fDCO(RSEL,DCO+1) faverage = MOD×fDCO(RSEL,DCO) +(32–MOD)×fDCO(RSEL,DCO+1) DCO Frequency overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC RSELx<14 1.8 3.6 V Supplyvoltage RSELx=14 2.2 3.6 V CC RSELx=15 3.0 3.6 f DCOfrequency(0,0) RSELx=0,DCOx=0,MODx=0 2.2V,3V 0.06 0.14 MHz DCO(0,0) f DCOfrequency(0,3) RSELx=0,DCOx=3,MODx=0 2.2V,3V 0.07 0.17 MHz DCO(0,3) f DCOfrequency(1,3) RSELx=1,DCOx=3,MODx=0 2.2V,3V 0.10 0.20 MHz DCO(1,3) f DCOfrequency(2,3) RSELx=2,DCOx=3,MODx=0 2.2V,3V 0.14 0.28 MHz DCO(2,3) f DCOfrequency(3,3) RSELx=3,DCOx=3,MODx=0 2.2V,3V 0.20 0.40 MHz DCO(3,3) f DCOfrequency(4,3) RSELx=4,DCOx=3,MODx=0 2.2V,3V 0.28 0.54 MHz DCO(4,3) f DCOfrequency(5,3) RSELx=5,DCOx=3,MODx=0 2.2V,3V 0.39 0.77 MHz DCO(5,3) f DCOfrequency(6,3) RSELx=6,DCOx=3,MODx=0 2.2V,3V 0.54 1.06 MHz DCO(6,3) f DCOfrequency(7,3) RSELx=7,DCOx=3,MODx=0 2.2V,3V 0.80 1.50 MHz DCO(7,3) f DCOfrequency(8,3) RSELx=8,DCOx=3,MODx=0 2.2V,3V 1.10 2.10 MHz DCO(8,3) f DCOfrequency(9,3) RSELx=9,DCOx=3,MODx=0 2.2V,3V 1.60 3.00 MHz DCO(9,3) f DCOfrequency(10,3) RSELx=10,DCOx=3,MODx=0 2.2V,3V 2.50 4.30 MHz DCO(10,3) f DCOfrequency(11,3) RSELx=11,DCOx=3,MODx=0 2.2V,3V 3.00 5.50 MHz DCO(11,3) f DCOfrequency(12,3) RSELx=12,DCOx=3,MODx=0 2.2V,3V 4.30 7.30 MHz DCO(12,3) f DCOfrequency(13,3) RSELx=13,DCOx=3,MODx=0 2.2V,3V 6.00 9.60 MHz DCO(13,3) f DCOfrequency(14,3) RSELx=14,DCOx=3,MODx=0 2.2V,3V 8.60 13.9 MHz DCO(14,3) f DCOfrequency(15,3) RSELx=15,DCOx=3,MODx=0 3V 12.0 18.5 MHz DCO(15,3) f DCOfrequency(15,7) RSELx=15,DCOx=7,MODx=0 3V 16.0 26.0 MHz DCO(15,7) Frequencystepbetween S S =f /f 2.2V,3V 1.55 ratio RSEL rangeRSELandRSEL+1 RSEL DCO(RSEL+1,DCO) DCO(RSEL,DCO) Frequencystepbetweentap S S =f /f 2.2V,3V 1.05 1.08 1.12 DCO DCOandDCO+1 DCO DCO(RSEL,DCO+1) DCO(RSEL,DCO) Dutycycle MeasuredatP1.4/SMCLK 2.2V,3V 40 50 60 % Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Calibrated DCO Frequencies - Tolerance at Calibration overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC Frequencytoleranceatcalibration 25°C 3V -1 ±0.2 +1 % BCSCTL1=CALBC1_1MHZ, f 1-MHzcalibrationvalue DCOCTL=CALDCO_1MHZ, 25°C 3V 0.990 1 1.010 MHz CAL(1MHz) Gatingtime:5ms BCSCTL1=CALBC1_8MHZ, f 8-MHzcalibrationvalue DCOCTL=CALDCO_8MHZ, 25°C 3V 7.920 8 8.080 MHz CAL(8MHz) Gatingtime:5ms BCSCTL1=CALBC1_12MHZ, f 12-MHzcalibrationvalue DCOCTL=CALDCO_12MHZ, 25°C 3V 11.88 12 12.12 MHz CAL(12MHz) Gatingtime:5ms BCSCTL1=CALBC1_16MHZ, f 16-MHzcalibrationvalue DCOCTL=CALDCO_16MHZ, 25°C 3V 15.84 16 16.16 MHz CAL(16MHz) Gatingtime:2ms Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC 1-MHztoleranceover 0°Cto85°C 3V -2.5 ±0.5 +2.5 % temperature 8-MHztoleranceover 0°Cto85°C 3V -2.5 ±1.0 +2.5 % temperature 12-MHztoleranceover 0°Cto85°C 3V -2.5 ±1.0 +2.5 % temperature 16-MHztoleranceover 0°Cto85°C 3V -3 ±2.0 +3 % temperature 2.2V 0.97 1 1.03 BCSCTL1=CALBC1_1MHZ, f 1-MHzcalibrationvalue DCOCTL=CALDCO_1MHZ, 0°Cto85°C 3V 0.975 1 1.025 MHz CAL(1MHz) Gatingtime:5ms 3.6V 0.97 1 1.03 2.2V 7.76 8 8.4 BCSCTL1=CALBC1_8MHZ, f 8-MHzcalibrationvalue DCOCTL=CALDCO_8MHZ, 0°Cto85°C 3V 7.8 8 8.2 MHz CAL(8MHz) Gatingtime:5ms 3.6V 7.6 8 8.24 2.2V 11.7 12 12.3 BCSCTL1=CALBC1_12MHZ, f 12-MHzcalibrationvalue DCOCTL=CALDCO_12MHZ, 0°Cto85°C 3V 11.7 12 12.3 MHz CAL(12MHz) Gatingtime:5ms 3.6V 11.7 12 12.3 BCSCTL1=CALBC1_16MHZ, 3V 15.52 16 16.48 f 16-MHzcalibrationvalue DCOCTL=CALDCO_16MHZ, 0°Cto85°C MHz CAL(16MHz) Gatingtime:2ms 3.6V 15 16 16.48 30 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Calibrated DCO Frequencies - Tolerance Over Supply Voltage V CC overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC 1-MHztoleranceoverV 25°C 1.8Vto3.6V -3 ±2 +3 % CC 8-MHztoleranceoverV 25°C 1.8Vto3.6V -3 ±2 +3 % CC 12-MHztoleranceoverV 25°C 2.2Vto3.6V -3 ±2 +3 % CC 16-MHztoleranceoverV 25°C 3Vto3.6V -6 ±2 +3 % CC BCSCTL1=CALBC1_1MHZ, f 1-MHzcalibrationvalue DCOCTL=CALDCO_1MHZ, 25°C 1.8Vto3.6V 0.97 1 1.03 MHz CAL(1MHz) Gatingtime:5ms BCSCTL1=CALBC1_8MHZ, f 8-MHzcalibrationvalue DCOCTL=CALDCO_8MHZ, 25°C 1.8Vto3.6V 7.76 8 8.24 MHz CAL(8MHz) Gatingtime:5ms BCSCTL1=CALBC1_12MHZ, f 12-MHzcalibrationvalue DCOCTL=CALDCO_12MHZ, 25°C 2.2Vto3.6V 11.64 12 12.36 MHz CAL(12MHz) Gatingtime:5ms BCSCTL1=CALBC1_16MHZ, f 16-MHzcalibrationvalue DCOCTL=CALDCO_16MHZ, 25°C 3Vto3.6V 15 16 16.48 MHz CAL(16MHz) Gatingtime:2ms Calibrated DCO Frequencies - Overall Tolerance overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC 1-MHztolerance I:-40°Cto85°C 1.8Vto3.6V -5 ±2 +5 % overall T:-40°Cto105°C 8-MHztolerance I:-40°Cto85°C 1.8Vto3.6V -5 ±2 +5 % overall T:-40°Cto105°C 12-MHz I:-40°Cto85°C 2.2Vto3.6V -5 ±2 +5 % toleranceoverall T:-40°Cto105°C 16-MHz I:-40°Cto85°C 3Vto3.6V -6 ±3 +6 % toleranceoverall T:-40°Cto105°C BCSCTL1=CALBC1_1MHZ, 1-MHz I:-40°Cto85°C f DCOCTL=CALDCO_1MHZ, 1.8Vto3.6V 0.95 1 1.05 MHz CAL(1MHz) calibrationvalue T:-40°Cto105°C Gatingtime:5ms BCSCTL1=CALBC1_8MHZ, 8-MHz I:-40°Cto85°C f DCOCTL=CALDCO_8MHZ, 1.8Vto3.6V 7.6 8 8.4 MHz CAL(8MHz) calibrationvalue T:-40°Cto105°C Gatingtime:5ms BCSCTL1=CALBC1_12MHZ, 12-MHz I:-40°Cto85°C f DCOCTL=CALDCO_12MHZ, 2.2Vto3.6V 11.4 12 12.6 MHz CAL(12MHz) calibrationvalue T:-40°Cto105°C Gatingtime:5ms BCSCTL1=CALBC1_16MHZ, 16-MHz I:-40°Cto85°C f DCOCTL=CALDCO_16MHZ, 3Vto3.6V 15 16 17 MHz CAL(16MHz) calibrationvalue T:-40°Cto105°C Gatingtime:2ms Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Typical Characteristics - Calibrated 1-MHz DCO Frequency CALIBRATED1-MHzFREQUENCY CALIBRATED1-MHzFREQUENCY vs vs TEMPERATURE SUPPLYVOLTAGE 1.03 1.03 1.02 1.02 VCC= 1.8 V 1.01 z 1.01 TA= 105°C H Hz M −M 1.00 VCC= 2.2 V cy− 1.00 TA= 85°C cy VCC= 3.0 V en en qu TA= 25°C u e eq 0.99 Fr 0.99 Fr VCC= 3.6 V TA=−40°C 0.98 0.98 0.97 0.97 −50.0 −25.0 0.0 25.0 50.0 75.0 100.0 1.5 2.0 2.5 3.0 3.5 4.0 TA−Temperature−°C VCC−Supply Voltage−V Figure11. Figure12. 32 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Wake-Up From Lower-Power Modes (LPM3, LPM4) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC BCSCTL1=CALBC1_1MHZ, 2 DCOCTL=CALDCO_1MHZ BCSCTL1=CALBC1_8MHZ, 2.2V,3V 1.5 DCOclockwake-uptime DCOCTL=CALDCO_8MHZ tDCO,LPM3/4 fromLPM3orLPM4(1) BCSCTL1=CALBC1_12MHZ, µs 1 DCOCTL=CALDCO_12MHZ BCSCTL1=CALBC1_16MHZ, 3V 1 DCOCTL=CALDCO_16MHZ CPUwake-uptimefrom 1/f + tCPU,LPM3/4 LPM3orLPM4(2) t MCLK Clock,LPM3/4 (1) TheDCOclockwake-uptimeismeasuredfromtheedgeofanexternalwake-upsignal(forexample,portinterrupt)tothefirstclock edgeobservableexternallyonaclockpin(MCLKorSMCLK). (2) ParameterapplicableonlyifDCOCLKisusedforMCLK. Typical Characteristics - DCO Clock Wake-Up Time From LPM3 or LPM4 DCOWAKE-UPTIMEFROMLPM3 vs DCOFREQUENCY 10.00 s u − e m Ti e k RSELx = 0...11 a W 1.00 RSELx = 12...15 O C D 0.10 0.10 1.00 10.00 DCO Frequency−MHz Figure13. Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Crystal Oscillator, XT1, Low-Frequency Mode(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC LFXT1oscillatorcrystal f XTS=0,LFXT1Sx=0or1 1.8Vto3.6V 32768 Hz LFXT1,LF frequency,LFmode0,1 LFXT1oscillatorlogiclevel f squarewaveinputfrequency, XTS=0,LFXT1Sx=3 1.8Vto3.6V 10000 32768 50000 Hz LFXT1,LF,logic LFmode XTS=0,LFXT1Sx=0, 500 Oscillationallowancefor fLFXT1,LF=32768Hz,CL,eff=6pF OA kΩ LF LFcrystals XTS=0,LFXT1Sx=0, 200 f =32768Hz,C =12pF LFXT1,LF L,eff XTS=0,XCAPx=0 1 Integratedeffectiveload XTS=0,XCAPx=1 5.5 CL,eff capacitance,LFmode(2) XTS=0,XCAPx=2 8.5 pF XTS=0,XCAPx=3 11 XTS=0,MeasuredatP1.0/ACLK, Dutycycle,LFmode 2.2V,3V 30 50 70 % f =32768Hz LFXT1,LF fFault,LF OLFscmilloadtoer(3f)aultfrequency, XTS=0,LFXT1Sx=3(4) 2.2V,3V 10 10000 Hz (1) ToimproveEMIontheXT1oscillator,thefollowingguidelinesshouldbeobserved. (a)Keepthetracebetweenthedeviceandthecrystalasshortaspossible. (b)Designagoodgroundplanearoundtheoscillatorpins. (c)PreventcrosstalkfromotherclockordatalinesintooscillatorpinsXINandXOUT. (d)AvoidrunningPCBtracesunderneathoradjacenttotheXINandXOUTpins. (e)UseassemblymaterialsandpraxistoavoidanyparasiticloadontheoscillatorXINandXOUTpins. (f)Ifconformalcoatingisused,ensurethatitdoesnotinducecapacitive/resistiveleakagebetweentheoscillatorpins. (g)DonotroutetheXOUTlinetotheJTAGheadertosupporttheserialprogrammingadapterasshowninotherdocumentation.This signalisnolongerrequiredfortheserialprogrammingadapter. (2) Includesparasiticbondandpackagecapacitance(approximately2pFperpin). SincethePCBaddsadditionalcapacitance,itisrecommendedtoverifythecorrectloadbymeasuringtheACLKfrequency.Fora correctsetup,theeffectiveloadcapacitanceshouldalwaysmatchthespecificationoftheusedcrystal. (3) FrequenciesbelowtheMINspecificationsetthefaultflag.FrequenciesabovetheMAXspecificationdonotsetthefaultflag. Frequenciesinbetweenmightsettheflag. (4) Measuredwithlogic-levelinputfrequencybutalsoappliestooperationwithcrystals. Internal Very-Low-Power Low-Frequency Oscillator (VLO) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER T V MIN TYP MAX UNIT A CC -40°Cto85°C 4 12 20 f VLOfrequency 2.2V,3V kHz VLO 105°C 22 df /dT VLOfrequencytemperaturedrift(1) I:-40°Cto85°C 2.2V,3V 0.5 %/°C VLO T:-40°Cto105°C df /dV VLOfrequencysupplyvoltagedrift(2) 25°C 1.8Vto3.6V 4 %/V VLO CC (1) Calculatedusingtheboxmethod: I:(MAX(-40to85°C)-MIN(-40to85°C))/MIN(-40to85°C)/(85°C-(-40°C)) T:(MAX(-40to105°C)-MIN(-40to105°C))/MIN(-40to105°C)/(105°C-(-40°C)) (2) Calculatedusingtheboxmethod:(MAX(1.8to3.6V)-MIN(1.8to3.6V))/MIN(1.8to3.6V)/(3.6V-1.8V) Timer_A overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC Internal:SMCLK,ACLK 2.2V 10 f Timer_Aclockfrequency External:TACLK,INCLK MHz TA Dutycycle=50%±10% 3V 16 t Timer_Acapturetiming TA0,TA1 2.2V,3V 20 ns TA,cap 34 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 USI, Universal Serial Interface (MSP430F20x2, MSP430F20x3) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC External:SCLK, 2.2V 10 f USIclockfrequency Dutycycle=50%±10%, MHz USI SPIslavemode 3V 16 USImoduleinI2Cmode, V Low-leveloutputvoltageonSDAandSCL 2.2V,3V V V +0.4 V OL,I2C I =1.5mA SS SS (OLmax) Typical Characteristics, USI Low-Level Output Voltage on SDA and SCL (MSP430F20x2, MSP430F20x3) USILOW-LEVELOUTPUTVOLTAGE USILOW-LEVELOUTPUTVOLTAGE vs vs OUTPUTCURRENT OUTPUTCURRENT 5.0 5.0 VCC= 2.2 V VCC= 3 V TA= 25°C A TA= 25°C A m 4.0 m 4.0 − − Current 3.0 Current 3.0 TA= 85°C Output TA= 85°C Output w-Level 2.0 w-Level 2.0 Lo Lo − 1.0 − 1.0 OL OL I I 0.0 0.0 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0 VOL−Low-Level Output Voltage−V VOL−Low-Level Output Voltage−V Figure14. Figure15. Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Comparator_A+ (MSP430F20x1)(1) overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 2.2V 25 40 I CAON=1,CARSEL=0,CAREF=0 μA (DD) 3V 45 60 CAON=1,CARSEL=0,CAREF=1/2/3, 2.2V 30 50 I μA (Refladder/RefDiode) NoloadatP1.0/CA0andP1.1/CA1 3V 45 71 Common-modeinputvoltage V CAON=1 2.2V,3V 0 V -1 V IC range CC Voltageat0.25V node/ PCA0=1,CARSEL=1,CAREF=1, V CC 2.2V,3V 0.23 0.24 0.25 (Ref025) V NoloadatP1.0/CA0andP1.1/CA1 CC Voltageat0.5V node/ PCA0=1,CARSEL=1,CAREF=2, V CC 2.2V,3V 0.47 0.48 0.5 (Ref050) V NoloadatP1.0/CA0andP1.1/CA1 CC PCA0=1,CARSEL=1,CAREF=3, 2.2V 390 480 540 V SeeFigure20andFigure21 NoloadatP1.0/CA0andP1.1/CA1, mV (RefVT) T =85°C 3V 400 490 550 A V -V Offsetvoltage(2) 2.2V,3V -30 30 mV p S V Inputhysteresis CAON=1 2.2V,3V 0 0.7 1.4 mV hys T =25°C,Overdrive10mV, 2.2V 80 165 300 A Withoutfilter:CAF=0(3) ns Responsetime (seeFigure16andFigure17) 3V 70 120 240 t (response) (low-highandhigh-low) T =25°C,Overdrive10mV, 2.2V 1.4 1.9 2.8 A Withfilter:CAF=1(3) μs (seeFigure16andFigure17) 3V 0.9 1.5 2.2 (1) TheleakagecurrentfortheComparator_A+terminalsisidenticaltoI specification. lkg(Px.y) (2) TheinputoffsetvoltagecanbecancelledbyusingtheCAEXbittoinverttheComparator_A+inputsonsuccessivemeasurements.The twosuccessivemeasurementsarethensummedtogether. (3) ResponsetimemeasuredatP1.3/CAOUT 36 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 0 V VCC 0 1 CAF CAON Low Pass Filter To Internal Modules 0 0 V+ + V− _ 1 1 CAOUT Set CAIFG Flag τ≈2.0µs Figure16. BlockDiagramofComparator_A+Module Overdrive VCAOUT V− 400 mV V+ t(response) Figure17. OverdriveDefinition Figure18. Comparator_A+ShortResistanceTestCondition CASHORT CA0 CA1 1 + VIN Comparator_A+ IOUT= 10µA − CASHORT=1 Figure19. Comparator_A+ShortResistanceTestCondition Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Typical Characteristics, Comparator_A+ (MSP430x20x1) V V (RefVT) (RefVT) vs vs TEMPERATURE TEMPERATURE (V =3V) (V =2.2V) CC CC 650 650 VCC= 3 V VCC= 2.2 V V 600 V 600 m m − − Volts Typical Volts Typical Reference 550500 Reference 550500 − − T) T) V V F F E E V(R 450 V(R 450 400 400 −45 −25 −5 15 35 55 75 95 115 −45 −25 −5 15 35 55 75 95 115 TA−Free-AirTemperature− °C TA−Free-AirTemperature− °C Figure20. Figure21. SHORTRESISTANCE vs V /V IN CC 100.00 s m VCC= 1.8V h kO VCC= 2.2V − ce VCC= 3.0V n 10.00 a st si e R ort h S VCC= 3.6V 1.00 0.0 0.2 0.4 0.6 0.8 1.0 VIN/VCC−Normalized Input Voltage−V/V Figure22. 38 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 10-Bit ADC, Power Supply and Input Range Conditions (MSP430F20x2)(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC Analogsupplyvoltage V V =0V 2.2 3.6 V CC range SS AllAxterminals, Analoginputvoltage VAx range(2) Analoginputsselectedin 0 VCC V ADC10AEregister f =5MHz, 2.2V 0.52 1.05 ADC10CLK I ADC10supplycurrent(3) ADC10ON=1,REFON=0, I:-40°Cto85°C mA ADC10 ADC10SHT0=1, T:-40°Cto105°C 3V 0.6 1.2 ADC10SHT1=0,ADC10DIV=0 f =5MHz, ADC10CLK ADC10ON=0,REF2_5V=0, 2.2V,3V 0.25 0.4 Referencesupply REFON=1,REFOUT=0 I:-40°Cto85°C I current,referencebuffer mA REF+ disabled(4) fADC10CLK=5MHz, T:-40°Cto105°C ADC10ON=0,REF2_5V=1, 3V 0.25 0.4 REFON=1,REFOUT=0 f =5MHz -40°Cto85°C 2.2V,3V 1.1 1.4 Referencebuffersupply ADC10CLK ADC10ON=0,REFON=1, I currentwith mA REFB,0 ADC10SR=0(4) REF2_5V=0,REFOUT=1, 105°C 2.2V,3V 1.8 ADC10SR=0 f =5MHz, -40°Cto85°C 2.2V,3V 0.5 0.7 Referencebuffersupply ADC10CLK ADC10ON=0,REFON=1, I currentwith mA REFB,1 ADC10SR=1(4) REF2_5V=0,REFOUT=1, 105°C 2.2V,3V 0.8 ADC10SR=1 OnlyoneterminalAxselectedat I:-40°Cto85°C C Inputcapacitance 27 pF I atime T:-40°Cto105°C InputMUXON I:-40°Cto85°C R 0V≤V ≤V 2.2V,3V 2000 Ω I resistance Ax CC T:-40°Cto105°C (1) TheleakagecurrentisdefinedintheleakagecurrenttablewithPx.x/Axparameter. (2) TheanaloginputvoltagerangemustbewithintheselectedreferencevoltagerangeV toV forvalidconversionresults. R+ R- (3) TheinternalreferencesupplycurrentisnotincludedincurrentconsumptionparameterI . ADC10 (4) TheinternalreferencecurrentissuppliedviaterminalV .ConsumptionisindependentoftheADC10ONcontrolbit,unlessa CC conversionisactive.TheREFONbitenablesthebuilt-inreferencetosettlebeforestartinganA/Dconversion. Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com 10-Bit ADC, Built-In Voltage Reference (MSP430F20x2) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC I ≤1mA,REF2_5V=0 2.2 Positivebuilt-in VREF+ V referenceanalog I ≤0.5mA,REF2_5V=1 2.8 V CC,REF+ VREF+ supplyvoltagerange I ≤1mA,REF2_5V=1 2.9 VREF+ Positivebuilt-in IVREF+≤IVREF+max,REF2_5V=0 2.2V,3V 1.41 1.5 1.59 V V REF+ referencevoltage I ≤I max,REF2_5V=1 3V 2.35 2.5 2.65 VREF+ VREF+ MaximumV load 2.2V ±0.5 I REF+ mA LD,VREF+ current 3V ±1 I =500µA±100µA, VREF+ AnaloginputvoltageV ≈0.75V, 2.2V,3V ±2 Ax REF2_5V=0 V loadregulation LSB REF+ I =500µA±100µA, VREF+ AnaloginputvoltageV ≈1.25V, 3V ±2 Ax REF2_5V=1 I =100µAto900µA, ADC10SR=0 400 VREF+ V loadregulation V ≈0.5xV , REF+ Ax REF+ 3V ns responsetime Errorofconversionresult ADC10SR=1 2000 ≤1LSB Maximumcapacitance I ≤±1mA, CVREF+ atpinV (1) RVEREFFO+N=1,REFOUT=1 2.2V,3V 100 pF REF+ Temperature I =constantwith T VREF+ 2.2V,3V ±100 ppm/°C CREF+ coefficient 0mA≤I ≤1mA VREF+ Settlingtimeofinternal I =0.5mA,REF2_5V=0, tREFON referencevoltage(2) RVEREFFO+N=0to1 3.6V 30 µs I =0.5mA, ADC10SR=0 1 VREF+ REF2_5V=0, 2.2V REFON=1, ADC10SR=1 2.5 Settlingtimeof REFBURST=1 tREFBURST referencebuffer(2) I =0.5mA, ADC10SR=0 2 µs VREF+ REF2_5V=1, 3V REFON=1, ADC10SR=1 4.5 REFBURST=1 (1) Thecapacitanceappliedtotheinternalbufferoperationalamplifier,ifswitchedtoterminalP1.4/SMCLK/A4/VREF+/VeREF+/TCK (REFOUT=1),mustbelimited;otherwise,thereferencebuffermaybecomeunstable. (2) Theconditionisthattheerrorinaconversionstartedaftert ort islessthan±0.5LSB. REFON RefBuf 40 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 10-Bit ADC, External Reference (MSP430F20x2)(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC V >V , eREF+ eREF- 1.4 V Positiveexternalreferenceinput SREF1=1,SREF0=0 CC VeREF+ voltagerange(2) V ≤V ≤V -0.15V, V SeRREEFF-1=e1R,ESFR+EF0CC=1(3) 1.4 3 Negativeexternalreferenceinput VeREF- voltagerange(4) VeREF+>VeREF- 0 1.2 V Differentialexternalreference ΔV inputvoltagerange V >V (5) 1.4 V V eREF eREF+ eREF- CC ΔV =V -V eREF eREF+ eREF- 0V≤V ≤V , eREF+ CC ±1 SREF1=1,SREF0=0 I StaticinputcurrentintoV 2.2V,3V µA VeREF+ eREF+ 0V≤V ≤V -0.15V≤3V, SREF1e=RE1F,+SRECFC0=1(3) 0 I StaticinputcurrentintoV 0V≤V ≤V 2.2V,3V ±1 µA VeREF- eREF- eREF- CC (1) Theexternalreferenceisusedduringconversiontochargeanddischargethecapacitancearray.Theinputcapacitance,C,isalsothe I dynamicloadforanexternalreferenceduringconversion.Thedynamicimpedanceofthereferencesupplyshouldfollowthe recommendationsonanalog-sourceimpedancetoallowthechargetosettlefor10-bitaccuracy. (2) Theaccuracylimitstheminimumpositiveexternalreferencevoltage.Lowerreferencevoltagelevelsmaybeappliedwithreduced accuracyrequirements. (3) Underthiscondition,theexternalreferenceisinternallybuffered.Thereferencebufferisactiveandrequiresthereferencebuffersupply currentI .ThecurrentconsumptioncanbelimitedtothesampleandconversionperiodwithREBURST=1. REFB (4) Theaccuracylimitsthemaximumnegativeexternalreferencevoltage.Higherreferencevoltagelevelsmaybeappliedwithreduced accuracyrequirements. (5) Theaccuracylimitstheminimumexternaldifferentialreferencevoltage.Lowerdifferentialreferencevoltagelevelsmaybeappliedwith reducedaccuracyrequirements. 10-Bit ADC, Timing Parameters (MSP430F20x2) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC ADC10inputclock Forspecifiedperformanceof ADC10SR=0 0.45 6.3 f 2.2V,3V MHz ADC10CLK frequency ADC10linearityparameters ADC10SR=1 0.45 1.5 ADC10built-in ADC10DIVx=0,ADC10SSELx=0, f 2.2V,3V 3.7 6.3 MHz ADC10OSC oscillatorfrequency f =f ADC10CLK ADC10OSC ADC10built-inoscillator,ADC10SSELx=0, 2.2V,3V 2.06 3.51 f =f ADC10CLK ADC10OSC tCONVERT Conversiontime 13× µs f fromACLK,MCLKorSMCLK, ADC10CLK ADC10DIVx× ADC10SSELx≠0 1/f ADC10CLK Turnonsettlingtime tADC10ON oftheADC(1) 100 ns (1) Theconditionisthattheerrorinaconversionstartedaftert islessthan±0.5LSB.Thereferenceandinputsignalarealready ADC10ON settled. Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com 10-Bit ADC, Linearity Parameters (MSP430F20x2) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC E Integrallinearityerror 2.2V,3V ±1 LSB I E Differentiallinearityerror 2.2V,3V ±1 LSB D E Offseterror SourceimpedanceR <100Ω 2.2V,3V ±1 LSB O S E Gainerror 2.2V,3V ±1.1 ±2 LSB G E Totalunadjustederror 2.2V,3V ±2 ±5 LSB T 10-Bit ADC, Temperature Sensor and Built-In V (MSP430F20x2)(1) MID overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC Temperaturesensorsupply REFON=0,INCHx=0Ah, 2.2V 40 120 ISENSOR current(1) TA=25°C 3V 60 160 µA TC ADC10ON=1,INCHx=0Ah(2) 2.2V,3V 3.44 3.55 3.66 mV/°C SENSOR V Sensoroffsetvoltage ADC10ON=1,INCHx=0Ah(2) -100 100 mV Offset,Sensor Temperaturesensorvoltageat 1265 1365 1465 T =105°C(Tversiononly) A Temperaturesensorvoltageat 1195 1295 1395 T =85°C V Sensoroutputvoltage(3) A 2.2V,3V mV SENSOR Temperaturesensorvoltageat 985 1085 1185 T =25°C A Temperaturesensorvoltageat 895 995 1095 T =0°C A Sampletimerequiredif ADC10ON=1,INCHx=0Ah, tSENSOR(sample) channel10isselected(4) Errorofconversionresult≤1LSB 2.2V,3V 30 µs Currentintodividerat 2.2V N/A IVMID channel11(4) ADC10ON=1,INCHx=0Bh 3V N/A µA ADC10ON=1,INCHx=0Bh, 2.2V 1.06 1.1 1.14 V V divideratchannel11 V MID CC VMID≈0.5×VCC 3V 1.46 1.5 1.54 Sampletimerequiredif ADC10ON=1,INCHx=0Bh, 2.2V 1400 tVMID(sample) channel11isselected(5) Errorofconversionresult≤1LSB 3V 1220 ns (1) ThesensorcurrentI isconsumedif(ADC10ON=1andREFON=1),or(ADC10ON=1andINCH=0Ahandsamplesignalis SENSOR high).WhenREFON=1,I isincludedinI .WhenREFON=0,I appliesduringconversionofthetemperaturesensor SENSOR REF+ SENSOR input(INCH=0Ah). (2) Thefollowingformulacanbeusedtocalculatethetemperaturesensoroutputvoltage: V =TC (273+T[°C])+V [mV]or Sensor,typ Sensor Offset,sensor V =TC T[°C]+V (T =0°C)[mV] Sensor,typ Sensor Sensor A (3) Resultsbasedoncharacterizationand/orproductiontest,notTC orV . Sensor Offset,sensor (4) Noadditionalcurrentisneeded.TheV isusedduringsampling. MID (5) Theontime,t ,isincludedinthesamplingtime,t ;noadditionalontimeisneeded. VMID(on) VMID(sample) 42 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 SD16_A, Power Supply and Recommended Operating Conditions (MSP430F20x3) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC Analogsupplyvoltage AV =DV =V , AV CC CC CC 2.5 3.6 V CC range AV =DV =V =0V SS SS SS -40°Cto85°C 730 1050 GAIN:1,2 105°C 1170 SD16LP=0, -40°Cto85°C 810 1150 f =1MHz, GAIN:4,8,16 SD16 SD16OSR=256 105°C 1300 Analogsupplycurrent -40°Cto85°C 1160 1700 I includinginternal GAIN:32 3V µA SD16 reference 105°C 1850 -40°Cto85°C 720 1030 GAIN:1 SD16LP=1, 105°C 1160 f =0.5MHz, SD16 SD16OSR=256 -40°Cto85°C 810 1150 GAIN:32 105°C 1300 SD16LP=0 0.03 1 1.1 SD16inputclock (Lowpowermodedisabled) f 3V MHz SD16 frequency SD16LP=1 0.03 0.5 (Lowpowermodeenabled) SD16_A, Input Range (MSP430F20x3) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC -(V /2)/ +(V /2)/ Bipolarmode,SD16UNI=0 REF REF Differentialfullscaleinputvoltage GAIN GAIN VID,FSR range(1) +(V /2)/ mV Unipolarmode,SD16UNI=1 0 REF GAIN SD16GAINx=1 ±500 SD16GAINx=2 ±250 Differentialinputvoltagerangefor SD16GAINx=4 ±125 VID specifiedperformance(1) SD16REFON=1 SD16GAINx=8 ±62 mV SD16GAINx=16 ±31 SD16GAINx=32 ±15 Inputimpedance SD16GAINx=1 200 Z f =1MHz 3V kΩ I (oneinputpintoAVSS) SD16 SD16GAINx=32 75 Differentialinputimpedance SD16GAINx=1 300 400 Z f =1MHz 3V kΩ ID (IN+toIN-) SD16 SD16GAINx=32 100 150 V Absoluteinputvoltagerange AV -0.1 AV V I SS CC Common-modeinputvoltage V AV -0.1 AV V IC range SS CC (1) TheanaloginputrangedependsonthereferencevoltageappliedtoV .IfV issourcedexternally,thefull-scalerangeisdefined REF REF byV =+(V /2)/GAINandV =-(V /2)/GAIN.Theanaloginputrangeshouldnotexceed80%ofV orV . FSR+ REF FSR- REF FSR+ FSR- Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 43

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com SD16_A, SINAD Performance (f = 1 MHz, SD16OSRx = 1024, SD16REFON = 1) SD16 (MSP430F20x3) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PW,N RSA PARAMETER TESTCONDITIONS V UNIT CC MIN TYP MIN TYP SD16GAINx=1, Signalamplitude:V =500mV, 84 85 86 87 IN Signalfrequency:f =100Hz IN SD16GAINx=2, Signalamplitude:V =250mV, 82 83 82 83 IN Signalfrequency:f =100Hz IN SD16GAINx=4, Signalamplitude:V =125mV, 78 79 78 79 IN Signal-to-noise+distortionratio Signalfrequency:fIN=100Hz SINAD 3V dB 1024 (OSR=1024) SD16GAINx=8, Signalamplitude:V =62mV, 73 74 73 74 IN Signalfrequency:f =100Hz IN SD16GAINx=16, Signalamplitude:V =31mV, 68 69 68 69 IN Signalfrequency:f =100Hz IN SD16GAINx=32, Signalamplitude:V =15mV, 62 63 62 63 IN Signalfrequency:f =100Hz IN SD16_A, SINAD Performance (f = 1 MHz, SD16OSRx = 256, SD16REFON = 1) (MSP430F20x3) SD16 overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PW,N RSA PARAMETER TESTCONDITIONS V UNIT CC MIN TYP MIN TYP SD16GAINx=1, Signalamplitude:V =500mV, 80 81 82 83 IN Signalfrequency:f =100Hz IN SD16GAINx=2, Signalamplitude:V =250mV, 74 75 76 77 IN Signalfrequency:f =100Hz IN SD16GAINx=4, Signalamplitude:V =125mV, 69 70 71 72 IN Signal-to-noise+distortionratio Signalfrequency:fIN=100Hz SINAD 3V dB 256 (OSR=256) SD16GAINx=8, Signalamplitude:V =62mV, 63 64 67 68 IN Signalfrequency:f =100Hz IN SD16GAINx=16, Signalamplitude:V =31mV, 58 59 63 64 IN Signalfrequency:f =100Hz IN SD16GAINx=32, Signalamplitude:V =15mV, 52 53 57 58 IN Signalfrequency:f =100Hz IN 44 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Typical Characteristics, SD16_A SINAD Performance Over OSR (MSP430F20x3) SINADPERFORMANCE vs OSR (f =1MHz,SD16REFON=1,SD16GAINx=1) SD16 90.0 85.0 80.0 B 75.0 d − D A N 70.0 SI 65.0 RSA PW, or N 60.0 55.0 10.00 100.00 1000.00 OSR Figure23. SD16_A, Performance (f = 1 MHz, SD16OSRx = 256, SD16REFON = 1) (MSP430F20x3) SD16 overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC SD16GAINx=1 0.97 1.00 1.02 SD16GAINx=2 1.90 1.96 2.02 SD16GAINx=4 3.76 3.86 3.96 G Nominalgain 3V SD16GAINx=8 7.36 7.62 7.84 SD16GAINx=16 14.56 15.04 15.52 SD16GAINx=32 27.20 28.35 29.76 ΔG/ΔT Gaintemperaturedrift SD16GAINx=1(1) 3V 15 ppm/°C SD16GAINx=1 ±0.2 E Offseterror 3V %FSR OS SD16GAINx=32 ±1.5 Offseterrortemperature SD16GAINx=1 ±4 ±20 ppm ΔE /ΔT 3V OS coefficient SD16GAINx=32 ±20 ±100 FSR/°C SD16GAINx=1, Common-modeinputsignal: >90 Common-moderejection VID=500mV,fIN=50Hz,100Hz CMRR 3V dB ratio SD16GAINx=32, Common-modeinputsignal: >75 V =16mV,f =50Hz,100Hz ID IN SD16GAINx=1,V =500mV, DCPSR DCpowersupplyrejection V =2.5Vto3.6VIN(2) 2.5Vto3.6V 0.35 %/V CC ACpowersupplyrejection SD16GAINx=1, ACPSRR 3V >80 dB ratio V =3V±100mV,f =50Hz CC IN (1) Calculatedusingtheboxmethod:(MAX(-40°Cto85°C)-MIN(-40°Cto85°C))/MIN(-40°Cto85°C)/(85°C-(-40°C)) (2) CalculatedusingtheADCoutputcodeandtheboxmethod: (MAX-code(2.5Vto3.6V)-MIN-code(2.5Vto3.6V))/MIN-code(2.5Vto3.6V)/(3.6V-2.5V) Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 45

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com SD16_A, Built-In Voltage Reference (MSP430F20x3) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC SD16REFON=1, V Internalreferencevoltage 3V 1.14 1.20 1.26 V REF SD16VMIDON=0 SD16REFON=1, -40°Cto85°C 3V 190 280 I Referencesupplycurrent µA REF SD16VMIDON=0 105°C 3V 295 SD16REFON=1, TC Temperaturecoefficient 3V 18 50 ppm/°C SD16VMIDON=0 SD16REFON=1, CREF VREFloadcapacitance SD16VMIDON=0(1) 100 nF SD16REFON=1, I V maximumloadcurrent 3V ±200 nA LOAD REF(I) SD16VMIDON=0 SD16REFON=0→1, t Turn-ontime SD16VMIDON=0, 3V 5 ms ON C =100nF REF SD16REFON=1, DCpowersupplyrejection DCPSR SD16VMIDON=0, 2.5Vto3.6V 100 µV/V ΔV /ΔV REF CC V =2.5Vto3.6V CC (1) ThereisnocapacitancerequiredonV .However,acapacitanceofatleast100nFisrecommendedtoreduceanyreferencevoltage REF noise. SD16_A, Reference Output Buffer (MSP430F20x3) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS T V MIN TYP MAX UNIT A CC SD16REFON=1, V Referencebufferoutputvoltage 3V 1.2 V REF,BUF SD16VMIDON=1 Referencesupply+reference SD16REFON=1, -40°Cto85°C 385 600 I 3V µA REF,BUF outputbufferquiescentcurrent SD16VMIDON=1 105°C 660 Requiredloadcapacitanceon SD16REFON=1, C 470 nF REF(O) V SD16VMIDON=1 REF SD16REFON=1, I MaximumloadcurrentonV 3V ±1 mA LOAD,Max REF SD16VMIDON=1 Maximumvoltagevariationvs |I |=0to1mA 3V -15 +15 mV loadcurrent LOAD SD16REFON=0→1, t Turnontime SD16VMIDON=1, 3V 100 µs ON C =470nF REF SD16_A, External Reference Input (MSP430F20x3) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC V Inputvoltagerange SD16REFON=0 3V 1 1.25 1.5 V REF(I) I Inputcurrent SD16REFON=0 3V 50 nA REF(I) 46 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 SD16_A, Temperature Sensor(1) (MSP430F20x3) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC TC Sensortemperaturecoefficient 1.18 1.32 1.46 mV/°C Sensor V Sensoroffsetvoltage -100 100 mV Offset,Sensor Temperaturesensorvoltageat 435 475 515 T =85°C A V Sensoroutputvoltage(2) Temperaturesensorvoltageat 3V 355 395 435 mV Sensor T =25°C A Temperaturesensorvoltageat 320 360 400 T =0°C A (1) ValuesarenotbasedoncalculationsusingTC orV butonmeasurements. Sensor Offset,sensor (2) Thefollowingformulacanbeusedtocalculatethetemperaturesensoroutputvoltage: V =TC (273+T[°C])+V [mV]or Sensor,typ Sensor Offset,sensor V =TC T[°C]+V (T =0°C)[mV] Sensor,typ Sensor Sensor A Flash Memory overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) TEST PARAMETER V MIN TYP MAX UNIT CONDITIONS CC V Programanderasesupplyvoltage 2.2 3.6 V CC(PGM/ERASE) f Flashtiminggeneratorfrequency 257 476 kHz FTG I SupplycurrentfromV duringprogram 2.2V/3.6V 1 5 mA PGM CC I SupplycurrentfromV duringerase 2.2V/3.6V 1 7 mA ERASE CC t Cumulativeprogramtime(1) 2.2V/3.6V 10 ms CPT t Cumulativemasserasetime 2.2V/3.6V 20 ms CMErase Program/eraseendurance 104 105 cycles t Dataretentionduration T =25°C 100 years Retention J t Wordorbyteprogramtime (2) 30 t Word FTG t Blockprogramtimeforfirstbyteorword (2) 25 t Block,0 FTG t Blockprogramtimeforeachadditionalbyteor (2) 18 t Block,1-63 word FTG t Blockprogramend-sequencewaittime (2) 6 t Block,End FTG t Masserasetime (2) 10593 t MassErase FTG t Segmenterasetime (2) 4819 t SegErase FTG (1) Thecumulativeprogramtimemustnotbeexceededwhenwritingtoa64-byteflashblock.Thisparameterappliestoallprogramming methods:individualword/bytewriteandblockwritemodes. (2) ThesevaluesarehardwiredintotheFlashController'sstatemachine(t =1/f ). FTG FTG RAM overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT V RAMretentionsupplyvoltage (1) CPUhalted 1.6 V (RAMh) (1) ThisparameterdefinestheminimumsupplyvoltageV whenthedatainRAMremainsunchanged.Noprogramexecutionshould CC happenduringthissupplyvoltagecondition. Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 47

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com JTAG and Spy-Bi-Wire Interface overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER V MIN TYP MAX UNIT CC f Spy-Bi-Wireinputfrequency 2.2V,3V 0 20 MHz SBW t Spy-Bi-Wirelowclockpulselength 2.2V,3V 0.025 15 µs SBW,Low t Spy-Bi-Wireenabletime(TESThightoacceptanceoffirstclockedge(1)) 2.2V,3V 1 µs SBW,En t Spy-Bi-Wirereturntonormaloperationtime 2.2V,3V 15 100 µs SBW,Ret 2.2V 0 5 MHz f TCKinputfrequency(2) TCK 3V 0 10 MHz R InternalpulldownresistanceonTEST 2.2V,3V 25 60 90 kΩ Internal (1) ToolsaccessingtheSpy-Bi-Wireinterfaceneedtowaitforthemaximumt timeafterpullingtheTEST/SBWCLKpinhighbefore SBW,En applyingthefirstSBWCLKclockedge. (2) f mayberestrictedtomeetthetimingrequirementsofthemoduleselected. TCK JTAG Fuse(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN MAX UNIT V Supplyvoltageduringfuse-blowcondition T =25°C 2.5 V CC(FB) A V VoltagelevelonTESTforfuseblow 6 7 V FB I SupplycurrentintoTESTduringfuseblow 100 mA FB t Timetoblowfuse 1 ms FB (1) Oncethefuseisblown,nofurtheraccesstotheJTAG/Test,Spy-Bi-Wire,andemulationfeatureispossible,andJTAGisswitchedto bypassmode. 48 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 APPLICATION INFORMATION, MSP430F20X1 Port P1 (P1.0 to P1.3) Pin Schematics, MSP430F20x1 Pad Logic To Comparator_A+ From Comparator_A+ CAPD.x P1REN.x DVSS 0 DVCC 1 1 P1DIR.x 0 Direction 1 0:Input 1:Output P1OUT.x 0 Module X OUT 1 P1.0/TACLK/ACLK/CA0 P1.1/TA0/CA1 P1SEL.x Bus P1.2/TA1/CA2 Keeper P1.3/CAOUT/CA3 P1IN.x EN EN Module X IN D P1IE.x EN P1IRQ.x Q Set P1IFG.x P1SEL.x Interrupt Edge P1IES.x Select Table16.ControlSignal"FromComparator_A+" SIGNAL"FromComparator_A+"=1(1) PINNAME FUNCTION P2CA4 P2CA0 P2CA3 P2CA2 P2CA1 P1.0/TACLK/ACLK/CA0 CA0 0 1 N/A N/A N/A P1.1/TA0/CA1 CA1 1 0 0 0 1 OR P1.2/TA1/CA2 CA2 1 1 0 1 0 P1.3/CAOUT/CA3 CA3 N/A N/A 0 1 1 (1) N/A=Notavailableornotapplicable Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 49

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Table17.PortP1(P1.0toP1.3)PinFunctions,MSP430F20x1 CONTROLBITS/SIGNALS(1) PINNAME(P1.x) x FUNCTION P1DIR.x P1SEL.x CAPD.x P1.0(2)input/output 0/1 0 0 Timer_A2.TACLK/INCLK 0 1 0 P1.0/TACLK/ACLK/CA0 0 ACLK 1 1 0 CA0(3) X X 1 P1.1(2)input/output 0/1 0 0 Timer_A2.CCI0A 0 1 0 P1.1/TA0/CA1 1 Timer_A2.TA0 1 1 0 CA1(3) X X 1 P1.2(2)input/output 0/1 0 0 Timer_A2.CCI1A 0 1 0 P1.2/TA1/CA2 2 Timer_A2.TA1 1 1 0 CA2(3) X X 1 P1.3(2)input/output 0/1 0 0 N/A 0 1 0 P1.3/CAOUT/CA3 3 CAOUT 1 1 0 CA3(3) X X 1 (1) X=Don'tcare (2) Defaultafterreset(PUC/POR) (3) SettingtheCAPD.xbitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplyinganalog signals.SelectingtheCAxinputpintothecomparatormultiplexerwiththeP2CAxbitsautomaticallydisablestheinputbufferforthatpin, regardlessofthestateoftheassociatedCAPD.xbit. 50 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Port P1 (P1.4 to P1.6) Pin Schematics, MSP430F20x1 Pad Logic To Comparator_A+ From Comparator_A+ CAPD.x P1REN.x DVSS 0 DVCC 1 1 P1DIR.x 0 Direction 1 0:Input 1:Output P1OUT.x 0 Module X OUT 1 P1.4/SMCLK/CA4/TCK P1.5/TA0/CA5/TMS P1SEL.x Bus P1.6/TA1/CA6/TDI Keeper P1IN.x EN EN Module X IN D P1IE.x EN P1IRQ.x Q Set P1IFG.x P1SEL.x Interrupt Edge P1IES.x Select To JTAG From JTAG Table18.ControlSignal"FromComparator_A+" SIGNAL"FromComparator_A+"=1 PINNAME FUNCTION P2CA3 P2CA2 P2CA1 P1.4/SMCLK/CA4/TCK CA4 1 0 0 P1.5/TA0/CA5/TMS CA5 1 0 1 P1.6/TA1/CA6/TDI CA6 1 1 0 Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 51

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Port P1 (P1.7) Pin Schematics, MSP430F20x1 Pad Logic To Comparator_A+ From Comparator_A+ CAPD.7 P1REN.7 DVSS 0 DVCC 1 1 P1DIR.7 0 Direction 1 0:Input 1:Output P1OUT.7 0 Module X OUT 1 P1.7/CAOUT/CA7/TDO/TDI P1SEL.7 Bus Keeper P1IN.7 EN EN Module X IN D P1IE.7 EN P1IRQ.7 Q Set P1IFG.7 P1SEL.7 Interrupt Edge P1IES.7 Select To JTAG From JTAG From JTAG From JTAG (TDO) Table19.ControlSignal"FromComparator_A+" SIGNAL"FromComparator_A+"=1 PINNAME FUNCTION P2CA3 P2CA2 P2CA1 P1.7/CAOUT/CA7/TDO/TDI CA7 1 1 1 52 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Table20.PortP1(P1.4toP1.7)PinFunctions,MSP430F20x1 CONTROLBITS/SIGNALS(2) PINNAME(P1.x) x FUNCTION(1) P1DIR.x P1SEL.x CAPD.x JTAGMode P1.4(3)input/output 0/1 0 0 0 N/A 0 1 0 0 P1.4/SMCLK/CA4/TCK 4 SMCLK 1 1 0 0 CA4(4) X X 1 0 TCK(5) X X X 1 P1.5(3)input/output 0/1 0 0 0 N/A 0 1 0 0 P1.5/TA0/CA5/TMS 5 Timer_A2.TA0 1 1 0 0 CA5(4) X X 1 0 TMS(5) X X X 1 P1.6(3)input/output 0/1 0 0 0 N/A 0 1 0 0 P1.6/TA1/CA6/TDI 6 Timer_A2.TA1 1 1 0 0 CA6(4) X X 1 0 TDI(5) X X X 1 P1.7(3)input/output 0/1 0 0 0 N/A 0 1 0 0 P1.7/CAOUT/CA7/TDO/TDI 7 CAOUT 1 1 0 0 CA7(4) X X 1 0 TDO/TDI(5)(6) X X X 1 (1) N/A=Notavailableornotapplicable (2) X=Don'tcare (3) Defaultafterreset(PUC/POR) (4) SettingtheCAPD.xbitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplyinganalog signals.SelectingtheCAxinputpintothecomparatormultiplexerwiththeP2CAxbitsautomaticallydisablestheinputbufferforthatpin, regardlessofthestateoftheassociatedCAPD.xbit. (5) InJTAGmodetheinternalpullup/downresistorsaredisabled. (6) FunctioncontrolledbyJTAG Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 53

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Port P2 (P2.6) Pin Schematics, MSP430F20x1 BCSCTL3.LFXT1Sx=11 LFXT1Oscillator P2.7/XOUT LFXT1off 0 LFXT1CLK 1 P2SEL.7 Pad Logic P2REN.6 DVSS 0 DVCC 1 1 P2DIR.6 0 Direction 1 0:Input 1:Output P2OUT.6 0 Module X OUT 1 P2.6/XIN/TA1 P2SEL.6 Bus Keeper EN P2IN.6 EN Module X IN D P2IE.6 EN P2IRQ.6 Q Set P2IFG.6 P2SEL.6 Interrupt Edge P2IES.6 Select Table21.PortP2(P2.6)PinFunctions,MSP430F20x1 CONTROLBITS/SIGNALS PINNAME(P2.x) x FUNCTION P2DIR.x P2SEL.x P2.6input/output 0/1 0 P2.6/XIN/TA1 6 XIN(1)(2) 0 1 Timer_A2.TA1 1 1 (1) Defaultafterreset(PUC/POR) (2) XINisusedasdigitalclockinputifthebitsLFXT1SxinregisterBCSCTL3aresetto11. 54 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Port P2 (P2.7) Pin Schematics, MSP430F20x1 BCSCTL3.LFXT1Sx=11 LFXT1Oscillator LFXT1off 0 LFXT1CLK From P2.6/XIN P2.6/XIN/TA1 1 P2SEL.6 Pad Logic P2REN.7 DVSS 0 DVCC 1 1 P2DIR.7 0 Direction 1 0:Input 1:Output P2OUT.7 0 Module X OUT 1 P2.7/XOUT P2SEL.7 Bus Keeper EN P2IN.7 EN Module X IN D P2IE.7 EN P2IRQ.7 Q Set P2IFG.7 P2SEL.7 Interrupt Edge P2IES.7 Select Table22.PortP2(P2.7)PinFunctions,MSP430F20x1 CONTROLBITS/SIGNALS PINNAME(P2.x) x FUNCTION P2DIR.x P2SEL.x P2.7input/output 0/1 0 P2.7/XOUT 7 DVSS 0 1 XOUT(1)(2) 1 1 (1) Defaultafterreset(PUC/POR) (2) IfthepinP2.7/XOUTisusedasaninputacurrentcanflowuntilP2SEL.7isclearedduetotheoscillatoroutputdriverconnectiontothis pinafterreset. Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 55

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com APPLICATION INFORMATION, MSP430F20X2 Port P1 (P1.0 to P1.2) Pin Schematics, MSP430F20x2 Pad Logic ToADC10 INCHx=x ADC10AE.x P1REN.x DVSS 0 DVCC 1 1 P1DIR.x 0 Direction 1 0:Input 1:Output P1OUT.x 0 Module X OUT 1 P1.0/TACLK/ACLK/A0 P1.1/TA0/A1 P1SEL.x Bus P1.2/TA1/A2 Keeper P1IN.x EN EN Module X IN D P1IE.x EN P1IRQ.x Q Set P1IFG.x P1SEL.x Interrupt Edge P1IES.x Select 56 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Table23.PortP1(P1.0toP1.2)PinFunctions,MSP430F20x2 CONTROLBITS/SIGNALS(1)(2) PINNAME(P1.x) x FUNCTION P1DIR.x P1SEL.x ADC10AE.x INCHx P1.0(3)input/output 0/1 0 0 N/A Timer_A2.TACLK/INCLK 0 1 0 N/A P1.0/TACLK/ACLK/A0 0 ACLK 1 1 0 N/A A0(4) X X 1 0 P1.1(3)input/output 0/1 0 0 N/A Timer_A2.CCI0A 0 1 0 N/A P1.1/TA0/A1 1 Timer_A2.TA0 1 1 0 N/A A1(4) X X 1 1 P1.2(3)input/output 0/1 0 0 N/A Timer_A2.CCI1A 0 1 0 N/A P1.2/TA1/A2 2 Timer_A2.TA1 1 1 0 N/A A2(4) X X 1 2 (1) X=Don'tcare (2) N/A=Notavailableornotapplicable (3) Defaultafterreset(PUC/POR) (4) SettingtheADC10AE.xbitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplying analogsignals. Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 57

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Port P1 (P1.3) Pin Schematics, MSP430F20x2 SREF2 0 VSS Pad Logic ToADC10V R− 1 A3 INCHx=3 ADC10AE.3 P1REN.3 DVSS 0 DVCC 1 1 P1DIR.3 0 Direction 1 0:Input 1:Output P1OUT.3 0 Module X OUT 1 P1.3/ADC10CLK/ A3/VREF−/VeREF− P1SEL.3 Bus Keeper P1IN.3 EN EN Module X IN D P1IE.3 EN P1IRQ.3 Q Set P1IFG.3 P1SEL.3 Interrupt Edge P1IES.3 Select Table24.PortP1(P1.3)PinFunctions,MSP430F20x2 CONTROLBITS/SIGNALS(1)(2) PINNAME(P1.x) x FUNCTION P1DIR.x P1SEL.x ADC10AE.x INCHx P1.3(3)input/output 0/1 0 0 N/A N/A 0 1 0 N/A P1.3/ADC10CLK/A3/VREF- 3 ADC10CLK 1 1 0 N/A /VeREF- A3(4) X X 1 3 VREF-/VeREF-(4)(5) X X 1 N/A (1) X=Don'tcare (2) N/A=Notavailableornotapplicable (3) Defaultafterreset(PUC/POR) (4) SettingtheADC10AE.xbitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplying analogsignals. (5) AnappliedvoltageisusedasnegativereferenceifbitSREF3inregisterADC10CTL0isset. 58 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Port P1 (P1.4) Pin Schematic, MSP430F20x2 Pad Logic To/fromADC10 positive reference A4 INCHx=4 ADC10AE.4 P1REN.4 DVSS 0 DVCC 1 1 P1DIR.4 0 Direction 1 0:Input 1:Output P1OUT.4 0 Module X OUT 1 P1.4/SMCLK/A4/VREF+/VeREF+/TCK P1SEL.4 Bus Keeper EN EN Module X IN D P1IE.4 EN P1IRQ.4 Q Set P1IFG.4 P1SEL.4 Interrupt Edge P1IES.4 Select To JTAG From JTAG Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 59

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Port P1 (P1.5) Pin Schematics, MSP430F20x2 Pad Logic A5 INCHx=5 ADC10AE.5 P1REN.5 P1SEL.5 USIPE5 DVSS 0 DVCC 1 1 P1DIR.5 0 Direction USI Module Direction 1 0:Input 1:Output P1OUT.5 0 Module X OUT 1 P1.5/TA0/SCLK/A5/TMS Bus Keeper P1IN.5 EN EN Module X IN D P1IE.5 EN P1IRQ.5 Q Set P1IFG.5 P1SEL.5 Interrupt Edge P1IES.5 Select To JTAG From JTAG 60 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Port P1 (P1.6) Pin Schematics, MSP430F20x2 Pad Logic A6 INCHx=6 ADC10AE.6 P1REN.6 P1SEL.6 USIPE6 DVSS 0 DVCC 1 1 P1DIR.6 0 Direction USI Module Direction 1 0:Input 1:Output P1OUT.6 0 Module X OUT 1 P1.6/TA1/SDO/SCL/A6/TDI USI Module Output 2 (I C Mode) Bus Keeper P1IN.6 EN EN Module X IN D P1IE.6 EN P1IRQ.6 Q Set P1IFG.6 P1SEL.6 Interrupt Edge P1IES.6 Select To JTAG From JTAG Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 61

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Port P1 (P1.7) Pin Schematics, MSP430F20x2 Pad Logic A7 INCHx=7 ADC10AE.7 P1REN.7 P1SEL.7 USIPE7 DVSS 0 DVCC 1 1 P1DIR.7 0 Direction USI Module Direction 1 0:Input 1:Output P1OUT.7 0 Module X OUT 1 P1.7/SDI/SDA/A7/TDO/TDI USI Module Output 2 (I C Mode) Bus Keeper P1IN.7 EN EN Module X IN D P1IE.7 EN P1IRQ.7 Q Set P1IFG.7 P1SEL.7 Interrupt Edge P1IES.7 Select To JTAG From JTAG From JTAG From JTAG (TDO) 62 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Table25.PortP1(P1.4toP1.7)PinFunctions,MSP430F20x2 CONTROLBITS/SIGNALS(1)(2) PINNAME(P1.x) x FUNCTION P1DIR.x P1SEL.x USIP.x ADC10AE.x INCHx JTAGMode P1.4(3)input/output 0/1 0 N/A 0 N/A 0 N/A 0 1 N/A 0 N/A 0 P1.4/SMCLK/A4/ SMCLK 1 1 N/A 0 N/A 0 4 VREF+/VeREF+/TCK A4(4) X X N/A 1 4 0 VREF+/VeREF+(4)(5) X X N/A 1 N/A 0 TCK(6) X X N/A X X 1 P1.5(3)input/output 0/1 0 0 0 N/A 0 N/A 0 1 0 0 N/A 0 Timer_A2.TA0 1 1 0 0 N/A 0 P1.5/TA0/SCLK/A5/TMS 5 SCLK X X 1 0 N/A 0 A5(4) X X X 1 5 0 TMS(6) X X X X X 1 P1.6(3)input/output 0/1 0 0 0 N/A 0 Timer_A2.CCI1B 0 1 0 0 N/A 0 Timer_A2.TA1 1 1 0 0 N/A 0 P1.6/TA1/SDO/SCL/A6/TDI 6 SDO(SPI)/SCL(I2C) X X 1 0 N/A 0 A6(4) X X X 1 6 0 TDI(6) X X X X X 1 P1.7(3)input/output 0/1 0 0 0 N/A 0 N/A 0 1 0 0 N/A 0 DVSS 1 1 0 0 N/A 0 P1.7/SDI/SDA/A7/TDO/TDI 7 SDI(SPI)/SDA(I2C) X X 1 0 N/A 0 A7(4) X X X 1 7 0 TDO/TDI(6)(7) X X X X X 1 (1) X=Don'tcare (2) N/A=Notavailableornotapplicable (3) Defaultafterreset(PUC/POR) (4) SettingtheADC10AE.xbitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplying analogsignals. (5) ThereferencevoltageisoutputifbitREFOUTinregisterADC10CTL0isset.Anappliedvoltageisusedaspositivereferenceifbits SREF0/1inregisterADC10CTL0aresetto10or11. (6) InJTAGmodetheinternalpullup/downresistorsaredisabled. (7) FunctioncontrolledbyJTAG. Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 63

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Port P2 (P2.6) Pin Schematics, MSP430F20x2 BCSCTL3.LFXT1Sx=11 LFXT1Oscillator P2.7/XOUT LFXT1off 0 LFXT1CLK 1 P2SEL.7 Pad Logic P2REN.6 DVSS 0 DVCC 1 1 P2DIR.6 0 Direction 1 0:Input 1:Output P2OUT.6 0 Module X OUT 1 P2.6/XIN/TA1 P2SEL.6 Bus Keeper EN P2IN.6 EN Module X IN D P2IE.6 EN P2IRQ.6 Q Set P2IFG.6 P2SEL.6 Interrupt Edge P2IES.6 Select Table26.PortP2(P2.6)PinFunctions,MSP430F20x2 CONTROLBITS/SIGNALS PINNAME(P2.x) x FUNCTION P2DIR.x P2SEL.x P2.6input/output 0/1 0 P2.6/XIN/TA1 6 XIN(1)(2) 0 1 Timer_A2.TA1 1 1 (1) Defaultafterreset(PUC/POR) (2) XINisusedasdigitalclockinputifthebitsLFXT1SxinregisterBCSCTL3aresetto11. 64 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Port P2 (P2.7) Pin Schematics, MSP430F20x2 BCSCTL3.LFXT1Sx=11 LFXT1Oscillator LFXT1off 0 LFXT1CLK From P2.6/XIN P2.6/XIN/TA1 1 P2SEL.6 Pad Logic P2REN.7 DVSS 0 DVCC 1 1 P2DIR.7 0 Direction 1 0:Input 1:Output P2OUT.7 0 Module X OUT 1 P2.7/XOUT P2SEL.7 Bus Keeper EN P2IN.7 EN Module X IN D P2IE.7 EN P2IRQ.7 Q Set P2IFG.7 P2SEL.7 Interrupt Edge P2IES.7 Select Table27.PortP2(P2.7)PinFunctions,MSP430F20x2 CONTROLBITS/SIGNALS PINNAME(P2.x) x FUNCTION P2DIR.x P2SEL.x P2.7input/output 0/1 0 P2.7/XOUT 7 DVSS 0 1 XOUT(1)(2) 1 1 (1) Defaultafterreset(PUC/POR) (2) IfthepinP2.7/XOUTisusedasaninputacurrentcanflowuntilP2SEL.7isclearedduetotheoscillatoroutputdriverconnectiontothis pinafterreset. Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 65

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com APPLICATION INFORMATION, MSP430F20X3 Port P1 (P1.0) Pin Schematics, MSP430F20x3 INCH=0 Pad Logic A0+ SD16AE.0 P1REN.0 DVSS 0 DVCC 1 1 P1DIR.0 0 Direction 1 0:Input 1:Output P1OUT.0 0 Module X OUT 1 P1.0/TACLK/ACLK/A0+ P1SEL.0 Bus Keeper P1IN.0 EN EN Module X IN D P1IE.0 EN P1IRQ.0 Q Set P1IFG.0 P1SEL.0 Interrupt Edge P1IES.0 Select 66 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Port P1 (P1.1) Pin Schematics, MSP430F20x3 INCH=4 Pad Logic A4+ INCH=0 0 AV SS A0− 1 SD16AE.1 P1REN.1 DVSS 0 DVCC 1 1 P1DIR.1 0 Direction 1 0:Input 1:Output P1OUT.1 0 Module X OUT 1 P1.1/TA0/A0−/A4+ P1SEL.1 Bus Keeper P1IN.1 EN EN Module X IN D P1IE.1 EN P1IRQ.1 Q Set P1IFG.1 P1SEL.1 Interrupt Edge P1IES.1 Select Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 67

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Port P1 (P1.2) Pin Schematics, MSP430F20x3 INCH=1 Pad Logic A1+ INCH=4 0 AV SS A4− 1 SD16AE.2 P1REN.2 DVSS 0 DVCC 1 1 P1DIR.2 0 Direction 1 0:Input 1:Output P1OUT.2 0 Module X OUT 1 P1.2/TA1/A1+/A4− P1SEL.2 Bus Keeper P1IN.2 EN EN Module X IN D P1IE.2 EN P1IRQ.2 Q Set P1IFG.2 P1SEL.2 Interrupt Edge P1IES.2 Select 68 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Port P1 (P1.3) Pin Schematics, MSP430F20x3 Pad Logic V REF INCH=1 0 AV SS A1− 1 SD16AE.3 P1REN.3 DVSS 0 DVCC 1 1 P1DIR.3 0 Direction 1 0:Input 1:Output P1OUT.3 0 1 P1.3/VREF/A1− P1SEL.3 Bus Keeper P1IN.3 EN P1IE.3 EN P1IRQ.3 Q Set P1IFG.3 P1SEL.3 Interrupt Edge P1IES.3 Select Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 69

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Table28.PortP1(P1.0toP1.3)PinFunctions,MSP430F20x3 CONTROLBITS/SIGNALS(1)(2) PINNAME(P1.x) x FUNCTION P1DIR.x P1SEL.x SD16AE.x INCHx P1.0(3)input/output 0/1 0 0 N/A Timer_A2.TACLK/INCLK 0 1 0 N/A P1.0/TACLK/ACLK/A0+ 0 ACLK 1 1 0 N/A A0+(4) X X 1 0 P1.1(3)input/output 0/1 0 0 N/A Timer_A2.CCI0A 0 1 0 N/A P1.1/TA0/A0-/A4+ 1 Timer_A2.TA0 1 1 0 N/A A0-(4)(5) X X 1 0 A4+(4) X X 1 4 P1.2(3)input/output 0/1 0 0 N/A Timer_A2.CCI1A 0 1 0 N/A P1.2/TA1/A1+/A4- 2 Timer_A2.TA1 1 1 0 N/A A1+(4) X X 1 1 A4-(4)(5) X X 1 4 P1.3(3)input/output 0/1 0 0 N/A P1.3/VREF/A1- 3 VREF X 1 0 N/A A1-(4)(5) X X 1 1 (1) X=Don'tcare (2) N/A=Notavailableornotapplicable (3) Defaultafterreset(PUC/POR) (4) SettingtheSD16AE.xbitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplying analogsignals. (5) WithSD16AE.x=0thenegativeinputsareconnectedtoVSSifthecorrespondinginputisselected. 70 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Port P1 (P1.4) Pin Schematics, MSP430F20x3 INCH=2 Pad Logic A2+ SD16AE.4 P1REN.4 DVSS 0 DVCC 1 1 P1DIR.4 0 Direction 1 0:Input 1:Output P1OUT.4 0 Module X OUT 1 P1.4/SMCLK/A2+/TCK P1SEL.4 Bus Keeper P1IN.4 EN EN Module X IN D P1IE.4 EN P1IRQ.4 Q Set P1IFG.4 P1SEL.4 Interrupt Edge P1IES.4 Select To JTAG From JTAG Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 71

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Port P1 (P1.5) Pin Schematics, MSP430F20x3 Pad Logic INCH=2 0 AV SS A2− 1 SD16AE.5 P1REN.5 P1SEL.5 USIPE5 DVSS 0 DVCC 1 1 P1DIR.5 0 Direction USI Module Direction 1 0:Input 1:Output P1OUT.5 0 Module X OUT 1 P1.5/TA0/SCLK/A2−/TMS Bus Keeper P1IN.5 EN EN Module X IN D P1IE.5 EN P1IRQ.5 Q Set P1IFG.5 P1SEL.5 Interrupt Edge P1IES.5 Select To JTAG From JTAG 72 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Port P1 (P1.6) Pin Schematics, MSP430F20x3 Pad Logic INCH=3 A3+ SD16AE.6 P1REN.6 P1SEL.6 USIPE6 DVSS 0 DVCC 1 1 P1DIR.6 0 Direction USI Module Direction 1 0:Input 1:Output P1OUT.6 0 Module X OUT 1 P1.6/TA1/SDO/SCL/A3+/TDI USI Module Output (I2C Mode) Bus Keeper P1IN.6 EN EN Module X IN D P1IE.6 EN P1IRQ.6 Q Set P1IFG.6 P1SEL.6 Interrupt Edge P1IES.6 Select To JTAG From JTAG Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 73

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Port P1 (P1.7) Pin Schematics, MSP430F20x3 Pad Logic INCH=3 0 AV SS A3− 1 SD16AE.x P1REN.x P1SEL.x USIPE7 DVSS 0 DVCC 1 1 P1DIR.x 0 Direction USI Module Direction 1 0:Input 1:Output P1OUT.x 0 Module X OUT 1 P1.7/SDI/SDA/A3−/TDO/TDI USI Module Output (I2C Mode) Bus Keeper P1IN.x EN EN Module X IN D P1IE.x EN P1IRQ.x Q Set P1IFG.x P1SEL.x Interrupt Edge P1IES.x Select To JTAG From JTAG From JTAG From JTAG (TDO) 74 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Table29.PortP1(P1.4toP1.7)PinFunctions,MSP430F20x3 CONTROLBITS/SIGNALS(1)(2) PINNAME(P1.x) x FUNCTION P1DIR.x P1SEL.x USIP.x SD16AE.x INCHx JTAGMode P1.4(3)input/output 0/1 0 N/A 0 N/A 0 N/A 0 1 N/A 0 N/A 0 P1.4/SMCLK/A2+/TCK 4 SMCLK 1 1 N/A 0 N/A 0 A2+(4) X X N/A 1 2 0 TCK(5) X X N/A X X 1 P1.5(3)input/output 0/1 0 0 0 N/A 0 N/A 0 1 0 0 N/A 0 Timer_A2.TA0 1 1 0 0 N/A 0 P1.5/TA0/SCLK/A2-/TMS 5 SCLK X X 1 0 N/A 0 A2-(4)(6) X X X 1 2 0 TMS(5) X X X X X 1 P1.6(3)input/output 0/1 0 0 0 N/A 0 Timer_A2.CCI1B 0 1 0 0 N/A 0 P1.6/TA1/SDO/SCL/ Timer_A2.TA1 1 1 0 0 N/A 0 6 A3+/TDI SDO(SPI)/SCL(I2C) X X 1 0 N/A 0 A3+(4) X X X 1 3 0 TDI(5) X X X X X 1 P1.7(3)input/output 0/1 0 0 0 N/A 0 N/A 0 1 0 0 N/A 0 P1.7/SDI/SDA/A3-/ DVSS 1 1 0 0 N/A 0 7 TDO/TDI SDI(SPI)/SDA(I2C) X X 1 0 N/A 0 A3-(4)(6) X X X 1 3 0 TDO/TDI(7)(5) X X X X X 1 (1) X=Don'tcare (2) N/A=Notavailableornotapplicable (3) Defaultafterreset(PUC/POR) (4) SettingtheSD16AE.xbitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplying analogsignals. (5) InJTAGmode,theinternalpullupandpulldownresistorsaredisabled. (6) WithSD16AE.x=0thenegativeinputsareconnectedtoVSSifthecorrespondinginputisselected. (7) FunctioncontrolledbyJTAG Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 75

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com Port P2 (P2.6) Pin Schematics, MSP430F20x3 BCSCTL3.LFXT1Sx=11 LFXT1Oscillator P2.7/XOUT LFXT1off 0 LFXT1CLK 1 P2SEL.7 Pad Logic P2REN.6 DVSS 0 DVCC 1 1 P2DIR.6 0 Direction 1 0:Input 1:Output P2OUT.6 0 Module X OUT 1 P2.6/XIN/TA1 P2SEL.6 Bus Keeper EN P2IN.6 EN Module X IN D P2IE.6 EN P2IRQ.6 Q Set P2IFG.6 P2SEL.6 Interrupt Edge P2IES.6 Select Table30.PortP2(P2.6)PinFunctions,MSP430F20x3 CONTROLBITS/SIGNALS PINNAME(P2.x) x FUNCTION P2DIR.x P2SEL.x P2.6input/output 0/1 0 P2.6/XIN/TA1 6 XIN(1)(2) 0 1 Timer_A2.TA1 1 1 (1) Defaultafterreset(PUC/POR) (2) XINisusedasdigitalclockinputifthebitsLFXT1SxinregisterBCSCTL3aresetto11. 76 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I–AUGUST2005–REVISEDDECEMBER2012 Port P2 (P2.7) Pin Schematics, MSP430F20x3 BCSCTL3.LFXT1Sx=11 LFXT1Oscillator LFXT1off 0 LFXT1CLK From P2.6/XIN P2.6/XIN/TA1 1 P2SEL.6 Pad Logic P2REN.7 DVSS 0 DVCC 1 1 P2DIR.7 0 Direction 1 0:Input 1:Output P2OUT.7 0 Module X OUT 1 P2.7/XOUT P2SEL.7 Bus Keeper EN P2IN.7 EN Module X IN D P2IE.7 EN P2IRQ.7 Q Set P2IFG.7 P2SEL.7 Interrupt Edge P2IES.7 Select Table31.PortP2(P2.7)PinFunctions,MSP430F20x3 CONTROLBITS/SIGNALS PINNAME(P2.x) x FUNCTION P2DIR.x P2SEL.x P2.7input/output 0/1 0 P2.7/XOUT 7 DVSS 0 1 XOUT(1)(2) 1 1 (1) Defaultafterreset(PUC/POR) (2) IfthepinP2.7/XOUTisusedasaninputacurrentcanflowuntilP2SEL.7isclearedduetotheoscillatoroutputdriverconnectiontothis pinafterreset. Copyright©2005–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 77

MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I–AUGUST2005–REVISEDDECEMBER2012 www.ti.com REVISION HISTORY LITERATURE SUMMARY NUMBER SLAS491 PreliminaryPRODUCTPREVIEWdatasheetrelease ProductiondatasheetreleaseforMSP430F20x3I. SLAS491A Updatedspecificationandaddedcharacterizationgraphs. ProductiondatasheetreleaseforMSP430F20x3T,MSP430F20x1IandMSP430F20x1T. 105°Ccharacterizationresultsadded. SD16_ASINADcharacterizationresultsforMSP430F20x3. RSApackageadded. SLAS491B UpdatedSD16_APowerSupplyRejectionspecification. DCOCalibrationRegisternames:lowercase"z"changedtouppercase"Z". V MAXspecificationincreasedfrom180mVto210mV. hys(B_IT-) MINandMAXpercentagesfor"calibratedDCOfrequencies-toleranceoversupplyvoltageVCC"correctedfrom2.5%to 3.0%tomatchthespecifiedfrequencyranges. SLAS491C ProductiondatasheetreleaseforMSP430F20x2IandMSP430F20x2T. Changedf to0HzinI testconditionsinLow-PowerModeSupplyCurrents(IntoV )ExcludingExternal SLAS491D ACLK LPM4 CC Current. SLAS491E ChangedT maximumforprogrammeddevicesto150°CinAbsoluteMaximumRatings. stg SLAS491F AddedADC10datatransferregisterstoPeripheralFileMap ChangedTestConditionsfor"Dutycycle,LFmode"inCrystalOscillator,XT1,Low-FrequencyMode. SLAS491G Changednote(1)on10-BitADC,Built-InVoltageReference. ChangedUSIP.xControlBitsinTable25andTable29. SLAS491H ChangedT ,Programmeddevice,to-55°Cto150°CinAbsoluteMaximumRatings. stg AddedtypicalvaluetestconditionstoRecommendedOperatingConditions. SLAS491I Addednote(2)toPORandBrownoutReset(BOR). 78 SubmitDocumentationFeedback Copyright©2005–2012,TexasInstrumentsIncorporated

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MSP430F2001IN ACTIVE PDIP N 14 25 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430F2001 (RoHS) MSP430F2001IPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 F2001 & no Sb/Br) MSP430F2001IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 F2001 & no Sb/Br) MSP430F2001IRSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F & no Sb/Br) 2001 MSP430F2001IRSAT ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F & no Sb/Br) 2001 MSP430F2001TN ACTIVE PDIP N 14 25 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 105 MSP430F2001T (RoHS) MSP430F2001TPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 F2001T & no Sb/Br) MSP430F2001TPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 F2001T & no Sb/Br) MSP430F2001TRSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F & no Sb/Br) 2001T MSP430F2001TRSAT ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F & no Sb/Br) 2001T MSP430F2002IN ACTIVE PDIP N 14 25 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430F2002 (RoHS) MSP430F2002IPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 F2002 & no Sb/Br) MSP430F2002IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 F2002 & no Sb/Br) MSP430F2002IRSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F & no Sb/Br) 2002 MSP430F2002IRSAT ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F & no Sb/Br) 2002 MSP430F2002TN ACTIVE PDIP N 14 25 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 105 MSP430F2002T (RoHS) MSP430F2002TPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 F2002T & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MSP430F2002TPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 F2002T & no Sb/Br) MSP430F2002TRSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F & no Sb/Br) 2002T MSP430F2002TRSAT ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F & no Sb/Br) 2002T MSP430F2003IN ACTIVE PDIP N 14 25 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430F2003 (RoHS) MSP430F2003IPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 F2003 & no Sb/Br) MSP430F2003IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 F2003 & no Sb/Br) MSP430F2003IRSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F & no Sb/Br) 2003 MSP430F2003IRSAT ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F & no Sb/Br) 2003 MSP430F2003TN ACTIVE PDIP N 14 25 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 105 MSP430F2003T (RoHS) MSP430F2003TPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 F2003T & no Sb/Br) MSP430F2003TPWR ACTIVE TSSOP PW 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 F2003T & no Sb/Br) MSP430F2003TRSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F & no Sb/Br) 2003T MSP430F2003TRSAT ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F & no Sb/Br) 2003T MSP430F2011IN ACTIVE PDIP N 14 25 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430F2011 (RoHS) MSP430F2011IPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 F2011 & no Sb/Br) MSP430F2011IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 F2011 & no Sb/Br) MSP430F2011IRSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F & no Sb/Br) 2011 MSP430F2011IRSAT ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F & no Sb/Br) 2011 Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MSP430F2011TN ACTIVE PDIP N 14 25 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 105 MSP430F2011T (RoHS) MSP430F2011TPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 F2011T & no Sb/Br) MSP430F2011TPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 F2011T & no Sb/Br) MSP430F2011TRSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F & no Sb/Br) 2011T MSP430F2011TRSAT ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F & no Sb/Br) 2011T MSP430F2012IN ACTIVE PDIP N 14 25 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430F2012 (RoHS) MSP430F2012IPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 F2012 & no Sb/Br) MSP430F2012IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 F2012 & no Sb/Br) MSP430F2012IRSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F & no Sb/Br) 2012 MSP430F2012IRSAT ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F & no Sb/Br) 2012 MSP430F2012TN ACTIVE PDIP N 14 25 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 105 MSP430F2012T (RoHS) MSP430F2012TPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 F2012T & no Sb/Br) MSP430F2012TPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 F2012T & no Sb/Br) MSP430F2012TRSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F & no Sb/Br) 2012T MSP430F2012TRSAT ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F & no Sb/Br) 2012T MSP430F2013IN ACTIVE PDIP N 14 25 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430F2013 (RoHS) MSP430F2013IPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 F2013 & no Sb/Br) MSP430F2013IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 F2013 & no Sb/Br) Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MSP430F2013IRSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F & no Sb/Br) 2013 MSP430F2013IRSAT ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F & no Sb/Br) 2013 MSP430F2013TN ACTIVE PDIP N 14 25 Pb-Free NIPDAU Level-1-260C-UNLIM -40 to 105 MSP430F2013T (RoHS) MSP430F2013TPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 F2013T & no Sb/Br) MSP430F2013TPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 F2013T & no Sb/Br) MSP430F2013TRSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F & no Sb/Br) 2013T MSP430F2013TRSAT ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F & no Sb/Br) 2013T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 4

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF MSP430F2013 : •Enhanced Product: MSP430F2013-EP NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 5

PACKAGE MATERIALS INFORMATION www.ti.com 12-Mar-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) MSP430F2001IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2001IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2001IRSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2001IRSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2001TPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2001TPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2001TRSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2001TRSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2002IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2002IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2002IRSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2002IRSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2002TPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2002TPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2002TRSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2002TRSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2003IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2003IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Mar-2020 Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) MSP430F2003IRSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2003IRSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2003TPWR TSSOP PW 14 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2003TPWR TSSOP PW 14 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2003TRSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2003TRSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2011IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2011IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2011IRSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2011IRSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2011TPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2011TPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2011TRSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2011TRSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2012IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2012IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2012IRSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2012IRSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2012TPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2012TPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2012TRSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2012TRSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2013IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2013IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2013IRSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2013IRSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2013TPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2013TPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2013TRSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2013TRSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 PackMaterials-Page2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Mar-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) MSP430F2001IPWR TSSOP PW 14 2000 350.0 350.0 43.0 MSP430F2001IPWR TSSOP PW 14 2000 367.0 367.0 35.0 MSP430F2001IRSAR QFN RSA 16 3000 367.0 367.0 35.0 MSP430F2001IRSAT QFN RSA 16 250 210.0 185.0 35.0 MSP430F2001TPWR TSSOP PW 14 2000 367.0 367.0 35.0 MSP430F2001TPWR TSSOP PW 14 2000 350.0 350.0 43.0 MSP430F2001TRSAR QFN RSA 16 3000 367.0 367.0 35.0 MSP430F2001TRSAT QFN RSA 16 250 210.0 185.0 35.0 MSP430F2002IPWR TSSOP PW 14 2000 350.0 350.0 43.0 MSP430F2002IPWR TSSOP PW 14 2000 367.0 367.0 35.0 MSP430F2002IRSAR QFN RSA 16 3000 367.0 367.0 35.0 MSP430F2002IRSAT QFN RSA 16 250 210.0 185.0 35.0 MSP430F2002TPWR TSSOP PW 14 2000 350.0 350.0 43.0 MSP430F2002TPWR TSSOP PW 14 2000 367.0 367.0 35.0 MSP430F2002TRSAR QFN RSA 16 3000 367.0 367.0 35.0 MSP430F2002TRSAT QFN RSA 16 250 210.0 185.0 35.0 MSP430F2003IPWR TSSOP PW 14 2000 350.0 350.0 43.0 MSP430F2003IPWR TSSOP PW 14 2000 367.0 367.0 35.0 MSP430F2003IRSAR QFN RSA 16 3000 367.0 367.0 35.0 MSP430F2003IRSAT QFN RSA 16 250 210.0 185.0 35.0 PackMaterials-Page3

PACKAGE MATERIALS INFORMATION www.ti.com 12-Mar-2020 Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) MSP430F2003TPWR TSSOP PW 14 2500 367.0 367.0 35.0 MSP430F2003TPWR TSSOP PW 14 2500 350.0 350.0 43.0 MSP430F2003TRSAR QFN RSA 16 3000 367.0 367.0 35.0 MSP430F2003TRSAT QFN RSA 16 250 210.0 185.0 35.0 MSP430F2011IPWR TSSOP PW 14 2000 350.0 350.0 43.0 MSP430F2011IPWR TSSOP PW 14 2000 367.0 367.0 35.0 MSP430F2011IRSAR QFN RSA 16 3000 367.0 367.0 35.0 MSP430F2011IRSAT QFN RSA 16 250 210.0 185.0 35.0 MSP430F2011TPWR TSSOP PW 14 2000 367.0 367.0 35.0 MSP430F2011TPWR TSSOP PW 14 2000 350.0 350.0 43.0 MSP430F2011TRSAR QFN RSA 16 3000 367.0 367.0 35.0 MSP430F2011TRSAT QFN RSA 16 250 210.0 185.0 35.0 MSP430F2012IPWR TSSOP PW 14 2000 367.0 367.0 35.0 MSP430F2012IPWR TSSOP PW 14 2000 350.0 350.0 43.0 MSP430F2012IRSAR QFN RSA 16 3000 367.0 367.0 35.0 MSP430F2012IRSAT QFN RSA 16 250 210.0 185.0 35.0 MSP430F2012TPWR TSSOP PW 14 2000 367.0 367.0 35.0 MSP430F2012TPWR TSSOP PW 14 2000 350.0 350.0 43.0 MSP430F2012TRSAR QFN RSA 16 3000 367.0 367.0 35.0 MSP430F2012TRSAT QFN RSA 16 250 210.0 185.0 35.0 MSP430F2013IPWR TSSOP PW 14 2000 350.0 350.0 43.0 MSP430F2013IPWR TSSOP PW 14 2000 367.0 367.0 35.0 MSP430F2013IRSAR QFN RSA 16 3000 367.0 367.0 35.0 MSP430F2013IRSAT QFN RSA 16 250 210.0 185.0 35.0 MSP430F2013TPWR TSSOP PW 14 2000 367.0 367.0 35.0 MSP430F2013TPWR TSSOP PW 14 2000 350.0 350.0 43.0 MSP430F2013TRSAR QFN RSA 16 3000 367.0 367.0 35.0 MSP430F2013TRSAT QFN RSA 16 250 210.0 185.0 35.0 PackMaterials-Page4

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