MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 (cid:2) (cid:2) Low Supply Voltage Range 1.8 V to 3.6 V Serial Communication Interface (USART0) (cid:2) Ultralow-Power Consumption: Software-Selects Asynchronous UART or − Active Mode: 200 μA at 1 MHz, 2.2 V Synchronous SPI − Standby Mode: 0.7 μA (cid:2) Serial Onboard Programming, − Off Mode (RAM Retention): 0.1 μA No External Programming Voltage Needed (cid:2) Five Power Saving Modes Programmable Code Protection by Security (cid:2) Fuse Wake-Up From Standby Mode in less (cid:2) than 6 μs Family Members Include: (cid:2) MSP430F122: 4KB + 256B Flash Memory 16-Bit RISC Architecture, 125 ns 256B RAM Instruction Cycle Time MSP430F123: 8KB + 256B Flash Memory (cid:2) Basic Clock Module Configurations: 256B RAM − Various Internal Resistors (cid:2) Available in a 28-Pin Plastic Small-Outline − Single External Resistor Wide Body (SOWB) Package, 28-Pin Plastic − 32 kHz Crystal Thin Shrink Small-Outline Package − High Frequency Crystal (TSSOP) and 32-Pin QFN Package − Resonator (cid:2) For Complete Module Descriptions, See the − External Clock Source MSP430x1xx Family User’s Guide, (cid:2) 16-Bit Timer_A With Three Literature Number SLAU049 Capture/Compare Registers (cid:2) On-Chip Comparator for Analog Signal Compare Function or Slope A/D Conversion description The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6μs. The MSP430F12x series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer and twenty-two I/O pins. The MSP430F12x series also has a built-in communication capability using asynchronous (UART) and synchronous (SPI) protocols in addition to a versatile analog comparator. Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data and display them or transmit them to a host system. Stand alone RF sensor front end is another area of application. The I/O port inputs provide single slope A/D conversion capability on resistive sensors. AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC 28-PIN SOWB PLASTIC 28-PIN TSSOP PLASTIC 32-PIN QFN (DW) (PW) (RHB) MMSSPP443300FF112222IIDDWW MMSSPP443300FF112222IIPPWW MMSSPP443300FF112222IIRRHHBB −4400°°CC ttoo 8855°°CC MSP430F123IDW MSP430F123IPW MSP430F123IRHB Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2001 − 2004 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 pin designation, MSP430x12x DW OR PW PACKAGE RHB PACKAGE (TOP VIEW) (TOP VIEW) K TEST 1 28 P1.7/TA2/TDO/TDI DIL K P2.5/RVOCSCC 23 2276 PP11..65//TTAA10//TTDMIS/TCLK DO/TDI/TCMSK/TC XOVUSTS 45 2254 PP11..43//STAM2CLK/TCK ROSC TA2/TTA1/TTA0/TSMCL XIN 6 23 P1.2/TA1 2.5/C CCEST1.7/1.6/1.5/1.4/ RST/NMI 7 22 P1.1/TA0 PNVTPPPP P2.0/ACLK 8 21 P1.0/TACLK P2.1/INCLK 9 20 P2.4/CA1/TA2 VSS 1 313029 28272624 P1.3/TA2 P2.2/CAOUT/TA0 10 19 P2.3/CA0/TA1 XOUT 2 23 P1.2/TA1 P3.0/STE0 11 18 P3.7 XIN 3 22 P1.1/TA0 P3.1/SIMO0 12 17 P3.6 NC 4 21 P1.0/TACLK P3.2/SOMI0 13 16 P3.5/URXD0 RST/NMI 5 20 NC P3.3/UCLK0 14 15 P3.4/UTXD0 P2.0/ACLK 6 19 P2.4/CA1/TA2 P2.1/INCLK 7 18 P2.3/CA0/TA1 P2.2/CAOUT/TA0 8 10111213 1415 17 NC 00000067 EOMIKDD3.3. 0/STSIMSOUCLUTXURXPP P3.P3.1/P3.2/P3.3/P3.4/P3.5/ Note: NC pins not internally connected Power Pad connection to VSS recommended functional block diagram XIN XOUT VCC VSS RST/NMI P1 P2 P3 JTAG 8 6 8 ROSC Oscillator ACLK 8KB Flash 256B RAM I/O Port 1 I/O Port 2 I/O Port 3 8 I/Os, with 6 I/Os, with 8 I/Os System SMCLK 4KB Flash Interrupt Interrupt Clock Capability Capability MCLK MAB, Test MAB,M 1A6B B, it16-Bit 4 Bit JTAG CPU MCB Incl. 16 Reg. n oe mulatiModul MDBM, D1B6 ,B 1it6-Bit Bus MDB, 8 Bit E Conv TEST Watchdog Timer_A3 POR Comparator USART0 Timer A 3 CC Reg UART Mode 15/16-Bit SPI Mode 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 Terminal Functions TERMINAL DW, PW RHB II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. NO. P1.0/TACLK 21 21 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input P1.1/TA0 22 22 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit P1.2/TA1 23 23 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 24 24 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK/TCK 25 25 I/O General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device programming and test P1.5/TA0/TMS 26 26 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for device programming and test P1.6/TA1/TDI/TCLK 27 27 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal or test clock input P1.7/TA2/TDO/TDI† 28 28 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input during programming P2.0/ACLK 8 6 I/O General-purpose digital I/O pin/ACLK output P2.1/INCLK 9 7 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK P2.2/CAOUT/TA0 10 8 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/comparator_A, output/BSL receive P2.3/CA0/TA1 19 18 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/comparator_A, input P2.4/CA1/TA2 20 19 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/comparator_A, input P2.5/ROSC 3 32 I/O General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency P3.0/STE0 11 9 I/O General-purpose digital I/O pin/slave transmit enable—USART0/SPI mode P3.1/SIMO0 12 10 I/O General-purpose digital I/O pin/slave in/master out of USART0/SPI mode P3.2/SOMI0 13 11 I/O General-purpose digital I/O pin/slave out/master in of USART0/SPI mode P3.3/UCLK0 14 12 I/O General-purpose digital I/O pin/external clock input—USART0/UART or SPI mode, clock output—USART0/SPI mode clock input P3.4/UTXD0 15 13 I/O General-purpose digital I/O pin/transmit data out—USART0/UART mode P3.5/URXD0 16 14 I/O General-purpose digital I/O pin/receive data in—USART0/UART mode P3.6 17 15 I/O General-purpose digital I/O pin P3.7 18 16 I/O General-purpose digital I/O pin RST/NMI 7 5 I Reset or nonmaskable interrupt input TEST 1 29 I Selects test mode for JTAG pins on Port1 VCC 2 30 Supply voltage VSS 4 1 Ground reference XIN 6 3 I Input terminal of crystal oscillator XOUT 5 2 O Output terminal of crystal oscillator NC 4, 17, No internal connection 20, 31 QFN Pad NA Package NA QFN package pad connection to VSS recommended. Pad †TDO or TDI is selected via JTAG instruction. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture Program Counter PC/R0 that is highly transparent to the application. All operations, other than program-flow instructions, Stack Pointer SP/R1 are performed as register operations in Status Register SR/CG1/R2 conjunction with seven addressing modes for source operand and four addressing modes for Constant Generator CG2/R3 destination operand. General-Purpose Register R4 The CPU is integrated with 16 registers that provide reduced instruction execution time. The General-Purpose Register R5 register-to-register operation execution time is one cycle of the CPU clock. General-Purpose Register R6 Four of the registers, R0 to R3, are dedicated as General-Purpose Register R7 program counter, stack pointer, status register, and constant generator respectively. The General-Purpose Register R8 remaining registers are general-purpose registers. General-Purpose Register R9 Peripherals are connected to the CPU using data, General-Purpose Register R10 address, and control buses, and can be handled with all instructions. General-Purpose Register R11 instruction set General-Purpose Register R12 The instruction set consists of 51 instructions with three formats and seven address modes. Each General-Purpose Register R13 instruction can operate on word and byte data. Table1 shows examples of the three types of General-Purpose Register R14 instruction formats; the address modes are listed General-Purpose Register R15 in Table2. Table 1. Instruction Word Formats Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 −−−> R5 Single operands, destination only e.g. CALL R8 PC −−>(TOS), R8−−> PC Relative jump, un/conditional e.g. JNE Jump-on-equal bit = 0 Table 2. Address Mode Descriptions ADDRESS MODE S D SYNTAX EXAMPLE OPERATION (cid:2) (cid:2) Register MOV Rs,Rd MOV R10,R11 R10 −−> R11 (cid:2) (cid:2) Indexed MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)−−> M(6+R6) (cid:2) (cid:2) Symbolic (PC relative) MOV EDE,TONI M(EDE) −−> M(TONI) (cid:2) (cid:2) Absolute MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT) (cid:2) Indirect MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6) Indirect (cid:2) M(R10) −−> R11 MOV @Rn+,Rm MOV @R10+,R11 autoincrement R10 + 2−−> R10 (cid:2) Immediate MOV #X,TONI MOV #45,TONI #45 −−> M(TONI) NOTE: S = source D = destination 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: (cid:2) Active mode AM; − All clocks are active (cid:2) Low-power mode 0 (LPM0); − CPU is disabled ACLK and SMCLK remain active. MCLK is disabled (cid:2) Low-power mode 1 (LPM1); − CPU is disabled ACLK and SMCLK remain active. MCLK is disabled DCO’s dc-generator is disabled if DCO not used in active mode (cid:2) Low-power mode 2 (LPM2); − CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator remains enabled ACLK remains active (cid:2) Low-power mode 3 (LPM3); − CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled ACLK remains active (cid:2) Low-power mode 4 (LPM4); − CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled Crystal oscillator is stopped POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up External reset WDTIFG (see Note1) Reset 0FFFEh 15, highest Watchdog KEYV (see Note 1) Flash memory NMI NMIIFG (see Notes 1 and 4) (non)-maskable, Oscillator fault OFIFG (see Notes 1 and 4) (non)-maskable, 0FFFCh 14 Flash memory access violation ACCVIFG (see Notes 1 and 4) (non)-maskable 0FFFAh 13 0FFF8h 12 Comparator_A CAIFG maskable 0FFF6h 11 Watchdog timer WDTIFG maskable 0FFF4h 10 Timer_A3 TACCR0 CCIFG (see Note 2) maskable 0FFF2h 9 TACCR1 and TACCR2 Timer_A3 CCIFGs, TAIFG maskable 0FFF0h 8 (see Notes 1 and 2) USART0 receive URXIFG0 maskable 0FFEEh 7 USART0 transmit UTXIFG0 maskable 0FFECh 6 0FFEAh 5 0FFE8h 4 I/O Port P2 P2IFG.0 to P2IFG.7 maskable 0FFE6h 3 (eight flags − see Note 3) (see Notes 1 and 2) I/O Port P1 P1IFG.0 to P1IFG.7 maskable 0FFE4h 2 (eight flags) (see Notes 1 and 2) 0FFE2h 1 0FFE0h 0, lowest NOTES: 1. Multiple source flags 2. Interrupt flags are located in the module 3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0−5) are implemented on the ’12x devices. 4. (non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 and 2 Address 7 6 5 4 3 2 1 0 0h ACCVIE NMIIE OFIE WDTIE rw-0 rw-0 rw-0 rw-0 WDTIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. OFIE: Oscillator-fault-interrupt enable NMIIE: Nonmaskable-interrupt enable ACCVIE: Flash access violation interrupt enable Address 7 6 5 4 3 2 1 0 01h UTXIE0 URXIE0 rw-0 rw-0 URXIE0: USART0: UART and SPI receive-interrupt enable UTXIE0: USART0: UART and SPI transmit-interrupt enable interrupt flag register 1 and 2 Address 7 6 5 4 3 2 1 0 02h NMIIFG OFIFG WDTIFG rw-0 rw-1 rw-(0) WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on V CC power up or a reset condition at the RST/NMI pin in reset mode. OFIFG: Flag set on oscillator fault NMIIFG: Set via RST/NMI pin Address 7 6 5 4 3 2 1 0 03h UTXIFG0 URXIFG0 rw-0 rw-0 URXIFG0: USART0: UART and SPI receive flag UTXIFG0: USART0: UART and SPI transmit flag POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 module enable registers 1 and 2 Address 7 6 5 4 3 2 1 0 04h Address 7 6 5 4 3 2 1 0 URXE0 05h UTXE0 USPIE0 rw-0 rw-0 URXE0: USART0: UART receive enable UTXE0: USART0: UART transmit enable USPIE0: USART0: SPI (synchronous peripheral interface) transmit and receive enable Legend rw: Bit can be read and written. rw-0,1: Bit can be read and written. It is Reset or Set by PUC rw-(0,1): Bit can be read and written. It is Reset or Set by POR SFR bit is not present in device. memory organization MSP430F122 MSP430F123 Memory Size 4KB Flash 8KB Flash Main: interrupt vector Flash 0FFFFh−0FFE0h 0FFFFh−0FFE0h Main: code memory Flash 0FFFFh−0F000h 0FFFFh−0E000h Information memory Size 256 Byte 256 Byte Flash 010FFh − 01000h 010FFh − 01000h Boot memory Size 1KB 1KB ROM 0FFFh − 0C00h 0FFFh − 0C00h RAM Size 256 Byte 256 Byte 02FFh − 0200h 02FFh − 0200h Peripherals 16-bit 01FFh − 0100h 01FFh − 0100h 8-bit 0FFh − 010h 0FFh − 010h 8-bit SFR 0Fh − 00h 0Fh − 00h bootstrap loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089. BSL Function DW & PW Package Pins RHB Package Pins Data Transmit 22 - P1.1 22 - P1.1 Data Receive 10 - P2.2 8 - P2.2 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: (cid:2) Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size. (cid:2) Segments 0 to n may be erased in one step, or each segment may be individually erased. (cid:2) Segments A and B can be erased individually, or as a group with segments 0−n. Segments A and B are also called information memory. (cid:2) New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use. peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number SLAU049. oscillator and system clock The clock system in the MSP430x12x devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The basic clock module provides the following clock signals: (cid:2) Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. (cid:2) Main clock (MCLK), the system clock used by the CPU. (cid:2) Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. digital I/O There are three 8-bit I/O ports implemented—ports P1, P2, and P3 (only six port P2 I/O signals are available on external pins): (cid:2) All individual I/O bits are independently programmable. (cid:2) Any combination of input, output, and interrupt conditions is possible. (cid:2) Edge-selectable interrupt input capability for all the eight bits of ports P1 and six bits of port P2. (cid:2) Read/write access to port-control registers is supported by all instructions. NOTE: Six bits of port P2, P2.0 to P2.5, are available on external pins − but all control and data bits for port P2 are implemented. Port P3 has no interrupt capability. watchdog timer The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 USART0 The MSP430x12x devices have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_A3 Signal Connections Input Pin Number Output Pin Number DDeevviiccee IInnppuutt SSiiggnnaall MMoodduullee IInnppuutt NNaammee MMoodduullee BBlloocckk MMoodduullee OOuuttppuutt SSiiggnnaall DW, PW RHB DW, PW RHB 21 - P1.0 21 - P1.0 TACLK TACLK ACLK ACLK TTiimmeerr NNAA SMCLK SMCLK 9 - P2.1 7 - P2.1 INCLK INCLK 22 - P1.1 22 - P1.1 TA0 CCI0A 22 - P1.1 22 - P1.1 10 - P2.2 8 - P2.2 TA0 CCI0B 26 - P1.5 26 - P1.5 CCCCRR00 TTAA00 DVSS GND DVCC VCC 23 - P1.2 23 - P1.2 TA1 CCI1A 19 - P2.3 18 - P2.3 CAOUT (internal) CCI1B 23 - P1.2 23 - P1.2 CCCCRR11 TTAA11 DVSS GND 27 - P1.6 27 - P1.6 DVCC VCC 24 - P1.3 24 - P1.3 TA2 CCI2A 20 - P2.4 19 - P2.4 ACLK (internal) CCI2B 24 - P1.3 24 - P1.3 CCCCRR22 TTAA22 DVSS GND 28 - P1.7 28 - P1.7 DVCC VCC comparator_A The primary function of the comparator_A module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 peripheral file map PERIPHERALS WITH WORD ACCESS Timer_A Reserved 017Eh Reserved 017Ch Reserved 017Ah Reserved 0178h Capture/compare register TACCR2 0176h Capture/compare register TACCR1 0174h Capture/compare register TACCR0 0172h Timer_A register TAR 0170h Reserved 016Eh Reserved 016Ch Reserved 016Ah Reserved 0168h Capture/compare control TACCTL2 0166h Capture/compare control TACCTL1 0164h Capture/compare control TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interrupt vector TAIV 012Eh Flash Memory Flash control 3 FCTL3 012Ch Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h Watchdog Watchdog/timer control WDTCTL 0120h PERIPHERALS WITH BYTE ACCESS USART0 Transmit buffer U0TXBUF 077h Receive buffer U0RXBUF 076h Baud rate U0BR1 075h Baud rate U0BR0 074h Modulation control U0MCTL 073h Receive control U0RCTL 072h Transmit control U0TCTL 071h USART control U0CTL 070h Comparator_A Comparator_A port disable CAPD 05Bh Comparator_A control2 CACTL2 05Ah Comparator_A control1 CACTL1 059h Basic Clock Basic clock sys. control2 BCSCTL2 058h Basic clock sys. control1 BCSCTL1 057h DCO clock freq. control DCOCTL 056h Port P3 Port P3 selection P3SEL 01Bh Port P3 direction P3DIR 01Ah Port P3 output P3OUT 019h Port P3 input P3IN 018h Port P2 Port P2 selection P2SEL 02Eh Port P2 interrupt enable P2IE 02Dh Port P2 interrupt edge select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h Port P1 Port P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS (CONTINUED) Special Function Module enable2 ME2 005h Module enable1 ME1 004h SFR interrupt flag2 IFG2 003h SFR interrupt flag1 IFG1 002h SFR interrupt enable2 IE2 001h SFR interrupt enable1 IE1 000h absolute maximum ratings† Voltage applied at V to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V CC SS Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V +0.3 V CC Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA Storage temperature, T (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C stg Storage temperature, T (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. recommended operating conditions MIN NOM MAX UNITS SSuuppppllyy vvoollttaaggee dduurriinngg pprrooggrraamm eexxeeccuuttiioonn, VVCC ((sseeee NNoottee 11)) 11.88 33.66 VV Supply voltage during program/erase flash memory, VCC 2.7 3.6 V Supply voltage, VSS 0 V Operating free-air temperature range, TA −40 85 °C LF mode selected, XTS=0 Watch crystal 32768 Hz LLFFXXTT11 crysttall ffrequency, ff(LFXT1) Ceramic resonator 450 8000 ((sseeee NNoottee 22)) XXTT11 sseelleecctteedd mmooddee, XXTTSS=11 kkHHzz Crystal 1000 8000 VCC = 1.8 V dc 4.15 PPrroocceessssoorr ffrreeqquueennccyy ff(system) ((MMCCLLKK ssiiggnnaall)) MMHHzz VCC = 3.6 V dc 8 NOTES: 1. The LFXT1 oscillator in LF-mode requires a resistor of 5.1 MΩ from XOUT to VSS when VCC <2.5 V. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 4 MHz at VCC ≥ 2.2 V. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 8 MHz at VCC ≥ 2.8 V. 2. The LFXT1 oscillator in LF-mode requires a watch crystal. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or crystal. f(system) (MHz) ÎÎÎÎ 8.0 MHz Supply voltage ranÎge,ÎÎÎ Supply voltage range, ’F12x, ’F12x, during ÎÎÎÎ during flash memory programming program execution ÎÎÎÎ ÎÎÎÎ 4.15 MHz ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1.8 V 2.7 V 3 V 3.6 V Supply Voltage − V NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.7 V. Figure 1. Frequency vs Supply Voltage, MSP430F12x 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) supply current (into V ) excluding external current CC PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA = −40°C +85°C, VCC = 2.2 V 200 250 ffMMCCLLKK == ff((SSMMCCLLKK)) == 11 MMHHzz,, μμAA II((AAMM)) AAccttiivvee mmooddee fP(AroCgLKra) m= 3e2x,e7c6u8t eHsz i,n Flash VCC = 3 V 300 350 TA = −40°C +85°C, VCC = 2.2 V 3 5 ff(MCLK) = ff(SMCLK) = ff(ACLK) = 44009966 HHzz, μμAA Program executes in Flash VCC = 3 V 11 18 TA = −40°C +85°C, VCC = 2.2 V 32 45 II((CCPUOOffff)) LLooww-ppoowweerr mmooddee, ((LLPPMM00)) ff(MCLK) = 00, ff(SMCLK) = 11 MMHHzz, μμAA f(ACLK) = 32,768 Hz VCC = 3 V 55 70 TA = −40°C +85°C, VCC = 2.2 V 11 14 II((LPM2)) LLooww-ppoowweerr mmooddee, ((LLPPMM22)) ff(MCLK) = ff(SMCLK) = 00 MMHHzz, μμAA f(ACLK) = 32,768 Hz, SCG0 = 0 VCC = 3 V 17 22 TA = −40°C 0.8 1.2 TA = 25°C VCCCC = 2.2 V 0.7 1 μμA TA = 85°C 1.6 2.3 II((LPM3)) LLooww-ppoowweerr mmooddee, ((LLPPMM33)) TA = −40°C 1.8 2.2 TA = 25°C VCCCC = 3 V 1.6 1.9 μμA TA = 85°C 2.3 3.4 TA = −40°C 0.1 0.5 I((LLPPMM44)) Low-ppower mode,, ((LPM4)) TA = 25°C VCCCC = 2.2 V/3 V 0.1 0.5 μμA TA = 85°C 0.8 1.9 NOTE: All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. current consumption of active mode versus system frequency IAM = IAM[1 MHz] × fsystem [MHz] current consumption of active mode versus supply voltage IAM = IAM[3 V] + 120 μA/V × (VCC−3 V) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs Port P1 to Port P3; P1.0 to P1.7, P2.0 to P2.5, P3.0 to P3.7 PARAMETER VCC MIN TYP MAX UNIT 2.2 V 1.1 1.5 VVIT+ PPoossiittiivvee-ggooiinngg iinnppuutt tthhrreesshhoolldd vvoollttaaggee 3 V 1.5 1.9 VV 2.2 V 0.4 0.9 VVIT− NNeeggaattiivvee-ggooiinngg iinnppuutt tthhrreesshhoolldd vvoollttaaggee 3 V 0.9 1.3 VV 2.2 V 0.3 1.1 VVhys IInnppuutt vvoollttaaggee hhyysstteerreessiiss, ((VVIT+ − VVIT−)) VV 3 V 0.5 1 standard inputs − RST/NMI, TEST; JTAG: TCK, TMS, TDI/TCLK PARAMETER VCC MIN TYP MAX UNIT VIL Low-level input voltage VSS VSS+0.6 V 22.22 VV//33 VV VIH High-level input voltage 0.8×VCC VCC V inputs Px.x, TAx PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 2.2 V/3 V 1.5 cycle PPoorrtt PP11,, PP22:: PP11..xx ttoo PP22..xx,, EExxtteerrnnaall t((iinntt)) External interruppt timingg trigggger siggnal for the interruppt flagg,, 2.2 V 62 ((see Note 1)) nnss 3 V 50 2.2 V 62 tt(cap) TTiimmeerr_AA, ccaappttuurree ttiimmiinngg TTAA00, TTAA11, TTAA22 nnss 3 V 50 TTiimmeerr__AA cclloocckk ffrreeqquueennccyy 2.2 V 8 ff(TAext) externally applied to pin TTAACCLLKK, IINNCCLLKK tt(H) == tt(L) 3 V 10 MMHHzz 2.2 V 8 ff(TAint) TTiimmeerr_AA cclloocckk ffrreeqquueennccyy SSMMCCLLKK oorr AACCLLKK ssiiggnnaall sseelleecctteedd MMHHzz 3 V 10 NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in MCLK cycles. leakage current (see Notes 1 and 2) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Port P1: P1.x, 0 ≤ ×≤ 7 2.2 V/3 V ±50 IIlkg(Px.x) HHiigghh-iimmppeeddaannccee lleeaakkaaggee ccuurrrreenntt Port P2: P2.x, 0 ≤ ×≤ 5 2.2 V/3 V ±50 nnAA NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional pullup or pulldown resistor. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs Port 1 to Port 3; P1.0 to P1.7, P2.0 to P2.5, P3.0 to P3.7 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(OHmax) = −1.5 mA See Note 1 VCC−0.25 VCC I(OHmax) = −6 mA VVCC = 22.22 VV See Note 2 VCC−0.6 VCC VVOH HHiigghh-lleevveell oouuttppuutt vvoollttaaggee I(OHmax) = −1.5 mA See Note 1 VCC−0.25 VCC VV I(OHmax) = −6 mA VVCC = 33 VV See Note 2 VCC−0.6 VCC I(OLmax) = 1.5 mA See Note 1 VSS VSS+0.25 I(OLmax) = 6 mA VVCC = 22.22 VV See Note 2 VSS VSS+0.6 VVOL LLooww-lleevveell oouuttppuutt vvoollttaaggee I(OLmax) = 1.5 mA See Note 1 VSS VSS+0.25 VV VVCCCC == 33 VV I(OLmax) = 6 mA See Note 2 VSS VSS+0.6 NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop specified. 2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified. outputs P1.x, P2.x, P3.x, TAx PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT f(P20) P2.0/ACLK; CL = 20 pF 2.2 V/3 V fSystem f(TAx) Output frequency TInAte0r,n TaAl 1c,lo TcAk2 s;o CuLrc =e ,2 S0M pCF,LK signal applied (see Note 1) 2.2 V/3 V dc fSystem MHz fSMCLK = fLFXT1 = fXT1 40% 60% fSMCLK = fLFXT1 = fLF 35% 65% PP11.44//SSMMCCLLKK, 22.22 VV//33 VV 50%− 50%+ CL = 20 pF fSMCLK = fLFXT1/n 15 ns 50% 15 ns t(Xdc) Dffrreeuqqtyuu eecnnyccclyye of O/P fSMCLK = fDCOCLK 2.2 V/3 V 5105% n−s 50% 5105% n+s fP20 = fLFXT1 = fXT1 40% 60% PP22.00//AACCLLKK, CCLL == 2200 ppFF fP20 = fLFXT1 = fLF 2.2 V/3 V 30% 70% fP20 = fLFXT1/n 50% t(TAdc) TA0, TA1, TA2; CL = 20 pF, Duty cycle = 50% 2.2 V/3 V 0 ±50 ns NOTE 1: The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1, P2, and P3 TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT vs vs LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE mA 32 mA 50 ent − 28 VP1C.C0 = 2.2 V TA = 25°C ent − VP1C.C0 = 3 V TA = 25°C urr urr 40 put C 24 TA = 85°C put C TA = 85°C ut ut el O 20 el O 30 v v e e L 16 L w- w- o o L L 20 al 12 al c c pi pi y y T 8 T − − 10 L L O O I 4 I 0 0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOL − Low-Level Output Voltage − V VOL − Low-Level Output Voltage − V Figure 2 Figure 3 TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT vs vs HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE A A m 0 m 0 nt − VP1C.C0 = 2.2 V nt − VP1C.C0 = 3 V urre −4 urre −10 C C put −8 put ut ut −20 O O vel −12 vel e e L L −30 h- h- Hig −16 Hig pical −20 pical −40 TA = 85°C y y − T TA = 85°C − T H H −50 IO −24 IO TA = 25°C TA = 25°C −28 −60 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH − High-Level Output Voltage − V VOH − High-Level Output Voltage − V Figure 4 Figure 5 NOTE: Only one output is loaded at a time. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) USART (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC = 2.2 V 200 430 800 tt((τ)) UUSSAARRTT:: ddeegglliittcchh ttiimmee nnss VCC = 3 V 150 280 500 NOTE 1: The signal applied to the USART receive signal/terminal (URXD) should meet the timing requirements of t(τ) to ensure that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD line. wake-up from lower power modes (LPMx) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t(LPM0) VCC = 2.2 V/3 V 100 nnss t(LPM2) VCC = 2.2 V/3 V 100 f(MCLK) = 1 MHz, VCC = 2.2 V/3 V 6 t((LLPPMM33)) f(MCLK) = 2 MHz, VCC = 2.2 V/3 V 6 μμs DDeellaayy ttiimmee ((sseeee NNoottee 11)) f(MCLK) = 3 MHz, VCC = 2.2 V/3 V 6 f(MCLK) = 1 MHz, VCC = 2.2 V/3 V 6 t((LLPPMM44)) f(MCLK) = 2 MHz, VCC = 2.2 V/3 V 6 μμs f(MCLK) = 3 MHz, VCC = 2.2 V/3 V 6 NOTE 1: Parameter applicable only if DCOCLK is used for MCLK. RAM PARAMETER MIN NOM MAX UNIT V(RAMh) CPU halted (see Note 1) 1.6 V NOTE 1: This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program execution should happen during this supply voltage condition. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Comparator_A (see Note 1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 2.2 V 25 40 II((DD)) CCAAOONN==11, CCAARRSSEELL==00, CCAARREEFF==00 μμAA 3 V 45 60 CAON=1, CARSEL=0, 2.2 V 30 50 II((RReeffllaaddddeerr// CCAARREEFF=11//22//33, NNoo llooaadd aatt μμAA RefDiode) P2.3/CA0/TA1 and P2.4/CA1/TA2 3 V 45 71 V(IC) Common-mode input voltage CAON =1 2.2 V/3 V 0 VCC−1 V PCA0=1, CARSEL=1, CAREF=1, V(Ref025) Voltageat0.25VCCnode No load at P2.3/CA0/TA1 and 2.2 V/3 V 0.23 0.24 0.25 V P2.4/CA1/TA2 CC PCA0=1, CARSEL=1, CAREF=2, Voltageat0.5V node V(Ref050) CC No load at P2.3/CA0/TA1 and 2.2 V/3 V 0.47 0.48 0.5 V CC P2.4/CA1/TA2 PCA0=1, CARSEL=1, CAREF=3, 2.2 V 390 480 540 VV(RefVT) ((sseeee FFiigguurree 66 aanndd FFiigguurree 77)) NNoo llooaadd aatt PP22.33//CCAA00//TTAA11 aanndd mmVV P2.4/CA1/TA2, TA = 85°C 3 V 400 490 550 V(offset) Offset voltage See Note 2 2.2 V/3 V −30 30 mV Vhys Input hysteresis CAON=1 2.2 V/3 V 0 0.7 1.4 mV TTAA == 2255°CC,, OOvveerrddrriivvee 1100 mmVV,, 2.2 V 160 210 300 nnss Without filter: CAF=0 3 V 80 150 240 tt(response LH) TTAA == 2255°CC,, OOvveerrddrriivvee 1100 mmVV,, 2.2 V 1.4 1.9 3.4 μμss With filter: CAF=1 3 V 0.9 1.5 2.6 TTAA == 2255°CC,, 2.2 V 130 210 300 nnss Overdrive 10 mV, without filter: CAF=0 3 V 80 150 240 tt(response HL) TTAA == 2255°CC,, 2.2 V 1.4 1.9 3.4 μμss Overdrive 10 mV, with filter: CAF=1 3 V 0.9 1.5 2.6 NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 650 650 VCC = 3 V VCC = 2.2 V V 600 V 600 m m − − s s olt Typical olt Typical V V e 550 e 550 c c n n e e er er ef ef − R 500 − R 500 T) T) V V F F E E V(R 450 V(R 450 400 400 −45 −25 −5 15 35 55 75 95 −45 −25 −5 15 35 55 75 95 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 6. V vs Temperature, V = 3 V Figure 7. V vs Temperature, V = 2.2 V (RefVT) CC (RefVT) CC 0 V VCC 0 1 CAF CAON Low Pass Filter To Internal Modules 0 0 V+ + _ V− 1 1 CAOUT Set CAIFG Flag τ ≈ 2.0 μs Figure 8. Block Diagram of Comparator_A Module Overdrive VCAOUT V− 400 mV V+ t(response) Figure 9. Overdrive Definition POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) PUC/POR PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t(POR_Delay) Internal time delay to release POR 150 250 μs VVCCCC tthhrreesshhoolldd aatt wwhhiicchh PPOORR TA = −40°C 1.4 1.8 V VVPPOORR rreelleeaassee ddeellaayy ttiimmee bbeeggiinnss TA = 25°C 1.1 1.5 V (see Note 1) TA = 85°C VCC = 2.2 V/3 V 0.8 1.2 V V(min) VgeCnCe trhartees ah oPldO Rre q(sueiree dN otote 2) VCC |dV/dt| ≥ 1V/ms 0.2 V t(reset) RST/NMI low time for PUC/POR Reset is accepted internally 2 μs NOTES: 1. VCC rise time dV/dt ≥ 1V/ms. 2. When driving VCC low in order to generate a POR condition, VCC should be driven to 200mV or lower with a dV/dt equal to or less than −1V/ms. The corresponding rising VCC must also meet the dV/dt requirement equal to or greater than +1V/ms. V VCC V POR No POR POR POR V (min) t Figure 10. Power-On Reset (POR) vs Supply Voltage 2.0 1.8 1.8 1.6 1.5 Max V [V]POR 111...204 1.4 1.1 Min 1.2 0.8 0.8 0.6 0.4 0.2 25°C 0 −40 −20 0 20 40 60 80 Temperature [°C] Figure 11. V vs Temperature POR 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) DCO PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 2.2 V 0.08 0.12 0.15 ff(DCO03) RRsel = 00, DDCCOO = 33, MMOODD = 00, DDCCOORR = 00, TTA = 2255°°CC 3 V 0.08 0.13 0.16 MMHHzz 2.2 V 0.14 0.19 0.23 ff(DCO13) RRsel = 11, DDCCOO = 33, MMOODD = 00, DDCCOORR = 00, TTA = 2255°°CC 3 V 0.14 0.18 0.22 MMHHzz 2.2 V 0.22 0.30 0.36 ff((DCCOO23)) RRsel == 22, DDCCOO == 33, MMOODD == 00, DDCCOORR == 00, TTA == 2255°°CC MMHHzz 3 V 0.22 0.28 0.34 2.2 V 0.37 0.49 0.59 ff((DCCOO33)) RRsel == 33, DDCCOO == 33, MMOODD == 00, DDCCOORR == 00, TTA == 2255°°CC MMHHzz 3 V 0.37 0.47 0.56 2.2 V 0.61 0.77 0.93 ff((DCCOO43)) RRsel == 44, DDCCOO == 33, MMOODD == 00, DDCCOORR == 00, TTA == 2255°°CC MMHHzz 3 V 0.61 0.75 0.9 2.2 V 1 1.2 1.5 ff((DCCOO53)) RRsel == 55, DDCCOO == 33, MMOODD == 00, DDCCOORR == 00, TTA == 2255°°CC MMHHzz 3 V 1 1.3 1.5 2.2 V 1.6 1.9 2.2 ff((DCCOO63)) RRsel == 66, DDCCOO == 33, MMOODD == 00, DDCCOORR == 00, TTA == 2255°°CC MMHHzz 3 V 1.69 2 2.29 2.2 V 2.4 2.9 3.4 ff((DCCOO73)) RRsel == 77, DDCCOO == 33, MMOODD == 00, DDCCOORR == 00, TTA == 2255°°CC MMHHzz 3 V 2.7 3.2 3.65 2.2 V 4 4.5 4.9 ff((DCCOO77)) RRsel == 77, DDCCOO == 77, MMOODD == 00, DDCCOORR == 00, TTA == 2255°°CC MMHHzz 3 V 4.4 4.9 5.4 ff((DCCOO47)) RRsel == 44, DDCCOO == 77, MMOODD == 00, DDCCOORR == 00, TTA == 2255°°CC 22.22 VV//33 VV FFDDCCxOO144.700 FFDDCCxOO244.100 FFDDCCxOO244.500 MMHHzz S(Rsel) SR = fRsel+1/fRsel 2.2 V/3 V 1.35 1.65 2 rraattiioo S(DCO) SDCO = fDCO+1/fDCO 2.2 V/3 V 1.07 1.12 1.16 2.2 V −0.31 −0.36 −0.40 DDt TTeemmppeerraattuurree ddrriifftt, RRsel == 44, DDCCOO == 33, MMOODD == 00 ((sseeee NNoottee 11)) %%//°°CC 3 V −0.33 −0.38 −0.43 DV D(sreifet wNiothte V 1C)C variation, Rsel = 4, DCO = 3, MOD = 0 2.2 V/3 V 0 5 10 %/V NOTES: 1. These parameters are not production tested. ÎÎÎÎÎ e Max nc f(DCOx7) ÎÎÎÎÎ a Min ari K V L y C nc 1 CO ue ÎÎÎÎÎ D q Max f re f(DCOx0) ÎÎÎÎÎ F Min 0 1 2 3 4 5 6 7 2.2 V 3 V VCC DCO Steps Figure 12. DCO Characteristics POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) main DCO characteristics (cid:2) Individual devices have a minimum and maximum operation frequency. The specified parameters for f(DCOx0) to f(DCOx7) are valid for all devices. (cid:2) All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7. (cid:2) DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter S . DCO (cid:2) Modulation control bits MOD0 to MOD4 select how often f(DCO+1) is used within the period of 32 DCOCLK cycles. The frequency f is used for the remaining cycles. The frequency is an average equal to: (DCO) 32(cid:3)f (cid:3)f f (cid:2) (DCO) (DCO(cid:4)1) average MOD(cid:3)f (cid:4)(32(cid:5)MOD)(cid:3)f (DCO) (DCO(cid:4)1) DCO when using ROSC (see Note 1) PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT ffDCO, DDCCOO oouuttppuutt ffrreeqquueennccyy RRTAss ee=ll ==2 544°,, CDDCCOO == 33,, MMOODD == 00,, DDCCOORR == 11,, 23. 2V V 11.9.85±±1155%% MMHHzz Dt, Temperature drift Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 2.2 V/3 V ±0.1 %/°C Dv, Drift with VCC variation Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 2.2 V/3 V 10 %/V NOTES: 1. ROSC = 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ±50ppm/°C. crystal oscillator, LFXT1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT XTS=0; LF mode selected. 12 VCC = 2.2 V / 3 V CCXIN IInnppuutt ccaappaacciittaannccee XTS=1; XT1 mode selected. ppFF 2 VCC = 2.2 V / 3 V (see Note 1) XTS=0; LF mode selected. 12 VCC = 2.2 V / 3 V CCXOOUT OOuuttppuutt ccaappaacciittaannccee ppFF XTS=1; XT1 mode selected. 2 VCC = 2.2 V / 3 V (see Note 1) VIL VSS 0.2×VCC VIH IInnppuutt lleevveellss aatt XXIINN VVCCCC == 22.22 VV//33 VV ((sseeee NNoottee 22)) 0.8×VCC VCC VV NOTES: 1. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Flash Memory TEST PARAMETER CONDITIONS VCC MIN NOM MAX UNIT VCC(PGM/ ERASE) Program and Erase supply voltage 2.7 3.6 V fFTG Flash Timing Generator frequency 257 476 kHz IPGM Supply current from VCC during program 2.7 V/ 3.6 V 3 5 mA IERASE Supply current from VCC during erase 2.7 V/ 3.6 V 3 7 mA tCPT Cumulative program time see Note 1 2.7 V/ 3.6 V 4 ms tCMErase Cumulative mass erase time see Note 2 2.7 V/ 3.6 V 200 ms Program/Erase endurance 104 105 cycles tRetention Data retention duration TJ = 25°C 100 years tWord Word or byte program time 35 tBlock, 0 Block program time for 1st byte or word 30 tBlock, 1-63 Block program time for each additional byte or word 21 tBlock, End Block program end-sequence wait time sseeee NNoottee 33 6 ttFTG tMass Erase Mass erase time 5297 tSeg Erase Segment erase time 4819 NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. 2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles are required). 3. These values are hardwired into the Flash Controller’s state machine; tFTG = 1/fFTG. JTAG Interface TEST PARAMETER CONDITIONS VCC MIN NOM MAX UNIT 2.2 V 0 5 MHz ffTCK TTCCKK iinnppuutt ffrreeqquueennccyy sseeee NNoottee 11 3 V 0 10 MHz RInternal Internal pull-down resistance on TEST see Note 2 2.2 V/ 3 V 25 60 90 kΩ NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected. 2. TEST pull-down resistor implemented in all versions. JTAG Fuse (see Note 1) TEST PARAMETER CONDITIONS VCC MIN NOM MAX UNIT VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V VFB Voltage level on TEST for fuse-blow 6 7 V IFB Supply current into TEST during fuse blow 100 mA tFB Time to blow fuse 1 ms NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION input/output schematic Port P1, P1.0 to P1.3, input/output with Schmitt-trigger P1SEL.x 0 P1DIR.x Direction Control 1 From Module 0 Pad Logic P1OUT.x 1 Module X OUT P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1IN.x EN Module X IN D P1IRQ.x P1IE.x Interrupt EN Q Edge P1IFG.x Set Select Interrupt Flag P1IES.x P1SEL.x NOTE: x = Bit/identifier, 0 to 3 for port P1 P1Sel.0 P1DIR.0 P1DIR.0 P1OUT.0 VSS P1IN.0 TACLK† P1IE.0 P1IFG.0 P1IES.0 P1Sel.1 P1DIR.1 P1DIR.1 P1OUT.1 Out0 signal† P1IN.1 CCI0A† P1IE.1 P1IFG.1 P1IES.1 P1Sel.2 P1DIR.2 P1DIR.2 P1OUT.2 Out1 signal† P1IN.2 CCI1A† P1IE.2 P1IFG.2 P1IES.2 P1Sel.3 P1DIR.3 P1DIR.3 P1OUT.3 Out2 signal† P1IN.3 CCI2A† P1IE.3 P1IFG.3 P1IES.3 †Signal from or to Timer_A 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION input/output schematic (continued) Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features P1SEL.x 0 P1DIR.x Direction Control 1 From Module 00 P1OUT.x Pad Logic 11 P1.4−P1.7 Module X OUT TST Bus Keeper P1IN.x EN DVCC Module X IN D TEST P1IRQ.x P1IE.x Interrupt 60 kΩ Q EN Edge Typical P1IFG.x Set Select Bum Interrupt Control by Flag P1IES.x JTAG and Test Fuse P1SEL.x P1.x TDO Controlled By JTAG P1.7/TA2/TDO/TDI Controlled by JTAG TDI/TCLK TST P1.x P1.6/TA1/TDI/TCLK NOTE: The test pin should be protected from potential EMI and ESD voltage spikes. This may require a smaller TST P1.x TMS external pulldown resistor in some applications. P1.5/TA0/TMS x = Bit identifier, 4 to 7 for port P1 During programming activity and during blowing TST P1.x the fuse, the pin TDO/TDI is used to apply the test TCK input for JTAG circuitry. P1.4/SMCLK/TCK P1Sel.4 P1DIR.4 P1DIR.4 P1OUT.4 SMCLK P1IN.4 unused P1IE.4 P1IFG.4 P1IES.4 P1Sel.5 P1DIR.5 P1DIR.5 P1OUT.5 Out0 signal† P1IN.5 unused P1IE.5 P1IFG.5 P1IES.5 P1Sel.6 P1DIR.6 P1DIR.6 P1OUT.6 Out1 signal† P1IN.6 unused P1IE.6 P1IFG.6 P1IES.6 P1Sel.7 P1DIR.7 P1DIR.7 P1OUT.7 Out2 signal† P1IN.7 unused P1IE.7 P1IFG.7 P1IES.7 †Signal from or to Timer_A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION input/output schematic (continued) Port P2, P2.0 to P2.2, input/output with Schmitt-trigger P2SEL.x 0 P2DIR.x 0: Input Direction Control 1 1: Output From Module 0 Pad Logic P2OUT.x P2.0/ACLK 1 Module X OUT P2.1/INCLK P2.2/CAOUT/TA0 Bus Keeper P2IN.x EN Module X IN D CAPD.X P2IRQ.x P2IE.x Interrupt EN Q Edge P2IFG.x Set Select Interrupt NOTE: x = Bit identifier, 0 to 2 for port P2 Flag P2IES.x P2SEL.x DIRECTION PnSel.x PnDIR.x CONTROL PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x FROM MODULE P2Sel.0 P2DIR.0 P2DIR.0 P2OUT.0 ACLK P2IN.0 unused P2IE.0 P2IFG.0 P1IES.0 P2Sel.1 P2DIR.1 P2DIR.1 P2OUT.1 VSS P2IN.1 INCLK† P2IE.1 P2IFG.1 P1IES.1 P2Sel.2 P2DIR.2 P2DIR.2 P2OUT.2 CAOUT P2IN.2 CCI0B† P2IE.2 P2IFG.2 P1IES.2 †Signal from or to Timer_A 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION input/output schematic (continued) Port P2, P2.3 to P2.4, input/output with Schmitt-trigger P2SEL.3 0 P2DIR.3 0: Input Direction Control 1 1: Output From Module P2OUT.3 0 Pad Logic P2.3/CA0/TA1 1 Module X OUT P2IN.3 Bus Keeper EN Module X IN D P2IRQ.3 P2IE.3 EN Interrupt P2IFG.3 Q Set SEedlegcet CAPD.3 Interrupt Comparator_A CAREF P2CA CAEX Flag P2IES.3 P2SEL.3 CAF CCI1B + _ 0 V Interrupt P2IES.4 P2SEL.4 Flag CAREF Reference Block P2IFG.4 Q Set InEtedrgruept CAPD.4 P2IRQ.4 P2IE.4 EN Select Module X IN D EN Bus Keeper P2IN.4 Module X OUT 1 P2OUT.4 0 Pad Logic P2.4/CA1/TA2 Direction Control From Module 1 1: Output P2DIR.4 0: Input P2SEL.4 0 DIRECTION PnSel.x PnDIR.x CONTROL PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x FROM MODULE P2Sel.3 P2DIR.3 P2DIR.3 P2OUT.3 Out1 signal† P2IN.3 unused P2IE.3 P2IFG.3 P1IES.3 P2Sel.4 P2DIR.4 P2DIR.4 P2OUT.4 Out2 signal† P2IN.4 unused P2IE.4 P2IFG.4 P1IES.4 †Signal from Timer_A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION input/output schematic (continued) Port P2, P2.5, input/output with Schmitt-trigger and R function for the Basic Clock module OSC P2SEL.5 0 0: Input Pad Logic P2DIR.5 1: Output Direction Control 1 From Module 00 P2OUT.5 P2.5/ROSC 11 Module X OUT P2IN.5 Bus Keeper EN Module X IN D Internal to Basic Clock P2IRQ.5 P2IE.5 Module EN Interrupt VCC 0 1 Q Edge P2IFG.5 Select Set Interrupt Flag P2IES.5 DCOR DC Generator P2SEL.5 CAPD.5 NOTE: DCOR: Control bit from Basic Clock Module if it is set, P2.5 Is disconnected from P2.5 pad DIRECTION PnSel.x PnDIR.x CONTROL PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x FROM MODULE P2Sel.5 P2DIR.5 P2DIR.5 P2OUT.5 VSS P2IN.5 unused P2IE.5 P2IFG.5 P2IES.5 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION input/output schematic (continued) Port P2, unbonded bits P2.6 and P2.7 P2SEL.x 0 0: Input P2DIR.x 1: Output Direction Control 1 From Module 00 P2OUT.x 11 Module X OUT P2IN.x Node Is Reset With PUC EN Bus Keeper Module X IN D P2IRQ.x P2IE.x Interrupt PUC EN Q Edge P2IFG.x Select Set Interrupt P2IES.x Flag P2SEL.x NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins DIRECTION- P2Sel.x P2DIR.x CONTROL P2OUT.x MODULE X OUT P2IN.x MODULE X IN P2IE.x P2IFG.x P2IES.x FROM MODULE P2Sel.6 P2DIR.6 P2DIR.6 P2OUT.6 VSS P2IN.6 unused P2IE.6 P2IFG.6 P2IES.6 P2Sel.7 P2DIR.7 P2DIR.7 P2OUT.7 VSS P2IN.7 unused P2IE.7 P2IFG.7 P2IES.7 NOTE: Unbonded bits 6 and 7 of port P2 can be used as interrupt flags. Only software can affect the interrupt flags. They work as software interrupts. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION input/output schematic (continued) port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt-trigger P3SEL.x 0: Input P3DIR.x 0 1: Output Direction Control From Module 1 Pad Logic 0 P3.0/STE0 P3OUT.x Module X OUT 1 P3.4/UTXD0 P3.5/URXD0 P3.6 P3.7 P3IN.x EN Module X IN D x: Bit Identifier, 0 and 4 to 7 for Port P3 DIRECTION PnSel.x PnDIR.x CONTROL PnOUT.x MODULE X OUT PnIN.x MODULE X IN FROM MODULE P3Sel.0 P3DIR.0 VSS P3OUT.0 VSS P3IN.0 STE0 P3Sel.4 P3DIR.4 VCC P3OUT.4 UTXD0† P3IN.4 Unused P3Sel.5 P3DIR.5 VSS P3OUT.5 VSS P3IN.5 URXD0‡ P3Sel.6 P3DIR.6 VSS P3OUT.6 VSS P3IN.6 Unused P3Sel.7 P3DIR.7 VSS P3OUT.7 VSS P3IN.7 Unused †Output from USART0 module ‡Input to USART0 module port P3, P3.1, input/output with Schmitt-trigger P3SEL.1 0: Input 0 1: Output SYNC P3DIR.1 MM DCM_SIMO 1 STC Pad Logic STE 0 P3.1/SIMO0 P3OUT1 (SI)MO0 1 From USART0 P3IN.1 EN SI(MO)0 D To USART0 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION input/output schematic (continued) port P3, P3.2, input/output with Schmitt-trigger P3SEL.2 0: Input 0 1: Output SYNC P3DIR.2 MM DCM_SOMI 1 STC Pad Logic STE 0 P3.2/SOMI0 P3OUT.2 SO(MI)0 1 From USART0 P3IN.2 EN (SO)MI0 D To USART0 port P3, P3.3, input/output with Schmitt-trigger P3SEL.3 0: Input 0 1: Output SYNC P3DIR.3 MM DCM_UCLK 1 STC Pad Logic STE 0 P3.3/UCLK0 P3OUT.3 UCLK.0 1 From USART0 P3IN.3 EN UCLK0 D To USART0 NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always an input. SPI, slave mode: The clock applied to UCLK0 is used to shift data in and out. SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31

MSP430x12x MIXED SIGNAL MICROCONTROLLER SLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION JTAG fuse check mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, a fuse check current, I , of 1 mA at 3 V, 2.5 mA at 5 V can flow from from the TEST pin to ground if TF the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense currents are terminated. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see Figure 13). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). Time TMS Goes Low After POR TMS ITF ITEST Figure 13. Fuse Check Mode Current, MSP430F12x NOTE: The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader access key is used. Also see the bootstrap loader section for more information. 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MSP430F122IDW ACTIVE SOIC DW 28 20 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 M430F122 & no Sb/Br) MSP430F122IPW ACTIVE TSSOP PW 28 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 M430F122 & no Sb/Br) MSP430F122IPWR ACTIVE TSSOP PW 28 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 M430F122 & no Sb/Br) MSP430F122IRHBR ACTIVE VQFN RHB 32 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 MSP430 & no Sb/Br) F122 MSP430F122IRHBT ACTIVE VQFN RHB 32 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 MSP430 & no Sb/Br) F122 MSP430F123IDW ACTIVE SOIC DW 28 20 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 M430F123 & no Sb/Br) MSP430F123IDWR ACTIVE SOIC DW 28 1000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 M430F123 & no Sb/Br) MSP430F123IPW ACTIVE TSSOP PW 28 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 M430F123 & no Sb/Br) MSP430F123IPWR ACTIVE TSSOP PW 28 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 M430F123 & no Sb/Br) MSP430F123IPWR-HYD ACTIVE TSSOP PW 28 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 M430F123 & no Sb/Br) MSP430F123IRHBR ACTIVE VQFN RHB 32 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 MSP430 & no Sb/Br) F123 MSP430F123IRHBT ACTIVE VQFN RHB 32 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 MSP430 & no Sb/Br) F123 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) MSP430F122IPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 MSP430F122IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 MSP430F122IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 MSP430F123IDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 MSP430F123IPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 MSP430F123IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 MSP430F123IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) MSP430F122IPWR TSSOP PW 28 2000 350.0 350.0 43.0 MSP430F122IRHBR VQFN RHB 32 3000 367.0 367.0 35.0 MSP430F122IRHBT VQFN RHB 32 250 210.0 185.0 35.0 MSP430F123IDWR SOIC DW 28 1000 350.0 350.0 66.0 MSP430F123IPWR TSSOP PW 28 2000 350.0 350.0 43.0 MSP430F123IRHBR VQFN RHB 32 3000 367.0 367.0 35.0 MSP430F123IRHBT VQFN RHB 32 250 210.0 185.0 35.0 PackMaterials-Page2

GENERIC PACKAGE VIEW RHB 32 VQFN - 1 mm max height 5 x 5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224745/A www.ti.com

PACKAGE OUTLINE RHB0032E VQFN - 1 mm max height SCALE 3.000 PLASTIC QUAD FLATPACK - NO LEAD A 5.1 B 4.9 PIN 1 INDEX AREA 5.1 (0.1) 4.9 SIDE WALL DETAIL OPTIONAL ME20.000TAL THICKNESS C 1 MAX SEATING PLANE 0.05 0.00 0.08 C 2X 3.5 3.45 0.1 (0.2) TYP 9 16 EXPOSED THERMAL PAD 28X 0.5 8 17 SEE SIDE WALL DETAIL 2X 33 SYMM 3.5 0.3 32X 0.2 24 0.1 C A B 1 0.05 C 32 25 PIN 1 ID SYMM (OPTIONAL) 0.5 32X 0.3 4223442/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RHB0032E VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 3.45) SYMM 32 25 32X (0.6) 1 24 32X (0.25) (1.475) 28X (0.5) 33 SYMM (4.8) ( 0.2) TYP VIA 8 17 (R0.05) TYP 9 16 (1.475) (4.8) LAND PATTERN EXAMPLE SCALE:18X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL OPENING SOLDER MASK METAL UNDER OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4223442/B 08/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RHB0032E VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4X ( 1.49) (R0.05) TYP (0.845) 32 25 32X (0.6) 1 24 32X (0.25) 28X (0.5) (0.845) SYMM 33 (4.8) 8 17 METAL TYP 9 16 SYMM (4.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 33: 75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4223442/B 08/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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