(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 (cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:13)(cid:15)(cid:16)(cid:17)(cid:18)(cid:16)(cid:19)(cid:20)(cid:15)(cid:21)(cid:22)(cid:23)(cid:15)(cid:22)(cid:24)(cid:13)(cid:21)(cid:13)(cid:23)(cid:19)(cid:20)(cid:17)(cid:3)(cid:15)(cid:16)(cid:25)(cid:11)(cid:10)(cid:23)(cid:11)(cid:10) (cid:26)(cid:18)(cid:24)(cid:3)(cid:27) (cid:19)(cid:16)(cid:28) (cid:24)(cid:13)(cid:21)(cid:13)(cid:23)(cid:19)(cid:20)(cid:22)(cid:23)(cid:15)(cid:22)(cid:18)(cid:16)(cid:19)(cid:20)(cid:15)(cid:21) (cid:3)(cid:15)(cid:16)(cid:25)(cid:11)(cid:10)(cid:23)(cid:11)(cid:10)(cid:14) (cid:26)(cid:24)(cid:18)(cid:3)(cid:14)(cid:27) (cid:29)(cid:13)(cid:23)(cid:30) (cid:31)!"(cid:4) (cid:1)(cid:13)(cid:12)(cid:10)(cid:15)(cid:12)(cid:15)(cid:16)(cid:23)(cid:10)(cid:15)(cid:20)(cid:20)(cid:11)(cid:10) (cid:19)(cid:16)(cid:28) #(cid:20)(cid:19)(cid:14)(cid:30) (cid:1)(cid:11)$(cid:15)(cid:10)% FEATURES Peripheral Features (cid:1) 34 I/O Pins ANALOG FEATURES (cid:1) Additional 32-Bit Accumulator (cid:1) (cid:1) 24 Bits No Missing Codes Three 16-Bit Timer/Counters (cid:1) (cid:1) 22 Bits Effective Resolution at 10Hz System Timers − Low Noise: 75nV (cid:1) Programmable Watchdog Timer (cid:1) PGA From 1 to 128 (cid:1) Full-Duplex Dual USARTs (cid:1) Precision On-Chip Voltage Reference (cid:1) Master/Slave SPI with DMA − Accuracy: 0.2% (cid:1) Multi-master I2C (MSC1211 and MSC1213) − Drift: 5ppm/°C (cid:1) 16-Bit PWM (cid:1) 8 Differential/Single-Ended Channels (cid:1) Power Management Control (cid:1) On-Chip Offset/Gain Calibration (cid:1) Internal Clock Divider (cid:1) Offset Drift: 0.1ppm/°C (cid:1) Idle Mode Current < 200µA (cid:1) Gain Drift: 0.5ppm/°C (cid:1) Stop Mode Current < 100nA (cid:1) On-Chip Temperature Sensor (cid:1) Programmable Brownout Reset (cid:1) Selectable Buffer Input (cid:1) Programmable Low-Voltage Detect (cid:1) Burnout Detect (cid:1) 24 Interrupt Sources (cid:1) 16-Bit Monotonic Voltage DACS: (cid:1) Two Hardware Breakpoints − Quad Voltage DACs (MSC1211, MSC1212) − Dual Voltage DACs (MSC1213, MSC1214) GENERAL FEATURES (cid:1) DIGITAL FEATURES Pin-Compatible with MSC1210 (cid:1) Package: TQFP-64 Microcontroller Core (cid:1) (cid:1) Low Power: 4mW 8051-Compatible (cid:1) (cid:1) Industrial Temperature Range: High-Speed Core −40°C to +125°C − 4 Clocks per Instruction Cycle (cid:1) (cid:1) DC to 40MHz at +85(cid:1)C Power Supply: 2.7V to 5.25V (cid:1) Single Instruction 100ns (cid:1) Dual Data Pointer APPLICATIONS Memory (cid:1) Industrial Process Control (cid:1) Up To 32kB Flash Memory (cid:1) Instrumentation (cid:1) Flash Memory Partitioning (cid:1) Liquid/Gas Chromatography (cid:1) Endurance 1M Erase/Write Cycles, (cid:1) Blood Analysis 100-Year Data Retention (cid:1) Smart Transmitters (cid:1) In-System Serially Programmable (cid:1) Portable Instruments (cid:1) External Program/Data Memory (64kB) (cid:1) Weigh Scales (cid:1) 1,280 Bytes Data SRAM (cid:1) Pressure Transducers (cid:1) Flash Memory Security (cid:1) Intelligent Sensors (cid:1) 2kB Boot ROM (cid:1) Portable Applications (cid:1) Programmable Wait State Control (cid:1) DAS Systems Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of Philips corporation. SPI is a trademark of Motorola Inc. All other trademarks are the property of their respective owners. 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(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 PACKAGE/ORDERING INFORMATION(1) FLASH PACKAGE PRODUCT MEMORY 16-BIT DACS I2C MARKING MSC1211Y2 4k 4 Y MSC1211Y2 MSC1211Y3 8k 4 Y MSC1211Y3 MSC1211Y4 16k 4 Y MSC1211Y4 MSC1211Y5 32k 4 Y MSC1211Y5 MSC1212Y2 4k 4 N MSC1212Y2 MSC1212Y3 8k 4 N MSC1212Y3 MSC1212Y4 16k 4 N MSC1212Y4 MSC1212Y5 32k 4 N MSC1212Y4 MSC1213Y2 4k 2 Y MSC1213Y2 MSC1213Y3 8k 2 Y MSC1213Y3 MSC1213Y4 16k 2 Y MSC1213Y4 MSC1213Y5 32k 2 Y MSC1213Y5 MSC1214Y2 4k 2 N MSC1214Y2 MSC1214Y3 8k 2 N MSC1214Y3 MSC1214Y4 16k 2 N MSC1214Y4 MSC1214Y5 32k 2 N MSC1214Y5 (1)For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet, or refer to our web site at www.ti.com. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS(1) MSC1211/12/13/14 UNITS Analog Inputs Momentary 100 mA IInnppuutt ccuurrrreenntt Continuous 10 mA Input voltage AGND − 0.3 to AVDD + 0.3 V Power Supply DVDD to DGND −0.3 to +6 V AVDD to AGND −0.3 to +6 V AGND to DGND −0.3 to +0.3 V VREF to AGND −0.3 to AVDD + 0.3 V Digital input voltage to DGND −0.3 to DVDD + 0.3 V Digital output voltage to DGND −0.3 to DVDD + 0.3 V Maximum junction temperature (TJ Max) +150 °C Operating temperature range −40 to +125 °C Storage temperature range −65 to +150 °C High K (2s 2p) 48.9 °C/W TThheerrmmaall rreessiissttaannccee JJuunnccttiioonn ttoo aammbbiieenntt (((cid:1)(cid:1)JJAA)) Low K (1s) 72.9 °C/W Junction to case ((cid:1)JC) 12.2 °C/W Package power dissipation (TJ Max − TAMBIENT)/(cid:1)JA W Output current, all pins 200 mA Output pin short-circuit 10 s Digital Outputs Output current Continuous 100 mA I/O source/sink current 100 mA Power pin maximum 300 mA (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. 2

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 MSC121xYX FAMILY FEATURES FEATURES(1) MSC121xY2(2) MSC121xY3(2) MSC121xY4(2) MSC121xY5(2) Flash Program Memory (Bytes) Up to 4k Up to 8k Up to 16k Up to 32k Flash Data Memory (Bytes) Up to 4k Up to 8k Up to 16k Up to 32k Internal Scratchpad SRAM (Bytes) 256 256 256 256 Internal MOVX RAM (Bytes) 1024 1024 1024 1024 Externally Accessible Memory (Bytes) 64k Program, 64k Data 64k Program, 64k Data 64k Program, 64k Data 64k Program, 64k Data (1) All peripheral features are the same on all devices; the flash memory size is the only difference. (2) The last digit of the part number (N) represents the onboard flash size = (2N)kBytes. ELECTRICAL CHARACTERISTICS: AV = 5V DD All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +5V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted. MSC1211/12/13/14 PARAMETER CONDITIONS MIN TYP MAX UNITS Analog Inputs (AIN0−AIN7, AINCOM) Buffer OFF AGND − 0.1 AVDD + 0.1 V AAnnaalloogg IInnppuutt RRaannggee Buffer ON AGND + 50mV AVDD − 1.5 V Full-Scale Input Voltage Range (AIN+) − (AIN−) ±VREF/PGA V Differential Input Impedance Buffer OFF 7/PGA(1) MΩ Input Current Buffer ON 0.5 nA Fast Settling Filter −3dB 0.469 • fDATA BBaannddwwiiddtthh Sinc2 Filter −3dB 0.318 • fDATA Sinc3 Filter −3dB 0.262 • fDATA Programmable Gain Amplifier User-Selectable Gain Range 1 128 Input Capacitance Buffer ON 9 pF Input Leakage Current Multiplexer Channel OFF, T = +25°C 0.5 pA Burnout Current Sources Buffer ON ±2 µA ADC Offset DAC Offset DAC Range Bipolar Mode ±VREF/(2 •PGA) V Offset DAC Monotonicity 8 Bits Offset DAC Gain Error ±1.5 % of Range Offset DAC Gain Error Drift 1 ppm/°C System Performance Resolution 24 Bits ENOB See Typical Characteristics 22 Bits Output Noise See Typical Characteristics No Missing Codes Sinc3 Filter, Decimation > 360 24 Bits Integral Nonlinearity End Point Fit, Bipolar Mode 0.0003 ±0.0015 %FSR Offset Error After Calibration ±3.5 ppm of FS Offset Drift(2) Before Calibration 0.1 ppm of FS/°C Gain Error(3) After Calibration −0.002 % Gain Error Drift(2) Before Calibration 0.5 ppm/°C System Gain Calibration Range 80 120 % of FS System Offset Calibration Range −50 50 % of FS At DC 115 dB fCM = 60Hz, fDATA = 10Hz 130 dB CCoommmmoonn--MMooddee RReejjeeccttiioonn fCM = 50HZ, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB fSIG = 50Hz, fDATA = 50Hz 100 dB NNoorrmmaall--MMooddee RReejjeeccttiioonn fSIG = 60Hz, fDATA = 60Hz 100 dB Power-Supply Rejection At DC, dB = −20log(∆VOUT/∆VDD)(4) 92 dB (1) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). (2) Calibration can minimize these errors. (3) The self gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. (4) ∆VOUT is change in digital result. (5) 9pF switched capacitor at fSAMP clock frequency (see Figure 14). (6) Linearity calculated using a reduced code range of 512 to 65024; output unloaded. (7) Ensured by design and characterization; not production tested. (8) Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1). 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS: AV = 5V (continued) DD All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +5V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted. MSC1211/12/13/14 PARAMETER CONDITIONS MIN TYP MAX UNITS Voltage Reference Inputs Reference Input Range REF IN+, REF IN− AGND AVDD(3) V VREF VREF ≡ (REF IN+) − (REF IN−) 0.1 2.5 AVDD V VREF Common-Mode Rejection At DC 110 dB Input Current(5) VREF = 2.5V, ADC Only 1 µA DAC Reference Input Resistance For Each DAC, PGA = 1 20 kΩ On-Chip Voltage Reference VREFH = 1 at +25°C, REFCLK = 250kHz 2.495 2.5 2.505 V OOuuttppuutt VVoollttaaggee VREFH = 0 at +25°C, REFCLK = 250kHz 1.25 V Power-Supply Rejection Ratio 65 dB Short-Circuit Current Source 2.6 mA Short-Circuit Current Sink 50 µA Short-Circuit Duration Sink or Source Indefinite Drift 5 ppm/°C Output Impedance Sourcing 100µA 3 Ω Startup Time from Power ON CREFOUT = 0.1µF 8 ms Temperature Sensor Voltage Buffer ON, T = +25°C 115 mV Temperature Sensor Coefficient Buffer ON 375 µV/°C Voltage DAC Static Performance(6) Resolution 16 Bits Relative Accuracy ±0.05 ±0.146 %FSR Differential Nonlinearity Ensured Monotonic by Design ±1 LSB Zero Code Error All 0s Loaded to DAC Register +13 +35 mV Full-Scale Error All 1s Loaded to DAC Register −1.25 0 % of FSR Gain Error −1.25 0 +1.25 % of FSR Zero Code Error Drift ±20 µV/°C Gain Temperature Coefficient ±5 ppm of FSR/°C Voltage DAC Output Characteristics(7) Output Voltage Range REF IN+ = AVDD AGND AVDD V Output Voltage Settling Time To ±0.003% FSR, 0200h to FD00h 8 µs Slew Rate 1 V/µs DC Output Impedance 7 Ω Short-Circuit Current All 1s Loaded to DAC Register 20 mA IDAC Output Characteristics Full-Scale Output Current Maximum VREF = 2.5V 25 mA Maximum Short-Circuit Current Duration Indefinite Compliance Voltage AVDD − 1.5 V Relative Accuracy 0.185 % of FSR Zero Code Error All 0s Loaded to DAC Register 0.5 µA Full-Scale Error All 1s Loaded to DAC Register −0.4 % of FSR Gain Error −0.6 % of FSR (1) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). (2) Calibration can minimize these errors. (3) The self gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. (4) ∆VOUT is change in digital result. (5) 9pF switched capacitor at fSAMP clock frequency (see Figure 14). (6) Linearity calculated using a reduced code range of 512 to 65024; output unloaded. (7) Ensured by design and characterization; not production tested. (8) Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1). 4

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS: AV = 5V (continued) DD All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +5V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted. MSC1211/12/13/14 PARAMETER CONDITIONS MIN TYP MAX UNITS Analog Power-Supply Requirements Analog Power-Supply Voltage AVDD 4.75 5 5.25 V Analog Off Current(8) Analog OFF, PDCON = 48h < 1 nA PGA = 1, Buffer OFF 200 µA PGA = 128, Buffer OFF 500 µA AAnnaalloogg AADDCC CCuurrrreenntt ((IIAADDCC)) PGA = 1, Buffer ON 240 µA PPoowweerr--SSuuppppllyy PGA = 128, Buffer ON 850 µA CCuurrrreenntt VDAC Current (IVDAC) Excluding Load Current, External Reference 250 µA V(IVRREEFF S)upply Current ADC ON, VDAC OFF 250 µA (1) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). (2) Calibration can minimize these errors. (3) The self gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. (4) ∆VOUT is change in digital result. (5) 9pF switched capacitor at fSAMP clock frequency (see Figure 14). (6) Linearity calculated using a reduced code range of 512 to 65024; output unloaded. (7) Ensured by design and characterization; not production tested. (8) Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1). ELECTRICAL CHARACTERISTICS: AV = 3V DD All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +3V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted. MSC1211/12/13/14 PARAMETER CONDITIONS MIN TYP MAX UNITS Analog Inputs (AIN0−AIN7, AINCOM) Buffer OFF AGND − 0.1 AVDD + 0.1 V AAnnaalloogg IInnppuutt RRaannggee Buffer ON AGND + 50mV AVDD − 1.5 V Full-Scale Input Voltage Range (AIN+) − (AIN−) ±VREF/PGA V Differential Input Impedance Buffer OFF 7/PGA(1) MΩ Input Current Buffer ON 0.5 nA Fast Settling Filter −3dB 0.469 • fDATA BBaannddwwiiddtthh Sinc2 Filter −3dB 0.318 • fDATA Sinc3 Filter −3dB 0.262 • fDATA Programmable Gain Amplifier User-Selectable Gain Range 1 128 Input Capacitance Buffer ON 9 pF Input Leakage Current Multiplexer Channel OFF, T = +25°C 0.5 pA Burnout Current Sources Sensor Input Open Circuit ±2 µA (1) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). (2) Calibration can minimize these errors. (3) The gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. (4) ∆VOUT is change in digital result. (5) 9pF switched capacitor at fSAMP clock frequency (see Figure 14). (6) Linearity calculated using a reduced code range of 512 to 65024; output unloaded. (7) Ensured by design and characterization; not production tested. (8) Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1). 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS: AV = 3V (continued) DD All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +3V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted. MSC1211/12/13/14 PARAMETER CONDITIONS MIN TYP MAX UNITS ADC Offset DAC Offset DAC Range Bipolar Mode ±VREF/(2•PGA) V Offset DAC Monotonicity 8 Bits Offset DAC Gain Error ±1.5 % of Range Offset DAC Gain Error Drift 1 ppm/°C System Performance Resolution 24 Bits ENOB 22 Bits Output Noise See Typical Characteristics No Missing Codes Sinc3 Filter 24 Bits Integral Nonlinearity End Point Fit, Bipolar Mode 0.0003 ±0.0015 %FSR Offset Error After Calibration ±3.5 ppm of FS Offset Drift(2) Before Calibration 0.1 ppm of FS/°C Gain Error(3) After Calibration −0.002 % Gain Error Drift(2) Before Calibration 1.0 ppm/°C System Gain Calibration Range 80 120 % of FS System Offset Calibration Range −50 50 % of FS At DC 115 dB fCM = 60Hz, fDATA = 10Hz 130 dB CCoommmmoonn--MMooddee RReejjeeccttiioonn fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB fSIG = 50Hz, fDATA = 50Hz 100 dB NNoorrmmaall MMooddee RReejjeeccttiioonn fSIG = 60Hz, fDATA = 60Hz 100 dB Power-Supply Rejection At DC, dB = −20log(∆VOUT/∆VDD)(4) 92 dB Voltage Reference Inputs Reference Input Range REF IN+, REF IN− AGND AVDD(3) V VREF VREF ≡ (REF IN+) − (REF IN−) 0.1 1.25 AVDD V VREF Common-Mode Rejection At DC 110 dB Input Current(5) VREF = 1.25V, ADC Only 3 µA DAC Reference Input Resistance For Each DAC, PGA = 1 20 kΩ On-Chip Voltage Reference Output Voltage VREFH = 0 at +25°C, REFCLK = 250kHz 1.245 1.25 1.255 V Power-Supply Rejection Ratio 65 dB Short-Circuit Current Source 2.6 mA Short-Circuit Current Sink 50 µA Short-Circuit Duration Sink or Source Indefinite Drift 5 ppm/°C Output Impedance Sourcing 100µA 3 Ω Startup Time from Power ON CREFOUT = 0.1µF 8 ms Temperature Sensor Voltage Buffer ON, T = +25°C 115 mV Temperature Sensor Coefficient Buffer ON 375 µV/°C (1) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). (2) Calibration can minimize these errors. (3) The gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. (4) ∆VOUT is change in digital result. (5) 9pF switched capacitor at fSAMP clock frequency (see Figure 14). (6) Linearity calculated using a reduced code range of 512 to 65024; output unloaded. (7) Ensured by design and characterization; not production tested. (8) Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1). 6

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS: AV = 3V (continued) DD All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +3V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted. MSC1211/12/13/14 PARAMETER CONDITIONS MIN TYP MAX UNITS Voltage DAC Static Performance(6) Resolution 16 Bits Relative Accuracy ±0.05 ±0.146 % of FSR Differential Nonlinearity Ensured Monotonic by Design ±1 LSB Zero Code Error All 0s Loaded to DAC Register +13 +35 mV Full-Scale Error All 1s Loaded to DAC Register −1.25 0 % of FSR Gain Error −1.25 0 ±1.25 % of FSR Zero Code Error Drift ±20 µV/°C Gain Temperature Coefficient ±5 ppm of FSR/°C Voltage DAC Output Characteristics(7) Output Voltage Range AGND AVDD V Output Voltage Settling Time To ±0.003% FSR, 0200h to FD00h 8 µs Slew Rate 1 V/µs DC Output Impedance 7 Ω Short-Circuit Current All 1s Loaded to DAC Register 16 mA IDAC Output Characteristics Full-Scale Output Current Maximum VREF = 1.25V 25 mA Maximum Short-Circuit Current Duration Indefinite Compliance Voltage AVDD − 1.5 V Relative Accuracy Over Full Range 0.185 % of FSR Zero Code Error 0.5 % of FSR Full-Scale Error −0.4 % of FSR Gain Error −0.6 % of FSR Analog Power-Supply Requirements Analog Power-Supply Voltage AVDD 2.7 3.0 3.6 V Analog Off Current(8) Analog OFF, PDCON = 47h < 1 nA PGA = 1, Buffer OFF 200 µA PGA = 128, Buffer OFF 500 µA AAnnaalloogg AADDCC CCuurrrreenntt ((IIAADDCC)) PGA = 1, Buffer ON 240 µA PPoowweerr--SSuuppppllyy PGA = 128, Buffer ON 850 µA CCuurrrreenntt Excluding Load Current, External VDAC Current (IVDAC) Reference 250 µA V(IVRDEAFC S)upply Current ADC ON, VDAC OFF 250 µA (1) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). (2) Calibration can minimize these errors. (3) The gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. (4) ∆VOUT is change in digital result. (5) 9pF switched capacitor at fSAMP clock frequency (see Figure 14). (6) Linearity calculated using a reduced code range of 512 to 65024; output unloaded. (7) Ensured by design and characterization; not production tested. (8) Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1). 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DIGITAL CHARACTERISTICS: DV = 2.7V to 5.25V DD All specifications from TMIN to TMAX, FMCON = 10h, all digital outputs high, PDCON = 00h (all peripherals ON) or PDCON = FFh (all peripherals OFF), PSEN and ALE enabled (all peripherals ON) or PSEN and ALE disabled (all peripherals OFF), unless otherwise specified. MSC1211/12/13/14 PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Power-Supply Requirements DVDD 2.7 3 3.6 V Normal Mode, fOSC = 1MHz, peripherals OFF 0.9 mA Normal Mode, fOSC = 1MHz, peripherals ON 1.1 mA DDiiggiittaall PPoowweerr--SSuuppppllyy CCuurrrreenntt Normal Mode, fOSC = 8MHz, peripherals OFF 5.7 mA Normal Mode, fOSC = 8MHz, peripherals ON 7.5 mA Crystal Operation Stop Mode(1) 100 nA DVDD 4.75 5 5.25 V Normal Mode, fOSC = 1MHz, peripherals OFF 1.7 mA Normal Mode, fOSC = 1MHz, peripherals ON 2.4 mA DDiiggiittaall PPoowweerr--SSuuppppllyy CCuurrrreenntt Normal Mode, fOSC = 8MHz, peripherals OFF 11 mA Normal Mode, fOSC = 8MHz, peripherals ON 14.8 mA Crystal Operation Stop Mode(1) 100 nA DIGITAL INPUT/OUTPUT (CMOS) VIH (except XIN pin) 0.6 •DVDD DVDD V LLooggiicc LLeevveell VIL (except XIN pin) DGND 0.2 •DVDD V I/O Pin Hysteresis 700 mV Ports 0−3, Input Leakage Current, Input Mode VIH = DVDD or VIH = 0V < 1 pA Pins EA, RST Input Leakage Current < 1 pA IOL = −1mA DGND 0.4 V VVOOLL,, AALLEE,, PPSSEENN,, PPoorrttss 00−−33,, AAllll OOuuttppuutt MMooddeess IOL = −30mA (5V), −20mA (3V) 1.5 V IOH = 1mA DVDD − 0.4 DVDD − 0.1 DVDD V VVOOHH,, AALLEE,, PPSSEENN,, PPoorrttss 00−−33,, SSttrroonngg DDrriivvee OOuuttppuutt IOH = 30mA (5V), 20mA (5V) DVDD − 1.5 V Ports 0−3, Pull-Up Resistors 9 kΩ Pins ALE, PSEN, Pull-Up Resistors During Reset Flash Programming Mode Only 9 kΩ OSCILLATOR/CLOCK INPUT/OUTPUT VIH (except XIN pin) XOUT must be unconnected 0.6 •DVDD DVDD V EExxtteerrnnaall OOsscciillllaattoorr//CClloocckk VIL (except XIN pin) XOUT must be unconnected DGND 0.2 •DVDD V (1) Digital Brownout Detect disabled (HCR1.2 = 1), Low Voltage Detect disabled (LVDCON.3 = 1). Ports configured for CMOS output low. FLASH MEMORY CHARACTERISTICS: DV = 2.7V to 5.25V DD MSC1211/12/13/14 PARAMETER CONDITIONS MIN TYP MAX UNITS Flash Memory Endurance 100,000 1,000,000 Cycles Flash Memory Data Retention 100 Years Mass and Page Erase Time Set with FER in FTCON 10 ms Flash Memory Write Time Set with FWR in FTCON 30 40 µs DVDD = 3.0V 10 mA FFllaasshh PPrrooggrraammmmiinngg CCuurrrreenntt((11)) DVDD = 5.0V 25 mA (1) Peak current during Mass and Page Erase Time and Memory Write Time. 8

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 AC ELECTRICAL CHARACTERISTICS(1)(2): DV = 2.7V to 5.25V DD 2.7V to 3.6V 4.75V to 5.25V SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNITS System Clock fOSC(3) 4 External Crystal Frequency (fOSC) 1 24 1 33 MHz External Clock Frequency (fOSC) at +85°C 0 24 0 40 MHz 11//ttOOSSCC((33)) 44 External Clock Frequency (fOSC) at +125°C 0 22 0 36 MHz fOSC(3) 4 External Ceramic Resonator Frequency (fOSC) 1 12 1 12 MHz Program Memory tLHLL 1 ALE Pulse Width 1.5tCLK − 5 1.5tCLK − 5 ns tAVLL 1 Address Valid to ALE Low 0.5tCLK − 10 0.5tCLK − 7 ns tLLAX 1 Address Hold After ALE Low 0.5tCLK 0.5tCLK ns tLLIV 1 ALE Low to Valid Instruction In 2.5tCLK − 35 2.5tCLK − 25 ns tLLPL 1 ALE Low to PSEN Low 0.5tCLK 0.5tCLK ns tPLPH 1 PSEN Pulse Width 2tCLK − 5 2tCLK − 5 ns tPLIV 1 PSEN Low to Valid Instruction In 2tCLK − 40 2tCLK − 30 ns tPXIX 1 Input Instruction Hold After PSEN 5 −5 ns tPXIZ 1 Input Instruction Float After PSEN tCLK − 5 tCLK ns tAVIV 1 Address to Valid Instruction In 3tCLK − 40 3tCLK − 25 ns tPLAZ 1 PSEN Low to Address Float 0 0 ns Data Memory ttRRLLRRHH 22 RRDD PPuullssee WWiiddtthh ((ttMMCCSS => 00))((44)) 2tMtCCLSK −− 55 2tMtCCLSK − − 5 5 nnss ttWWLLWWHH 33 WWRR PPuullssee WWiiddtthh ((ttMMCCSS => 00))((44)) 2tMtCCLSK −− 55 2tMtCCLSK −− 55 nnss ttRRLLDDVV 22 RRDD LLooww ttoo VVaalliidd DDaattaa IInn ((ttMMCCSS => 00))((44)) 2tMtCCLSK −− 4400 2tMtCCLSK −− 3300 nnss tRHDX 2 Data Hold After Read −5 −5 ns ttRRHHDDZZ 22 DDaattaa FFllooaatt AAfftteerr RReeaadd ((ttMMCCSS => 00))((44)) 2tCtCLLKK 2tCtCLLKK nnss ttLLLLDDVV 22 AALLEE LLooww ttoo VVaalliidd DDaattaa IInn ((ttMMCCSS => 00))((44)) tC2L.K5 t+C LtMKC −S 4 −0 40 tC2L.K5 t+C LtMKC −S 2 −5 25 nnss ttAAVVDDVV 22 AAddddrreessss ttoo VVaalliidd DDaattaa IInn ((ttMMCCSS => 00))((44)) 1.5t3CtLCKL K+ tM− C4S0 −40 1.5t3CtLCKL +K t M−C 2S5 − 25 nnss ttLLLLWWLL 22,, 33 AALLEE LLooww ttoo RRDD oorr WWRR LLooww ((ttMMCCSS => 00))((44)) 0.t5CtLCKL K− −5 5 0.t5CtLCKL K+ +5 5 0.t5CtLCKL K− −5 5 0.t5CtLCKL K+ +5 5 nnss ttAAVVWWLL 22,, 33 AAddddrreessss ttoo RRDD oorr WWRR LLooww ((ttMMCCSS => 00))((44)) 2tCtCLLKK − − 5 5 2tCtCLLKK − − 5 5 nnss tQVWX 3 Data Valid to WR Transition −8 −5 ns tWHQX 3 Data Hold After WR tCLK − 8 tCLK − 5 ns tRLAZ 2 RD Low to Address Float −0.5tCLK − 5 −0.5tCLK − 5 ns ttWWHHLLHH 22,, 33 RRDD oorr WWRR HHiigghh ttoo AALLEE HHiigghh ((ttMMCCSS => 00))((44)) tCL−K5 − 5 tCLK5 + 5 tCL−K5 − 5 tCLK5 + 5 nnss External Clock tHIGH 4 High Time(5) 15 10 ns tLOW 4 Low Time(5) 15 10 ns tR 4 Rise Time(5) 5 5 ns tF 4 Fall Time(5) 5 5 ns (1) Parameters are valid over operating temperature range, unless otherwise specified. (2) Load capacitance for Port 0, ALE, and PSEN = 100pF; load capacitance for all other outputs = 80pF. (3) tCLK = 1/fOSC = one oscillator clock period for clock divider = 1. (4) tMCS is a time period related to the Stretch MOVX selection. The following table shows the value of tMCS for each stretch selection: (5) These values are characterized, but not 100% production tested. MD2 MD1 MD0 MOVX DURATION tMCS 0 0 0 2 Machine Cycles 0 0 0 1 3 Machine Cycles (default) 4tCLK 0 1 0 4 Machine Cycles 8tCLK 0 1 1 5 Machine Cycles 12tCLK 1 0 0 6 Machine Cycles 16tCLK 1 0 1 7 Machine Cycles 20tCLK 1 1 0 8 Machine Cycles 24tCLK 1 1 1 9 Machine Cycles 28tCLK 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 EXPLANATION OF THE AC SYMBOLS Each Timing Symbol has five characters. The first character is always ’t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designators are: AAddress RRD Signal CClock tTime DInput Data VValid HLogic Level High WWR Signal IInstruction (program memory contents) XNo Longer a Valid Logic Level LLogic Level Low, or ALE ZFloat PPSEN Examples: QOutput Data (1) tAVLL = Time for address valid to ALE Low. (2) tLLPL = Time for ALE Low to PSEN Low. t LHLL ALE tAVLL tLLPL tPLPH t LLIV PSEN tPLIV t PXIZ t t LLAX PLAZ t PXIX PORT0 A0−A7 INSTRIN A0−A7 t AVIV PORT2 A8−A15 A8−A15 Figure 1. External Program Memory Read Cycle ALE t WHLH PSEN t LLDV t t LLWL RLRH RD tAVLL tLLAX t tRHDZ RLDV t RLAZ t RHDX A0−A7 PORT0 DATAIN A0−A7fromPCL INSTRIN fromRIorDPL t AVWL t AVDV PORT2 P2.0−P2.7orA8−A15fromDPH A8−A15fromPCH Figure 2. External Data Memory Read Cycle 10

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ALE t WHLH PSEN t t LLWL WLWH WR tAVLL tLLAX tQVWX t WHQX t DW A0−A7 PORT0 DATAOUT A0−A7fromPCL INSTRIN fromRIorDPL t AVWL PORT2 P2.0−P2.7orA8−A15fromDPH A8−A15fromPCH Figure 3. External Data Memory Write Cycle t HIGH t t r f V V V V IH1 IH1 IH1 IH1 0.8V 0.8V 0.8V 0.8V t LOW t OSC Figure 4. External Clock Drive CLK 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 RESET AND POWER-ON TIMING t RW RST tRRD tRFD PSEN t t RRD RFD ALE t t RS RH EA NOTE:PSENandALEareinternallypulledupwith~9kΩduringRSThigh. Figure 5. Reset Timing, User Application Mode t RW RST tRRD tRFD PSEN tRRD tRS tRH ALE NOTE:PSENandALEareinternallypulledupwith~9kΩduringRSThigh. Figure 6. Parallel Flash Programming Power-On Timing (EA is ignored) t RW RST tRRD tRS tRH PSEN tRRD tRFD ALE NOTE:PSENandALEareinternallypulledupwith~9kΩduringRSThigh. Figure 7. Serial Flash Programming Power-On Timing (EA is ignored) Table 1. Serial/Parallel Flash Programming Timing SYMBOL PARAMETER MIN MAX UNIT tRW RST width 2tOSC — — tRRD RST rise to PSEN ALE internal pull high — 5 µs tRFD RST falling to PSEN and ALE start — (217 + 512)tOSC — tRS Input signal to RST falling setup time tOSC — — tRH RST falling to input signal hold time (217 + 512)tOSC — — 12

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 (1)L (1)DA C S SCK/S MISO/ MOSI SS 1.7/INT5/ 1.6/INT4/ 1.5/INT3/ 1.4/INT2/ 1.3/TxD1 1.2/RxD1 VDD GND 1.1/T2EX 1.0/T2 0.0/AD0 0.1/AD1 0.2/AD2 0.3/AD3 0.4/AD4 0.5/AD5 P P P P P P D D P P P P P P P P 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 XOUT 1 48 EA XIN 2 47 P0.6/AD6 P3.0/RxD0 3 46 P0.7/AD7 P3.1/TxD0 4 45 ALE P3.2/INT0 5 44 PSEN/OSCCLK/MODCLK P3.3/INT1/TONE/PWM 6 43 P2.7/A15 P3.4/T0 7 42 DV DD MSC1211 P3.5/T1 8 41 DGND MSC1212 P3.6/WR 9 MSC1213 40 P2.6/A14 MSC1214 P3.7/RD 10 39 P2.5/A13 DV 11 38 P2.4/A12 DD DGND 12 37 P2.3/A11 RST 13 36 P2.2/A10 DV 14 35 P2.1/A09 DD DV 15 34 P2.0/A08 DD RDAC0 16 33 NC(3) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDAC0 AIN0/IDAC0 AIN1/IDAC1 (2)AIN2/VDAC2 (2)AIN3/VDAC3 AIN4 AIN5 AIN6/EXTD AIN7/EXTA AINCOM AGND AVDD −REFIN FOUT/REFIN+ VDAC1 RDAC1 E R NOTES:(1)SCLandSDAareonlyavailableontheMSC1211andMSC1213. (2)VDAC2andVDAC3areonlyavailableontheMSC1211andMSC1212. (3)NCpinshouldbeleftunconnected. 13

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 PIN DESCRIPTIONS PIN # NAME DESCRIPTION 1 XOUT The crystal oscillator pin XOUT supports parallel resonant AT-cut fundamental frequency crystals and ceramic resonators. XOUT serves as the output of the crystal amplifier. 2 XIN The crystal oscillator pin XIN supports parallel resonant AT-cut fundamental frequency crystals and ceramic resonators. XIN can also be an input if there is an external clock source instead of a crystal. 33--1100 PP33..00--PP33..77 Port 3 is a bidirectional I/O port. The alternate functions for Port 3 are listed below. Refer to P3DDR, SFR B3h−B4h. Port Alternate Name(s) Alternate Use P3.0 RxD0 Serial port 0 input P3.1 TxD0 Serial port 1 input P3.2 INT0 External interrupt 0 P3.3 INT1/TONE/PWM External interrupt 1/TONE/PWM output P3.4 T0 Timer 0 external input P3.5 T1 Timer 1 external input P3.6 WR External memory data write strobe P3.7 RD External memory data read strobe 11, 14, 15, 42, 58 DVDD Digital Power Supply 12, 41, 57 DGND Digital Ground 13 RST Holding the reset input high for two t periods will reset the device. OSC 16 RDAC0 IDAC0 Reference Resistor Pin 17 VDAC0 VDAC0 Output 27 AGND Analog Ground 18 AIN0/IDAC0 Analog Input Channel 0 / IDAC0 Output 19 AIN1/IDAC1 Analog Input Channel 1 / IDAC1 Output 20 AIN2/VDAC2 Analog Input Channel 2 / VDAC2 Output (MSC1211 and MSC1212 only) 21 AIN3V/DAC3 Analog Input Channel 3 / VDAC3 Output (MSC1211 and MSC1212 only) 22 AIN4 Analog Input Channel 4 23 AIN5 Analog Input Channel 5 24 AIN6/EXTD Analog Input Channel 6 / LVD Comparator Input, Generates DLVD Interrupt 25 AIN7/EXTA Analog Input Channel 7 / LVD Comparator Input, Generates ALVD Interrupt 26 AINCOM Analog Common; can be used like any analog input except during Offset − Inputs shorted to this pin. 28 AVDD Analog Power Supply 29 REF IN− Voltage Reference Negative Input (must be tied to AGND for internal VREF use) 30 REFOUT/REF IN+ Internal Voltage Reference Output / Voltage Reference Positive Input 31 VDAC1 VDAC1 Output 32 RDAC1 IDAC1 Reference Resistor Pin 33 NC No Connection; leave unconnected. 3344--4400,, 4433 PP22..00--PP22..77 Port 2 is a bidirectional I/O port. The alternate functions for Port 2 are listed below. Refer to P2DDR, SFR B1h−B2h. Port Alternate Name Alternate Use P2.0 A8 Address bit 8 P2.1 A9 Address bit 9 P2.2 A10 Address bit 10 P2.3 A11 Address bit 11 P2.4 A12 Address bit 12 P2.5 A13 Address bit 13 P2.6 A14 Address bit 14 P2.7 A15 Address bit 15 (1)SDA and SCL are only available on the MSC1213. 14

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 PIN DESCRIPTIONS (continued) PIN # NAME DESCRIPTION 44 PSEN Program Store Enable: Connected to optional external memory as a chip enable. PSEN will provide an active low pulse. OSCCLK In programming mode, PSEN is used as an input along with ALE to define serial or parallel programming mode. MODCLK PSEN is held high for parallel programming and held low for serial programming. This pin can also be selected (when not using external memory) to output the Oscillator clock, Modulator clock, high, or low. Care should be taken so that loading on this pin should not inadvertently cause the device to enter programming mode. ALE PSEN Program Mode Selection During Reset NC NC Normal operation (User Application mode) 0 NC Parallel programming NC 0 Serial programming 0 0 Reserved 45 ALE Address Latch Enable: Used for latching the low byte of the address during an access to external memory. ALE is emitted at a constant rate of 1/4 the oscillator frequency, and can be used for external timing or clocking. One ALE pulse is skipped during each access to external data memory. In programming mode, ALE is used as an input along with PSEN to define serial or parallel programming mode. ALE is held high for serial programming and held low for parallel programming. This pin can also be selected (when not using external memory) to output high or low. Care should be taken so that loading on this pin should not inadvertently cause the device to enter programming mode. 48 EA External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations starting with 0000h. No internal pull-up on this pin. 4466,, 4477,, 4499--5544 PP00..00--PP00..77 Port 0 is a bidirectional I/O port. The alternate functions for Port 0 are listed below. Port Alternate Name Alternate Use P0.0 AD0 Address/Data bit 0 P0.1 AD1 Address/Data bit 1 P0.2 AD2 Address/Data bit 2 P0.3 AD3 Address/Data bit 3 P0.4 AD4 Address/Data bit 4 P0.5 AD5 Address/Data bit 5 P0.6 AD6 Address/Data bit 6 P0.7 AD7 Address/Data bit 7 5555,, 5566,, 5599--6644 PP11..00--PP11..77 Port 1 is a bidirectional I/O port. The alternate functions for Port 1 are listed below. Refer to P1DDR, SFR AEh−AFh. Port Alternate Name(s) Alternate Use P1.0 T2 T2 input P1.1 T2EX T2 external input P1.2 RxD1 Serial port input P1.3 TxD1 Serial port output P1.4 INT2/SS External Interrupt / Slave Select P1.5 INT3/MOSI External Interrupt / Master Out-Slave In P1.6 INT4/MISO/SDA(1) External Interrupt / Master In-Slave Out / SDA P1.7 INT5/SCK/SCL(1) External Interrupt / Serial Clock (1)SDA and SCL are only available on the MSC1213. 15

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. EFFECTIVENUMBEROFBITS EFFECTIVENUMBEROFBITSvsDATARATE vsDECIMATIONRATIO 23 22 22 PGA1 PGA2 PGA4 PGA8 PGA1 21 21 PGA8 20 PGA32 20 PGA64 19 19 PGA128 ms) 18 ms) 18 OB(r 1176 OB(r 17 PGA16 PGA32 PGA64 PGA128 EN 15 EN 16 14 15 13 14 12 Sinc3Filter,BufferOFF Sinc3Filter,BufferOFF 11 13 10 12 1 10 100 1000 0 500 1000 1500 2000 DataRate(SPS) f DecimationRatio= MOD f DATA EFFECTIVENUMBEROFBITS EFFECTIVENUMBEROFBITS vsDECIMATIONRATIO vsDECIMATIONRATIO 22 22 PGA2 PGA4 PGA8 PGA1 PGA2 PGA4 PGA8 21 21 PGA1 20 20 19 19 ms) 18 ms) 18 B(r 17 B(r 17 PGA32 O PGA32 PGA64 PGA128 O PGA16 PGA64 PGA128 N 16 N 16 E PGA16 E 15 15 14 14 Sinc3Filter,BufferON AV =3V,Sinc3Filter, 13 13 V DD=1.25V,BufferOFF REF 12 12 0 500 1000 1500 2000 0 500 1000 1500 2000 f f DecimationRatio= MOD DecimationRatio= MOD f f DATA DATA EFFECTIVENUMBEROFBITS EFFECTIVENUMBEROFBITS vsDECIMATIONRATIO vsDECIMATIONRATIO 22 22 PGA2 PGA4 PGA8 PGA2 PGA4 PGA8 21 21 PGA1 PGA1 20 20 19 19 ms) 18 ms) 18 B(r 17 B(r 17 O O PGA32 PGA16 PGA64 PGA128 N 16 N 16 E PGA16 PGA32 PGA64 PGA128 E 15 15 14 14 AV =3V,Sinc3Filter, Sinc2Filter 13 DD 13 V =1.25V,BufferON REF 12 12 0 500 1000 1500 2000 0 500 1000 1500 2000 f f DecimationRatio= MOD DecimationRatio= MOD f f DATA DATA 16

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. FASTSETTLINGFILTER EFFECTIVENUMBEROFBITSvsf MOD EFFECTIVENUMBEROFBITSvsDECIMATIONRATIO (setwithACLK) 20 25 19 Gain1 f =203kHz MOD 18 20 1176 Gain16 ms) 15 fMOD=15.6kHz fMOD=110kHz NOB 15 B(r fMOD=31.25kHz E O 14 N 10 Gain128 E 13 12 5 f =62.5kHz 11 MOD 10 0 0 500 1000 11550000 2000 1 10 100 1k 10k 100k DataRate(SPS) DecimationValue EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) EFFECTIVENUMBEROFBITSvsINPUTSIGNAL WITH FIXED DECIMATION, PGA = 1 (InternalandExternalV ) REF 25 22.0 DEC=2020 External DEC=500 21.5 20 21.0 DEC=50 Internal ms) 15 DEC=255 ms) 20.5 B(r DEC=20 B(r 20.0 O O EN 10 EN 19.5 19.0 5 DEC=10 18.5 0 18.0 10 100 1k 10k 100k −2.5 −1.5 −0.5 0.5 1.5 2.5 DataRate(SPS) V (V) IN NOISEvsINPUTSIGNAL INLERRORvsPGA 0.8 100 90 0.7 80 S) 0.6 F 70 mof 0.5 FS) 60 p of p 0.4 m 50 (rms, 0.3 L(pp 40 e N s I 30 oi 0.2 N 20 0.1 10 0 0 −2.5 −1.5 −0.5 0.5 1.5 2.5 1 2 4 8 16 32 64 128 VIN(V) PGASetting 17

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. ADCINTEGRALNONLINEARITY ADCINTEGRALNONLINEARITY vsINPUTSIGNAL vsINPUTSIGNAL 15 15 AV =5V AV =5V V DD=2.5V V DD=2.5V +25(cid:2)C 10 BRuEffFerON 10 BRuEffFerOFF S) +85(cid:2)C S) F 5 F 5 of of m m pp 0 pp 0 ( ( CINL −5 +25(cid:2)C +125(cid:2)C CINL −5 +85(cid:2)C +125(cid:2)C D D A −40(cid:2)C A −55(cid:2)C −10 −10 −40(cid:2)C −15 −15 −2.5 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 −2.5 −2.0 −1.5 −1.0 −0.5 0 0.5 1.0 1.5 2.0 2.5 VIN(V) VIN(V) ADCINTEGRALNONLINEARITY ADCINTEGRALNONLINEARITY vsINPUTSIGNAL vsV REF 30 35 V =AV REF DD BufferOFF BufferOFF 30 20 AV =3V DD S) S) 25 F 10 F of of m m 20 p p p 0 p AV =5V ( ( DD L L 15 N N CI −10 CI D D 10 A A −20 5 −30 0 V =−V 0 V =+V 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 IN REF IN REF V (V) V (V) IN REF ANALOGSUPPLYCURRENT vsANALOGSUPPLYVOLTAGE ADCCURRENTvsPGA 2.6 PGA=128,ADCON, +125(cid:2)C 900 AV =5V,Buffer=ON 2.5 BrownoutDetectON, +85(cid:2)C 800 DD A) 2.4 AllVDACsON=FFFFh, Buffer=OFF m VDACsREF=AV 700 ( 2.3 DD ent 2.2 600 urr +25(cid:2)C A) C 2.1 µ 500 Supply 21..09 −40(cid:2)C I (ADC 400 AVDD=B3uVff,eBru=ffOeFr=FON 300 g o 1.8 Anal 1.7 200 1.6 100 1.5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 1 2 4 8 16 32 64 128 AnalogSupplyVoltage(V) PGASetting 18

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. PGASUPPLYCURRENT NORMALIZEDGAINvsPGA 300 101 AV =DV DD DD f =8MHz 250 CLK µ(A) VIN=0V AVDD=5.0V %)100 BufferOFF urrent 200 Gain( 99 C 150 d y e Suppl 100 maliz 98 GA AVDD=3.0V Nor BufferON P 97 50 0 96 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 PGASetting PGAGain HISTOGRAMOF ADCOFFSETvsTEMPERATURE TEMPERATURESENSORVALUES (OffsetCalibrationat+25(cid:2)COnly) 200 10 8 6 es150 nc m) 4 Occurre100 set(pp 20 erof COff −2 mb AD −4 u 50 N −6 −8 0 −10 0 5 0 5 0 5 0 5 0 5 0 5 0 −50 −25 0 25 50 75 100 125 150 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 6. 7. 11 11 11 11 11 11 11 11 11 11 11 11 11 Temperature((cid:2)C) TemperatureSensorValue(mV) OFFSETDAC:OFFSETvsTEMPERATURE OFFSETDAC:GAINvsTEMPERATURE 20 1.00008 15 1.00006 10 1.00004 FSR) 5 Gain 1.00002 of d ppm 0 alize 1 Offset( −−150 Norm 00..9999999986 −15 0.99994 −20 0.99992 −40 +25 +125 −40 +25 +125 Temperature((cid:2)C) Temperature((cid:2)C) 19

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. HISTOGRAMOFOUTPUTDATA V vsLOADCURRENT REFOUT 4500 2.510 4000 2.508 s 3500 2.506 e enc 3000 2.504 urr V) 2.502 c 2500 ( c T O OU 2.500 of 2000 EF ber 1500 VR 2.498 m 2.496 u N 1000 2.494 500 2.492 0 2.490 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 0 0.4 0.8 1.2 1.6 2.0 2.4 ppmofFS V CurrentLoad(mA) REFOUT DIGITALSUPPLYCURRENTvsFREQUENCY DIGITALSUPPLYCURRENTvsCLOCKDIVIDER 100 100 DividerValues OFF A) IMIN,DVDD=5V A) 2 m m 4 ent( IMAX,DVDD=5V IMAX,DVDD=3V ent( 10 8 urr urr 16 yC 10 IMIN,DVDD=3V yC 32 pl pl 1024 Sup IMAXIDLE,DVDD=5V Sup 1 2048 gital IMINIDLE,DVDD=3V gital 4096 Di Di I :PDCON=FFh,PSENandALEdisabled,LVDCON=FFh MIN I :PDCON=00h,PSENandALEenabled,LVDCON=00h 1 MAX 0.1 1 10 100 1 10 100 ClockFrequency(MHz) ClockFrequency(MHz) DIGITALSUPPLYCURRENTvsSUPPLYVOLTAGE CMOSDIGITALOUTPUT 15 5.0 4.5 5V A) +125(cid:2)C 4.0 Low m Output plyCurrent( 10 +25(cid:2)C −40(cid:2)C Voltage(V) 332...505 OLu3otVpwut alSup Output 21..05 Digit 1.0 5V 0.5 3V 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 10 20 30 40 50 60 70 SupplyVoltage(V) OutputCurrent(mA) 20

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS: VDACs AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. For VDAC: VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF unless otherwise noted. VDACINTEGRALNONLINEARITYvsCODE VDACDIFFERENTIALNONLINEARITYvsCODE 40 1.0 +125(cid:2)C 0.8 +85(cid:2)C 0.6 20 0.4 B) SB) 0.2 (LS 0 L(L 0 NL DN −0.2 I +25(cid:2)C −0.4 −20 −0.6 −40(cid:2)C −0.8 −40 −1.0 0000h 2000h 4000h 6000h 8000h A000hC000h E000hFFFFh 0000h 2000h 4000h 6000h 8000h A000h C000h E000hFFFFh DACCode DACCode VDACSOURCECURRENTCAPABILITY VDACSINKCURRENTCAPABILITY 5.0 0.6 DAC=All0s DAC=All1s 0.5 4.9 V) V) 0.4 ut( 4.8 ut( p p ut ut 0.3 O O C 4.7 C A A VD VD 0.2 4.6 0.1 4.5 0 0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 I (mA) I (mA) SOURCE SINK VDAC FULL−SCALE ERROR vs LOAD RESISTOR 1 0 S) −1 F %of −2 ( or Err −3 −4 −5 0.5 1 10 100 1k 10k LoadResistor(kΩ) 21

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS: VDACs (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. For VDAC: VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF unless otherwise noted. VDAC FULL−SCALE SETTLING TIME VDAC FULL−SCALE SETTLING TIME ScopeTrigger(5.0V/div) ScopeTrigger(5.0V/div) Full−ScaleCodeChange 0200 toFFFF H H OutputLoadedwith 10kΩand200pFtoGND Large−SignalOutput(1.0V/div) Full−ScaleCodeChange FFFF to0200 H H OutputLoadedwith Large−SignalOutput(1.0V/div) 10kΩand200pFtoGND Time (1µs/div) Time (1µs/div) VDAC HALF−SCALE SETTLING TIME VDAC HALF−SCALE SETTLING TIME ScopeTrigger(5.0V/div) Half−ScaleCodeChange 4000 toC000 ScopeTrigger(5.0V/div) H H OutputLoadedwith 10kΩand200pFtoGND Half−ScaleCodeChange C000 to4000 H H OutputLoadedwith 10kΩand200pFtoGND Large−SignalOutput(1.0V/div) Large−SignalOutput(1.0V/div) Time (1µs/div) Time (1µs/div) 22

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DESCRIPTION The MSC1211/12/13/14 are completely integrated The microcontroller core is 8051 instruction set families of mixed-signal devices incorporating a compatible. The microcontroller core is an optimized 8051 high-resolution delta-sigma (∆Σ) ADC, 16-bit DACs, core that executes up to three times faster than the 8-channel multiplexer, burnout detect current sources, standard 8051 core, given the same clock source. This selectable buffered input, offset DAC, Programmable Gain design makes it possible to run the devices at a lower Amplifier (PGA), temperature sensor, voltage reference, external clock frequency and achieve the same 8-bit microcontroller, Flash Program Memory, Flash Data performance at lower power than the standard 8051 core. Memory, and Data SRAM, as shown in Figure 8. The MSC1211/12/13/14 allow users to uniquely configure the On-chip peripherals include an additional 32-bit Flash and SRAM memory maps to meet the needs of their accumulator, an SPI-compatible serial port with FIFO, dual applications. The Flash is programmable down to 2.7V using USARTs, multiple digital input/output ports, a watchdog both serial and parallel programming methods. The Flash timer, low-voltage detect, on-chip power-on reset, 16-bit endurance is 100k Erase/Write cycles. In addition, 1280 PWM, breakpoints, brownout reset, three timer/counters, bytes of RAM are incorporated on-chip. and a system clock divider. The MSC1211 and MSC1213 The parts have separate analog and digital supplies, which also contain a hardware I2C peripheral. can be independently powered from 2.7V to +5.25V. The devices accept low-level differential or single-ended At +3V operation, the power dissipation for each part is signals directly from a transducer. The ADC provides 24 typically less than 4mW. The MSC1211/12/13/14 are all bits of resolution and 24 bits of no-missing-code available in a TQFP-64 package. performance using a Sinc3 filter with a programmable The MSC1211/12/13/14 are designed for high-resolution sample rate. The ADC also has a selectable filter that measurement applications in smart transmitters, industrial allows for high-resolution, single-cycle conversion. process control, weigh scales, chromatography, and portable instrumentation. AVDD AGND REFOUT/REFIN+ REFIN−(1) DVDD DGND AV DD Burnout VREF Timers/ Detect LVD Counters EA ALE PSEN BOR 8−Bit WDT AIN0/IDAC0 Temperature OffsetDAC Sensor AIN1/IDAC1 Alternate AIN2/VDAC2(3) Functions AIN3/VDAC3(3) Digital PORT0 8 ADDADTAR AIN4 MUX BUFFER PGA Modulator Filter AIN5 T2 PORT1 8 SPI/EXT/I2C(2) AIN6/EXTD Upto32K USART1 FLASH 32−Bit AIN7/EXTA V/I VDAC0 Accumulator AINCOM Converter PORT2 8 ADDR 1.2K IDAC0/ ConVv/eIrter VDAC1 SRAM 8051 UEXSTART0 PORT3 8 T0 AIN1 SFR T1 IDAC1/ AIN2 VDAC2(3) SPI PWM Burnout RW AIN1 FIFO Detect AIN3 VDAC3(3) SYSClock Clock POR Divider Generator RST AGND RDAC0 RDAC1 VDAC0 VDAC1 XIN XOUT NOTES:(1)REFIN−mustbetiedtoAGNDwhenusinginternalV . REF (2)I2ConlyavailableontheMSC1213. (3)VDAC2andVDAC3onlyavailableonMSC1211andMSC1212. Figure 8. Block Diagram 23

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ENHANCED 8051 CORE Single-Byte, Single-Cycle Instruction All instructions in the MSC1211/12/13/14 families perform g n exactly the same functions as they would in a standard mi 8051. The effects on bits, flags, and registers is the same; Ti ALE 4 however, the timing is different. The MSC1211/12/13/14 1 3/ PSEN families utilize an efficient 8051 core which results in an 1 2/ improved instruction execution speed of between 1.5 and 1 1/ AD0−AD7 3 times faster than the original core for the same external 21 1 clock speed (4 clock cycles per instruction versus 12 clock C PORT2 S cycles per instruction, as shown in Figure 9). This M 4Cycles efficiency translates into an effective throughput improvement of more than 2.5 times, using the same code CLK and same external clock speed. Therefore, a device 12Cycles frequency of 40MHz for the MSC1211/12/13/14 actually g performs at an equivalent execution speed of 100MHz min ALE compared to the standard 8051 core. This increased Ti 1 PSEN performance allows the the device to be run at slower 5 0 external clock speeds, which reduces system noise and d8 AD0−AD7 power consumption, but provides greater throughput. This ar d performance difference can be seen in Figure 10. The an PORT2 timing of software loops will be faster with the St MSC1211/12/13/14. However, the timer/counter operation Single-Byte, Single-Cycle Instruction of the MSC1211/12/13/14 may be maintained at 12 clocks per increment, or optionally run at 4 clocks per increment. Figure 10. Comparison of MSC1211/12/13/14 The MSC1211/12/13/14 also provide dual data pointers Timing to Standard 8051 Timing (DPTRs) to speed block Data Memory moves. Additionally, both devices can stretch the number of RD or WR RD or WR memory cycles to access external Data Memory from CKCON INSTRUCTION STROBE STROBE between two and nine instruction cycles in order to (8Eh) CYCLES WIDTH WIDTH accommodate different speeds of memory or devices, as MD2:MD0 (for MOVX) (SYS CLKs) (µs) AT 12MHz shown in Table 2. The MSC1211/12/13/14 provide an 000 2 2 0.167 external memory interface with a 16-bit address bus (P0 001 3 (default) 4 0.333 and P2). The 16-bit address bus makes it necessary to 010 4 8 0.667 011 5 12 1.000 multiplex the low address byte through the P0 port. To 100 6 16 1.333 enhance P0 and P2 for high-speed memory access, 101 7 20 1.667 hardware configuration control is provided to configure the 110 8 24 2.000 ports for external memory/peripheral interface or 111 9 28 2.333 general-purpose I/O. Table 2. Memory Cycle Stretching (stretching of MOVX timing as defined by MD2, MD1, and MD0 bits in CKCON register at address 8Eh). CLK instr_cycle n+1 n+2 cpu_cycle C1 C2 C3 C4 C1 C2 C3 C4 C1 Figure 9. Instruction Timing Cycle 24

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Furthermore, improvements were made to peripheral This gives the user the ability to add or subtract software features that off-load processing from the core, and the functions and to freely migrate between family members. user, to further improve efficiency. For instance, the SPI Thus, the MSC1211/12/13/14 can become a standard interface uses a FIFO, which allows the SPI interface to device used across several application platforms. transmit and receive data with minimum overhead needed Family Development Tools from the core. Also, a 32-bit accumulator was added to significantly reduce the processing overhead for multiple The MSC1211/12/13/14 are fully compatible with the byte data from the ADC or other sources. This allows for standard 8051 instruction set. This compatibility means 32-bit addition, subtraction and shifting to be that users can develop software for the accomplished in a few instruction cycles, compared to MSC1211/12/13/14 with their existing 8051 development hundreds of instruction cycles executed through software tools. Additionally, a complete, integrated development implementation. environment is provided with each demo board, and third-party developers also provide support. Family Device Compatibility Power-Down Modes The hardware functionality and pin configuration across the MSC1211/12/13/14 families are fully compatible. To The MSC1211/12/13/14 can each power several of the the user, the only differences between family members are on-chip peripherals and put the CPU into Idle mode. This the memory configuration, the number of DACs, and the is accomplished by shutting off the clocks to those availability of I2C for the MSC1211 and MSC1213. This sections, as shown in Figure 11. design makes migration between family members simple. fOSC fSYS STOP SYSCLK C7 f CLK SPICON/ SCL/SCK I2CCON(1) 9A fCLK PDCON.0 PWMHI PWMLOW PWMClock A3 A2 PDCON.4 USEC µs FTCON FlashWrite (30µsto40µs) FB [3:0] EF Timing MSECH MSECL ms FTCON FlashErase (5msto11ms) FD FC [7:4] EF Timing milliseconds MSINT interrupt REFCLK divide REF FA SEL DC by4 CLOCK seconds PDCON.1 SECINT interrupt F9 watchdog HMSEC 100ms WDTCON interrupt fACLK FE FF PDCON.2 ACLK divide ADCON3 ADCON2 ADCOutputRate f F6 by64 DF DE DATA AnalogPowerDown DecimationRatio PDCON.3 ADCON0DC fSAMP (see Figure 14) f MOD Timers0/1/2 USART0/1 IDLE CPUClock NOTE:(1)I2CCONonlyavailableontheMSC1211andMSC1213. Figure 11. MSC1211/12/13/14 Timing Chain and Clock Control 25

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 OVERVIEW TEMPERATURE SENSOR The MSC1211/12/13/14 ADC structure is shown in On-chip diodes provide temperature sensing capability. Figure 12. The figure lists the components that make up When the configuration register for the input MUX is set to the ADC, along with the corresponding special function all 1s, the diodes are connected to the inputs of the ADC. register (SFR) associated with each component. All other channels are open. ADC INPUT MULTIPLEXER BURNOUT DETECT The input multiplexer provides for any combination of When the Burnout Detect (BOD) bit is set in the ADC differential inputs to be selected as the input channel, as control configuration register (ADCON0 DCh), two current shown in Figure 13. For example, if AIN0 is selected as the sources are enabled. The current source on the positive positive differential input channel, then any other channel input channel sources approximately 2µA of current. The can be selected as the negative differential input channel. current source on the negative input channel sinks With this method, it is possible to have up to eight fully approximately 2µA. The current sources allow for the differential input channels with common connections detection of an open circuit (full-scale reading) or short between them. It is also possible to switch the polarity of circuit (small differential reading) on the selected input the differential input pair to negate any offset voltages. In differential pair. The buffer should be on for sensor burnout addition, current sources are supplied that will source or detection. sink current to detect open or short circuits on the pins. AV DD REFOUT/ AIN0 BDuernteocutt REFIN+ AIN1 AIN2 f SAMP AIN3 Input AIN4 Multiplexer AIN5 AIN6 In+ Sample Σ AIN7 In− Buffer andHold PGA AINCOM Temperature Sensor Burnout Offset Detect REFIN− DAC D7h ADMUX DCh ADC0N0 F6h ACLK E6h ODAC AGND REFOUT/ A4h AIPOL.5 A4h AIPOL.6 REFIN+ fMOD fDATA A6h AIE.5 A6h AIE.6 A7h AISTAT.5 A7h AISTAT.6 FAST VIN M∆oΣdAulDatCor SSIINNCC23 Σ X ResulAtDRCegister Summation Block AUTO Offset Gain Calibration Calibration Σ REFIN− Register Register DDh ADCON1 OCR GCR ADRES DEh ADCON2 D3h D2h D1h D6h D5h D4h DBh DAh D9h SUMR DFh ADCON3 E5h E4h E3h E2h E1h SSCON Figure 12. MSC1211/12/13/14 ADC Structure 26

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC ANALOG INPUT When the buffer is not selected, the input impedance of the analog input changes with ACLK clock frequency (ACLK AIN0 F6h) and gain (PGA). The relationship is: AIN1 AVDD Impedance((cid:1))(cid:1)fSAMP1(cid:2)CS (cid:3) (cid:5) (cid:3) (cid:5) AIN2 Burnout Detect (2µA) A Impedance((cid:1))(cid:1) 1(cid:4)106 (cid:2) 7M(cid:1) IN ACLKFrequency PGA f AIN3 where ACLK frequency (f )(cid:1) CLK ACLK ACLK(cid:6)1 In+ f AIN4 Buffer and modclk(cid:1)f (cid:1) ACLK. MOD 64 In− NOTE:The input impedance for PGA = 128 is the same as AIN5 that for PGA = 64 (thatis,7M(cid:1)). 64 Burnout Detect (2µA) Figure 14 shows the basic input structure of the AIN6 Temperature Sensor MSC1211/12/13/14. The sampling frequency varies AVDD AGND AVDD according to the PGA settings, as shown in the table in 80 • I Figure 14. AIN7 I AINCOM R SWITCH (3ktypical) High A Impedance IN >1GΩ C S (9pF typical) Figure 13. Input Multiplexer Configuration Sampling Frequency=fSAMP AGND ADC INPUT BUFFER PGA C S 1 9pF The analog input impedance is always high, regardless of 2 18pF 4to128 36pF PGA setting (when the buffer is enabled). With the buffer enabled, the input voltage range is reduced and the analog BIPOLAR MODE UNIPOLAR MODE power-supply current is higher. If the limitation of input voltage range is acceptable, then the buffer is always PGA FULL-SCALE RANGE FULL-SCALE RANGE fSAMP 1 ±VREF +VREF fMOD preferred. The input impedance of the MSC1211/12/13/14 2 ±VREF/2 +VREF/2 fMOD without the buffer is 7MΩ/PGA. The buffer is controlled by 4 ±VREF/4 +VREF/4 fMOD the state of the BUF bit in the ADC control register (ADCON0 8 ±VREF/8 +VREF/8 fMOD (cid:3) 2 16 ±VREF/16 +VREF/16 fMOD (cid:3) 4 DCh). 32 ±VREF/32 +VREF/32 fMOD (cid:3) 8 64 ±VREF/64 +VREF/64 fMOD (cid:3) 16 128 ±VREF/128 +VREF/128 fMOD (cid:3) 16 NOTE: fMOD = ACLK frequency/64 Figure 14. Analog Input Structure 27

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC PGA For system calibration, the appropriate signal must be applied to the inputs. The system offset calibration The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. requires a zero input signal. It then computes an offset that Using the PGA can actually improve the effective will nullify offset in the system. The system gain calibration resolution of the ADC. For instance, with a PGA of 1 on a ±2.5V full-scale range (FSR), the ADC can resolve to requires a positive full-scale input signal. It then computes 1.5µV. With a PGA of 128 on a ±19mV FSR, the ADC can a value to nullify gain errors in the system. Each of these calibrations will take seven t periods to complete. resolve to 75nV, as shown in Table 3. DATA Calibration should be performed after power on. It should Table 3. Sampling Frequency versus PGA Setting also be done after a change in temperature, decimation ratio, buffer, Power Supply, voltage reference, or PGA. BIPOLAR MODE RMS The Offset DAC wil affect offset calibration; therefore, the PGA FULL-SCALE ENOB(1) INPUT-REFERRED value of the Offset DAC should be zero until prior to SETTING RANGE (V) AT 10HZ NOISE (nV) performing a calibration. 1 ±2.5V 21.7 1468 2 ±1.25 21.5 843 At the completion of calibration, the ADC Interrupt bit goes 4 ±0.625 21.4 452 high, which indicates the calibration is finished and valid 8 ±0.313 21.2 259 data is available. 16 ±0.156 20.8 171 32 ±0.0781 20.4 113 ADC DIGITAL FILTER 64 ±0.039 20 74.5 128 ±0.019 19 74.5 The Digital Filter can use either the Fast Settling, Sinc2, or (1)ENOB = Log2(FSR/RMS Noise) = Log2(224) − Log2(σCODES) Sinc3 filter, as shown in Figure 15. In addition, the Auto = 24 − Log2(σCODES) mode changes the Sinc filter after the input channel or PGA is changed. When switching to a new channel, it will use the Fast Settling filter for the next two conversions, the ADC OFFSET DAC first of which should be discarded. The analog input to the PGA can be offset (in bipolar mode) by up to half the full-scale input range of the PGA by using the ODAC register (SFR E6h). The ODAC (Offset DAC) register is an 8-bit value; the MSB is the sign and the seven AdjustableDigitalFilter LSBs provide the magnitude of the offset. Since the ODAC introduces an analog (instead of digital) offset to the PGA, Sinc3 using the ODAC does not reduce the range of the ADC. ADC MODULATOR Modulator Sinc2 DataOut The modulator is a single-loop, 2nd-order system. The modulator runs at a clock speed (f ) that is derived from FastSettling MOD the CLK using the value in the Analog Clock (ACLK) register (SFR F6h). The data output rate is: FILTER SETTLING TIME SETTLING TIME DataRate(cid:1)f (cid:1) fMOD FILTER (Conversion Cycles)(1) DATA DecimationRatio Sinc3 3 Sinc2 2 f f Fast 1 where f (cid:1) CLK (cid:1) ACLK MOD (ACLK(cid:6)1)(cid:2)64 64 NOTE: (1) MUX change may add one cycle. and Decimation Ratio is set in [ADCON3:ADCON2]. AUTO MODE FILTER SELECTION CONVERSION CYCLE ADC CALIBRATION 1 2 3 4 Fast Fast Sinc2 Sinc3 The offset and gain errors in the MSC1211/12/13/14, or the complete system, can be reduced with calibration. Calibration is controlled through the ADCON1 register (SFR DDh), bits CAL2:CAL0. Each calibration process Figure 15. Filter Step Responses takes seven t periods (data conversion time) to DATA complete. Therefore, it takes 14 t periods to complete DATA both an offset and gain calibration. 28

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 It will then use the Sinc2 followed by the Sinc3 filter to SINC3FILTERRESPONSE improve noise performance. This combines the low-noise (−3dB=0.262•f ) advantage of the Sinc3 filter with the quick response of the 0 DATA Fast Settling Time filter. The frequency response of each filter is shown in Figure 16. −20 VOLTAGE REFERENCE −40 B) The MSC1211/12/13/14 can use either an internal or n(d −60 ai external voltage reference. The voltage reference G −80 selection is controlled via ADC Control Register 0 (ADCON0, SFR DCh). The default power-up −100 configuration for the voltage reference is 2.5V internal. The internal voltage reference can be selected as either −120 0 1 2 3 4 5 1.25V or 2.5V. The analog power supply (AV ) must be DD f within the specified range for the selected internal voltage DATA reference. The valid ranges are: VREF = 2.5 internal SINC2FILTERRESPONSE (AVDD = 3.3V to 5.25V) and VREF = 1.25 internal (−3dB=0.318•f ) DATA (AVDD = 2.7V to 5.25V). If the internal VREF is selected, 0 then AGND must be connected to REF IN−. The REFOUT/REF IN+ pin should also have a 0.1µF capacitor −20 connected to AGND as close as possible to the pin. If the internal VREF is not used, then VREF should be disabled in −40 ADCON0. B) (d −60 n If the external voltage reference is selected, it can be used ai G as either a single-ended input or differential input, for −80 ratiometric measures. When using an external reference, it is important to note that the input current will increase for −100 VREF with higher PGA settings and with a higher modulator −120 frequency. The external voltage reference can be used 0 1 2 3 4 5 over the input range specified in the Electrical f DATA Characteristics section. For applications requiring higher performance than that FASTSETTLINGFILTERRESPONSE (−3dB=0.469• f ) obtainable from the internal reference, use an external DATA 0 precision reference such as the REF50xx. The internal reference performance can be observed in the noise (and −20 ENOB) versus input signal graphs in the Typical Characteristics section. All of the other ENOB plots are −40 obtained with the inputs shorted together. By shorting the B) inputs, the inherent noise performance of only the ADC (d −60 n can be determined and displayed. When the inputs are not Gai shorted, the extra noise comes from the reference. As can −80 be seen in the ENOB vs Input Signal graph, the external −100 reference adds about 0.7 bits of noise, whereas the internal reference adds about 2.3 bits of noise. This ENOB −120 performance of 19.4 represents 21.16 bits of noise. With 0 1 2 3 4 5 an LSB of 298nV, that translates to 6.3µV or a f DATA peak-to-peak noise of almost 42µV. The internal reference is initialized each time power is applied. That initialization can cause a shift in the output that is within the specified NOTE:fDATA=Normalized DataOutputRate=1/tDATA accuracy. An external reference provides the best noise, drift, and repeatability performance for high-precision Figure 16. Filter Frequency Responses applications. 29

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 VDAC DAC OUTPUT AMPLIFIER The architecture of the MSC1211/12/13/14 consists of a The output buffer amplifier is capable of generating string DAC followed by an output buffer amplifier. rail-to-rail voltages on its output, which provides an output Figure 17 shows a block diagram of the DAC architecture. range of AGND to AV . It is capable of driving a load of DD 2kΩ in parallel with 1000pF to GND. The source and sink The input coding to the DAC is straight binary, so the ideal capabilities of the output amplifier can be seen in the output voltage is given by: typical curves. The slew rate is 1V/µs with a full-scale (cid:3) (cid:5) VDAC(cid:1)V (cid:2) D settling time of 8µs. REF 65536 DAC REFERENCE where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535. Each DAC can be selected to use the REFOUT/REF IN+ pin voltage or the supply voltage AV as the reference for DD the DAC. DAC RESISTOR STRING DAC LOADING The DAC selects the voltage from a string of resistors from the reference to AGND. It is essentially a string of resistors, The DAC can be selected to be turned off with a 1kΩ, each of value R. The code loaded into the DAC register 100kΩ, or open circuit on the DAC outputs. determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. It is ensured monotonic because of the design architecture. DAC3 21 AIN3/VDAC3 DAC2 20 AIN2/VDAC2 DAC1 31 VDAC1 Sink 19 AIN1/IDAC1 AVDD 28 Source Current Mirror RDAC1 32 REFOUT/ REFIN+ DAC0 17 VDAC0 30 Sink DAC 0.1µF 18 AIN0/IDAC0 Sink Source Connection REF Current 2.5V/1.25V Mirror RDAC0 16 Figure 17. DAC Architecture 30

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 BIPOLAR OPERATION USING THE DAC ANALOG/DIGITAL LOW-VOLTAGE DETECT The DAC can be used for a bipolar output range, as shown The MSC1211/12/13/14 contain an analog or digital in Figure 18; the circuit illustrates an output voltage range low-voltage detect. When the analog or digital supply of ±V . Rail-to-rail operation at the amplifier output is drops below the value programmed in LVDCON (SFR REF achievable using an OPA703 as the output amplifier. E7h), an interrupt is generated (one for each supply). RESET R 1002kΩ The device can be reset from the following sources: +6V (cid:1) R Power-on reset 1001kΩ DACREF (cid:1) External reset OPA703 VREF VDAC ±(DACREF) (cid:1) Software reset (cid:1) −6V Watchdog timer reset (cid:1) Brownout reset Figure 18. Bipolar Operation with the DAC An external reset is accomplished by taking the RST pin The output voltage for any input code can be calculated as high for two t periods, followed by taking the RST pin OSC follows: low. A software reset is accomplished through the System (cid:7) (cid:3) (cid:5) (cid:3) (cid:5)(cid:9) V (cid:1) DAC (cid:2)(cid:3) D (cid:5)(cid:2) R1(cid:6)R2 (cid:8)DAC (cid:2) R1 Reneasbelte rde gainsdte rc o(SnRtroTlSleTd, 0thFr7ohu)g. hA H waartdcwhadroeg Ctimonefrig ruersaetito ins O REF 65536 R REF R 1 2 Register 0 (HCR0) and the Watchdog Timer register where D represents the input code in decimal (0 to 65535). (WDTCON, 0FFh). A brownout reset is enabled through Hardware Configuration Register 1 (HCR1). External With DAC = 5V, R = R : REF 1 2 reset, software reset, and watchdog timer reset complete (cid:3) (cid:5) V (cid:1) 10(cid:2)D (cid:8)5V after 217 clock cycles. A brownout reset completes after 215 O 65536 clock cycles. This is an output voltage range of ±5V with 0000h All sources of reset cause the digital pins to be pulled high corresponding to a –5V output and FFFFh corresponding from the initiation of the reset. For an external reset, taking to a +5V output. Similarly, using DAC = 2.5V, a ±2.5V the RST pin high stops device operation (crystal REF output voltage can be achieved. oscillation, internal oscillator, or PLL circuit operation) and causes all digital pins to be pulled high from that point. IDAC Taking the RST pin low initiates the reset procedure. A recommended external reset circuit is shown in The IDAC can source current and sink current (through an Figure 19. The serial 10kΩ resistor is recommended for external transistor). The compliance specification of the any external reset circuit configuration. IDAC output defines the maximum output voltage to achieve the expected current. (cid:12)4(cid:2)V DVDD (cid:10) DAC for Source mode MSC1211/12/13/14 IDACOUT(cid:1)(cid:11)(cid:10)VRDAC 0.1µF 10kΩ 13 RST (cid:13) DAC for Sink mode R DAC 1MΩ with V < (AV − 2V) for maximum code. DAC DD Refer to Figure 17 for the IDAC structure. Figure 19. Typical Reset Circuit 31

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 POWER ON RESET peripherals not in use in the PDCON register (0F1h) and reducing the system clock frequency by using the System The on-chip Power On Reset (POR) circuitry releases the Clock Divider register (SYSCLK, 0C7h). device from reset when DV ≈ 2.0V. The power supply DD ramp rate does not affect the POR. If the power supply falls below 1.0V for more than 200ms, then the POR will STOP MODE execute. If the power supply falls below 1.0V for less than 200ms, unexpected operation may occur. If these Stop mode is entered by setting the STOP bit in the Power conditions are not met, the POR will not execute. For Control register (PCON, 087h). In STOP mode, all internal example, a negative spike on the DV supply that does clocks are halted. This mode has the lowest power DD not remain below 1.0V for at least 200ms, will not initiate consumption. The device can be returned to active mode a POR. only via an external or power-on reset (not brownout reset). If the Analog/Digital Brownout Reset circuit is on, the POR has no effect. By configuring the device prior to entering Stop mode, further power reductions can be achieved (while in Stop mode). These power reductions include halting the BROWNOUT RESET external clock into the device, configuring all digital I/O pins as open drain with low output drive, disabling the ADC The Brownout Reset (BOR) is enabled through HCR1. If buffer, disabling the internal V , disabling the DACs, and REF the conditions for proper POR are not met, or the device setting PDCON to 0FFh to power down all peripherals. encounters a brownout condition that does not generate a In Stop mode, all digital pins retain their values. If the BOR POR, the BOR can be used to ensure proper device is enabled before entering Stop mode, the BOR circuit will operation. The BOR will hold the state of the device when continue to draw approximately 25µA of current from the the power supply drops below the threshold level power supply during Stop mode. To minimize power programmed in HCR1, and then generate a reset when the consumption, disable the BOR circuit before entering Stop supply rises above the threshold level. Note that, as the mode. device is released from reset and program execution begins, the device current consumption may increase, which can result in a power supply voltage drop, which POWER CONSUMPTION CONSIDERATIONS may initiate another brownout condition. The BOR level should be chosen to match closely with the The following suggestions will reduce current application. That is, with a high external clock frequency, consumption in the MSC1211/12/13/14 devices: the BOR level should match the minimum operating 1. Use the lowest supply voltage that will work in the voltage range for the device or improper operation may still application for both AV and DV . DD DD occur. 2. Use the lowest clock frequency that will work in the The BOR voltage is not calibrated until the end of the reset application. cycle; therefore, the actual BOR voltage will be 3. Use Idle mode and the system clock divider approxiamtely 25% higher than the selected voltage. This whenever possible. Note that the system clock can create a condition where the reset never ends (for divider also affects the ADC clock. example, when selecting a 4.5V BOR voltage for a 5V 4. Avoid using 8051-compatible I/O mode on the I/O power supply). ports. The internal pull-up resistors will draw current when the outputs are low. IDLE MODE 5. Use the delay line for Flash Memory control by setting the FRCM bit in the FMCON register (SFR Idle mode is entered by setting the IDLE bit in the Power EEh) Control register (PCON, 087h). In Idle mode, the CPU, Timer0, Timer1, and USARTs are stopped, but all other 6. Power down peripherals when they are not needed. peripherals and digital pins remain active. The device can Refer to SFR PDCON, LVDCON, ADCON0, and be returned to active mode via an active internal or external DACCONx. interrupt. This mode is typically used for reducing power For more information about power cunsumption consumption between ADC samples. considerations, refer to application report SBAA139, By configuring the device prior to entering Idle mode, Minimizing Power Consumption on the MSC12xx, further power reductions can be achieved (while in Idle available for download at www.ti.com. mode). These reductions include powering down 32

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 MEMORY MAP FLASH MEMORY The MSC1211/12/13/14 contain on-chip SFR, Flash The page size for Flash memory is 128 bytes. The Memory, Scratchpad SRAM Memory, Boot ROM, and respective page must be erased before it can be written to, SRAM. The SFR registers are primarily used for control regardless of whether it is mapped to Program or Data and status. The standard 8051 features and additional Memory space. The MSC1211/12/13/14 use a memory peripheral features of the MSC1211/12/13/14 are addressing scheme that separates Program Memory controlled through the SFR. Reading from an undefined (FLASH/ROM) from Data Memory (FLASH/RAM). Each SFR will return zero; writing to an undefined SFR is not area is 64kB beginning at address 0000h and ending at recommended, and will have indeterminate effects. FFFFh, as shown in Figure 20. The program and data segments can overlap since they are accessed in different Flash Memory is used for both Program Memory and Data ways. Program Memory is fetched by the microcontroller Memory. The user has the ability to select the partition size automatically. There is one instruction (MOVC) that is of Program and Data Memory. The partition size is set used to explicitly read the program area. This instruction through hardware configuration bits, which are is commonly used to read lookup tables. The Data Memory programmed through either the parallel or serial area is accessed explicitly using the MOVX instruction. programming methods. Both Program and Data Flash This instruction provides multiple ways of specifying the Memory are erasable and writable (programmable) in User target address. It is also used to access the 64kB of Data Application mode (UAM). However, program execution Memory. The address and data range of devices with can only occur from Program Memory. As an added on-chip Program and Data Memory overlap the 64kB precaution, a lock feature can be activated through the memory space. When on-chip memory is enabled, hardware configuration bits, which disables erase and accessing memory in the on-chip range will cause the writes to 4kB of Program Flash Memory or the entire device to access internal memory. Memory accesses Program Flash Memory in UAM. beyond the internal range will be addressed externally via The MSC1211/12/13/14 include 1kB of SRAM on-chip. Ports 0 and 2. SRAM starts at address 0 and is accessed through the The MSC1211/12/13/14 have two hardware configuration MOVX instruction. This SRAM can also be located to start registers (HCR0 and HCR1) that are programmable only at 8400h and can be accessed as both Program and Data during Flash Memory Programming mode. Memory. Program Data Memory Memory in0 FFFFh FFFFh ctR 2kInternalBootROM eleHC F800h S External MappedtoBoth External Flash User Program MemorySpaces Data Configuration Programming Application (vonNeumann) Mode Mode Memory Memory Memory Address Address(1) SelectinMCON 1kExRtAerMnaolrMEexmteorrnyal 88784F00F00Fhhh,32k(Y5) 1kRAMorExternal 8838F00Fhh,33k(Y5) FUPAMM::RReeaadd/WOrniltye 807Fh 7Fh 8079h 79h On−Chip 43FFh,17k(Y4) UAM:ReadOnly On−Chip 3FFFh,16k(Y4) inN FPM:ReadOnly Flash 1FFFh,8k(Y3) electMCO Flash 23FFh,9k(Y3) UAM:ReadOnly 8070h 70h S FPM:Read/Write 13FFh,5k(Y2) 8000h 00h 0FFFh,4k(Y2) 03FFh,1k NOTE:(1)CanbeaccessedusingCADDR 0000h,0k 1kRAMorExternal orthefaddr_data_readBootROMroutine. Figure 20. Memory Map 33

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 The MSC1211/12/13/14 allow the user to partition the It is important to note that the Flash Memory is readable Flash Memory between Program Memory and Data and writable by the user through the MOVX instruction Memory. For instance, the MSC1213Y5 contains 32kB of when configured as either Program or Data Memory (via Flash Memory on-chip. Through the hardware the MXWS bit in the MWS SFR 8Fh). This flexibility means configuration registers, the user can define the partition that the device can be partitioned for maximum Flash between Program Memory (PM) and Data Memory (DM), Program Memory size (no Flash Data Memory) and Flash as shown in Table 4 and Table 5. The MSC1211/12/13/14 Program Memory can be used as Flash Data Memory. families offer four memory configurations. However, this configuration may lead to undesirable behavior if the PC points to an area of Flash Program Memory that is being used for data storage. Therefore, it Table 4. MSC1211/12/13/14 Flash Partitioning is recommended to use Flash partitioning when Flash Memory is used for data storage. Flash partitioning HCR0 MSC121xY2 MSC121xY3 MSC121xY4 MSC121xY5 prohibits execution of code from Data Flash Memory. DFSEL PM DM PM DM PM DM PM DM Additionally, the Program Memory erase/write can be 000 0kB 4kB 0kB 8kB 0kB 16kB 0kB 32kB disabled through hardware configuration bits (HCR0), 001 0kB 4kB 0kB 8kB 0kB 16kB 0kB 32kB while still providing access (read/write/erase) to Data 010 0kB 4kB 0kB 8kB 0kB 16kB 16kB 16kB Flash Memory. 011 0kB 4kB 0kB 8kB 8kB 8kB 24kB 8kB The effect of memory mapping on Program and Data 100 0kB 4kB 4kB 4kB 12kB 4kB 28kB 4kB Memory is straightforward. The Program Memory is 101 2kB 2kB 6kB 2kB 14kB 2kB 30kB 2kB decreased in size from the top of internal Program 110 3kB 1kB 7kB 1kB 15kB 1kB 31kB 1kB Memory. Therefore, for example, if the MSC1213Y5 is 111 (default) 4kB 0kB 8kB 0kB 16kB 0kB 32kB 0kB partitioned with 31kB of Flash Program Memory and 1kB NOTE: When a 0kB Program Memory configuration is selected, program of Flash Data Memory, external Program Memory execution is external. execution will begin at 7C00h (versus 8000h for 32kB). The Flash Data Memory is added on top of the SRAM Table 5. MSC1211/12/13/14 Flash Memory memory. Thus, access to Data Memory (through MOVX) Partitioning will access SRAM for addresses 0000h−03FFh and access Flash Memory for addresses 0400h−07FFh. HCR0 MSC121xY2 MSC121xY3 MSC121xY4 MSC121xY5 DFSEL PM DM PM DM PM DM PM DM Data Memory 000 0000 0400- 0000 0400- 0000 0400- 0000 0400- The MSC1211/12/13/14 can address 64kB of Data 13FF 23FF 43FF 83FF Memory. Scratchpad Memory provides 256 bytes in 001 0000 0400- 0000 0400- 0000 0400- 0000 0400- 13FF 23FF 43FF 83FF addition to the 64kB of Data Memory. The MOVX instruction is used to access the Data SRAM Memory. This 010 0000 0400- 0000 0400- 0000 0400- 0000- 0400- 13FF 23FF 43FF 3FFF 43FF includes 1024 bytes of on-chip Data SRAM Memory. The 011 0000 0400- 0000 0400- 0000- 0400- 0000- 0400- data bus values do not appear on Port 0 (during data bus 13FF 23FF 1FFF 23FF 5FFF 23FF timing) for internal memory access. 100 0000 0400- 0000- 0400- 0000- 0400- 0000- 0400- The MSC1211/12/13/14 also have on-chip Flash Data 13FF 0FFF 13FF 2FFF 13FF 6FFF 13FF Memory which is readable and writable (depending on 101 0000- 0400- 0000- 0400- 0000- 0400- 0000- 0400- Memory Write Select register) during normal operation (full 07FF 0BFF 17FF 0BFF 37FF 0BFF 77FF 0BFF V range). This memory is mapped into the external Data 110 0000- 0400- 0000- 0400- 0000- 0400- 0000- 0400- DD 0BFF 07FF 1BFF 07FF 3BFF 07FF 7BFF 07FF Memory space directly above the SRAM. 111 0000- − − 0000- − − 0000- − − 0000- − − The MOVX instruction is used to write to Flash Memory. (default) 0FFF 1FFF 3FFF 7FFF Flash Memory must be erased before it can be written. NOTE: Program Memory accesses above the highest listed address will Flash Memory is erased in 128 byte pages. access external Program Memory. 34

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 CONFIGURATION MEMORY The MSC121x Configuration Memory consists of 128 bytes. In UAM, all Configuration Memory is readable using the 255 FFh 255 FFh Direct faddr_data_read Boot ROM routine, and the CADDR and Indirect SpecialFunction CDATA registers. In UAM, however, none of the RAM Registers 128 80h 128 Configuration Memory is writable. 80h 127 7Fh SFRRegisters In serial or parallel programming mode, all Configuration Direct Memory is readable. Most locations are also writable, except RAM 0 00h for addresses 8070h through 8079h, which are read-only. Scratchpad The two hardware configuration registers reside in RAM configuration memory at 807Eh (HCR1) and 807Fh (HCR0). Figure 21 shows the configuration register mapping for programming mode and UAM. Note that reading/writing configuration memory in Flash Programming mode (FPM) Figure 22. Register Map requires 16-bit addressing; whereas, reading configuration memory in User Application mode (UAM) SFRs are accessed directly between 80h and FFh (128 to requires only 8-bit addressing. 255). The RAM locations between 128 and 255 can be reached through an indirect reference to those locations. Scratchpad RAM is available for general-purpose data User storage. It is commonly used in place of off-chip RAM Flash Application Programming Mode when the total data contents are small. When off-chip RAM Mode (Read−Only) is needed, the Scratchpad area will still provide the fastest HCR0 general-purpose access. Within the 256 bytes of RAM, 0807Fh 7Fh there are several special-purpose areas. HCR1 0807Eh 7Fh 08079h 79h Bit Addressable Locations Read−OnlyinBoth FPMandUAM In addition to direct register access, some individual bits 08070h 70h are also accessible. These are individually addressable bits in both the RAM and SFR area. In the Scratchpad RAM area, registers 20h to 2Fh are bit addressable. This 08000h 00h UAMAddress provides 128 (16 • 8) individual bits available to software. A bit access is distinguished from a full-register access by NOTE:AllConfigurationMemoryisR/Winprogrammingmode,except the type of instruction. In the SFR area, any register addresses8070h−8079h,whichareread−only.AllConfiguration location ending in a 0 or 8 is bit addressable. Figure 23 Memoryisread−onlyinUAM. shows details of the on-chip RAM addressing including the locations of individual RAM bits. Figure 21. Configuration Memory Mapping for Programming Mode and UAM Working Registers As part of the lower 128 bytes of RAM, there are four banks REGISTER MAP of Working Registers, as shown in Figure 23. The Working Registers are general-purpose RAM locations that can be Figure 22 illustrates the Register Map. It is entirely addressed in a special way. They are designated R0 separate from the Program and Data Memory areas through R7. Since there are four banks, the currently discussed previously. A separate class of instructions is selected bank will be used by any instruction using used to access the registers. There are 256 potential R0—R7. This design allows software to change context by register locations. In practice, the MSC1211/12/13/14 simply switching banks. Bank access is controlled via the have 256 bytes of Scratchpad RAM and up to 128 SFRs. Program Status Word register (PSW; 0D0h) in the SFR area described below. Registers R0 and R1 also allow This is possible, since the upper 128 Scratchpad RAM their contents to be used for indirect addressing of the locations can only be accessed indirectly. Thus, a direct upper 128 bytes of RAM. reference to one of the upper 128 locations must be an SFR access. Direct RAM is reached at locations 0 to 7Fh (0 to 127). 35

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Thus, an instruction can designate the value stored in R0 (for example) to address the upper RAM. The 16 bytes immediately above the these registers are bit addressable. FFh So any of the 128 bits in this area can be directly accessed Indirect using bit addressable instructions. RAM 7Fh Stack Direct RAM Another use of the Scratchpad area is for the programmer’s stack. This area is selected using the Stack 2Fh 7F 7E 7D 7C 7B 7A 79 78 Pointer (SP; 81h) SFR. Whenever a call or interrupt is 2Eh 77 76 75 74 73 72 71 70 invoked, the return address is placed on the Stack. It also is available to the programmer for variables, etc., since the 2Dh 6F 6E 6D 6C 6B 6A 69 68 Stack can be moved and there is no fixed location within 2Ch 67 66 65 64 63 62 61 60 the RAM designated as Stack. The Stack Pointer will 2Bh 5F 5E 5D 5C 5B 5A 59 58 default to 07h on reset. The user can then move it as needed. A convenient location would be the upper RAM 2Ah 57 56 55 54 53 52 51 50 area (> 7Fh) since this is only available indirectly. The SP 29h 4F 4E 4D 4C 4B 4A 49 48 e will point to the last used value. Therefore, the next value bl 28h 47 46 45 44 43 42 41 40 ssa placed on the Stack is put at SP + 1. Each PUSH or CALL e 27h 3F 3E 3D 3C 3B 3A 39 38 ddr will increment the SP by the appropriate value. Each POP A or RET will decrement as well. 26h 37 36 35 34 33 32 31 30 Bit- Program Memory 25h 2F 2E 2D 2C 2B 2A 29 28 After reset, the CPU begins execution from Program 24h 27 26 25 24 23 22 21 20 Memory location 0000h. The selection of where Program 23h 1F 1E 1D 1C 1B 1A 19 18 Memory execution begins is made by tying the EA pin to DV for internal access, or DGND for external access. 22h 17 16 15 14 13 12 11 10 DD When EA is tied to DV , any PC fetches outside the DD 21h 0F 0E 0D 0C 0B 0A 09 08 internal Program Memory address occur from external 20h 07 06 05 04 03 02 01 00 memory. If EA is tied to DGND, then all PC fetches 1Fh address external memory. Table 6 shows the standard Bank3 internal Program Memory size for MSC1211/12/13/14 18h family members. If enabled the Boot ROM will appear from 17h address F800h to FFFFh. Bank2 10h 0Fh Bank1 Table 6. MSC1211/12/13/14 Maximum Internal 08h Program Memory Sizes 07h Bank0 STANDARD INTERNAL 0000h MODEL NUMBER PROGRAM MEMORY SIZE (BYTES) MSB LSB MSC121xY5 32k MSC121xY4 16k MSC121xY3 8k MSC121xY2 4k Figure 23. Scratchpad Register Addressing 36

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ACCESSING EXTERNAL MEMORY The functions of Port 0 and Port 2 are selected in HCR1. (Hardware configuration registers can only be changed If external memory is used, P0 and P2 must be configured during Flash Programming mode.) The default state is for as address and data lines. If external memory is not used, P0 Port 0 and Port 2 to be used as general-purpose I/O. If an and P2 can be configured as general-purpose I/O lines external memory access is attempted when they are through the hardware configuration register (HCR0, HCR1). configured as general-purpose I/O, the values of Port 0 and Port 2 will not be affected. To enable access to external memory, bits 0 and 1 of the HCR1 register must be set to ‘0’. When these bits are External Program Memory is accessed under two conditions: enabled all memory accesses for both internal and 1. Whenever signal EA is low during reset, then all future external memory will appear on Ports 0 and 2. During the code and data accesses are external; or data portion of the cycle for internal memory, Port 0 will be 2. Whenever the Program Counter (PC) contains a zero for security purposes. number that is outside of the internal Program Memory Accesses to external memory are of two types: to external address range, if the ports are enabled. Program Memory and to external Data Memory. Accesses If Port 0 and Port 2 are selected for external memory, all 8 to external Program Memory use signal PSEN (program bits of Port 0 and Port 2, as well as P3.6 and P3.7, are store enable) as the read strobe. Accesses to external dedicated to an output function and may not be used for Data Memory use RD or WR (alternate functions of P3.7 general-purpose I/O. During external program fetches, and P3.6) to strobe the memory. Port 2 outputs the high byte of the PC. If desired, External Program Memory and external Data Programming Flash Memory Memory may be combined by applying the RD and PSEN signals to the inputs of an AND gate and using the output There are four sections of Flash Memory for programming: of the gate as the read strobe to the external Program/Data 1. 128 configuration bytes. Memory. 2. Reset sector (4kB) (not to be confused with the 2kB A program fetch from external Program Memory uses a Boot ROM). 16-bit address. Accesses to external Data Memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit 3. Program Memory. address (MOVX @R). I 4. Data Memory. If Port 2 is selected for external memory use (HCR1, bit 0), it cannot be used as general-purpose I/O. This bit (or Bit Boot ROM 1 of HCR1) also forces bits P3.6 and P3.7 to be used for There is a 2kB Boot ROM that controls operation during WR and RD instead of I/O. Port 2, P3.6, and P3.7 should serial or parallel programming. Additionally, the Boot ROM all be written to ‘1.’ routines can be accessed during the user mode if it is If an 8-bit address is being used (MOVX @R), the contents enabled. When enabled, the Boot ROM routines will be I of the MPAGE (92h) SFR remain at the Port 2 pins located at memory addresses F800h−FFFFh during user throughout the external memory cycle, which facilitates mode. In program mode the Boot ROM is located in the first paging. 2kB of Program Memory. For additional information, refer to Application Note SBAA085, available for download from In any case, the low byte of the address is time-multiplexed the TI web site (www.ti.com). with the data byte on Port 0. The ADDR/DATA signals use CMOS drivers in the Port 0, Port 2, WR, and RD output The MSC1211/12/13/14 are shipped with Flash Memory buffers. Thus, in this application, the Port 0 pins are not erased (all 1s). Parallel programming methods typically open-drain outputs, and do not require external pull-ups for involve a third-party programmer. Serial programming high-speed access. Signal ALE (Address Latch Enable) methods typically involve in-system programming. UAM should be used to capture the address byte into an external allows Code Program and Data Memory programming. latch. The address byte is valid at the negative transition The actual code for Flash programming cannot execute of ALE. Then, in a write cycle, the data byte to be written from Flash. That code must execute from the Boot ROM appears on Port 0 just before WR is activated, and remains or internal (von Neumann) RAM. there until after WR is deactivated. In a read cycle, the incoming byte is accepted at Port 0 just before the read strobe is deactivated. 37

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Flash Programming Mode MSC1211/12/13/14 HOST There are two programming modes: parallel and serial. PSEL The programming mode is selected by the state of the ALE P2[7] Flash and PSEN signals during reset (BOR, WDT, software, or AddrHi[6:0] Programmer P2[6:0] POR). Serial programming mode is selected with PSEN = NC PSEN AddrLo[7:0] 0 and ALE = 1. Parallel programming mode is selected P1[7:0] with PSEN = 1 and ALE = 0, as shown in Figure 24. If they Data[7:0] are both high, the MSC1211/12/13/14 will operate in User P0[7:0] ALE Application mode. For both signals, low is a reserved Cmd[2:0] P3[7:5] mode and is not defined. Programming mode is exited with Req a reset and the normal mode selected. P3[4] Ack Figure 25 shows the serial programming conection. P3[3] Pass Serial programming mode works through USART0, and P3[2] has special protocols. Table 7 describes these protocols, RST which are discussed at length in Application Note RST SBAA076 (available for download at www.ti.com). The CLK XIN serial programming mode works at a maximum baud rate determined by f . OSC Figure 24. Parallel Programming Configuration MSC121x ResetCircuit(orV ) DD RST DV DD P3.1TXD PSEN HostPC Serial RS232 Port0 P3.0RXD Transceiver or SerialTerminal NotConnected ALE ClockSource X IN NOTE:SerialprogrammingisselectedwithPSEN=0andALE=1oropen. Figure 25. Serial Programming Connection 38

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 7. MSC121x Boot ROM Routines ADDRESS ROUTINE C DECLARATIONS DESCRIPTION FFD5 put_string void put_string (char code *string); Output string FFD7 page_erase char page_erase (int faddr, char fdata, char fdm); Erase flash page FFD9 write_flash Assembly only; DPTR = address, R5 = data Fast flash write FFDB write_flash_chk char write_flash_chk (int faddr, char fdata, char fdm); Write flash byte, verify FFDD write_flash_byte char write_flash_byte (int faddr, char fdata, char fdm); Write flash byte FFDF faddr_data_read char faddr_data_read (char faddr); Read HW config byte from addr FFE1 data_x_c_read char data_x_c_read (int faddr, char fdm); Read xdata or code byte FFE3 tx_byte void tx_byte (char); Send byte to USART0 FFE5 tx_hex void tx_hex (char); Send hex value to USART0 FFE7 putok void putok (void); Send “OK” to USART0 FFE9 rx_byte char rx_byte (void); Read byte from USART0 FFEB rx_byte_echo char rx_byte_echo (void); Read and echo byte on USART0 FFED rx_hex_echo int rx_hex_echo (void); Read and echo hex on USART0 FFEF rx_hex_int_echo int rx_hex_int_echo (void); Read int as hex and echo: USART0 FFF1 rx_hex_rev_echo int rx_hex_rev_echo (void); Read int reversed as hex and echo: USART0 FFF3 autobaud void autobaud (void); Set baud with received CR FFF5 putspace4 void putspace4 (void); Output 4 spaces to USART0 FFF7 putspace3 void putspace3 (void); Output 3 spaces to USART0 FFF9 putspace2 void putspace2 (void); Output 2 spaces to USART0 FFFB putspace1 void putspace1 (void); Output 1 space to USART0 FFFB putcr void putcr (void); Output CR, LF to USART0 F97D(1) cmd_parse void cmd_parser (void); See SBAA076 FD3B(1) monitor_isr void monitor_isr ( ) interrupt 6 Push registers and call cmd_parser (1) These addresses only relate to version 1.0 of the MSC1211/12/13/14 Boot ROM. 39

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 INTERRUPTS (except that nine interrupts share the Auxiliary Interrupt (AI) at the highest priority). In addition, interrupts can be The MSC1211/12/13/14 use a three-priority interrupt globally enabled or disabled. The interrupt structure is system. As shown in Table 8, each interrupt source has an compatible with the original 8051 family. All of the standard independent priority bit, flag, interrupt vector, and enable interrupts are available. Table 8. Interrupt Summary INTERRUPT PPRRIIOORRIITTYY INTERRUPT/EVENT ADDR NUM PRIORITY FLAG ENABLE CONTROL DVDD Low Voltage/HW Break- 33h 6 High EDLVB (AIE.0 or AIPOL.0)(1)(2) EDLVB (AIE.0)(1) N/A point EBP (BPCON.7)(1) EBP (BPCON.0)(1) AVDD Low Voltage 33h 6 0 EALV (AIE.1 or AIPOL.1)(1)(2) EALV (AIE.1)(1) N/A SPI Receive / I2C(3) 33h 6 0 ESPIR/EI2C (AIE.2 or AIPOL.2)(1)(2) ESPIR/EI2C (AIE.2)(1) N/A SPI Transmit 33h 6 0 ESPIT (AIE.3 or AIPOL.3)(1)(2) ESPIT (AIE.3)(1) N/A Milliseconds Timer 33h 6 0 EMSEC (AIE.4 or AIPOL.4)(1)(2) EMSEC (AIE.4)(1) N/A ADC 33h 6 0 EADC (AIE.5 or AIPOL.5)(1)(2) EADC (AIE.5)(1) N/A Summation Register 33h 6 0 ESUM (AIE.6 or AIPOL.6)(1)(2) ESUM (AIE.6)(1) N/A Seconds Timer 33h 6 0 ESEC (AIE.7 or AIPOL.7)(1)(2) ESEC (AIE.7)(1) N/A External Interrupt 0 03h 0 1 IE0 (TCON.1)(4) EX0 (IE.0)(6) PX0 (IP.0) Timer 0 Overflow 0Bh 1 2 TF0 (TCON.5)(5) ET1 (IE.1)(6) PT0 (IP.1) External Interrupt 1 13h 2 3 IE1 (TCON.3)(4) EX1 (IE.2)(6) PX1 (IP.2) Timer 1 Overflow 0Bh 3 4 TF1 (TCON.7)(5) ET1 (IE.3)(6) PT1 (IP.3) Serial Port 0 23h 4 5 RI_0 (SCON0.0) ES0 (IE.4)(6) PS0 (IP.4) TI_0 (SCON0.1) Timer 2 Overflow 2Bh 5 6 TF2 (T2CON.7) ET2 (IE.5)(6) PT2 (IP.5) Serial Port 1 3Bh 7 7 RI_1 (SCON1.0) ES1 (IE.6)(6) PS1 (IP.6) TI_1 (SCON1.1) External Interrupt 2 43h 8 8 IE2 (EXIF.4)(4) EX2 (EIE.0)(6) PX2 (EIP.0) External Interrupt 3 4Bh 9 9 IE3 (EXIF.5)(4) EX3 (EIE.1)(6) PX3 (EIP.1) External Interrupt 4 53h 10 10 IE4 (EXIF.6)(4) EX4 (EIE.2)(6) PX4 (EIP.2) External Interrupt 5 5Bh 11 11 IE5 (EXIF.7)(4) EX5 (EIE.3)(6) PX5 (EIP.3) Watchdog 63h 12 12 WDTI (EICON.3) EWDI (EIE.4)(6) PWDI (EIP.4) Low (1)These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5). (2)For AIPOL.RDSEL = 1, reading AIPOL register gives current value of Auxiliary interrupts before masking. Reading AIE register gives value of AIE register contents. For AIPOL.RDSEL = 0, Reading AIPOL register gives value of AIE register contents. Reading AIE register gives current value of Auxiliary interrupts before masking. (3)I2C is only available on the MSC1211 and MSC1213. (4)If edge-triggered, cleared automatically by hardware on interrupt service routine vector. For EX0 or EX1, if level-triggered, the flag follows the state of the pin. (5)Cleared automatically by hardware when interrupt vector occurs. (6)Globally enabled by EA (IE.7). 40

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Hardware Configuration Register 0 (HCR0)—Accessed Using SFR Registers CADDR and CDATA. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CADDR 7Fh EPMA PML RSL EBR EWDR DFSEL2 DFSEL1 DFSEL0 NOTE: HCR0 is programmable only in Flash Programming mode, but can be read in User Application mode using the CADDR and CDATA SFRs or the faddr_data_read Boot ROM routine. EPMA Enable Programming Memory Access (Security Bit). bit 7 0: After reset in programming modes, Flash Memory can only be accessed in UAM until a mass erase is done. 1: Fully Accessible (default) PML Program Memory Lock (PML has priority over RSL). bit 6 0: Enable writing to Program Memory in UAM. 1: Disable writing to Program Memory in UAM (default). RSL Reset Sector Lock. The reset sector can be used to provide another method of Flash Memory programming, which bit 5 allows Program Memory updates without changing the jumpers for in-circuit code updates or program development. The code in this boot sector would then provide the monitor and programming routines with the ability to jump into the main Flash code when programming is finished. 0: Enable Reset Sector Writing 1: Enable Read-Only Mode for Reset Sector (4kB) (default) EBR Enable Boot ROM. Boot ROM is 2kB of code located in ROM, not to be confused with the 4kB Boot Sector located bit 4 in Flash Memory. 0: Disable Internal Boot ROM 1: Enable Internal Boot ROM (default) EWDR Enable Watchdog Reset. bit 3 0: Disable Watchdog Reset 1: Enable Watchdog Reset (default) DFSEL1−0 Data Flash Memory Size (see Table 4 and Table 5). bits 2−0 000: Reserved 001: 32kB, 16kB, 8kB, or 4kB Data Flash Memory 010: 16kB, 8kB, or 4kB Data Flash Memory 011: 8kB or 4kB Data Flash Memory 100: 4kB Data Flash Memory 101: 2kB Data Flash Memory 110: 1kB Data Flash Memory 111: No Data Flash Memory (default) 41

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Hardware Configuration Register 1 (HCR1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CADDR 7Eh DBLSEL1 DBLSEL0 ABLSEL1 ABLSEL0 DAB DDB EGP0 EGP23 NOTE: HCR1 is programmable only in Flash Programming mode, but can be read in User Application mode using the CADDR and CDATA SFRs or the faddr_data_read Boot ROM routine. DBLSEL Digital Supply Brownout Level Select bits 7−6 00: 4.5V 01: 4.2V 10: 2.7V 11: 2.5V (default) ABLSEL Analog Supply Brownout Level Select bits 5−4 00: 4.5V 01: 4.2V 10: 2.7V 11: 2.5V (default) DAB Disable Analog Power-Supply Brownout Reset bit 3 0: Enable Analog Brownout Reset 1: Disable Analog Brownout Reset (default) DDB Disable Digital Power-Supply Brownout Reset bit 2 0: Enable Digital Brownout Reset 1: Disable Digital Brownout Reset (default) EGP0 Enable General-Purpose I/O for Port 0 bit 1 0: Port 0 is Used for External Memory, P3.6 and P3.7 Used for WR and RD. 1: Port 0 is Used as General-Purpose I/O (default) EGP23 Enable General-Purpose I/O for Ports 2 and 3 bit 0 0: Port 2 is Used for External Memory, P3.6 and P3.7. Used for WR and RD. 1: Port 2 and Port3 are Used as General-Purpose I/O (default) Configuration Memory Programming Hardware Configuration Memory can be changed only in Serial Flash Programming mode or Parallel Programming mode. 42

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 9. Special Function Registers NOTE: (Boldface are in addition to standard 8051 registers, and unique to the MSC1211/12/13/14). ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUE 80h P0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 FFh 81h SP 07h 82h DPL0 00h 83h DPH0 00h 84h DPL1 00h 85h DPH1 00h 86h DPS 0 0 0 0 0 0 0 SEL 00h 87h PCON SMOD 0 1 1 GF1 GF0 STOP IDLE 30h 88h TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h 8899hh TTMMOODD −−−−−−−−−−−−−−−Timer 1−−−−−−−−−−−−−−− −−−−−−−−−−−−−−−Timer 0−−−−−−−−−−−−−−− 0000hh GATE C/T M1 M0 GATE C/T M1 M0 8Ah TL0 00h 8Bh TL1 00h 8Ch TH0 00h 8Dh TH1 00h 8Eh CKCON 0 0 T2M T1M T0M MD2 MD1 MD0 01h 8Fh MWS 0 0 0 0 0 0 0 MXWS 00h 90h P1 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 FFh INT5/SCK/SCL INT4/MISO/SDA INT3/MOSI INT2/SS TXD1 RXD1 T2EX T2 91h EXIF IE5 IE4 IE3 IE2 1 0 0 0 08h 92h MPAGE 08h 93hv CADDR 00h 94h CDATA 00h 95h MCON BPSEL 0 0 RAMMAP 00h 96h 00h 97h 98h SCON0 SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00h 99h SBUF0 00h 9Ah SPICON SCK2 SCK1 SCK0 FIFO ORDER MSTR CPHA CPOL 00h I2CCON(1) START STOP ACK 0 FAST MSTR SCLA FILEN 9Bh SPIDATA 00h I2CDATA(1) 9Ch SPIRCON RXCNT7 RXCNT6 RXCNT5 RXCNT4 RXCNT3 RXCNT2 RXCNT1 RXCNT0 00h I2CGM(1) RXFLUSH RXIRQ2 RXIRQ1 RXIRQ0 GCMEN 9Dh SPITCON TXCNT7 TXCNT6 TXCNT5 TXCNT4 TXCNT3 TXCNT2 TXCNT1 TXCNT0 00h I2CSTAT(1) TXFLUSH CLK_EN DRV_DLY DRV_EN TXIRQ2 TXIRQ1 TXIRQ0 STAT7 STAT5 STAT5 STAT4 STAT3 0 0 0 SCKD7/SAE SCKD6/SA6 SCKD5/SA5 SCKD4/SA4 SCKD3/SA3 SCKD2/SA2 SCKD1/SA1 SCKD0/SA0 9Eh SPISTART 1 80h I2CSTART(1) 9Fh SPIEND 1 80h A0h P2 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 FFh A1h PWMCON PPOL PWMSEL SPDSEL TPCNTL2 TPCNTL1 TPCNTL0 00h A2h PWMLOW PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 00h TONELOW TDIV7 TDIV6 TDIV5 TDIV4 TDIV3 TDIV2 TDIV1 TDIV0 A3h PWMHI PWM15 PWM14 PWM13 PWM12 PWM11 PWM10 PWM9 PWM8 00h TONEHI TDIV15 TDIV14 TDIV13 TDIV12 TDIV11 TDIV10 TDIV9 TDIV8 A4h AIPOL ESEC ESUM EADC EMSEC ESPIT ESPIR/EI2C EALV EDLVB 00h RDSEL (1)I2C is only available on the MSC1211 and MSC1213. (2)Applies to MSC1211 and MSC1213 only. See HWPC0 for MSC1212 and MSC1214. (3)Applies to the MSC1211 and MSC1212. See HWPC1 for MSC1213 and MSC1214. 43

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 9. Special Function Registers (continued) NOTE: (Boldface are in addition to standard 8051 registers, and unique to the MSC1211/12/13/14). ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUE A5h PAI 0 0 0 0 PAI3 PAI2 PAI1 PAI0 00h A6h AIE ESEC ESUM EADC EMSEC ESPIT ESPIR/EI2C EALV EDLVB 00h A7h AISTAT SEC SUM ADC MSEC SPIT SPIR/I2CSI ALVD DLVD 00h A8h IE EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00h A9h BPCON BP 0 0 0 0 0 PMSEL EBP 00h AAh BPL ABh BPH ACh P0DDRL P03H P03L P02H P02L P01H P01L P00H P00L 00h ADh P0DDRH P07H P07L P06H P06L P05H P05L P04H P04L 00h AEh P1DDRL P13H P13L P12H P12L P11H P11L P10H P10L 00h AFh P1DDRH P17H P17L P16H P16L P15H P15L P14H P14L 00h B0h P3 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 FFh RD WR T1 T0 INT1 INT0 TXD0 RXD0 B1h P2DDRL P23H P23L P22H P22L P21H P21L P20H P20L 00h B2h P2DDRH P27H P27L P26H P26L P25H P25L P24H P24L 00h B3h P3DDRL P33H P33L P32H P32L P31H P31L P30H P30L 00h B4h P3DDRH P37H P33L P32H P32L P31H P31L P30H P30L 00h B5h DACL B6h DACH B7h DACSEL DSEL7 DSEL6 DSEL5 DSEL4 DSEL3 DSEL2 DSEL1 DSEL0 00h B8h IP 1 PS1 PT2 PS0 PT1 PX1 PT0 PX0 80h B9h BAh BBh BCh BDh BEh BFh C0h SCON1 SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00h C1h SBUF1 00h C2h C3h C4h C5h C6h EWU EWUWDT EWUEX1 EWUEX0 00h C7h SYSCLK 0 0 DIVMOD1 DIVMOD0 0 DIV2 DIV1 DIV0 00h C8h T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00h C9h CAh RCAP2L 00h CBh RCAP2H 00h CCh TL2 00h CDh TH2 00h CEh CFh D0h PSW CY AC F0 RS1 RS0 OV F1 P 00h D1h OCL LSB 00h (1)I2C is only available on the MSC1211 and MSC1213. (2)Applies to MSC1211 and MSC1213 only. See HWPC0 for MSC1212 and MSC1214. (3)Applies to the MSC1211 and MSC1212. See HWPC1 for MSC1213 and MSC1214. 44

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 9. Special Function Registers (continued) NOTE: (Boldface are in addition to standard 8051 registers, and unique to the MSC1211/12/13/14). ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUE D2h OCM 00h D3h OCH MSB 00h D4h GCL LSB 54h D5h GCM ECh D6h GCH MSB 5Fh D7h ADMUX INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 01h D8h EICON SMOD1 1 EAI AI WDTI 0 0 0 40h D9h ADRESL LSB 00h DAh ADRESM 00h DBh ADRESH MSB 00h DCh ADCON0 REFCLK BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 30h DDh ADCON1 OF_UF POL SM1 SM0 — CAL2 CAL1 CAL0 0000_0000b DEh ADCON2 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1Bh DFh ADCON3 0 0 0 0 0 DR10 DR9 DR8 06h E0h ACC 00h E1h SSCON SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00h E2h SUMR0 00h E3h SUMR1 00h E4h SUMR2 00h E5h SUMR3 00h E6h ODAC 00h E7h LVDCON ALVDIS ALVD2 ALVD1 ALVD0 DLVDIS DLVD2 DLVD1 DLVD0 00h E8h EIE 1 1 1 EWDI EX5 EX4 EX3 EX2 E0h E9h HWPC0 0 0 0 0 0 1 MEMORY SIZE 0000_01xxb(2) EAh HWPC1 0 0 0 0 1 0 0 0 08h(3) EBh HWVER ECh Reserved 00h EDh Reserved 00h EEh FMCON 0 PGERA 0 FRCM 0 BUSY SPM FPM 02h EFh FTCON FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 A5h F0h B B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 00h F1h PDCON 0 PDDAC PDI2C PDPWM PDADC PDWDT PDST PDSPI 7Fh F2h PASEL 0 0 PSEN2 PSEN1 PSEN0 0 ALE1 ALE0 00h F3h F4h F5h F6h ACLK 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h F7h SRST 0 0 0 0 0 0 0 RSTREQ 00h F8h EIP 1 1 1 PWDI PX5 PX4 PX3 PX2 E0h F9h SECINT WRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 7Fh FAh MSINT WRT MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 7Fh FBh USEC 0 0 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h FCh MSECL 9Fh FDh MSECH 0Fh FEh HMSEC 63h FFh WDTCON EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00h (1)I2C is only available on the MSC1211 and MSC1213. (2)Applies to MSC1211 and MSC1213 only. See HWPC0 for MSC1212 and MSC1214. (3)Applies to the MSC1211 and MSC1212. See HWPC1 for MSC1213 and MSC1214. 45

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 10. Special Function Register Cross Reference POWER SERIAL AND TIMER FLASH SFR ADDRESS FUNCTIONS CPU INTERRUPTS PORTS COMM. CLOCKS COUNTERS PWM MEMORY ADC DAC P0 80h Port 0 X SP 81h Stack Pointer X DPL0 82h Data Pointer Low 0 X DPH0 83h Data Pointer High 0 X DPL1 84h Data Pointer Low 1 X DPH1 85h Data Pointer High 1 X DPS 86h Data Pointer Select X PCON 87h Power Control X TCON 88h Timer/Counter Control X X TMOD 89h Timer Mode Control X X TL0 8Ah Timer0 LSB X TL1 8Bh Timer1 LSB X TH0 8Ch Timer0 MSB X TH1 8Dh Timer1 MSB X CKCON 8Eh Clock Control X X X MWS 8Fh Memory Write Select X P1 90h Port 1 X EXIF 91h External Interrupt Flag X MPAGE 92h Memory Page X CADDR 93h Configuration Address X CDATA 94h Configuration Data X MCON 95h Memory Control X SCON0 98h Serial Port 0 Control X X SBUF0 99h Serial Data Buffer 0 X SPICON SPI Control X 99AAhh I2CCON I2C Control X SPIDATA SPI Data X 99BBhh I2CDATA I2C Data X SPIRCON SPI Receive Control X 99CChh I2CGM I2C Gen Call/Mult Master Enable X SPITCON SPI Transmit Control X 99DDhh I2CSTAT I2C Status X SPISTART SPI Buffer Start Address X 99EEhh I2CSTART I2C Start X SPIEND 9Fh SPI Buffer End Address X P2 A0h Port 2 X PWMCON A1h PWM Control X X PWMLOW PWM Low Byte X AA22hh TONELOW Tone Low Byte X PWMHI PWM HIgh Byte X AA33hh TONEHI Tone Low Byte X AIPOL A4h Auxiliary Interrupt Poll X X X X X X PAI A5h Pending Auxiliary Interrupt X X X X X X AIE A6h Auxiliary Interrupt Enable X X X X X X AISTAT A7h Auxiliary Interrupt Status X X X X X X IE A8h Interrupt Enable X 46

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 10. Special Function Register Cross Reference (continued) POWER SERIAL AND TIMER FLASH SFR ADDRESS FUNCTIONS CPU INTERRUPTS PORTS COMM. CLOCKS COUNTERS PWM MEMORY ADC DAC BPCON A9h Breakpoint Control X X BPL AAh Breakpoint Low Address X X BPH ABh Breakpoint High Address X X P0DDRL ACh Port 0 Data Direction Low X P0DDRH ADh Port 0 Data Direction High X P1DDRL AEh Port 1 Data Direction Low X P1DDRH AFh Port 1 Data Direction High X P3 B0h Port 3 X P2DDRL B1h Port 2 Data Direction Low X P2DDRH B2h Port 2 Data Direction High X P3DDRL B3h Port 3 Data Direction Low X P3DDRH B4h Port 3 Data Direction High X DACL B5h DAC Low Byte X DACH B6h DAC High Byte X DACSEL B7h DAC Select X DACCON B7h DAC Control X IP B8h Interrupt Priority X SCON1 C0h Serial Port 1 Control X X SBUF1 C1h Serial Data Buffer 1 X EWU C6h Enable Wake Up X X SYSCLK C7h System Clock Divider X X X X X X T2CON C8h Timer 2 Control X X RCAP2L CAh Timer 2 Capture LSB X X RCAP2H CBh Timer 2 Capture MSB X X TL2 CCh Timer 2 LSB X TH2 CDh Timer 2 MSB X PSW D0h Program Status Word X OCL D1h ADC Offset Calibration Low Byte X OCM D2h ADC Offset Calibration Mid Byte X OCH D3h ADC Offset Calibration High Byte X GCL D4h ADC Gain Calibration Low Byte X GCM D5h ADC Gain Calibration Mid Byte X GCH D6h ADC Gain Calibration High Byte X ADMUX D7h ADC Input Multiplexer X EICON D8h Enable Interrupt Control X X X X ADRESL D9h ADC Results Low Byte X ADRESM DAh ADC Results Middle Byte X ADRESH DBh ADC Results High Byte X ADCON0 DCh ADC Control 0 X ADCON1 DDh ADC Control 1 X ADCON2 DEh ADC Control 2 X ADCON3 DFh ADC Control 3 X ACC E0h Accumulator X SSCON E1h Summation/Shifter Control X X SUMR0 E2h Summation 0 X X SUMR1 E3h Summation 1 X X SUMR2 E4h Summation 2 X X SUMR3 E5h Summation 3 X X 47

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 10. Special Function Register Cross Reference (continued) POWER SERIAL AND TIMER FLASH SFR ADDRESS FUNCTIONS CPU INTERRUPTS PORTS COMM. CLOCKS COUNTERS PWM MEMORY ADC DAC ODAC E6h Offset DAC X LVDCON E7h Low Voltage Detect Control X EIE E8h Extended Interrupt Enable X HWPC0 E9h Hardware Product Code 0 X HWPC1 EAh Hardware Product Code 1 X HWVER EBh Hardware Version X FMCON EEh Flash Memory Control X FTCON EFh Flash Memory Timing Control X B F0h Second Accumulator X PDCON F1h Power Down Control X X X X X PASEL F2h PSEN/ALE Select X X ACLK F6h Analog Clock X X SRST F7h System Reset X X EIP F8h Extended Interrupt Priority X SECINT F9h Seconds Timer Interrupt X X MSINT FAh Milliseconds Timer Interrupt X X USEC FBh One Microsecond TImer X X X MSECL FCh One Millisecond TImer Low Byte X X MSECH FDh One Millisecond Timer High Byte X X HMSEC FEh One Hundred Millisecond TImer X WDTCON FFh Watchdog Timer X X HCR0 3Fh Hardware Configuration Reg. 0 X HCR1 3Eh Hardware Configuration Reg. 1 X 48

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 0 (P0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset Value SFR 80h P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 FFh P0.7−0 Port 0. This port functions as a multiplexed address/data bus during external memory access, and as a general- bits 7−0 purpose I/O port when external memory access is not needed. During external memory cycles, this port will contain the LSB of the address when ALE is high, and Data when ALE is low. When used as a general-purpose I/O, this port drive is selected by P0DDRL and P0DDRH (ACh, ADh). Whether Port 0 is used as general-purpose I/O or for external memory access is determined by the Flash Configuration Register (HCR1.1) (See SFR CADDR 93h). Stack Pointer (SP) 7 6 5 4 3 2 1 0 Reset Value SFR 81h SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0 07h SP.7−0 Stack Pointer. The stack pointer identifies the location where the stack will begin. The stack pointer is incremented bits 7−0 before every PUSH or CALL operation and decremented after each POP or RET/RETI. This register defaults to 07h after reset. Data Pointer Low 0 (DPL0) 7 6 5 4 3 2 1 0 Reset Value SFR 82h DPL0.7 DPL0.6 DPL0.5 DPL0.4 DPL0.3 DPL0.2 DPL0.1 DPL0.0 00h DPL0.7−0 Data Pointer Low 0. This register is the low byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are used bits 7−0 to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86h). Data Pointer High 0 (DPH0) 7 6 5 4 3 2 1 0 Reset Value SFR 83h DPH0.7 DPH0.6 DPH0.5 DPH0.4 DPH0.3 DPH0.2 DPH0.1 DPH0.0 00h DPH0.7−0 Data Pointer High 0. This register is the high byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are used bits 7−0 to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86h). Data Pointer Low 1 (DPL1) 7 6 5 4 3 2 1 0 Reset Value SFR 84h DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0 00h DPL1.7−0 Data Pointer Low 1. This register is the low byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) (SFR bits 7−0 86h) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations. Data Pointer High 1 (DPH1) 7 6 5 4 3 2 1 0 Reset Value SFR 85h DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0 00h DPH1.7−0 Data Pointer High. This register is the high byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) (SFR bits 7−0 86h) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations. 49

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Data Pointer Select (DPS) 7 6 5 4 3 2 1 0 Reset Value SFR 86h 0 0 0 0 0 0 0 SEL 00h SEL Data Pointer Select. This bit selects the active data pointer. bit 0 0: Instructions that use the DPTR will use DPL0 and DPH0. 1: Instructions that use the DPTR will use DPL1 and DPH1. Power Control (PCON) 7 6 5 4 3 2 1 0 Reset Value SFR 87h SMOD 0 1 1 GF1 GF0 STOP IDLE 30h SMOD Serial Port 0 Baud Rate Doubler Enable. The serial baud rate doubling function for Serial Port 0. bit 7 0: Serial Port 0 baud rate will be a standard baud rate. 1: Serial Port 0 baud rate will be double that defined by baud rate generation equation. GF1 General-Purpose User Flag 1. This is a general-purpose flag for software control. bit 3 GF0 General-Purpose User Flag 0. This is a general-purpose flag for software control. bit 2 STOP Stop Mode Select. Setting this bit halts the oscillator and blocks external clocks. This bit always reads as a 0. bit 1 All digital pins and DACs keep their respective output values. Internal REF dies. Exit with RESET. IDLE Idle Mode Select. Setting this bit freezes the CPU, Timer 0, 1, and 2, and the USARTs; other peripherals remain bit 0 active. This bit will always be read as a 0. All digital pins and DACs keep their respective output values. Internal REF remains unchanged. Exit with AI (A6h) and EWU (C6h) interrupts. 50

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Timer/Counter Control (TCON) 7 6 5 4 3 2 1 0 Reset Value SFR 88h TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h TF1 Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined by the current mode. bit 7 This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine. 0: No Timer 1 overflow has been detected. 1: Timer 1 has overflowed its maximum count. TR1 Timer 1 Run Control. This bit enables/disables the operation of Timer 1. Halting this timer preserves the current bit 6 count in TH1, TL1. 0: Timer is halted. 1: Timer is enabled. TF0 Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its maximum count as defined by the current mode. bit 5 This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine. 0: No Timer 0 overflow has been detected. 1: Timer 0 has overflowed its maximum count. TR0 Timer 0 Run Control. This bit enables/disables the operation of Timer 0. Halting this timer preserves the current bit 4 count in TH0, TL0. 0: Timer is halted. 1: Timer is enabled. IE1 Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined by IT1 is detected. If IT1 = 1, this bit bit 3 will remain set until cleared in software or the start of the External Interrupt 1 service routine. If IT1 = 0, this bit will inversely reflect the state of the INT1 pin. IT1 Interrupt 1 Type Select. This bit selects whether the INT1 pin will detect edge or level triggered interrupts. bit 2 0: INT1 is level-triggered. 1: INT1 is edge-triggered. IE0 Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined by IT0 is detected. If IT0 = 1, this bit bit 1 will remain set until cleared in software or the start of the External Interrupt 0 service routine. If IT0 = 0, this bit will inversely reflect the state of the INT0 pin. IT0 Interrupt 0 Type Select. This bit selects whether the INT0 pin will detect edge or level triggered interrupts. bit 0 0: INT0 is level-triggered. 1: INT0 is edge-triggered. 51

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Timer Mode Control (TMOD) 7 6 5 4 3 2 1 0 Reset Value TIMER 1 TIMER 0 SSFFRR 8899hh 0000hh GATE C/T M1 M0 GATE C/T M1 M0 GATE Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment. bit 7 0: Timer 1 will clock when TR1 = 1, regardless of the state of pin INT1. 1: Timer 1 will clock only when TR1 = 1 and pin INT1 = 1. C/T Timer 1 Counter/Timer Select. bit 6 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on T1 pin when TR1 (TCON.6, SFR 88h) is 1. M1, M0 Timer 1 Mode Select. These bits select the operating mode of Timer 1. bits 5−4 M1 M0 MODE 0 0 Mode 0: 8-bit counter with 5-bit prescale. 0 1 Mode 1: 16 bits. 1 0 Mode 2: 8-bit counter with auto reload. 1 1 Mode 3: Timer 1 is halted, but holds its count. GATE Timer 0 Gate Control. This bit enables/disables the ability of Timer 0 to increment. bit 3 0: Timer 0 will clock when TR0 = 1, regardless of the state of pin INT0 (software control). 1: Timer 0 will clock only when TR0 = 1 and pin INT0 = 1 (hardware control). C/T Timer 0 Counter/Timer Select. bit 2 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on pin T0 when TR0 (TCON.4, SFR 88h) is 1. M1, M0 Timer 0 Mode Select. These bits select the operating mode of Timer 0. bits 1−0 M1 M0 MODE 0 0 Mode 0: 8-bit counter with 5-bit prescale. 0 1 Mode 1: 16 bits. 1 0 Mode 2: 8-bit counter with auto reload. 1 1 Mode 3: Two 8-bit counters. Timer 0 LSB (TL0) 7 6 5 4 3 2 1 0 Reset Value SFR 8Ah TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0 00h TL0.7−0 Timer 0 LSB. This register contains the least significant byte of Timer 0. bits 7−0 Timer 1 LSB (TL1) 7 6 5 4 3 2 1 0 Reset Value SFR 8Bh TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0 00h TL1.7−0 Timer 1 LSB. This register contains the least significant byte of Timer 1. bits 7−0 52

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Timer 0 MSB (TH0) 7 6 5 4 3 2 1 0 Reset Value SFR 8Ch TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 00h TH0.7−0 Timer 0 MSB. This register contains the most significant byte of Timer 0. bits 7−0 Timer 1 MSB (TH1) 7 6 5 4 3 2 1 0 Reset Value SFR 8Dh TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 00h TH1.7−0 Timer 1 MSB. This register contains the most significant byte of Timer 1. bits 7−0 Clock Control (CKCON) 7 6 5 4 3 2 1 0 Reset Value SFR 8Eh 0 0 T2M T1M T0M MD2 MD1 MD0 01h T2M Timer 2 Clock Select. This bit controls the division of the system clock that drives Timer 2. This bit has no effect when bit 5 the timer is in baud rate generator or clock output modes. Clearing this bit to 0 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 2 uses a divide by 12 of the crystal frequency. 1: Timer 2 uses a divide by 4 of the crystal frequency. T1M Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer 1. Clearing this bit to 0 bit 4 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 1 uses a divide by 12 of the crystal frequency. 1: Timer 1 uses a divide by 4 of the crystal frequency. T0M Timer 0 Clock Select. This bit controls the division of the system clock that drives Timer 0. Clearing this bit to 0 bit 3 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 0 uses a divide by 12 of the crystal frequency. 1: Timer 0 uses a divide by 4 of the crystal frequency. MD2, MD1, MD0 Stretch MOVX Select 2−0. These bits select the time by which external MOVX cycles are to be stretched. This bits 2−0 allows slower memory or peripherals to be accessed without using ports or manual software intervention. The width of the RD or WR strobe will be stretched by the specified interval, which will be transparent to the software except for the increased time to execute the MOVX instruction. All internal MOVX instructions on devices containing MOVX SRAM are performed at the 2 instruction cycle rate. STRETCH RD or WR STROBE RD or WR STROBE MD2 MD1 MD0 VALUE MOVX DURATION WIDTH (SYS CLKs) WIDTH ((cid:1)s) at 12MHz 0 0 0 0 2 Instruction Cycles 2 0.167 0 0 1 1 3 Instruction Cycles (default) 4 0.333 0 1 0 2 4 Instruction Cycles 8 0.667 0 1 1 3 5 Instruction Cycles 12 1.000 1 0 0 4 6 Instruction Cycles 16 1.333 1 0 1 5 7 Instruction Cycles 20 1.667 1 1 0 6 8 Instruction Cycles 24 2.000 1 1 1 7 9 Instruction Cycles 28 2.333 53

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Memory Write Select (MWS) 7 6 5 4 3 2 1 0 Reset Value SFR 8Fh 0 0 0 0 0 0 0 MXWS 00h MXWS MOVX Write Select. This allows writing to the internal Flash Program Memory. bit 0 0: MOVX operations will access Data Memory (default). 1: MOVX operations will access Program Memory. Write operations can be inhibited by the PML or RSL bits in HCR0. Port 1 (P1) 7 6 5 4 3 2 1 0 Reset Value P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 SFR 90h FFh INT5/SCK/SCL INT4/MISO/SDA INT3/MOSI INT2/SS TXD1 RXD1 T2EX T2 P1.7−0 General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all the pins have an bits 7−0 alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 1 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. To use the alternate function, set the appropriate mode in P1DDRL (SFR AEh), P1DDRH (SFR AFh). INT5/SCK/SCL External Interrupt 5. A falling edge on this pin will cause an external interrupt 5 if enabled. bit 7 SPI Clock. The master clock for SPI data transfers. Serial Clock. The serial clock for I2C data transfers (MSC1211 and MSC1213 only). INT4/MISO/SDA External Interrupt 4. A rising edge on this pin will cause an external interrupt 4 if enabled. bit 6 Master In Slave Out. For SPI data transfers, this pin receives data for the master and transmits data from the slave. SDA. For I2C data transfers, this pin is the data line (MSC1211 and MSC1213 only). NT3/MOSI External Interrupt 3. A falling edge on this pin will cause an external interrupt 3 if enabled. bit 5 Master Out Slave In. For SPI data transfers, this pin transmits master data and receives slave data. INT2/SS External Interrupt 2. A rising edge on this pin will cause an external interrupt 2 if enabled. bit 4 Slave Select. During SPI operation, this pin provides the select signal for the slave device. TXD1 Serial Port 1 Transmit. This pin transmits the serial Port 1 data in serial port modes 1, 2, 3, and emits the bit 3 synchronizing clock in serial port mode 0. RXD1 Serial Port 1 Receive. This pin receives the serial Port 1 data in serial port modes 1, 2, 3, and is a bidirectional data bit 2 transfer pin in serial port mode 0. T2EX Timer 2 Capture/Reload Trigger. A 1 to 0 transition on this pin will cause the value in the T2 registers to be bit 1 transferred into the capture registers if enabled by EXEN2 (T2CON.3, SFR C8h). When in auto-reload mode, a 1 to 0 transition on this pin will reload the Timer 2 registers with the value in RCAP2L and RCAP2H if enabled by EXEN2 (T2CON.3, SFR C8h). T2 Timer 2 External Input. A 1 to 0 transition on this pin will cause Timer 2 to increment or decrement depending on bit 0 the timer configuration. 54

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 External Interrupt Flag (EXIF) 7 6 5 4 3 2 1 0 Reset Value SFR 91h IE5 IE4 IE3 IE2 1 0 0 0 08h IE5 External Interrupt 5 Flag. This bit will be set when a falling edge is detected on INT5. This bit must be cleared bit 7 manually by software. Setting this bit in software will cause an interrupt if enabled. IE4 External Interrupt 4 Flag. This bit will be set when a rising edge is detected on INT4. This bit must be cleared bit 6 manually by software. Setting this bit in software will cause an interrupt if enabled. IE3 External Interrupt 3 Flag. This bit will be set when a falling edge is detected on INT3. This bit must be cleared bit 5 manually by software. Setting this bit in software will cause an interrupt if enabled. IE2 External Interrupt 2 Flag. This bit will be set when a rising edge is detected on INT2. This bit must be cleared bit 4 manually by software. Setting this bit in software will cause an interrupt if enabled. Memory Page (MPAGE) 7 6 5 4 3 2 1 0 Reset Value SFR 92h 00h MPAGE The 8051 uses Port 2 for the upper 8 bits of the external Data Memory access by MOVX A@Ri and MOVX @Ri, A bits 7−0 instructions. The MSC1211/12/13/14 uses register MPAGE instead of Port 2. To access external Data Memory using the MOVX A@Ri and MOVX @Ri, A instructions, the user should preload the upper byte of the address into MPAGE (versus preloading into P2 for the standard 8051). Configuration Address (CADDR) (write-only) 7 6 5 4 3 2 1 0 Reset Value SFR 93h 00h CADDR Configuration Address. This register supplies the address for reading bytes in the 128 bytes of Flash bits 7−0 Configuration Memory. It is recommended that faddr_data_read be used when accessing Configuration Memory. CAUTION:If this register is written to while executing from Flash Memory, the CDATA register will be incorrect. Configuration Data (CDATA) 7 6 5 4 3 2 1 0 Reset Value SFR 94h 00h CDATA Configuration Data. This register will contain the data in the 128 bytes of Flash Configuration Memory that bits 7−0 is located at the last written address in the CADDR register. This is a read-only register. Memory Control (MCON) 7 6 5 4 3 2 1 0 Reset Value SFR 95h BPSEL 0 0 — — — — RAMMAP 00h BPSEL Breakpoint Address Selection bit 7 Write: Select one of two Breakpoint registers: 0 or 1. 0: Select breakpoint register 0. 1: Select breakpoint register 1. Read: Provides the Breakpoint register that created the last interrupt: 0 or 1. RAMMAP Memory Map 1kB extended SRAM. bit 0 0: Address is: 0000h—03FFh (default) (Data Memory) 1: Address is 8400h—87FFh (Data and Program Memory) 55

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Serial Port 0 Control (SCON0) 7 6 5 4 3 2 1 0 Reset Value SFR 98h SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00h SM0−2 Serial Port 0 Mode. These bits control the mode of serial Port 0. Modes 1, 2, and 3 have 1 start and 1 stop bit in bits 7−5 addition to the 8 or 9 data bits. MODE SM0 SM1 SM2 FUNCTION LENGTH PERIOD 0 0 0 0 Synchronous 8 bits 12 pCLK(1) 0 0 0 1 Synchronous 8 bits 4 pCLK(1) 1(2) 0 1 0 Asynchronous 10 bits Timer 1 or 2 Baud Rate Equation 1(2) 0 1 1 Valid Stop Required(3) 10 bits Timer 1 Baud Rate Equation 2 1 0 0 Asynchronous 11 bits 64 pCLK(1) (SMOD = 0) 32 pCLK(1) (SMOD = 1) 2 1 0 1 Asynchronous with Multiprocessor Communication(4) 11 bits 64 pCLK(1) (SMOD = 0) 32 pCLK(1) (SMOD = 1) 3(2) 1 1 0 Asynchronous 11 bits Timer 1 or 2 Baud Rate Equation 3(2) 1 1 1 Asynchronous with Multiprocessor Communication(4) 11 bits Timer 1 or 2 Baud Rate Equation (1)pCLK will be equal to tCLK, except that pCLK will stop for Idle mode. (2)For modes 1 and 3, the selection of Timer 1 or 2 for baud rate is specified via the T2CON (C8h) register. (3)RI_0 will only be activated when a valid STOP is received. (4)RI_0 will not be activated if bit 9 = 0. REN_0 Receive Enable. This bit enables/disables the serial Port 0 received shift register. bit 4 0: Serial Port 0 reception disabled. 1: Serial Port 0 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0). TB8_0 9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 0 modes 2 and 3. bit 3 RB8_0 9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 0 modes bit 2 2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0. TI_0 Transmitter Interrupt Flag. This bit indicates that data in the serial Port 0 buffer has been completely shifted out. In serial bit 1 port mode 0, TI_0 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last data bit. This bit must be manually cleared by software. RI_0 Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 0 buffer. In serial bit 0 port mode 0, RI_0 is set at the end of the 8th bit. In serial port mode 1, RI_0 is set after the last sample of the incoming stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last sample of RB8_0. This bit must be manually cleared by software. Serial Data Buffer 0 (SBUF0) 7 6 5 4 3 2 1 0 Reset Value SFR 99h 00h SBUF0 Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and receive bits 7−0 buffers are separate registers, but both are addressed at this location. 56

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 SPI Control (SPICON). Any change resets the SPI interface, counters, and pointers. 7 6 5 4 3 2 1 0 Reset Value SFR 9Ah SCK2 SCK1 SCK0 FIFO ORDER MSTR CPHA CPOL 00h SCK SCK Selection. Selection of t divider for generation of SCK in Master mode. CLK bits 7−5 SCK2 SCK1 SCK0 SCK PERIOD 0 0 0 t /2 CLK 0 0 1 t /4 CLK 0 1 0 t /8 CLK 0 1 1 t /16 CLK 1 0 0 t /32 CLK 1 0 1 t /64 CLK 1 1 0 t /128 CLK 1 1 1 t /256 CLK FIFO Enable FIFO in On-Chip Indirect Memory. bit 4 0: Both transmit and receive are double buffers 1: Circular FIFO used for transmit and receive bytes ORDER Set Bit Order for Transmit and Receive. bit 3 0: Most Significant Bits First 1: Least Significant Bits First MSTR SPI Master Mode. bit 2 0: Slave Mode 1: Master Mode CPHA Serial Clock Phase Control. bit 1 0: Valid data starting from half SCK period before the first edge of SCK 1: Valid data starting from the first edge of SCK CPOL Serial Clock Polarity. bit 0 0: SCK idle at logic low 1: SCK idle at logic high 57

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 I2C Control (I2CCON) (Available only on the MSC1211 and MSC1213) 7 6 5 4 3 2 1 0 Reset Value SFR 9Ah START STOP ACK 0 FAST MSTR SCLS FILEN 00h START Start Condition (Master mode). bit 7 Read: Current status of start condition or repeated start condition. Write: When operating as a master, a start condition is transmitted when the START bit is set to 1. During a data transfer, if the START bit is set, a repeated start is transmitted after the current data transfer is complete. If no transfer is in progress when the START and STOP bits are set simultaneously, a START will be followed by a STOP. STOP Stop Condition (Master mode). bit 6 Read: Current status of stop condition. Write: Setting STOP to logic 1 causes a stop condition to be transmitted. When a stop condition is received, hardware clears STOP to logic 0. If both START and STOP are set during a transfer, a stop condition is transmitted followed by a start condition. ACK Acknowledge. Defines the ACK/NACK generation from the master/slave receiver during the acknowledge cycle. bit 5 0: A NACK (high level on SDA) is returned during the acknowledge cycle. 1: An ACK (low level on SDA) is returned during the acknowledge cycle. In slave transmit mode, 0 = Current byte is last byte, 1 = More to follow. 0 Always set this value to zero. bit 4 FAST Fast Mode Enable. bit 3 0: Standard Mode (100kHz) 1: Fast Mode (400kHz) MSTR SPI Master Mode. bit 2 0: Slave Mode 1: Master Mode SCLS Clock Stretch. bit 1 0: No effect 1: Release the clock line. For the slave mode, the clock is stretched for each data transfer. This bit releases the clock. FILEN Filter Enable. 50ns glitch filter. bit 0 0: Filter disabled 1: Filter enabled SPI Data (SPIDATA) / I2C Data (I2CDATA) 7 6 5 4 3 2 1 0 Reset Value SFR 9Bh 00h SPIDATA SPI Data. Data for SPI is read from or written to this location. The SPI transmit and receive buffers are bits 7−0 separate registers, but both are addressed at this location. Read to clear the receive interrupt and write to clear the transmit interrupt. I2CDATA I2C Data . (MSC1211 and MSC1213 only.) Data for I2C is read from or written to this location. The I2C transmit and receive buffers are separate registers, but both are addressed at this location. Writing to this register bits 7−0 starts transmission. In Master mode, reading this register starts a Master read cycle. 58

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 SPI Receive Control (SPIRCON) 7 6 5 4 3 2 1 0 Reset Value RXCNT7 RXCNT2 RXCNT1 RXCNT0 SFR 9Ch RXCNT6 RXCNT5 RXCNT4 RXCNT3 00h RXFLUSH RXIRQ2 RXIRQ1 RXIRQ0 RXCNT Receive Counter. Read-only bits which read the number of bytes in the receive buffer (0 to 128). bits 7−0 RXFLUSH Flush Receive FIFO. Write-only. bit 7 0: No Action 1: SPI Receive Buffer Set to Empty RXIRQ Read IRQ Level. Write-only. bits 2−0 000 Generate IRQ when Receive Count = 1 or more. 001 Generate IRQ when Receive Count = 2 or more. 010 Generate IRQ when Receive Count = 4 or more. 011 Generate IRQ when Receive Count = 8 or more. 100 Generate IRQ when Receive Count = 16 or more. 101 Generate IRQ when Receive Count = 32 or more. 110 Generate IRQ when Receive Count = 64 or more. 111 Generate IRQ when Receive Count = 128 or more. I2C GM (I2CGM) (Available only on the MSC1211 and MSC1213) 7 6 5 4 3 2 1 0 Reset Value SFR 9Ch GCMEN 00h GCMEN General Call/Multiple Master Enable. Write-only. bit 7 Slave mode: 0 = General call ignored, 1 = General call will be detected Master mode: 0 = Single master, 1 = Multiple master mode 59

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 SPI Transmit Control (SPITCON) 7 6 5 4 3 2 1 0 Reset Value TXCNT7 TXCNT5 TXCNT4 TXCNT3 TXCNT2 TXCNT1 TXCNT0 SFR 9Dh TXCNT6 00h TXFLUSH CLK_EN DRV_DLY DRV_EN TXIRQ2 TXIRQ1 TXIRQ0 TXCNT Transmit Counter. Read-only bits which read the number of bytes in the transmit buffer (0 to 128). bits 7−0 TXFLUSH Flush Transmit FIFO. This bit is write-only. When set, the SPI transmit pointer is set equal to the FIFO Output pointer. bit 7 This bit is 0 for a read operation. CLK_EN SCLK Driver Enable. bit 5 0: Disable SCLK Driver (Master Mode) 1: Enable SCLK Driver (Master Mode) DRV_DLY Drive Delay (refer to DRV_EN bit). bit 4 0: Drive Output Immediately 1: Drive Output After Current Byte Transfer DRV_EN Drive Enable. bit 3 DRV_DLY DRV_EN MOSI or MISO OUTPUT CONTROL 0 0 Tristate immediately. 0 1 Drive immediately. 1 0 Tristate after the current byte transfer. 1 1 Drive after the current byte transfer. TXIRQ Transmit IRQ Level. Write-only bits. bits 2−0 000 Generate IRQ when Transmit Count = 1 or less. 001 Generate IRQ when Transmit Count = 2 or less. 010 Generate IRQ when Transmit Count = 4 or less. 011 Generate IRQ when Transmit Count = 8 or less. 100 Generate IRQ when Transmit Count = 16 or less. 101 Generate IRQ when Transmit Count = 32 or less. 110 Generate IRQ when Transmit Count = 64 or less. 111 Generate IRQ when Transmit Count = 128 or less. 60

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 I2C Status (I2CSTAT) (Available only on the MSC1211 and MSC1213) 7 6 5 4 3 2 1 0 Reset Value STAT7 STAT6 STAT5 STAT4 STAT3 0 0 0 SFR 9Dh 00h SCKD7/SAE SCKD6/SA6 SCKD5/SA5 SCKD4/SA4 SCKD3/SA3 SCKD2/SA2 SCKD1/SA1 SCKD0/SA0 STAT7−3 Status Code. Read-only. Reading this register clears the status interrupt. bit 7−3 STATUS CODE STATUS OF THE HARDWARE MODE 0x08 START condition transmitted. Master 0x10 Repeated START condition transmitted. Master 0x18 Slave address + W transmitted and ACK received. Master 0x20 Slave address + W transmitted and NACK received. Master 0x28 Data byte transmitted and ACK received. Master 0x30 Data byte transmitted and NACK received. Master 0x38 Arbitration lost. Master 0x40 Slave address + R transmitted and ACK received. Master 0x48 Slave address + R transmitted and NACK received. Master 0x50 Data byte received and ACK transmitted. Master 0x58 Data byte received and NACK transmitted. Master 0x60 I2Cs slave address + W received and ACK transmitted. Slave 0x70 General call received and ACK transmitted. Slave 0x80 Previously addressed as slave, data byte received and ACK transmitted. Slave 0x88 Previously addressed as slave, data byte received and NACK transmitted. Slave 0x90 Previously addressed with GC, data byte received and ACK transmitted. Slave 0x98 Previously addressed with GC, data byte received and NACK transmitted. Slave 0xA0 A STOP or repeated START received when addressed as slave or GC. Slave 0xA8 I2Cs slave address + R received and ACK transmitted. Slave 0xB8 Previously addressed as slave, data byte transmitted and ACK received. Slave 0xC0 Previously addressed as slave, data byte transmitted and NACK received. Slave 0xC8 Previously addressed as slave, last data byte transmitted. Slave SCKD7−0 Serial Clock Divisor. Write-only, master mode. bit 7−0 The frequency of the SCL line is set equal to Sysclk/[2 • (SCKD + 1)]. The minimum value for SCKD is 3. SAE Slave Address Enable. Write-only, slave mode. bit 7 In slave mode, if this is set, address recognition is enabled. SA6−0 Slave Address. Write-only, slave mode. bit 6−0 The address of this device is used in slave mode for address recognition. 61

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 I2C Start (I2CSTART) (Available only on the MSC1211 and MSC1213) 7 6 5 4 3 2 1 0 Reset Value SFR 9Eh 80h I2CSTART I2C Start. Write-only. When any value is written to this register, the I2C system is reset; that is, the counters bits 7−0 and state machines will go back to the initial state. So, in multi-master mode when arbitration is lost, then the I2C should be reset so that the counters and finite state machines (FSMs) are brought back to the idle state. SPI Buffer Start Address (SPISTART) 7 6 5 4 3 2 1 0 Reset Value SFR 9Eh 1 80h SPISTART SPI FIFO Start Address. Write-only. This specifies the start address of the SPI data buffer. This is a circular FIFO bits 6−0 that is located in the 128 bytes of indirect RAM. The FIFO starts at this address and ends at the address specified in SPIEND. Must be less than SPIEND. Writing clears SPI transmit and receive counters. SPITP SPI Transmit Pointer. Read-only. This is the FIFO address for SPI transmissions. This is where the next byte will bits 6−0 be written into the byte will be written into the SPI FIFO buffer. This pointer increments after each write to the SPI Data register unless that would make it equal to the SPI Receive pointer. SPI Buffer End Address (SPIEND) 7 6 5 4 3 2 1 0 Reset Value SFR 9Fh 1 80h SPIEND SPI FIFO End Address. Write-only. This specifies the end address of the SPI data FIFO. This is a circular buffer that bits 6−0 is located in the 128 bytes of indirect RAM. The buffer starts at SPISTART and ends at this address. SPIRP SPI Receive Pointer. Read-only. This is the FIFO address for SPI received bytes. This is the location of the next byte bits 6−0 to be read from the SPI FIFO. This increments with each read from the SPI Data register until the RxCNT is zero. Port 2 (P2) 7 6 5 4 3 2 1 0 Reset Value SFR A0h FFh P2 Port 2. This port functions as an address bus during external memory access, and as a general-purpose I/O port. bits 7−0 During external memory cycles, this port will contain the MSB of the address. Whether Port 2 is used as general-purpose I/O or for external memory access is determined by the Flash Configuration Register (HCR1.0). 62

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 PWM Control (PWMCON) 7 6 5 4 3 2 1 0 Reset Value SFR A1h — — PPOL PWMSEL SPDSEL TPCNTL2 TPCNTL1 TPCNTL0 00h PPOL Period Polarity. Specifies the starting level of the PWM pulse. bit 5 0: ON Period. PWM Duty register programs the ON period. 1: OFF Period. PWM Duty register programs the OFF period. PWMSEL PWM Register Select. Select which 16-bit register is accessed by PWMLOW/PWMHI. bit 4 0: Period (must be 0 for TONE mode) 1: Duty SPDSEL Speed Select. bit 3 0: 1MHz (the USEC Clock) 1: SYSCLK TPCNTL Tone Generator/Pulse Width Modulation Control. bits 2−0 TPCNTL2 TPCNTL1 TPCNTL0 MODE 0 0 0 Disable (default) 0 0 1 PWM 0 1 1 TONE—Square 1 1 1 TONE—Staircase Tone Low (TONELOW) /PWM Low (PWMLOW) 7 6 5 4 3 2 1 0 Reset Value PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 SFR A2h 00h TDIV7 TDIV6 TDIV5 TDIV4 TDIV3 TDIV2 TDIV1 TDIV0 PWMLOW Pulse Width Modulator Low Bits. These 8 bits are the least significant 8 bits of the PWM register. bits 7−0 TDIV7−0 Tone Divisor. The low order bits that define the half-time period. For staircase mode the output is high impedance bits 7−0 for the last 1/4 of this period. Tone High (TONEHI)/PWM High (PWMHI) 7 6 5 4 3 2 1 0 Reset Value PWM15 PWM14 PWM13 PWM12 PWM11 PWM10 PWM9 PWM8 SFR A3h 00h TDIV15 TDIV14 TDIV13 TDIV12 TDIV11 TDIV10 TDIV9 TDIV8 PWMHI Pulse Width Modulator High Bits. These 8 bits are the high order bits of the PWM register. bits 7−0 TDIV15−8 Tone Divisor. The high order bits that define the half time period. For staircase mode the output is high impedance bits 7−0 for the last 1/4 of this period. 63

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Auxiliary Interrupt Poll (AIPOL) 7 6 5 4 3 2 1 0 Reset Value RD SFR A4h ESEC ESUM EADC EMSEC ESPIT ESPIR/EI2C EALV EDLVB 00h WR RDSEL 00h Auxiliary interrupts are enabled by EICON.4 (SFR D8h); other interrupts are enabled by the IE and EIE registers. ESEC Enable Seconds Timer Interrupt (lowest priority auxiliary interrupt). Read-only. bit 7 AIPOL.RDSEL = 1: Read: Current value of Seconds Timer Interrupt before masking. AIPOL.RDSEL = 0: Read: Value of ESEC bit. ESUM Enable Summation Interrupt. Read-only. bit 6 AIPOL.RDSEL = 1: Read: Current value of Summation Interrupt before masking. AIPOL.RDSEL = 0: Read: Value of ESUM bit. EADC Enable ADC Interrupt. Read-only. bit 5 AIPOL.RDSEL = 1: Read: Current value of ADC Interrupt before masking. AIPOL.RDSEL = 0: Read: Value of EADC bit. EMSEC Enable Millisecond System Timer Interrupt. Read-only. bit 4 AIPOL.RDSEL = 1: Read: Current value of Millisecond System Timer Interrupt before masking. AIPOL.RDSEL = 0: Read: Value of EMSEC bit. ESPIT Enable SPI Transmit Interrupt. Read-only. bit 3 AIPOL.RDSEL = 1: Read: Current value of Enable SPI Transmit Interrupt before masking. AIPOL.RDSEL = 0: Read: Value of ESPIT bit. ESPIR/EI2C Enable SPI Receive Interrupt. Enable I2C Status Interrupt (I2C available only on the MSC1213). Read-only. bit 2 AIPOL.RDSEL = 1: Read: Current value of Enable SPI Receive Interrupt or I2C Status Interrupt before masking. AIPOL.RDSEL = 0: Read: Value of ESPIR/EI2C bit. EALV Enable Analog Low Voltage Interrupt. Read-only. bit 1 AIPOL.RDSEL = 1: Read: Current value of Enable Analog Low Voltage Interrupt before masking. AIPOL.RDSEL = 0: Read: Value of EALV bit. EDLVB Enable Digital Low Voltage or Breakpoint Interrupt (highest priority auxiliary interrupt). Read-only. bit 0 AIPOL.RDSEL = 1: Read: Current value of Enable Digital Low Voltage or Breakpoint Interrupt before masking. AIPOL.RDSEL = 0: Read: Value of EDLVB bit. RDSEL Read Select. Write-only. bit 0 AIPOL.RDSEL = 1: Read state for AIE and AIPOL registers. Reading AIPOL register gives current value of Auxiliary interrupts before masking. Reading AIE register gives value of AIE register contents. AIPOL.RDSEL = 0: Read state for AIE and AIPOL registers. Reading AIPOL register gives value of AIE register contents. Reading AIE register gives current value of Auxiliary interrupts before masking. 64

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Pending Auxiliary Interrupt (PAI) 7 6 5 4 3 2 1 0 Reset Value SFR A5h 0 0 0 0 PAI3 PAI2 PAI1 PAI0 00h PAI3−0 Pending Auxiliary Interrupt. The results of this register can be used as an index to vector to the bits 3−0 appropriate interrupt routine. All of these interrupts vector through address 0033h. PAI3 PAI2 PAI1 PAI0 AUXILIARY INTERRUPT STATUS 0 0 0 0 No Pending Auxiliary IRQ 0 0 0 1 Digital Low Voltage IRQ Pending 0 0 1 0 Analog Low Voltage IRQ Pending 0 0 1 1 SPI Receive IRQ Pending. I2C Status Pending. 0 1 0 0 SPI Transmit IRQ Pending. 0 1 0 1 One Millisecond System Timer IRQ Pending. 0 1 1 0 Analog-to-Digital Conversion IRQ Pending. 0 1 1 1 Accumulator IRQ Pending. 1 0 0 0 One Second System Timer IRQ Pending. 65

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Auxiliary Interrupt Enable (AIE) 7 6 5 4 3 2 1 0 Reset Value SFR A6h ESEC ESUM EADC EMSEC ESPIT ESPIR/EI2C EALV EDLVB 00h Auxiliary interrupts are enabled by EICON.4 (SFR D8h); other interrupts are enabled by the IE and EIE registers. ESEC Enable Seconds Timer Interrupt (lowest priority auxiliary interrupt). bit 7 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: When AIPOL.RDSEL = 0: Current value of Seconds Timer Interrupt before masking. When AIPOL.RDSEL = 1: Value of ESEC bit. ESUM Enable Summation Interrupt. bit 6 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: When AIPOL.RDSEL = 0: Current value of Summation Interrupt before masking. When AIPOL.RDSEL = 1: Value of ESUM bit. EADC Enable ADC Interrupt. bit 5 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: When AIPOL.RDSEL = 0: Current value of ADC Interrupt before masking. When AIPOL.RDSEL = 1: Value of EADC bit. EMSEC Enable Millisecond System Timer Interrupt. bit 4 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: When AIPOL.RDSEL = 0: Current value of Millisecond System Timer Interrupt before masking. When AIPOL.RDSEL = 1: Value of EMSEC bit. ESPIT Enable SPI Transmit Interrupt. bit 3 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: When AIPOL.RDSEL = 0: Current value of SPI Transmit Interrupt before masking. When AIPOL.RDSEL = 1: Value of ESPIT bit. ESPIR/EI2C Enable SPI Receive Interrupt. Enable I2C Status Interrupt. (I2C available only on the MSC1213.) bit 2 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: When AIPOL.RDSEL = 0: Current value of SPI Receive Interrupt or I2C Status Interrupt before masking. When AIPOL.RDSEL = 1: Value of ESPIR/EI2C bit. EALV Enable Analog Low Voltage Interrupt. bit 1 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: When AIPOL.RDSEL = 0: Current value of Analog Low Voltage Interrupt before masking. When AIPOL.RDSEL = 1: Value of EALV bit. EDLVB Enable Digital Low Voltage or Breakpoint Interrupt (highest priority auxiliary interrupt). bit 0 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: When AIPOL.RDSEL = 0: Current value of Digital Low Voltage or Breakpoint Interrupt before masking. When AIPOL.RDSEL = 1: Value of EDLVB bit. 66

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Auxiliary Interrupt Status (AISTAT) 7 6 5 4 3 2 1 0 Reset Value SFR A7h SEC SUM ADC MSEC SPIT SPIR/I2CSI ALVD DLVD 00h SEC Second System Timer Interrupt Status Flag (lowest priority AI). bit 7 0: SEC interrupt inactive or masked. 1: SEC Interrupt active. SUM Summation Register Interrupt Status Flag. bit 6 0: SUM interrupt inactive or masked (if active, it is set inactive by reading the lowest byte of the Summation register). 1: SUM interrupt active. ADC ADC Interrupt Status Flag. bit 5 0: ADC interrupt inactive or masked (If active, it is set inactive by reading the lowest byte of the Data Output Register). 1: ADC interrupt active (If active no new data will be written to the Data Output Register). MSEC Millisecond System Timer Interrupt Status Flag. bit 4 0: MSEC interrupt inactive or masked. 1: MSEC interrupt active. SPIT SPI Transmit Interrupt Status Flag. bit 3 0: SPI transmit interrupt inactive or masked. 1: SPI transmit interrupt active. SPIR/I2CSI SPI Receive Interrupt Status Flag. I2C Status Interrupt. (I2C available only on the MSC1213.) bit 2 0: SPI receive or I2CSI interrupt inactive or masked. 1: SPI receive or I2CSI interrupt active. ALVD Analog Low Voltage Detect Interrupt Status Flag. bit 1 0: ALVD interrupt inactive or masked. 1: ALVD interrupt active. DLVD Digital Low Voltage Detect or Breakpoint Interrupt Status Flag (highest priority AI). bit 0 0: DLVD interrupt inactive or masked. 1: DLVD interrupt active. 67

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Interrupt Enable (IE) 7 6 5 4 3 2 1 0 Reset Value SFR A8h EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00h EA Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6h). bit 7 0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register. 1: Enable all individual interrupt masks. Individual interrupts in this register will occur if enabled. ES1 Enable Serial Port 1 Interrupt. This bit controls the masking of the serial Port 1 interrupt. bit 6 0: Disable all serial Port 1 interrupts. 1: Enable interrupt requests generated by the RI_1 (SCON1.0, SFR C0h) or TI_1 (SCON1.1, SFR C0h) flags. ET2 Enable Timer 2 Interrupt. This bit controls the masking of the Timer 2 interrupt. bit 5 0: Disable all Timer 2 interrupts. 1: Enable interrupt requests generated by the TF2 flag (T2CON.7, SFR C8h). ES0 Enable Serial port 0 interrupt. This bit controls the masking of the serial Port 0 interrupt. bit 4 0: Disable all serial Port 0 interrupts. 1: Enable interrupt requests generated by the RI_0 (SCON0.0, SFR 98h) or TI_0 (SCON0.1, SFR 98h) flags. ET1 Enable Timer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt. bit 3 0: Disable Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag (TCON.7, SFR 88h). EX1 Enable External Interrupt 1. This bit controls the masking of external interrupt 1. bit 2 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the INT1 pin. ET0 Enable Timer 0 Interrupt. This bit controls the masking of the Timer 0 interrupt. bit 1 0: Disable all Timer 0 interrupts. 1: Enable interrupt requests generated by the TF0 flag (TCON.5, SFR 88h). EX0 Enable External Interrupt 0. This bit controls the masking of external interrupt 0. bit 0 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the INT0 pin. 68

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Breakpoint Control (BPCON) 7 6 5 4 3 2 1 0 Reset Value SFR A9h BP 0 0 0 0 0 PMSEL EBP 00h Writing to this register sets the breakpoint condition specified by MCON, BPL, and BPH. BP Breakpoint Interrupt. This bit indicates that a break condition has been recognized by a hardware breakpoint register(s). bit 7 Read: Status of Breakpoint Interrupt. Will indicate a breakpoint match for any of the breakpoint registers. Write: 0: No effect. 1: Clear Breakpoint 1 for breakpoint register selected by MCON (SFR 95h). PMSEL Program Memory Select. Write this bit to select memory for address breakpoints of register selected in bit 1 MCON (SFR 95h). 0: Break on address in Data Memory. 1: Break on address in Program Memory. EBP Enable Breakpoint. This bit enables this breakpoint register. Address of breakpoint register selected by bit 0 MCON (SFR 95h). 0: Breakpoint disabled. 1: Breakpoint enabled. Breakpoint Low (BPL) Address for BP Register Selected in MCON (95h) 7 6 5 4 3 2 1 0 Reset Value SFR AAh BPL.7 BPL.6 BPL.5 BPL.4 BPL.3 BPL.2 BPL.1 BPL.0 00h BPL.7−0 Breakpoint Low Address. The low 8 bits of the 16-bit breakpoint address. bits 7−0 Breakpoint High Address (BPH) Address for BP Register Selected in MCON (95h) 7 6 5 4 3 2 1 0 Reset Value SFR ABh BPH.7 BPH.6 BPH.5 BPH.4 BPH.3 BPH.2 BPH.1 BPH.0 00h BPH.7−0 Breakpoint High Address. The high 8 bits of the 16-bit breakpoint address. bits 7−0 69

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 0 Data Direction Low (P0DDRL) 7 6 5 4 3 2 1 0 Reset Value SFR ACh P03H P03L P02H P02L P01H P01L P00H P00L 00h P0.3 Port 0 Bit 3 Control. bits 7−6 P03H P03L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P0.2 Port 0 Bit 2 Control. bits 5−4 P02H P02L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P0.1 Port 0 Bit 1 Control. bits 3−2 P01H P01L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P0.0 Port 0 Bit 0 Control. bits 1−0 P00H P00L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE: Port 0 also controlled by EA and Memory Access Control HCR1.EGP0. 70

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 0 Data Direction High (P0DDRH) 7 6 5 4 3 2 1 0 Reset Value SFR ADh P07H P07L P06H P06L P05H P05L P04H P04L 00h P0.7 Port 0 Bit 7 Control. bits 7−6 P07H P07L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P0.6 Port 0 Bit 6 Control. bits 5−4 P06H P06L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P0.5 Port 0 Bit 5 Control. bits 3−2 P05H P05L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P0.4 Port 0 Bit 4 Control. bits 1−0 P04H P04L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE: Port 0 also controlled by EA and Memory Access Control HCR1.EGP0. 71

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 1 Data Direction Low (P1DDRL) 7 6 5 4 3 2 1 0 Reset Value SFR AEh P13H P13L P12H P12L P11H P11L P10H P10L 00h P1.3 Port 1 Bit 3 Control. bits 7−6 P13H P13L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.2 Port 1 Bit 2 Control. bits 5−4 P12H P12L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.1 Port 1 Bit 1 Control. bits 3−2 P11H P11L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.0 Port 1 Bit 0 Control. bits 1−0 P10H P10L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input 72

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 1 Data Direction High (P1DDRH) 7 6 5 4 3 2 1 0 Reset Value SFR AFh P17H P17L P16H P16L P15H P15L P14H P14L 00h P1.7 Port 1 Bit 7 Control. bits 7−6 P17H P17L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.6 Port 1 Bit 6 Control. bits 5−4 P16H P16L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.5 Port 1 Bit 5 Control. bits 3−2 P15H P15L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P1.4 Port 1 Bit 4 Control. bits 1−0 P14H P14L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input 73

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 3 (P3) 7 6 5 4 3 2 1 0 Reset Value P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 SFR B0h FFh RD WR T1 T0 INT1 INT0 TXD0 RXD0 P3.7−0 General-Purpose I/O Port 3. This register functions as a general-purpose I/O port. In addition, all the pins have an bits 7−0 alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 3 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. RD External Data Memory Read Strobe. This pin provides an active low read strobe to an external memory device. bit 7 If Port 0 or Port 2 is selected for external memory in the HCR1 register, this function will be enabled even if a ‘1’ is not written to this latch bit. When external memory is selected, the settings of P3DRRH are ignored. WR External Data Memory Write Strobe. This pin provides an active low write strobe to an external memory device. bit 6 If Port 0 or Port 2 is selected for external memory in the HCR1 register, this function will be enabled even if a ‘1’ is not written to this latch bit. When external memory is selected, the settings of P3DRRH are ignored. T1 Timer/Counter 1 External Input. A 1 to 0 transition on this pin will increment Timer 1. bit 5 T0 Timer/Counter 0 External Input. A 1 to 0 transition on this pin will increment Timer 0. bit 4 INT1 External Interrupt 1. A falling edge/low level on this pin will cause an external interrupt 1 if enabled. bit 3 INT0 External Interrupt 0. A falling edge/low level on this pin will cause an external interrupt 0 if enabled. bit 2 TXD0 Serial Port 0 Transmit. This pin transmits the serial Port 0 data in serial port modes 1, 2, 3, and emits the bit 1 synchronizing clock in serial port mode 0. RXD0 Serial Port 0 Receive. This pin receives the serial Port 0 data in serial port modes 1, 2, 3, and is a bidirectional data bit 0 transfer pin in serial port mode 0. 74

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 2 Data Direction Low (P2DDRL) 7 6 5 4 3 2 1 0 Reset Value SFR B1h P23H P23L P22H P22L P21H P21L P20H P20L 00h P2.3 Port 2 Bit 3 Control. bits 7−6 P23H P23L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P2.2 Port 2 Bit 2 Control. bits 5−4 P22H P22L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P2.1 Port 2 Bit 1 Control. bits 3−2 P21H P21L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P2.0 Port 2 Bit 0 Control. bits 1−0 P20H P20L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE: Port 2 also controlled by EA and Memory Access Control HCR1.EGP23. 75

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 2 Data Direction High (P2DDRH) 7 6 5 4 3 2 1 0 Reset Value SFR B2h P27H P27L P26H P26L P25H P25L P24H P24L 00h P2.7 Port 2 Bit 7 Control. bits 7−6 P27H P27L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P2.6 Port 2 Bit 6 Control. bits 5−4 P26H P26L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P2.5 Port 2 Bit 5 Control. bits 3−2 P25H P25L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P2.4 Port 2 Bit 4 Control. bits 1−0 P24H P24L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE: Port 2 also controlled by EA and Memory Access Control HCR1.EGP23. 76

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 3 Data Direction Low (P3DDRL) 7 6 5 4 3 2 1 0 Reset Value SFR B3h P33H P33L P32H P32L P31H P31L P30H P30L 00h P3.3 Port 3 Bit 3 Control. bits 7−6 P33H P33L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P3.2 Port 3 Bit 2 Control. bits 5−4 P32H P32L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P3.1 Port 3 Bit 1 Control. bits 3−2 P31H P31L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P3.0 Port 3 Bit 0 Control. bits 1−0 P30H P30L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input 77

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 3 Data Direction High (P3DDRH) 7 6 5 4 3 2 1 0 Reset Value SFR B4h P37H P37L P36H P36L P35H P35L P34H P34L 00h P3.7 Port 3 Bit 7 Control. bits 7−6 P37H P37L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE: Port 3.7 also controlled by EA and Memory Access Control HCR1.1. P3.6 Port 3 Bit 6 Control. bits 5−4 P36H P36L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE: Port 3.6 also controlled by EA and Memory Access Control HCR1.1. P3.5 Port 3 Bit 5 Control. bits 3−2 P35H P35L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input P3.4 Port 3 Bit 4 Control. bits 1−0 P34H P34L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input 78

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DAC Low Byte (DACL) 7 6 5 4 3 2 1 0 Reset Value SFR B5h 00h DACL7−0 Least Significant Byte Register for DAC0−3, DAC Control (0 and 2), and DAC Load Control . bits 7−0 NOTE: DAC2 and DAC3 available only on the MSC1211 and MSC1212. DAC High Byte (DACH) 7 6 5 4 3 2 1 0 Reset Value SFR B6h 00h DACH7−0 Most Significant Byte Register for DAC0−3 and DAC Control (1 and 3). bits 7−0 NOTE: DAC2 and DAC3 available only on the MSC1211 and MSC1212. DAC Select (DACSEL) 7 6 5 4 3 2 1 0 Reset Value SFR B7h DSEL7 DSEL6 DSEL5 DSEL4 DSEL3 DSEL2 DSEL1 DSEL0 00h DSEL7−0 DAC Select and DAC Control Select. The DACSEL register selects which DAC output register or which DAC bits 7−0 control register is accessed by the DACL and DACH registers. DACSEL (B7h) DACH (B6h) DACL (B5h) RESET VALUE 00h DAC0 (high) DAC0 (low) 0000h 01h DAC1 (high) DAC1 (low) 0000h 02h DAC2(1) (high) DAC2(1) (low) 0000h 03h DAC3(1) (high) DAC3(1) (low) 0000h 04h DACCON1 DACCON0 6363h 05h DACCON3(1) DACCON2(1) 0303h 06h — LOADCON −−00h 07h — — — (1)DAC2 and DAC3 available only on the MSC1211 and MSC1212. 79

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DAC0 Control (DACCON0) DACSEL = 04h 7 6 5 4 3 2 1 0 Reset Value SFR B5h COR0 EOD0 IDAC0DIS IDAC0SINK 0 SELREF0 DOM0_1 DOM0_0 63h COR0 Current Over Range on DAC0 bit 7 Write: 0 = Clear to release from high-impedance state back to normal mode unless an over-range condition exists. 1 = NOP Read: 0 = No current over range for DAC0. 0 = NOP 1 = IDAC overcurrent for three consecutive ticks on ms clock USEC (EOD0 = 1) or Current Over Range raw signal (EOD0 = 0). EOD0 Enable Over-Current Detection bit 6 0 = Disable over-current detection. 1 = Enable over-current detection (default). After three consecutive ticks on MSEC clock of overcurrent, the DAC is disabled; however, the register values are preserved. Writing to COR0 releases the high-impedance state. IDAC0DIS IDAC0 Disable (for DOM0 = 00) bit 5 0 = IDAC on mode for DAC0. 1 = IDAC off mode for DAC0 (default). IDAC0SINK ENABLE CURRENT SINK bit 4 0 = DAC0 is sourcing current. 1 = DAC0 is sinking current using external device. Not Used bit 3 SELREF0 Select the Reference Voltage for DAC0 Voltage Reference. bit 2 0 = DAC0 V = AV (default). REF DD 1 = DAC0 V = voltage on REF IN+/REFOUT pin. REF DOM0_1−0 DAC Output Mode DAC0. bits 1−0 DOM0 OUTPUT MODE for DAC0 00 Normal VDAC output; IDAC controlled by IDAC0DIS bit. 01 Power-Down mode—VDAC output off 1kΩ to AGND, IDAC off. 10 Power-Down mode—VDAC output off 100kΩ to AGND, IDAC off. 11 Power-Down mode—VDAC output off high impedance, IDAC off (default). 80

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DAC1 Control (DACCON1) DACSEL = 04h 7 6 5 4 3 2 1 0 Reset Value SFR B6h COR1 EOD1 IDAC1DIS IDAC1SINK 0 SELREF1 DOM1_1 DOM1_0 63h COR1 Current Over Range on DAC1 bit 7 Write: 0 = Clear to release from high-impedance state back to normal mode unless an over-range condition exists. 1 = No effect. Read: 0 = No current over range for DAC1. 0 = No effect. 1 = IDAC overcurrent for three consecutive ticks on ms clock USEC (EOD1 = 1) or Current Over Range raw signal (EOD0 = 0). EOD1 Enable Over-Current Detection bit 6 0 = Disable over-current detection. 1 = Enable over-current detection (default). After three consecutive ticks on MSEC clock of overcurrent, the DAC is disabled; however, the register values are preserved. Writing to COR1 releases the high-impedance state. IDAC1DIS IDAC1 Disable (for DOM1 = 00) bit 5 0 = IDAC on mode for DAC1. 1 = IDAC off mode for DAC1 (default). IDAC1SINK ENABLE CURRENT SINK bit 4 0 = DAC1 is sourcing current. 1 = DAC1 is sinking current using external device. Not Used bit 3 SELREF1 Select the Reference Voltage for DAC1 Voltage Reference. bit 2 0 = DAC1 V = AV (default). REF DD 1 = DAC1 V = voltage on V IN pins. REF REF DOM1_1−0 DAC Output Mode DAC1. bits 1−0 DOM1 OUTPUT MODE for DAC1 00 Normal VDAC output; IDAC controlled by IDAC1DIS bit. 01 Power-Down mode—VDAC output off 1kΩ to AGND, IDAC off. 10 Power-Down mode—VDAC output off 100kΩ to AGND, IDAC off. 11 Power-Down mode—VDAC output off high impedance, IDAC off (default). 81

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DAC2 Control (DACCON2) (Available only on the MSC1211 and MSC1212) DACSEL = 05h 7 6 5 4 3 2 1 0 Reset Value SFR B5h 0 0 0 0 0 SELREF2 DOM2_1 DOM2_0 03h SELREF2 Select the Reference Voltage for DAC2 Voltage Reference. bit 2 0 = DAC2 V = AV (default). REF DD 1 = DAC2 V = internal V . REF REF DOM2_1−0 DAC Output Mode DAC2. bits 1−0 DOM2 OUTPUT MODE for DAC2 00 Normal VDAC output. 01 Power-Down mode—VDAC output off 1kΩ to AGND, IDAC off. 10 Power-Down mode—VDAC output off 100kΩ to AGND, IDAC off. 11 Power-Down mode—VDAC output off high impedance, IDAC off (default). DAC3 Control (DACCON3) (Available only on the MSC1211 and MSC1212) DACSEL = 05h 7 6 5 4 3 2 1 0 Reset Value SFR B6h 0 0 0 0 0 SELREF3 DOM3_1 DOM3_0 03h SELREF3 Select the Reference Voltage for DAC3 Voltage Reference. bit 2 0 = DAC3 V = AV (default). REF DD 1 = DAC3 V = internal V . REF REF DOM3_1−0 DAC Output Mode DAC3. bits 1−0 DOM2 OUTPUT MODE for DAC3 00 Normal VDAC output. 01 Power-Down mode—VDAC output off 1kΩ to AGND, IDAC off. 10 Power-Down mode—VDAC output off 100kΩ to AGND, IDAC off. 11 Power-Down mode—VDAC output off high impedance, IDAC off (default). 82

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DAC Load Control (LOADCON) DACSEL = 06h 7 6 5 4 3 2 1 0 Reset Value SFR B5h D3LOAD1 D3LOAD0 D2LOAD1 D2LOAD0 D1LOAD1 D1LOAD0 D0LOAD1 D0LOAD0 00h D3LOAD1−0 (Available only on MSC1211 and MSC1212) bit 7−6 The DAC load options are listed below: DxLOAD OUTPUT MODE for 00 Direct load: write to DACxL directly loads the DAC buffer and the DAC output (write to DACxH does not load DAC output). 01 Delay load: the values last written to DACxL/DACxH will be transferred to the DAC output on the next MSEC timer tick. 10 Delay load: the values last written to DACxL/DACxH will be transferred to the DAC output on the next HMSEC timer tick. 11 Sync load: the values contained in the DACxL/DACxH registers will be transferred to the DAC output immediately after 11b is written to this register. D2LOAD1−0 (Available only on MSC1211 and MSC1212) bit 5−4 D1LOAD1−0 bit 3−2 D0LOAD1−0 bit 1−0 Interrupt Priority (IP) 7 6 5 4 3 2 1 0 Reset Value SFR B8h 1 PS1 PT2 PS0 PT1 PX1 PT0 PX0 80h PS1 Serial Port 1 Interrupt. This bit controls the priority of the serial Port 1 interrupt. bit 6 0 = Serial Port 1 priority is determined by the natural priority order. 1 = Serial Port 1 is a high-priority interrupt. PT2 Timer 2 Interrupt. This bit controls the priority of the Timer 2 interrupt. bit 5 0 = Timer 2 priority is determined by the natural priority order. 1 = Timer 2 priority is a high-priority interrupt. PS0 Serial Port 0 Interrupt. This bit controls the priority of the serial Port 0 interrupt. bit 4 0 = Serial Port 0 priority is determined by the natural priority order. 1 = Serial Port 0 is a high-priority interrupt. PT1 Timer 1 Interrupt. This bit controls the priority of the Timer 1 interrupt. bit 3 0 = Timer 1 priority is determined by the natural priority order. 1 = Timer 1 priority is a high-priority interrupt. PX1 External Interrupt 1. This bit controls the priority of external interrupt 1. bit 2 0 = External interrupt 1 priority is determined by the natural priority order. 1 = External interrupt 1 is a high-priority interrupt. PT0 Timer 0 Interrupt. This bit controls the priority of the Timer 0 interrupt. bit 1 0 = Timer 0 priority is determined by the natural priority order. 1 = Timer 0 priority is a high-priority interrupt. PX0 External Interrupt 0. This bit controls the priority of external interrupt 0. bit 0 0 = External interrupt 0 priority is determined by the natural priority order. 1 = External interrupt 0 is a high-priority interrupt. 83

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Serial Port 1 Control (SCON1) 7 6 5 4 3 2 1 0 Reset Value SFR C0h SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00h SM0−2 Serial Port 1 Mode. These bits control the mode of serial Port 1. Modes 1, 2, and 3 have 1 start and 1 stop bit in bits 7−5 addition to the 8 or 9 data bits. MODE SM0 SM1 SM2 FUNCTION LENGTH PERIOD 0 0 0 0 Synchronous 8 bits 12 pCLK(1) 0 0 0 1 Synchronous 8 bits 4 pCLK(1) 1(2) 0 1 0 Asynchronous 10 bits Timer 1 Baud Rate Equation 1(2) 0 1 1 Valid Stop Required(3) 10 bits Timer 1 Baud Rate Equation 2 1 0 0 Asynchronous 11 bits 64 pCLK(1) (SMOD = 0) 32 pCLK(1) (SMOD = 1) 2 1 0 1 Asynchronous with Multiprocessor Communication(4) 11 bits 64 pCLK(1) (SMOD = 0) 32 pCLK(1) (SMOD = 1) 3(2) 1 1 0 Asynchronous 11 bits Timer 1 Baud Rate Equation 3(2) 1 1 1 Asynchronous with Multiprocessor Communication(4) 11 bits Timer 1 Baud Rate Equation (1) pCLK will be equal to tCLK, except that pCLK will stop for Idle mode. (2) For modes 1 and 3, the selection of Timer 1 for baud rate is specified via the T2CON (C8h) register. (3) RI_0 will only be activated when a valid STOP is received. (4) RI_0 will not be activated if bit 9 = 0. REN_1 Receive Enable. This bit enables/disables the serial Port 1 received shift register. bit 4 0 = Serial Port 1 reception disabled. 1 = Serial Port 1 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0). TB8_1 9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 1 modes 2 and 3. bit 3 RB8_1 9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 1 modes bit 2 2 and 3. In serial port mode 1, when SM2_1 = 0, RB8_1 is the state of the stop bit. RB8_1 is not used in mode 0. TI_1 Transmitter Interrupt Flag. This bit indicates that data in the serial Port 1 buffer has been completely shifted out. bit 1 In serial port mode 0, TI_1 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last data bit. This bit must be cleared by software to transmit the next byte. RI_1 Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 1 buffer. In serial bit 0 port mode 0, RI_1 is set at the end of the 8th bit. In serial port mode 1, RI_1 is set after the last sample of the incoming stop bit subject to the state of SM2_1. In modes 2 and 3, RI_1 is set after the last sample of RB8_1. This bit must be cleared by software to receive the next byte. Serial Data Buffer 1 (SBUF1) 7 6 5 4 3 2 1 0 Reset Value SFR C1h 00h SBUF1.7−0 Serial Data Buffer 1. Data for serial Port 1 is read from or written to this location. The serial transmit and receive bits 7−0 buffers are separate registers, but both are addressed at this location. 84

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Enable Wake Up (EWU) Waking Up from Idle Mode 7 6 5 4 3 2 1 0 Reset Value SFR C6h — — — — — EWUWDT EWUEX1 EWUEX0 00h Auxiliary interrupts will wake up from Idle mode. They are enabled with EAI (EICON.5). EWUWDT Enable Wake Up Watchdog Timer. Wake using watchdog timer interrupt. bit 2 0 = Don’t wake up on watchdog timer interrupt. 1 = Wake up on watchdog timer interrupt. EWUEX1 Enable Wake Up External 1. Wake using external interrupt source 1. bit 1 0 = Don’t wake up on external interrupt source 1. 1 = Wake up on external interrupt source 1. EWUEX0 Enable Wake Up External 0. Wake using external interrupt source 0. bit 0 0 = Don’t wake up on external interrupt source 0. 1 = Wake up on external interrupt source 0. System Clock Divider (SYSCLK) 7 6 5 4 3 2 1 0 Reset Value SFR C7h 0 0 DIVMOD1 DIVMOD0 0 DIV2 DIV1 DIV0 00h NOTE: Changing SYSCLK registers affects all internal clocks, including the ADC clock. DIVMOD1−0Clock Divide Mode bits 5−4 Write: DIVMOD DIVIDE MODE 00 Normal mode (default, no divide). 01 Immediate mode: start divide immediately; return to Normal mode on Idle mode wakeup condition or by direct write to SFR. 10 Delay mode: same as Immediate mode, except that the mode changes with the millisecond interrupt (MSINT). If MSINT is enabled, the divide will start on the next MSINT and return to normal mode on the following MSINT. If MSINT is not enabled, the divide will start on the next MSINT condition (even if masked) but will not leave the divide mode until the MSINT counter overflows, which follows a wakeup condition. Can exit by directly writing to SFR. 11 Manual mode: start divide immediately; exit mode only by directly writing to SFR. Same as immediate mode, but cannot return to Normal mode on Idle mode wakeup condition; only by directly writing to SFR. Read: DIVMOD DIVISION MODE STATUS 00 No divide 01 Divider is in Immediate mode 10 Divider is in Delay mode 11 Medium mode DIV2−0 Divide Mode bit 2−0 DIV DIVISOR fCLK FREQUENCY 000 Divide by 2 (default) fCLK = fSYS/2 001 Divide by 4 fCLK = fSYS/4 010 Divide by 8 fCLK = fSYS/8 011 Divide by 16 fCLK = fSYS/16 100 Divide by 32 fCLK = fSYS/32 101 Divide by 1024 fCLK = fSYS/1024 110 Divide by 2048 fCLK = fSYS/2048 111 Divide by 4096 fCLK = fSYS/4096 85

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Timer 2 Control (T2CON) 7 6 5 4 3 2 1 0 Reset Value SFR C8h TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00h TF2 Timer 2 Overflow Flag. This flag will be set when Timer 2 overflows from FFFFh. It must be cleared by software. bit 7 TF2 will only be set if RCLK and TCLK are both cleared to ‘0’. Writing a ‘1’ to TF2 forces a Timer 2 interrupt if enabled. EXF2 Timer 2 External Flag. A negative transition on the T2EX pin (P1.1) will cause this flag to be set based on the EXEN2 bit 6 (T2CON.3) bit. If set by a negative transition, this flag must be cleared to ‘0’ by software. Setting this bit in software will force a timer interrupt if enabled. RCLK Receive Clock Flag. This bit determines the serial Port 0 timebase when receiving data in serial modes 1 or 3. bit 5 0 = Timer 1 overflow is used to determine receiver baud rate for USART0. 1 = Timer 2 overflow is used to determine receiver baud rate for USART0. Setting this bit will force Timer 2 into baud rate generation mode. The timer will operate from a divide by 2 of the external clock. TCLK Transmit Clock Flag. This bit determines the serial Port 0 timebase when transmitting data in serial modes 1 or 3. bit 4 0 = Timer 1 overflow is used to determine transmitter baud rate for USART0. 1 = Timer 2 overflow is used to determine transmitter baud rate for USART0. Setting this bit will force Timer 2 into baud rate generation mode. The timer will operate from a divide by 2 of the external clock. EXEN2 Timer 2 External Enable. This bit enables the capture/reload function on the T2EX pin if Timer 2 is not generating bit 3 baud rates for the serial port. 0 = Timer 2 will ignore all external events at T2EX. 1 = Timer 2 will capture or reload a value if a negative transition is detected on the T2EX pin. TR2 Timer 2 Run Control. This bit enables/disables the operation of Timer 2. Halting this timer will preserve the current bit 2 count in TH2, TL2. 0 = Timer 2 is halted. 1 = Timer 2 is enabled. C/T2 Counter/Timer Select. This bit determines whether Timer 2 will function as a timer or counter. Independent of this bit 1 bit, Timer 2 runs at 2 clocks per tick when used in baud rate generator mode. 0 = Timer 2 functions as a timer. The speed of Timer 2 is determined by the T2M bit (CKCON.5). 1 = Timer 2 will count negative transitions on the T2 pin (P1.0). CP/RL2 Capture/Reload Select. This bit determines whether the capture or reload function will be used for Timer 2. If either bit 0 RCLK or TCLK is set, this bit will not function and the timer will function in an auto-reload mode following each overflow. 0 = Auto-reloads will occur when Timer 2 overflows or a falling edge is detected on T2EX if EXEN2 = 1. 1 = Timer 2 captures will occur when a falling edge is detected on T2EX if EXEN2 = 1. Timer 2 Capture LSB (RCAP2L) 7 6 5 4 3 2 1 0 Reset Value SFR CAh 00h RCAP2L Timer 2 Capture LSB. This register is used to capture the TL2 value when Timer 2 is configured in capture mode. bits 7−0 RCAP2L is also used as the LSB of a 16-bit reload value when Timer 2 is configured in auto-reload mode. 86

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Timer 2 Capture MSB (RCAP2H) 7 6 5 4 3 2 1 0 Reset Value SFR CBh 00h RCAP2H Timer 2 Capture MSB. This register is used to capture the TH2 value when Timer 2 is configured in capture mode. bits 7−0 RCAP2H is also used as the MSB of a 16-bit reload value when Timer 2 is configured in auto-reload mode. Timer 2 LSB (TL2) 7 6 5 4 3 2 1 0 Reset Value SFR CCh 00h TL2 Timer 2 LSB. This register contains the least significant byte of Timer 2. bits 7−0 Timer 2 MSB (TH2) 7 6 5 4 3 2 1 0 Reset Value SFR CDh 00h TH2 Timer 2 MSB. This register contains the most significant byte of Timer 2. bits 7−0 Program Status Word (PSW) 7 6 5 4 3 2 1 0 Reset Value SFR D0h CY AC F0 RS1 RS0 OV F1 P 00h CY Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (during addition) or a borrow (during bit 7 subtraction). Otherwise, it is cleared to ‘0’ by all arithmetic operations. AC Auxiliary Carry Flag. This bit is set to ‘1’ if the last arithmetic operation resulted in a carry into (during addition), or bit 6 a borrow (during subtraction) from the high order nibble. Otherwise, it is cleared to ‘0’ by all arithmetic operations. F0 User Flag 0. This is a bit-addressable, general-purpose flag for software control. bit 5 RS1, RS0 Register Bank Select 1−0. These bits select which register bank is addressed during register accesses. bits 4−3 RS1 RS0 REGISTER BANK ADDRESS 0 0 0 00h − 07h 0 1 1 08h − 0Fh 1 0 2 10h − 17h 1 1 3 18h − 1Fh OV Overflow Flag. This bit is set to ‘1’ if the last arithmetic operation resulted in a carry (addition), borrow (subtraction), bit 2 or overflow (multiply or divide). Otherwise, it is cleared to ‘0’ by all arithmetic operations. F1 User Flag 1. This is a bit-addressable, general-purpose flag for software control. bit 1 P Parity Flag. This bit is set to ‘1’ if the modulo-2 sum of the 8 bits of the accumulator is 1 (odd parity), and cleared to bit 0 ‘0’ on even parity. 87

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC Offset Calibration Low Byte (OCL) 7 6 5 4 3 2 1 0 Reset Value SFR D1h 00h OCL ADC Offset Calibration Low Byte. This is the low byte of the 24-bit word that contains the ADC offset bits 7−0 calibration. A value that is written to this location will set the ADC offset calibration value. ADC Offset Calibration Middle Byte (OCM) 7 6 5 4 3 2 1 0 Reset Value SFR D2h 00h OCM ADC Offset Calibration Middle Byte. This is the middle byte of the 24-bit word that contains the ADC offset bits 7−0 calibration. A value that is written to this location will set the ADC offset calibration value. ADC Offset Calibration High Byte (OCH) 7 6 5 4 3 2 1 0 Reset Value SFR D3h 00h OCH ADC Offset Calibration High Byte. This is the high byte of the 24-bit word that contains the ADC offset bits 7−0 calibration. A value that is written to this location will set the ADC offset calibration value. ADC Gain Calibration Low Byte (GCL) 7 6 5 4 3 2 1 0 Reset Value SFR D4h 5Ah GCL ADC Gain Calibration Low Byte. This is the low byte of the 24-bit word that contains the ADC gain bits 7−0 calibration. A value that is written to this location will set the ADC gain calibration value. ADC Gain Calibration Middle Byte (GCM) 7 6 5 4 3 2 1 0 Reset Value SFR D5h ECh GCM ADC Gain Calibration Middle Byte. This is the middle byte of the 24-bit word that contains the ADC gain bits 7−0 calibration. A value that is written to this location will set the ADC gain calibration value. ADC Gain Calibration High Byte (GCH) 7 6 5 4 3 2 1 0 Reset Value SFR D6h 5Fh GCH ADC Gain Calibration High Byte. This is the high byte of the 24-bit word that contains the ADC gain bits 7−0 calibration. A value that is written to this location will set the ADC gain calibration value. 88

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC Input Multiplexer (ADMUX) 7 6 5 4 3 2 1 0 Reset Value SFR D7h INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 01h INP3−0 Input Multiplexer Positive Input. This selects the positive signal input. bits 7−4 INP3 INP2 INP1 INP0 POSITIVE INPUT 0 0 0 0 AIN0 (default) 0 0 0 1 AIN1 0 0 1 0 AIN2 0 0 1 1 AIN3 0 1 0 0 AIN4 0 1 0 1 AIN5 0 1 1 0 AIN6 0 1 1 1 AIN7 1 0 0 0 AINCOM 1 1 1 1 Temperature Sensor (requires ADMUX = FFh) INN3−0 Input Multiplexer Negative Input. This selects the negative signal input. bits 3−0 INN3 INN2 INN1 INN0 NEGATIVE INPUT 0 0 0 0 AIN0 0 0 0 1 AIN1 (default) 0 0 1 0 AIN2 0 0 1 1 AIN3 0 1 0 0 AIN4 0 1 0 1 AIN5 0 1 1 0 AIN6 0 1 1 1 AIN7 1 0 0 0 AINCOM 1 1 1 1 Temperature Sensor (requires ADMUX = FFh) 89

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Enable Interrupt Control (EICON) 7 6 5 4 3 2 1 0 Reset Value SFR D8h SMOD1 1 EAI AI WDTI 0 0 0 40h SMOD1 Serial Port 1 Mode. When this bit is set the serial baud rate for Port 1 will be doubled. bit 7 0 = Standard baud rate for Port 1 (default). 1 = Double baud rate for Port 1. EAI Enable Auxiliary Interrupt. The Auxiliary Interrupt accesses nine different interrupts which are masked and bit 5 identified by SFR registers PAI (SFR A5h), AIE (SFR A6h), and AISTAT (SFR A7h). 0 = Auxiliary Interrupt disabled (default). 1 = Auxiliary Interrupt enabled. AI Auxiliary Interrupt Flag. AI must be cleared by software before exiting the interrupt service routine, after the source bit 4 of the interrupt is cleared. Otherwise, the interrupt occurs again. Setting AI in software generates an Auxiliary Interrupt, if enabled. 0 = No Auxiliary Interrupt detected (default). 1 = Auxiliary Interrupt detected. WDTI Watchdog Timer Interrupt Flag. WDTI must be cleared by software before exiting the interrupt service routine. bit 3 Otherwise, the interrupt occurs again. Setting WDTI in software generates a watchdog time interrupt, if enabled. The Watchdog timer can generate an interrupt or reset. The interrupt is available only if the reset action is disabled in HCR0. 0 = No Watchdog Timer Interrupt Detected (default). 1 = Watchdog Timer Interrupt Detected. ADC Results Low Byte (ADRESL) 7 6 5 4 3 2 1 0 Reset Value SFR D9h 00h ADRESL The ADC Results Low Byte. This is the low byte of the 24-bit word that contains the ADC results. bits 7−0 Reading from this register clears the ADC interrupt; however, AI in EICON (SFR D8) must also be cleared. ADC Results Middle Byte (ADRESM) 7 6 5 4 3 2 1 0 Reset Value SFR DAh 00h ADRESM The ADC Results Middle Byte. This is the middle byte of the 24-bit word that contains the A/D conversion results. bits 7−0 ADC Results High Byte (ADRESH) 7 6 5 4 3 2 1 0 Reset Value SFR DBh 00h ADRESH The ADC Results High Byte. This is the high byte of the 24-bit word that contains the A/D conversion results. bits 7−0 90

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC Control 0 (ADCON0) 7 6 5 4 3 2 1 0 Reset Value SFR DCh REFCLK BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 30h REFCLK Reference Clock. The reference is specified with a 250kHz clock. The REFCLK should be selected by choosing bit 7 the appropriate source so that it does not exceed 250kHz. t 0(cid:1) CLK (ACLK(cid:6)1)*4 1(cid:1)USEC 4 BOD Burnout Detect. When enabled this connects a positive current source to the positive channel and a negative bit 6 current source to the negative channel. If the channel is open circuit then the ADC results will be full-scale. Used with Buffer ON. 0 = Burnout Current Sources Off (default). 1 = Burnout Current Sources On. EVREF Enable Internal Voltage Reference. If the internal voltage reference is not used, it should be turned off to save power bit 5 and reduce noise. 0 = Internal Voltage Reference Off. 1 = Internal Voltage Reference On (default). REF IN− should be connected to AGND in this mode. REF IN+ should have a 0.1µF capacitor. VREFH Voltage Reference High Select. The internal voltage reference can be selected to be 2.5V or 1.25V. bit 4 0 = REFOUT/REF IN+ is 1.25V. 1 = REFOUT/REF IN+ is 2.5V (default). EBUF Enable Buffer. Enable the input buffer to provide higher input impedance but limits the input voltage range and bit 3 dissipates more power. 0 = Buffer disabled (default). 1 = Buffer enabled. PGA2−0 Programmable Gain Amplifier. Sets the gain for the PGA from 1 to 128. bits 2−0 PGA2 PGA1 PGA0 GAIN 0 0 0 1 (default) 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 91

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC Control 1 (ADCON1) 7 6 5 4 3 2 1 0 Reset Value SFR DDh OF_UF POL SM1 SM0 — CAL2 CAL1 CAL0 0000 0000b OF_UF Overflow/Underflow. If this bit is set, the data in the summation register is invalid. Either an overflow or underflow bit 7 occurred. The bit is cleared by writing a ‘0’ to it. POL Polarity. Polarity of the ADC result and Summation register. bit 6 0 = Bipolar. 1 = Unipolar. The LSB size is 1/2 the size of bipolar (twice the resolution). POL ANALOG INPUT DIGITAL OUTPUT +FSR 7FFFFFh 00 ZERO 000000h −FSR 800000h +FSR FFFFFFh 11 ZERO 000000h −FSR 000000h SM1−0 Settling Mode. Selects the type of filter or auto-select which defines the digital filter settling characteristics. bits 5−4 SM1 SM0 SETTLING MODE 0 0 Auto 0 1 Fast Settling Filter 1 0 Sinc2 Filter 1 1 Sinc3 Filter CAL2−0 Calibration Mode Control Bits. bits 2−0 Writing to these bits initiates the ADC calibration. CAL2 CAL1 CAL0 CALIBRATION MODE 0 0 0 No Calibration (default) 0 0 1 Self-Calibration, Offset and Gain 0 1 0 Self-Calibration, Offset only 0 1 1 Self-Calibration, Gain only 1 0 0 System Calibration, Offset only 1 0 1 System Calibration, Gain only 1 1 0 Reserved 1 1 1 Reserved NOTE: Read Value—000b. ADC Control 2 (ADCON2) 7 6 5 4 3 2 1 0 Reset Value SFR DEh DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1Bh DR7−0 Decimation Ratio LSB. bits 7−0 ADC Control 3 (ADCON3) 7 6 5 4 3 2 1 0 Reset Value SFR DFh — — — — — DR10 DR9 DR8 06h DR10−8 Decimation Ratio Most Significant 3 Bits. The ADC output data rate = (ACLK + 1)/64/Decimation Ratio. bits 2−0 92

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Accumulator (A or ACC) 7 6 5 4 3 2 1 0 Reset Value SFR E0h ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00h ACC.7−0 Accumulator. This register serves as the accumulator for arithmetic and logic operations. bits 7−0 Summation/Shifter Control (SSCON) 7 6 5 4 3 2 1 0 Reset Value SFR E1h SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00h The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register, the 32-bit SUMR3−0 registers will be cleared. The Summation registers will do sign-extend if Bipolar mode is selected in ADCON1. SSCON1−0 Summation/Shift Count. bits 7−6 SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 DESCRIPTION 0 0 0 0 0 0 0 0 Clear Summation Register 0 0 0 1 0 0 0 0 CPU Summation on Write to SUMR0 (sum count/shift ignored) 0 0 1 0 0 0 0 0 CPU Subtraction on Write to SUMR0 (sum count/shift ignored) 1 0 x x x Note (1) Note (1) Note (1) CPU Shift only 0 1 Note (1) Note (1) Note (1) x x x ADC Summation only 1 1 Note (1) Note (1) Note (1) Note (1) Note (1) Note (1) ADC Summation completes, then shift completes (1)Refer to register bit definition. SCNT2−0 Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the bits 5−3 SUMR0 register clears the interrupt. SCNT2 SCNT1 SCNT0 SUMMATION COUNT 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 SHF2−0 Shift Count. bits 2−0 SHF2 SHF1 SHF0 SHIFT DIVIDE 0 0 0 1 2 0 0 1 2 4 0 1 0 3 8 0 1 1 4 16 1 0 0 5 32 1 0 1 6 64 1 1 0 7 128 1 1 1 8 256 93

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Summation 0 (SUMR0) 7 6 5 4 3 2 1 0 Reset Value SFR E2h 00h SUMR0 Summation 0. This is the least significant byte of the 32-bit summation register, or bits 0 to 7. bits 7−0 Write: values in SUMR3−0 are added to the summation register. Read: clears the Summation Count Interrupt; however, AI in EICON (SFR D8) must also be cleared. Summation 1 (SUMR1) 7 6 5 4 3 2 1 0 Reset Value SFR E3h 00h SUMR1 Summation 1. This is the most significant byte of the lowest 16 bits of the summation register, or bits 8−15. bits 7−0 Summation 2 (SUMR2) 7 6 5 4 3 2 1 0 Reset Value SFR E4h 00h SUMR2 Summation 2. This is the most significant byte of the lowest 24 bits of the summation register, or bits 16−23. bits 7−0 Summation 3 (SUMR3) 7 6 5 4 3 2 1 0 Reset Value SFR E5h 00h SUMR3 Summation 3. This is the most significant byte of the 32-bit summation register, or bits 24−31. bits 7−0 Offset DAC (ODAC) 7 6 5 4 3 2 1 0 Reset Value SFR E6h 00h ODAC Offset DAC. This register will shift the input by up to half of the ADC full-scale input range. The Offset DAC bits 7−0 value is summed into the ADC prior to conversion. Writing 00h or 80h to ODAC turns off the Offset DAC.. The offset DAC should be cleared prior to calibration, since the offset DAC analog output is applied directly to the ADC input. bit 7 Offset DAC Sign bit. 0 = Positive 1 = Negative (cid:3) (cid:5) bit 6−0 Offset(cid:1) (cid:8)VREF (cid:2) ODAC(cid:7)6:0(cid:9) (cid:2)((cid:8)1)bit7 2(cid:2)PGA 127 NOTE: ODAC cannot be used to offset the analog inputs so that the buffer can be used for signals within 50mV of AGND. 94

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Low Voltage Detect Control (LVDCON) 7 6 5 4 3 2 1 0 Reset Value SFR E7h ALVDIS ALVD2 ALVD1 ALVD0 DLVDIS DLVD2 DLVD1 DLVD0 00h ALVDIS Analog Low Voltage Detect Disable. bit 7 0 = Enable Detection of Low Analog Supply Voltage. 1 = Disable Detection of Low Analog Supply Voltage. ALVD2−0 Analog Voltage Detection Level. bits 6−4 ALVD2 ALVD1 ALVD0 VOLTAGE LEVEL 0 0 0 AVDD 2.7V (default) 0 0 1 AVDD 3.0V 0 1 0 AVDD 3.3V 0 1 1 AVDD 4.0V 1 0 0 AVDD 4.2V 1 0 1 AVDD 4.5V 1 1 0 AVDD 4.7V 1 1 1 External Voltage AIN7 compared to 1.2V DLVDIS Digital Low Voltage Detect Disable. bit 3 0 = Enable Detection of Low Digital Supply Voltage. 1 = Disable Detection of Low Digital Supply Voltage. DLVD2−0 Digital Voltage Detection Level. bits 2−0 DLVD2 DLVD1 DLVD0 VOLTAGE LEVEL 0 0 0 DVDD 2.7V (default) 0 0 1 DVDD 3.0V 0 1 0 DVDD 3.3V 0 1 1 DVDD 4.0V 1 0 0 DVDD 4.2V 1 0 1 DVDD 4.5V 1 1 0 DVDD 4.7V 1 1 1 External Voltage AIN6 compared to 1.2V 95

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Extended Interrupt Enable (EIE) 7 6 5 4 3 2 1 0 Reset Value SFR E8h 1 1 1 EWDI EX5 EX4 EX3 EX2 E0h EWDI Enable Watchdog Interrupt. This bit enables/disables the watchdog interrupt. The Watchdog timer is enabled by bit 4 (SFR FFh) and PDCON (SFR F1h) registers. 0 = Disable the Watchdog Interrupt 1 = Enable Interrupt Request Generated by the Watchdog Timer EX5 External Interrupt 5 Enable. This bit enables/disables external interrupt 5. bit 3 0 = Disable External Interrupt 5 1 = Enable External Interrupt 5 EX4 External Interrupt 4 Enable. This bit enables/disables external interrupt 4. bit 2 0 = Disable External Interrupt 4 1 = Enable External Interrupt 4 EX3 External Interrupt 3 Enable. This bit enables/disables external interrupt 3. bit 1 0 = Disable External Interrupt 3 1 = Enable External Interrupt 3 EX2 External Interrupt 2 Enable. This bit enables/disables external interrupt 2. bit 0 0 = Disable External Interrupt 2 1 = Enable External Interrupt 2 Hardware Product Code 0 (HWPC0) 7 6 5 4 3 2 1 0 Reset Value SFR E9h 0 0 0 0 0 1 MEMORY SIZE 0000_01xxb(1) (1)Applies to MSC1211 and MSC1213 only. Reset value for MSC1212 and MSC1214 is 0000_00xxb. HWPC0.7−0 Hardware Product Code LSB. Read-only. bits 7−0 MEMORY SIZE MODEL FLASH MEMORY 0 0 MSC121xY2 4kB 0 0 MSC121xY3 8kB 1 0 MSC121xY4 16kB 1 1 MSC121xY5 32kB Hardware Product Code 1 (HWPC1) 7 6 5 4 3 2 1 0 Reset Value SFR EAh 0 0 0 0 1 0 0 0 08h(1) (1)Applies to MSC1211 and MSC1212 only. Reset value for MSC1213 and MSC1214 is 18h. HWPC1.7−0 Hardware Product Code MSB. Read-only. bits 7−0 96

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Hardware Version (HDWVER) 7 6 5 4 3 2 1 0 Reset Value SFR EBh Flash Memory Control (FMCON) 7 6 5 4 3 2 1 0 Reset Value SFR EEh 0 PGERA 0 FRCM 0 BUSY SPM FPM 02h PGERA Page Erase. Available in both user and program modes. bit 6 0 = Disable Page Erase Mode 1 = Enable Page Erase Mode (automatically set by page_erase Boot ROM routine). FRCM Frequency Control Mode. bit 4 0 = Bypass (default) 1 = Use Delay Line. Recommended for saving power. BUSY Write/Erase BUSY Signal. bit 2 0 = Idle or Available 1 = Busy SPM Serial/Parallel Programming Mode. Read-only. bit 1 0 = Indicates the device is in parallel programming mode. 1 = Indicates the device is in serial programming mode (if FPM also = 1). FPM Flash Programming Mode. Read-only. bit 0 0 = Indicates the device is operating in UAM. 1 = Indicates the device is operating in programming mode. Flash Memory Timing Control (FTCON) 7 6 5 4 3 2 1 0 Reset Value SFR EFh FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 A5h Refer to Flash Memory Characteristics FER3−0 Set Erase. Flash Erase Time = (1 + FER) • (MSEC + 1) • t . This can be broken into multiple shorter erase times. CLK bits 7−4 For more Information, see Application Report SBAA137, Incremental Flash Memory Page Erase, available for download from www.ti.com. Industrial temperature range: 10ms Commercial temperature range: 4ms FWR3−0 Set Write. Set Flash Write Time = (1 + FWR) • (USEC + 1) • 5 • t . Total writing time will be longer. For more CLK bits 3−0 Information, see Application Report SBAA087, In-Application Flash Programming, available for download from www.ti.com. Range: 30µs to 40µs. B Register (B) 7 6 5 4 3 2 1 0 Reset Value SFR F0h B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 00h B.7−0 B Register. This register serves as a second accumulator for certain arithmetic operations. bits 7−0 97

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Power-Down Control (PDCON) 7 6 5 4 3 2 1 0 Reset Value SFR F1h 0 PDDAC PDI2C PDPWM PDADC PDWDT PDST PDSPI 7Fh Turning peripheral modules off puts the MSC1211/12/13/14 in the lowest power mode. PDDAC DAC Module Control. bit 6 0 = DACs On 1 = DACs Power Down PDI2C I2C Control (MSC1211 and MSC1213 only). bit 5 0 = I2C On (the state is undefined if PDSPI is also = 0) 1 = I2C Power Down PDPWM Pulse Width Module Control. bit 4 0 = PWM On 1 = PWM Power Down PDADC ADC Control. bit 3 0 = ADC On 1 = ADC, V , and Summation registers are powered down. REF PDWDT Watchdog Timer Control. bit 2 0 = Watchdog Timer On 1 = Watchdog Timer Power Down PDST System Timer Control. bit 1 0 = System Timer On 1 = System Timer Power Down PDSPI SPI System Control. bit 0 0 = SPI System On (the state is undefined if PDI2C is also = 0) 1 = SPI System Power Down PSEN/ALE Select (PASEL) 7 6 5 4 3 2 1 0 Reset Value SFR F2h 0 0 PSEN2 PSEN1 PSEN0 0 ALE1 ALE0 00h PSEN2−0 PSEN Mode Select. bits 5−3 PSEN2 PSEN1 PSEN0 0 0 X PSEN 0 1 X CLK 1 0 X ADC MODCLK 1 1 0 Low 1 1 1 High ALE1−0 ALE Mode Select. bits 1−0 ALE1 ALE0 0 X ALE 1 0 Low 1 1 High NOTE: X = don’t care. 98

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Analog Clock (ACLK) 7 6 5 4 3 2 1 0 Reset Value SFR F6h 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h FREQ6−0 Clock Frequency Selection. This value + 1 divides the system clock to create the ACLK frequency. f bit 6−0 ACLKfrequency(cid:1) CLK FREQ(cid:6)1 f f (cid:1) CLK MOD (cid:1)ACLK(cid:6)1(cid:2)*64 f DataRate(cid:1) MOD Decimation System Reset (SRST) 7 6 5 4 3 2 1 0 Reset Value SFR F7h 0 0 0 0 0 0 0 RSTREQ 00h RSTREQ Reset Request. Setting this bit to ‘1’ and then clearing to ‘0’ will generate a system reset. bit 0 Extended Interrupt Priority (EIP) 7 6 5 4 3 2 1 0 Reset Value SFR F8h 1 1 1 PWDI PX5 PX4 PX3 PX2 E0h PWDI Watchdog Interrupt Priority. This bit controls the priority of the watchdog interrupt. bit 4 0 = The watchdog interrupt is low priority. 1 = The watchdog interrupt is high priority. PX5 External Interrupt 5 Priority. This bit controls the priority of external interrupt 5. bit 3 0 = External interrupt 5 is low priority. 1 = External interrupt 5 is high priority. PX4 External Interrupt 4 Priority. This bit controls the priority of external interrupt 4. bit 2 0 = External interrupt 4 is low priority. 1 = External interrupt 4 is high priority. PX3 External Interrupt 3 Priority. This bit controls the priority of external interrupt 3. bit 1 0 = External interrupt 3 is low priority. 1 = External interrupt 3 is high priority. PX2 External Interrupt 2 Priority. This bit controls the priority of external interrupt 2. bit 0 0 = External interrupt 2 is low priority. 1 = External interrupt 2 is high priority. 99

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Seconds Timer Interrupt (SECINT) 7 6 5 4 3 2 1 0 Reset Value SFR F9h WRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 7Fh This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then, that 1ms timer tick is divided by the register HMSEC which provides the 100ms signal used by this seconds timer. Therefore, this seconds timer can generate an interrupt which occurs from 100ms to 12.8 seconds. Reading this register will clear the Seconds Interrupt; however, AI in EICON (SFR D8h) must also be cleared. This Interrupt can be monitored in the AIE or AIPOL registers. WRT Write Control. Determines whether to write the value immediately or wait until the current count is finished. bit 7 Read = 0. 0 = Delay Write Operation. The SEC value is loaded when the current count expires. 1 = Write Immediately. The counter is loaded once the CPU completes the write operation. SECINT6−0 Seconds Count. Normal operation would use 100ms as the clock interval. bits 6−0 Seconds Interrupt = (1 + SEC) • (HMSEC + 1) • (MSEC + 1) • t . CLK Milliseconds Timer Interrupt (MSINT) 7 6 5 4 3 2 1 0 Reset Value SFR FAh WRT MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 7Fh The clock used for this timer is the 1ms clock, which results from dividing the system clock by the values in registers MSECH:MSECL. Reading this register is necessary for clearing the interrupt; however, AI in EICON (SFR D8h) must also be cleared. WRT Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0. bit 7 0 = Delay Write Operation. The MSINT value is loaded when the current count expires. 1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation. MSINT6−0 Milliseconds Count. Normal operation would use 1ms as the clock interval. bits 6−0 MS Interrupt Interval = (1 + MSINT) • (MSEC + 1) • t CLK One Microsecond Timer (USEC) 7 6 5 4 3 2 1 0 Reset Value SFR FBh 0 0 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h FREQ5−0 Clock Frequency − 1. This value + 1 divides the system clock to create a 1µs Clock. bits 5−0 USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EFh). One Millisecond Timer Low Byte (MSECL) 7 6 5 4 3 2 1 0 Reset Value SFR FCh MSECL7 MSECL6 MSECL5 MSECL4 MSECL3 MSECL2 MSECL1 MSECL0 9Fh MSECL7−0 One Millisecond Timer Low Byte. This value in combination with the next register is used to create a 1ms clock. bits 7−0 1ms = (MSECH • 256 + MSECL + 1) • t . This clock is used to set Flash erase time. See FTCON (SFR EFh). CLK 100

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:5) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 One Millisecond Timer High Byte (MSECH) 7 6 5 4 3 2 1 0 Reset Value SFR FDh MSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 0Fh MSECH7−0 One Millisecond Timer High Byte. This value in combination with the previous register is used to create a 1ms clock. bits 7−0 1ms = (MSECH • 256 + MSECL + 1) • t . CLK One Hundred Millisecond Timer (HMSEC) 7 6 5 4 3 2 1 0 Reset Value SFR FEh WRT HMSEC6 HMSEC5 HMSEC4 HMSEC3 HMSEC2 HMSEC1 HMSEC0 63h WRT Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0. bit 7 0 = Delay Write Operation. The MSINT value is loaded when the current count expires. 1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation. HMSEC6−0 One Hundred Millisecond. This clock divides the 1ms clock to create a 100ms clock. bits 6−0 100ms = (MSECH • 256 + MSECL + 1) • (HMSEC + 1) • t . CLK Watchdog Timer (WDTCON) 7 6 5 4 3 2 1 0 Reset Value SFR FFh EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00h EWDT Enable Watchdog (R/W). bit 7 Write 1/Write 0 sequence sets the Watchdog Enable Counting bit. DWDT Disable Watchdog (R/W). bit 6 Write 1/Write 0 sequence clears the Watchdog Enable Counting bit. RWDT Reset Watchdog (R/W). bit 5 Write 1/Write 0 sequence restarts the Watchdog Counter. WDCNT4−0 Watchdog Count (R/W). bits 4−0 Watchdog expires in (WDCNT + 1) • HMSEC to (WDCNT + 2) • HMSEC, if the sequence is not asserted. There is an uncertainty of 1 count. 101

www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Revision History DATE REV PAGE SECTION DESCRIPTION 10/07 G 29 Voltage Reference Added paragraph to end of section. 7/06 F 32 Brownout Reset Added paragraph on BOR voltage calibration. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 102

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) MSC1211Y3PAGT ACTIVE TQFP PAG 64 250 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 125 MSC1211Y3 & no Sb/Br) MSC1211Y4PAGT ACTIVE TQFP PAG 64 250 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 125 MSC1211Y4 & no Sb/Br) MSC1211Y4PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 125 MSC1211Y4 & no Sb/Br) MSC1211Y5PAGT ACTIVE TQFP PAG 64 250 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 125 MSC1211Y5 & no Sb/Br) MSC1212Y3PAGT ACTIVE TQFP PAG 64 250 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 125 MSC1212Y3 & no Sb/Br) MSC1212Y4PAGT ACTIVE TQFP PAG 64 250 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 125 MSC1212Y4 & no Sb/Br) MSC1212Y5PAGT ACTIVE TQFP PAG 64 250 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 125 MSC1212Y5 & no Sb/Br) MSC1213Y2PAGT ACTIVE TQFP PAG 64 250 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 125 MSC1213Y2 & no Sb/Br) MSC1213Y3PAGT ACTIVE TQFP PAG 64 250 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 125 MSC1213Y3 & no Sb/Br) MSC1213Y4PAGT ACTIVE TQFP PAG 64 250 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 125 MSC1213Y4 & no Sb/Br) MSC1213Y5PAGT ACTIVE TQFP PAG 64 250 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 125 MSC1213Y5 & no Sb/Br) MSC1213Y5PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 125 MSC1213Y5 & no Sb/Br) MSC1214Y3PAGT ACTIVE TQFP PAG 64 250 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 125 MSC1214Y3 & no Sb/Br) MSC1214Y4PAGT ACTIVE TQFP PAG 64 250 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 125 MSC1214Y4 & no Sb/Br) MSC1214Y5PAGR ACTIVE TQFP PAG 64 1500 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 125 MSC1214Y5 & no Sb/Br) MSC1214Y5PAGT ACTIVE TQFP PAG 64 250 Green (RoHS NIPDAU Level-4-260C-72 HR -40 to 125 MSC1214Y5 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) MSC1211Y3PAGT TQFP PAG 64 250 180.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 MSC1211Y4PAGT TQFP PAG 64 250 180.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 MSC1211Y5PAGT TQFP PAG 64 250 180.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 MSC1212Y3PAGT TQFP PAG 64 250 180.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 MSC1212Y4PAGT TQFP PAG 64 250 180.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 MSC1212Y5PAGT TQFP PAG 64 250 180.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 MSC1213Y2PAGT TQFP PAG 64 250 180.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 MSC1213Y3PAGT TQFP PAG 64 250 180.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 MSC1213Y4PAGT TQFP PAG 64 250 180.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 MSC1213Y5PAGT TQFP PAG 64 250 180.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 MSC1214Y3PAGT TQFP PAG 64 250 180.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 MSC1214Y4PAGT TQFP PAG 64 250 180.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 MSC1214Y5PAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 MSC1214Y5PAGT TQFP PAG 64 250 180.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) MSC1211Y3PAGT TQFP PAG 64 250 213.0 191.0 55.0 MSC1211Y4PAGT TQFP PAG 64 250 213.0 191.0 55.0 MSC1211Y5PAGT TQFP PAG 64 250 213.0 191.0 55.0 MSC1212Y3PAGT TQFP PAG 64 250 213.0 191.0 55.0 MSC1212Y4PAGT TQFP PAG 64 250 213.0 191.0 55.0 MSC1212Y5PAGT TQFP PAG 64 250 213.0 191.0 55.0 MSC1213Y2PAGT TQFP PAG 64 250 213.0 191.0 55.0 MSC1213Y3PAGT TQFP PAG 64 250 213.0 191.0 55.0 MSC1213Y4PAGT TQFP PAG 64 250 213.0 191.0 55.0 MSC1213Y5PAGT TQFP PAG 64 250 213.0 191.0 55.0 MSC1214Y3PAGT TQFP PAG 64 250 213.0 191.0 55.0 MSC1214Y4PAGT TQFP PAG 64 250 213.0 191.0 55.0 MSC1214Y5PAGR TQFP PAG 64 1500 350.0 350.0 43.0 MSC1214Y5PAGT TQFP PAG 64 250 213.0 191.0 55.0 PackMaterials-Page2

MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 M 0,17 48 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 0,25 SQ 0,05 MIN 11,80 0°–7° 1,05 0,95 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282/C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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