MRF24J40 Data Sheet IEEE 802.15.4™ 2.4 GHz RF Transceiver Preliminary © 2010 Microchip Technology Inc. DS39776C

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-459-9 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary DS39776C-page 2 © 2010 Microchip Technology Inc.

MRF24J40 IEEE 802.15.4™ 2.4 GHz RF Transceiver Features: RF/Analog Features: • IEEE 802.15.4™ Standard Compliant • ISM Band 2.405-2.48 GHz Operation RF Transceiver • Data Rate: 250 kbps (IEEE 802.15.4); • Supports ZigBee®, MiWi™, MiWi P2P and 625 kbps (Turbo mode) Proprietary Wireless Networking Protocols • -95 dBm Typical Sensitivity with +5 dBm • Simple, 4-Wire Serial Peripheral Interface (SPI) Maximum Input Level • Integrated 20 MHz and 32.768 kHz Crystal • +0 dBm Typical Output Power with 36 dB Oscillator Circuitry TX Power Control Range • Low-Current Consumption: • Differential RF Input/Output with Integrated TX/RX Switch - RX mode: 19 mA (typical) • Integrated Low Phase Noise VCO, Frequency - TX mode: 23 mA (typical) Synthesizer and PLL Loop Filter - Sleep: 2μ A (typical) • Digital VCO and Filter Calibration • Small, 40-Pin Leadless QFN 6x6 mm2 Package • Integrated RSSI ADC and I/Q DACs • Integrated LDO • High Receiver and RSSI Dynamic Range MAC/Baseband Features: • Hardware CSMA-CA Mechanism, Automatic Acknowledgement Response and FCS Check • Independent Beacon, Transmit and GTS FIFO • Supports all CCA modes and RSSI/ED • Automatic Packet Retransmit Capability • Hardware Security Engine (AES-128) with CTR, CCM and CBC-MAC modes • Supports Encryption and Decryption for MAC Sublayer and Upper Layer Pin Diagram: 40-Pin QFN P 12 CA DDCDDND DDSCSC DD DD LVNVGVOOVV 40393837363534333231 VDD 1 30 NC RFP 2 29 NC RFN 3 28 LPOSC1 VDD 4 27 LPOSC2 VDD 5 MRF24J40 26 NC GND 6 25 GND GPIO0 7 24 GND GPIO1 8 23 NC GPIO5 9 22 GND GPIO4 10 21 VDD 11121314151617181920 Note: Backside center pad is GND. GPIO2GPIO3RESETGNDWAKEINTSDOSDISCKCS Preliminary © 2010 Microchip Technology Inc. DS39776C-page 3

MRF24J40 1.0 Overview......................................................................................................................................................................................5 2.0 Hardware Description...................................................................................................................................................................7 3.0 Functional Description................................................................................................................................................................89 4.0 Applications..............................................................................................................................................................................135 5.0 Electrical Characteristics..........................................................................................................................................................141 6.0 Packaging Information..............................................................................................................................................................145 Appendix A: Revision History.............................................................................................................................................................147 Index..................................................................................................................................................................................................149 The Microchip Web Site.....................................................................................................................................................................153 Customer Change Notification Service..............................................................................................................................................153 Customer Support..............................................................................................................................................................................153 Reader Response..............................................................................................................................................................................154 Product Identification System.............................................................................................................................................................155 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. Preliminary DS39776C-page 4 © 2010 Microchip Technology Inc.

MRF24J40 1.0 OVERVIEW • Three CCA Modes • CSMA-CA Algorithm The MRF24J40 is an IEEE 802.15.4™ Standard com- • Automatic Packet Retransmission pliant 2.4 GHz RF transceiver. It integrates the PHY and MAC functionality in a single chip solution. • Automatic Acknowledgment Figure 1-1 shows a simplified block diagram of a • Independent Transmit, Beacon and GTS FIFO MRF24J40 wireless node. The MRF24J40 creates a Buffers low-cost, low-power, low data rate (250 or 625 kbps) • Security Engine supports Encryption and Wireless Personal Area Network (WPAN) device. The Decryption for MAC Sublayer and Upper Layer MRF24J40 interfaces to many popular Microchip PIC® These features reduce the processing load, allowing microcontrollers via a 4-wire serial SPI interface, the use of low-cost 8-bit microcontrollers. interrupt, wake and Reset pins. The MRF24J40 is compatible with Microchip's The MRF24J40 provides hardware support for: ZigBee®, MiWi™ and MiWi P2P software stacks. Each • Energy Detection software stack is available as a free download, includ- • Carrier Sense ing source code, from the Microchip web site: http://www.microchip.com/wireless. FIGURE 1-1: WIRELESS NODE BLOCK DIAGRAM Antenna MRF24J40 PIC® MCU CS I/O e SDI SDO Matching RFP ac Circuitry RFN PHY MAC nterf SDO SDI I SCK SCK INT INTx Power Memory WAKE I/O Management RESET I/O 20 MHz Crystal Preliminary © 2010 Microchip Technology Inc. DS39776C-page 5

MRF24J40 1.1 IEEE 802.15.4-2003 Standard It is highly recommended that the design engineer be familiar with the IEEE 802.15.4-2003 Standard in order The MRF24J40 is compliant with the to best understand the configuration and operation of the IEEE 802.15.4™-2003 Standard. The Standard speci- MRF24J40. The Standard can be downloaded from the fies the physical (PHY) and Media Access Controller IEEE web site: http://www.ieee.org. (MAC) functions that form the basis for a wireless net- work device. Figure 1-2 shows the structure of the PHY packet and MAC frame. FIGURE 1-2: IEEE 802.15.4™ PHY PACKET AND MAC FRAME STRUCTURE 2 1 2 octets MAC Sublayer Acknowledgment Frame Sequence FCS Frame Control Number MHR MFR 2 1 4 to 20 n 2 octets MAC Sublayer Data Frame Sequence Adressing Data Payload FCS Frame Control Number Fields MHR MSDU MFR 2 1 4 to 20 1 n 2 octets MAC Sublayer MAC Command Frame Sequence Adressing Command Command Payload FCS Frame Control Number Fields Type MHR MSDU MFR 2 1 4 or 10 2 k m n 2 octets MAC Sublayer BFeraamcoen CForanmtroel SNeuqmuebnecre AdFrieesldssing SSpuepceifrifcraamtioen FGieTldSs PAFedindedrledinssgs Beacon Payload FCS MHR MSDU MFR 4 1 1 5 – 127 octets Frame PHY Layer Preamble SFD Length PSDU SHR PHR PHY Payload On air PPDU packet Preliminary DS39776C-page 6 © 2010 Microchip Technology Inc.

MRF24J40 2.0 HARDWARE DESCRIPTION Six General Purpose Input/Output (GPIO) pins can be configured for control or monitoring purposes. They can also be configured to control external PA/LNA RF 2.1 2.1 Overview switches. The MRF24J40 is an IEEE 802.15.4 Standard The power management circuitry consists of an compliant 2.4 GHz RF transceiver. It integrates the integrated Low Dropout (LDO) voltage regulator. The PHY and MAC functionality in a single chip solution. MRF24J40 can be placed into a very low-current (2 μA Figure 2-1 is a block diagram of the MRF24J40 typical) Sleep mode. An internal 100 kHz oscillator or circuitry. 32 kHz external crystal oscillator can be used for Sleep A frequency synthesizer is clocked by an external mode timing. 20 MHz crystal and generates a 2.4 GHz RF frequency. The Media Access Controller (MAC) circuitry verifies The receiver is a low-IF architecture consisting of a Low reception and formats for transmission IEEE 802.15.4 Noise Amplifier (LNA), down conversion mixers, poly- Standard compliant packets. Data is buffered in Trans- phase channel filters and baseband limiting amplifiers mit and Receive FIFOs. Carrier Sense Multiple with a Receiver Signal Strength Indicator (RSSI). Access-Collision Avoidance (CSMA-CA), superframe constructor, receive frame filter and security engine The transmitter is a direct conversion architecture with functionality are implemented in hardware. The a 0 dBm maximum output (typical) and 36 dB power security engine provides hardware circuitry for control range. AES-128 with CTR, CCM and CBC-MAC modes. An internal Transmit/Receive (TR) switch combines the Control of the transceiver is via a 4-wire SPI, interrupt, transmitter and receiver circuits into differential RFP wake and Reset pins. and RFN pins. These pins are connected to impedance matching circuitry (balun) and antenna. An external Power Amplifier (PA) and/or LNA can be controlled via the GPIO pins. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 7

MRF24J40 2.2 Block Diagram FIGURE 2-1: MRF24J40 ARCHITECTURE BLOCK DIAGRAM SPI INT WAKE RESET GPIO 4 6 e c a erf nt I ControlRegisters Security Key FIFO Y R O M Interrupts ME RXFIFO TXNFIFO TXBFIFO TXG1FIFO TXG2FIFO C MA MAC FrameChecker C PacketRetriever CSMA-CA SecurityEngine X A R M FCSChecker TX FCSGenerator SuperframeStateMachine PowerManagement d d n n Xba Xba RBase TBase CK 100 kHzInternalOscillator O L C ADC SIADC ADC DAC DAC SLEEP 32 kHz CrystalOscillator PHY FilterRS FrequencySynthesizer 20MHz CrystalOscillator LNA PA F R Preliminary DS39776C-page 8 © 2010 Microchip Technology Inc.

MRF24J40 2.3 Pin Descriptions TABLE 2-1: MRF24J40 PIN DESCRIPTIONS Pin Symbol Type Description 1 VDD Power RF power supply. Bypass with a capacitor as close to the pin as possible. 2 RFP AIO Differential RF input/output (+). 3 RFN AIO Differential RF input/output (-). 4 VDD Power RF power supply. Bypass with a capacitor as close to the pin as possible. 5 VDD Power Guard ring power supply. Bypass with a capacitor as close to the pin as possible. 6 GND Ground Guard ring ground. 7 GPIO0 DIO General purpose digital I/O, also used as external PA enable. 8 GPIO1 DIO General purpose digital I/O, also used as external TX/RX switch control. 9 GPIO5 DIO General purpose digital I/O. 10 GPIO4 DIO General purpose digital I/O. 11 GPIO2 DIO General purpose digital I/O, also used as external TX/RX switch control. 12 GPIO3 DIO General purpose digital I/O. 13 RESET DI Global hardware Reset pin active-low. 14 GND Ground Ground for digital circuit. 15 WAKE DI External wake-up trigger (must be enabled in software). 16 INT DO Interrupt pin to microcontroller. 17 SDO DO Serial interface data output from MRF24J40. 18 SDI DI Serial interface data input to MRF24J40. 19 SCK DI Serial interface clock. 20 CS DI Serial interface enable. 21 VDD Power Digital circuit power supply. Bypass with a capacitor as close to the pin as possible. 22 GND Ground Ground for digital circuit. 23 NC — No Connection. 24 GND Ground Ground for digital circuit. 25 GND Ground Ground for digital circuit. 26 NC — No Connection. (Allow pin to float; do not connect signal.) 27 LPOSC2 AI 32 kHz crystal input. 28 LPOSC1 AI 32 kHz crystal input. 29 NC — No Connection. (Allow pin to float; do not connect signal.) 30 NC — No Connection. (Allow pin to float; do not connect signal.) 31 VDD Power Power supply for band gap reference circuit. Bypass with a capacitor as close to the pin as possible. 32 VDD Power Power supply for analog circuit. Bypass with a capacitor as close to the pin as possible. 33 OSC2 AI 20 MHz crystal input. 34 OSC1 AI 20 MHz crystal input. 35 VDD Power PLL power supply. Bypass with a capacitor as close to the pin as possible. 36 GND Ground Ground for PLL. 37 VDD Power Charge pump power supply. Bypass with a capacitor as close to the pin as possible. 38 NC — No Connection. 39 VDD Power VCO supply. Bypass with a capacitor as close to the pin as possible. 40 LCAP — PLL loop filter external capacitor. Connected to external 100 pF capacitor. Legend: A = Analog, D = Digital, I = Input, O = Output Preliminary © 2010 Microchip Technology Inc. DS39776C-page 9

MRF24J40 2.4 Power and Ground Pins FIGURE 2-2: 20 MHz MAIN OSCILLATOR CRYSTAL Recommended bypass capacitors are listed in CIRCUIT Table 2-2. VDD pins 1 and 31 require two bypass capacitors to ensure sufficient bypass decoupling. Min- CL2 imize trace length from the VDD pin to the bypass OSC2 capacitors and make them as short as possible. TABLE 2-2: RECOMMENDED BYPASS 20 MHz X1 Main Oscillator CAPACITOR VALUES VDD Pin Bypass Capacitor 1 47 pF and 0.01 μF CL1 OSC1 4 47 pF 5 0.1 μF 21 0.01 μF 2.6 Phase-Locked Loop 31 47 pF and 0.01 μF 32 47 pF The Phase-Locked Loop (PLL) circuitry requires one 35 47 pF external capacitor connected to pin 40 (LCAP). The recommended value is 100 pF. The PCB layout around 37 0.01 μF the capacitor and pin 40 should be designed carefully 39 1 μF such as to minimize interference to the PLL. 2.7 32 kHz External Crystal Oscillator 2.5 20 MHz Main Oscillator The 32 kHz external crystal oscillator provides one of two The 20 MHz main oscillator provides the main Sleep clock (SLPCLK) frequencies to Sleep mode frequency (MAINCLK) signal to internal RF, baseband counters. The Sleep mode counters time the Beacon and MAC circuitry. An external 20 MHz quartz crystal is Interval (BI) and inactive period for a beacon-enabled connected to the OSC1 and OSC2 pins as shown in device and the Sleep interval for a nonbeacon-enabled Figure 2-2. The crystal parameters are listed in device. Refer to Section 3.15 “Sleep” for more Table 2-3. information. TABLE 2-3: 20 MHz CRYSTAL The SLPCLK frequency is selectable between the 32 PARAMETERS(1) kHz external crystal oscillator or 100 kHz internal oscil- lator. The 32 kHz external crystal oscillator provides Parameter Value better frequency accuracy and stability than the 100 Frequency 20 MHz kHz internal oscillator. An external 32 kHz tuning fork crystal is connected to the LPOSC1 and LPOSC2 pins, Frequency Tolerance at 25°C ±20 ppm(2) as shown in Figure 2-3. The crystal parameters are Frequency Stability over Operating ±20 ppm(2) listed in Table 2-4. Temperature Range Mode Fundamental TABLE 2-4: 32 kHz CRYSTAL Load Capacitance 10-15 pF PARAMETERS(1) ESR 80Ω max. Parameter Value Note 1: These values are for design guidance only. Frequency 32.768 kHz 2: IEEE 802.15.4™ Standard specifies Frequency Tolerance ±20 ppm transmitted center frequency tolerance Load Capacitance 12.5 pF shall be ±40 ppm maximum. ESR 70 kΩ max. Note 1: These values are for design guidance only. Preliminary DS39776C-page 10 © 2010 Microchip Technology Inc.

MRF24J40 FIGURE 2-3: 32 kHz EXTERNAL OSCILLATOR CRYSTAL Note: The INT pin will remain high or low, CIRCUIT depending on INTEDGE polarity setting, until INSTAT register is read. CL22 LPOSC2 2.11 Wake (WAKE) Pin 32 kHz The Wake (WAKE) pin 15 provides an external External X2 Crystal wake-up signal to the MRF24J40 from the host micro- Oscillator controller. It is used in conjunction with the Sleep modes of the MRF24J40. The WAKE pin is disabled by default. Refer to Section 3.15.2 “Immediate Sleep LPOSC1 CL11 and Wake-up Mode” for a functional description of the Immediate Sleep and Wake-up modes. 2.12 General Purpose Input/Output 2.8 100 kHz Internal Oscillator (GPIO) Pins The 100 kHz internal oscillator requires no external components and provides one of two Sleep clock Six GPIO pins can be configured individually for control (SLPCLK) frequencies to Sleep mode counters. The or monitoring purposes. Input or output selection is Sleep mode counters time the Beacon Interval (BI) and configured by the TRISGPIO (0x34) register. GPIO inactive period for a beacon-enabled device and the data can be read/written to via the GPIO (0x33) Sleep interval for a nonbeacon-enabled device. Refer register. to Section 3.15 “Sleep” for more information. The GPIO pins have limited output drive capability. The SLPCLK frequency is selectable between the Table 2-5 lists the individual GPIO pin source current 32 kHz external crystal oscillator or 100 kHz internal limits. oscillator. The 32 kHz external crystal oscillator provides better frequency accuracy and stability than TABLE 2-5: GPIO SOURCE CURRENT the 100 kHz internal oscillator. It is recommended that LIMITS the 100 kHz internal oscillator be calibrated before use. Pin Maximum Current Sourced The calibration procedure is given in Section 3.15.1.2 “Sleep Clock Calibration”. GPIO0 4 mA GPIO1 1 mA 2.9 Reset (RESET) Pin GPIO2 1 mA An external hardware Reset can be performed by GPIO3 1 mA asserting the RESET pin 13 low. The MRF24J40 will be GPIO4 1 mA released from Reset approximately 250 μs after the GPIO5 1 mA RESET pin is released. The RESET pin has an internal weak pull-up resistor. GPIO0, GPIO1 and GPIO2 can be configured to control external PA, LNA and RF switches by the internal RF 2.10 Interrupt (INT) Pin state machine. This allows the external PA and LNA to The Interrupt (INT) pin 16 provides an interrupt signal be controlled by the MRF24J40 without any host micro- to the host microcontroller from the MRF24J40. The controller intervention. Refer to Section 4.2 “External polarity is configured via the INTEDGE bit in the PA/LNA Control” for control register configuration, SLPCON0 (0x211<1>) register. Interrupts have to be timing diagrams and application information. enabled and unmasked before the INT pin is active. Refer to Section 3.3 “Interrupts” for a functional description of interrupts. Note: The INTEDGE polarity defaults to, 0 = Falling Edge. Ensure that the interrupt polarity matches the interrupt pin polarity on the host microcontroller. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 11

MRF24J40 2.13 Serial Peripheral Interface (SPI) Note: The SDO pin 17 defaults to a low state Port Pins when CS is high (the MRF24J40 is not selected). If the MRF24J40 is to share a The MRF24J40 communicates with a host micro- SPI bus, a tri-state buffer should be placed controller via a 4-wire SPI port as a slave device. The on the SDO signal to provide a MRF24J40 supports SPI (mode 0,0) which requires high-impedance signal to the SPI bus. See that SCK idles in a low state. The CS pin must be held Section 4.4 “MRF24J40 Schematic and low while communicating with the MRF24J40. Bill of Materials” for an example Figure 2-4 shows timing for a write operation. Data is application circuit. received by the MRF24J40 via the SDI pin and is clocked in on the rising edge of SCK. Figure 2-5 shows timing for a read operation. Data is sent by the MRF24J40 via the SDO pin and is clocked out on the falling edge of SCK. FIGURE 2-4: SPI PORT WRITE (INPUT) TIMING CS SCK SDI MSb LSb SDO FIGURE 2-5: SPI PORT READ (OUTPUT) TIMING CS SCK SDI SDO MSb LSb Preliminary DS39776C-page 12 © 2010 Microchip Technology Inc.

MRF24J40 2.14 Memory Organization provide control, status and device addressing for MRF24J40 operations. FIFOs serve as temporary Memory in the MRF24J40 is implemented as static buffers for data transmission, reception and security RAM and is accessible via the SPI port. Memory is keys. Memory is accessed via two addressing functionally divided into control registers and data buf- methods: Short and Long. fers (FIFOs), as shown in Figure 2-6. Control registers FIGURE 2-6: MEMORY MAP FOR MRF24J40 Short Address Long Address Memory Space Memory Space 0x00 0x000 Control Registers 64 bytes 0x3F TX Normal FIFO 128 bytes 0x07F 0x080 TX Beacon FIFO 128 bytes 0x0FF 0x100 TX GTS1 FIFO 128 bytes 0x17F 0x180 TX GTS2 FIFO 128 bytes 0x1FF 0x200 Control Registers 128 bytes 0x27F 0x280 Security Key FIFO 64 bytes 0x2BF 0x2C0 Reserved 0x2FF 0x300 RX FIFO 144 bytes 0x38F Preliminary © 2010 Microchip Technology Inc. DS39776C-page 13

MRF24J40 2.14.1 SHORT ADDRESS REGISTER begins with a ‘0’ to indicate a short address transaction. INTERFACE It is followed by the 6-bit register address, Most Signif- icant bit (MSb) first. The 8th bit indicates if it is a read The short address memory space contains control (‘0’) or write (‘1’) transaction. registers with a 6-bit address range of 0x00 to 0x3F. Figure 2-7 shows a short address read and Figure 2-8 shows a short address write. The 8-bit SPI transfer FIGURE 2-7: SHORT ADDRESS READ CS SCK SDI 0 A5 A4 A3 A2 A1 A0 0 X SDO D7 D6 D5 D4 D3 D2 D1 D0 FIGURE 2-8: SHORT ADDRESS WRITE CS SCK SDI 0 A5 A4 A3 A2 A1 A0 1 D7 D6 D5 D4 D3 D2 D1 D0 SDO Preliminary DS39776C-page 14 © 2010 Microchip Technology Inc.

MRF24J40 2.14.2 LONG ADDRESS REGISTER SPI transfer begins with a ‘1’ to indicate a long address INTERFACE transaction. It is followed by the 10-bit register address, Most Significant bit (MSb) first. The 12th bit indicates if The long address memory space contains control it is a read (‘0’) or write (‘1’) transaction. registers and FIFOs with a 10-bit address range of 0x000 to 0x38F. Figure 2-9 shows a long address read and Figure 2-10 shows a long address write. The 12-bit FIGURE 2-9: LONG ADDRESS READ CS SCK SDI 1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 X SDO D7 D6 D5 D4 D3 D2 D1 D0 FIGURE 2-10: LONG ADDRESS WRITE CS SCK SDI 1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 X D7 D6 D5 D4 D3 D2 D1 D0 SDO Preliminary © 2010 Microchip Technology Inc. DS39776C-page 15

MRF24J40 2.15 Control Register Description Control registers provide control, status and device addressing for MRF24J40 operations. The following figures, tables and register definitions describe the control register operation. 2.15.1 CONTROL REGISTER MAP FIGURE 2-11: SHORT ADDRESS CONTROL REGISTER MAP FOR MRF24J40 0x00 RXMCR 0x10 ORDER 0x20 ESLOTG67 0x30 RXSR 0x01 PANIDL 0x11 TXMCR 0x21 TXPEND 0x31 INTSTAT 0x02 PANIDH 0x12 ACKTMOUT 0x22 WAKECON 0x32 INTCON 0x03 SADRL 0x13 ESLOTG1 0x23 FRMOFFSET 0x33 GPIO 0x04 SADRH 0x14 SYMTICKL 0x24 TXSTAT 0x34 TRISGPIO 0x05 EADR0 0x15 SYMTICKH 0x25 TXBCON1 0x35 SLPACK 0x06 EADR1 0x16 PACON0 0x26 GATECLK 0x36 RFCTL 0x07 EADR2 0x17 PACON1 0x27 TXTIME 0x37 SECCR2 0x08 EADR3 0x18 PACON2 0x28 HSYMTMRL 0x38 BBREG0 0x09 EADR4 0x19 Reserved 0x29 HSYMTMRH 0x39 BBREG1 0x0A EADR5 0x1A TXBCON0 0x2A SOFTRST 0x3A BBREG2 0x0B EADR6 0x1B TXNCON 0x2B Reserved 0x3B BBREG3 0x0C EADR7 0x1C TXG1CON 0x2C SECCON0 0x3C BBREG4 0x0D RXFLUSH 0x1D TXG2CON 0x2D SECCON1 0x3D Reserved 0x0E Reserved 0x1E ESLOTG23 0x2E TXSTBL 0x3E BBREG6 0x0F Reserved 0x1F ESLOTG45 0x2F Reserved 0x3F CCAEDTH FIGURE 2-12: LONG ADDRESS CONTROL REGISTER MAP FOR MRF24J40 0x200 RFCON0 0x210 RSSI 0x220 SLPCON1 ox230 ASSOEADR0 0x240 UPNONCE0 0x201 RFCON1 0x211 SLPCON0 0x221 Reserved 0x231 ASSOEADR1 0x241 UPNONCE1 0x202 RFCON2 0x212 Reserved 0x222 WAKETIMEL 0x232 ASSOEADR2 0x242 UPNONCE2 0x203 RFCON3 0x213 Reserved 0x223 WAKETIMEH 0x233 ASSOEADR3 0x243 UPNONCE3 0x204 Reserved 0x214 Reserved 0x224 REMCNTL 0x234 ASSOEADR4 0x244 UPNONCE4 0x205 RFCON5 0x215 Reserved 0x225 REMCNTH 0x235 ASSOEADR5 0x245 UPNONCE5 0x206 RFCON6 0x216 Reserved 0x226 MAINCNT0 0x236 ASSOEADR6 0x246 UPNONCE6 0x207 RFCON7 0x217 Reserved 0x227 MAINCNT1 0x237 ASSOEADR7 0x247 UPNONCE7 0x208 RFCON8 0x218 Reserved 0x228 MAINCNT2 0x238 ASSOSADR0 0x248 UPNONCE8 0x209 SLPCAL0 0x219 Reserved 0x229 MAINCNT3 0x239 ASSOSADR1 0x249 UPNONCE9 0x20A SLPCAL1 0x21A Reserved 0x22A Reserved 0x23A Reserved 0x24A UPNONCE10 0x20B SLPCAL2 0x21B Reserved 0x22B Reserved 0x23B Reserved 0x24B UPNONCE11 0x20C Reserved 0x21C Reserved 0x22C Reserved 0x23C Unimplemented 0x24C UPNONCE12 0x20D Reserved 0x21D Reserved 0x22D Reserved 0x23D Unimplemented 0x20E Reserved 0x21E Reserved 0x22E Reserved 0x23E Unimplemented 0x20F RFSTATE 0x21F Reserved 0x22F TESTMODE 0x23F Unimplemented Preliminary DS39776C-page 16 © 2010 Microchip Technology Inc.

MRF24J40 2.15.2 CONTROL REGISTER SUMMARY TABLE 2-6: SHORT ADDRESS CONTROL REGISTER SUMMARY FOR MRF24J40 Details Value on Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR Page: 0x00 RXMCR r r NOACKRSP r PANCOORD COORD ERRPKT PROMI 0000 22 0000 0x01 PANIDL PAN ID Low Byte (PANIDL<7:0>) 0000 23 0000 0x02 PANIDH PAN ID High Byte (PANIDH<15:8>) 0000 23 0000 0x03 SADRL Short Address Low Byte (SADRL<7:0>) 0000 24 0000 0x04 SADRH Short Address High Byte (SADRH<15:8>) 0000 24 0000 0x05 EADR0 64-Bit Extended Address bits (EADR0<7:0>) 0000 25 0000 0x06 EADR1 64-Bit Extended Address bits (EADR1<15:8>) 0000 25 0000 0x07 EADR2 64-Bit Extended Address bits (EADR2<23:16>) 0000 25 0000 0x08 EADR3 64-Bit Extended Address bits (EADR3<31:24>) 0000 26 0000 0x09 EADR4 64-Bit Extended Address bits (EADR4<39:32>) 0000 26 0000 0x0A EADR5 64-Bit Extended Address bits (EADR5<47:40>) 0000 26 0000 0x0B EADR6 64-Bit Extended Address bits (EADR6<55:48>) 0000 27 0000 0x0C EADR7 64-Bit Extended Address bits (EADR7<63:56>) 0000 27 0000 0x0D RXFLUSH r WAKEPOL WAKEPAD r CMDONLY DATAONLY BCNONLY RXFLUSH 0000 28 0000 0x0E Reserved r r r r r r r r 0000 — 0000 0x0F Reserved r r r r r r r r 0000 — 0000 0x10 ORDER BO3 BO2 BO1 BO0 SO3 SO2 SO1 SO0 1111 29 1111 0x11 TXMCR NOCSMA BATLIFEXT SLOTTED MACMINBE1 MACMINBE0 CSMABF2 CSMABF1 CSMABF0 0001 30 1100 0x12 ACKTMOUT DRPACK MAWD6 MAWD5 MAWD4 MAWD3 MAWD2 MAWD1 MAWD0 0011 31 1001 0x13 ESLOTG1 GTS1-3 GTS1-2 GTS1-1 GTS1-0 CAP3 CAP2 CAP1 CAP0 0000 32 0000 0x14 SYMTICKL TICKP7 TICKP6 TICKP5 TICKP4 TICKP3 TICKP2 TICKP1 TICKP0 0100 33 0000 0x15 SYMTICKH TXONT6 TXONT5 TXONT4 TXONT3 TXONT2 TXONT1 TXONT0 TICKP8 0101 33 0001 0x16 PACON0 PAONT7 PAONT6 PAONT5 PAONT4 PAONT3 PAONT2 PAONT1 PAONT0 0010 34 1001 0x17 PACON1 r r r PAONTS3 PAONTS2 PAONTS1 PAONTS0 PAONT8 0000 34 0010 0x18 PACON2 FIFOEN r TXONTS3 TXONTS2 TXONTS1 TXONTS0 TXONT8 TXONT7 1000 35 1000 0x19 Reserved r r r r r r r r 0000 — 0000 0x1A TXBCON0 r r r r r r TXBSECEN TXBTRIG 0000 36 0000 0x1B TXNCON r r r FPSTAT INDIRECT TXNACKREQ TXNSECEN TXNTRIG 0000 37 0000 0x1C TXG1CON TXG1RETRY1 TXG1RETRY0 TXG1SLOT2 TXG1SLOT1 TXG1SLOT0 TXG1ACKREQ TXG1SECEN TXG1TRIG 0000 38 0000 0x1D TXG2CON TXG2RETRY1 TXG2RETRY0 TXG2SLOT2 TXG2SLOT1 TXG2SLOT0 TXG2ACKREQ TXG2SECEN TXG2TRIG 0000 38 0000 Legend: r = reserved Preliminary © 2010 Microchip Technology Inc. DS39776C-page 17

MRF24J40 TABLE 2-6: SHORT ADDRESS CONTROL REGISTER SUMMARY FOR MRF24J40 (CONTINUED) Details Value on Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR Page: 0x1E ESLOTG23 GTS3-3 GTS3-2 GTS3-1 GTS3-0 GTS2-3 GTS2-2 GTS2-1 GTS2-0 0000 39 0000 0x1F ESLOTG45 GTS5-3 GTS5-2 GTS5-1 GTS5-0 GTS4-3 GTS4-2 GTS4-1 GTS4-0 0000 39 0000 0x20 ESLOTG67 r r r r GTS6-3 GTS6-2 GTS6-1 GTS6-0 0000 39 0000 0x21 TXPEND MLIFS5 MLIFS4 MLIFS3 MLIFS2 MLIFS1 MLIFS0 GTSSWITCH FPACK 1000 40 0100 0x22 WAKECON IMMWAKE REGWAKE INTL INTL INTL INTL INTL INTL 0000 41 0000 0x23 FRMOFFSET OFFSET7 OFFSET6 OFFSET5 OFFSET4 OFFSET3 OFFSET2 OFFSET1 OFFSET0 0000 42 0000 0x24 TXSTAT TXNRETRY1 TXNRETRY0 CCAFAIL TXG2FNT TXG1FNT TXG2STAT TXG1STAT TXNSTAT 0000 43 0000 0x25 TXBCON1 TXBMSK WU/BCN RSSINUM1 RSSINUM0 r r r r 0011 44 0000 0x26 GATECLK r r r r GTSON r r r 0000 45 0000 0x27 TXTIME TURNTIME3 TURNTIME2 TURNTIME1 TURNTIME0 r r r r 0100 46 1000 0x28 HSYMTMRL HSYMTMR7 HSYMTMR6 HSYMTMR5 HSYMTMR4 HSYMTMR3 HSYMTMR2 HSYMTMR1 HSYMTMR0 0000 47 0000 0x29 HSYMTMRH HSYMTMR15 HSYMTMR14 HSYMTMR13 HSYMTMR12 HSYMTMR11 HSYMTMR10 HSYMTMR09 HSYMTMR08 0000 47 0000 0x2A SOFTRST r r r r r RSTPWR RSTBB RSTMAC 0000 48 0000 0x2B Reserved r r r r r r r r 0000 — 0000 0x2C SECCON0 SECIGNORE SECSTART RXCIPHER2 RXCIPHER1 RXCIPHER0 TXNCIPHER2 TXNCIPHER1 TXNCIPHER0 0000 49 0000 0x2D SECCON1 r TXBCIPHER2 TXBCIPHER1 TXBCIPHER0 r r DISDEC DISENC 0000 50 0000 0x2E TXSTBL RFSTBL3 RFSTBL2 RFSTBL1 RFSTBL0 MSIFS3 MSIFS2 MSIFS1 MSIFS0 0111 51 0101 0x2F Reserved r r r r r r r r 0000 — 0000 Legend: r = reserved Preliminary DS39776C-page 18 © 2010 Microchip Technology Inc.

MRF24J40 TABLE 2-6: SHORT ADDRESS CONTROL REGISTER SUMMARY FOR MRF24J40 (CONTINUED) Details Value on Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR Page: 0x30 RXSR r UPSECERR BATIND r r SECDECERR r r 0000 52 0000 0x31 INTSTAT SLPIF WAKEIF HSYMTMRIF SECIF RXIF TXG2IF TXG1IF TXNIF 0000 53 0000 0x32 INTCON SLPIE WAKEIE HSYMTMRIE SECIE RXIE TXG2IE TXG1IE TXNIE 1111 54 1111 0x33 GPIO r r GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 0000 55 0000 0x34 TRISGPIO r r TRISGP5 TRISGP4 TRISGP3 TRISGP2 TRISGP1 TRISGP0 0000 55 0000 0x35 SLPACK SLPACK WAKECNT6 WAKECNT5 WAKECNT4 WAKECNT3 WAKECNT2 WAKECNT1 WAKECNT0 0000 56 0000 0x36 RFCTL r r r WAKECNT8 WAKECNT7 RFRST RFTXMODE RFRXMODE 0000 57 0000 0x37 SECCR2 UPDEC UPENC TXG2CIPHER2 TXG2CIPHER1 TXG2CIPHER0 TXG1CIPHER2 TXG1CIPHER1 TXG1CIPHER0 0000 58 0000 0x38 BBREG0 r r r r r r r TURBO 0000 59 0000 0x39 BBREG1 r r r r r RXDECINV r r 0000 59 0000 0x3A BBREG2 CCAMODE1 CCAMODE0 CCACSTH3 CCACSTH2 CCACSTH1 CCACSTH0 r r 0100 60 1000 0x3B BBREG3 PREVALIDTH3 PREVALIDTH2 PREVALIDTH1 PREVALIDTH0 PREDETTH2 PREDETTH1 PREDETTH0 r 1101 60 1000 0x3C BBREG4 CSTH2 CSTH1 CSTH0 PRECNT2 PRECNT1 PRECNT0 r r 1001 61 1100 0x3D Reserved r r r r r r r r 0000 — 0000 0x3E BBREG6 RSSIMODE1 RSSIMODE2 r r r r r RSSIRDY 0000 61 0001 0x3F CCAEDTH CCAEDTH7 CCAEDTH6 CCAEDTH5 CCAEDTH4 CCAEDTH3 CCAEDTH2 CCAEDTH1 CCAEDTH0 0000 62 0000 Legend: r = reserved TABLE 2-7: LONG ADDRESS CONTROL REGISTER SUMMARY FOR MRF24J40 Details Value on Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR Page: 0x200 RFCON0 CHANNEL3 CHANNEL2 CHANNEL1 CHANNEL0 RFOPT3 RFOPT2 RFOPT1 RFOPT0 0000 0000 63 0x201 RFCON1 VCOOPT7 VCOOPT6 VCOOPT5 VCOOPT4 VCOOPT3 VCOOPT2 VCOOPT1 VCOOPT0 0000 0000 63 0x202 RFCON2 PLLEN r r r r r r r 0000 0000 64 0x203 RFCON3 TXPWRL1 TXPWRL0 TXPWRS2 TXPWRS1 TXPWRS0 r r r 0000 0000 64 0x204 Reserved r r r r r r r r 0000 0000 — 0x205 RFCON5 BATTH3 BATTH2 BATTH1 BATTH0 r r r r 0000 0000 65 0x206 RFCON6 TXFIL r r 20MRECVR BATEN r r r 0000 0000 65 0x207 RFCON7 SLPCLKSEL1 SLPCLKSEL0 r r r r CLKOUTMODE1 CLKOUTMODE0 0000 0000 66 0x208 RFCON8 r r r RFVCO r r r r 0000 0000 66 0x209 SLPCAL0 SLPCAL7 SLPCAL6 SLPCAL5 SLPCAL4 SLPCAL3 SLPCAL2 SLPCAL1 SLPCAL0 0000 0000 67 0x20A SLPCAL1 SLPCAL15 SLPCAL14 SLPCAL13 SLPCAL12 SLPCAL11 SLPCAL10 SLPCAL9 SLPCAL8 0000 0000 67 0x20B SLPCAL2 SLPCALRDY r r SLPCALEN SLPCAL19 SLPCAL18 SLPCAL17 SLPCAL16 0000 0000 68 0x20C Reserved r r r r r r r r 0000 0000 — 0x20D Reserved r r r r r r r r 0000 0000 — 0x20E Reserved r r r r r r r r 0000 0000 — 0x20F RFSTATE RFSTATE2 RFSTATE1 RFSTATE0 r r r r r 0000 0000 69 0x210 RSSI RSSI7 RSSI6 RSSI5 RSSI4 RSSI3 RSSI2 RSSI1 RSSI0 0000 0000 69 0x211 SLPCON0 r r r r r r INTEDGE SLPCLKEN 0000 0000 70 0x212 Reserved r r r r r r r r 0000 0000 — Legend: r = reserved Preliminary © 2010 Microchip Technology Inc. DS39776C-page 19

MRF24J40 TABLE 2-7: LONG ADDRESS CONTROL REGISTER SUMMARY FOR MRF24J40 (CONTINUED) Details Value on Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR Page: 0x213 Reserved r r r r r r r r 0000 0000 — 0x214 Reserved r r r r r r r r 0000 0000 — 0x215 Reserved r r r r r r r r 0000 0000 — 0x216 Reserved r r r r r r r r 0000 0000 — 0x217 Reserved r r r r r r r r 0000 0000 — 0x218 Reserved r r r r r r r r 0000 0000 — 0x219 Reserved r r r r r r r r 0000 0000 — 0x21A Reserved r r r r r r r r 0000 0000 — 0x21B Reserved r r r r r r r r 0000 0000 — 0x21C Reserved r r r r r r r r 0000 0000 — 0x21D Reserved r r r r r r r r 0000 0000 — 0x21E Reserved r r r r r r r r 0000 0000 — 0x21F Reserved r r r r r r r r 0000 0000 — 0x220 SLPCON1 r r CLKOUTEN SLPCLKDIV4 SLPCLKDIV3 SLPCLKDIV2 SLPCLKDIV1 SLPCLKDIV0 0000 0000 70 0x221 Reserved r r r r r r r r 0000 0000 — 0x222 WAKETIMEL WAKETIME7 WAKETIME6 WAKETIME5 WAKETIME4 WAKETIME3 WAKETIME2 WAKETIME1 WAKETIME0 0000 1010 71 0x223 WAKETIMEH r r r r r WAKETIME10 WAKETIME9 WAKETIME8 0000 0000 71 0x224 REMCNTL REMCNT7 REMCNT6 REMCNT5 REMCNT4 REMCNT3 REMCNT2 REMCNT1 REMCNT0 0000 0000 72 0x225 REMCNTH REMCNT15 REMCNT14 REMCNT13 REMCNT12 REMCNT11 REMCNT10 REMCNT9 REMCNT8 0000 0000 72 0x226 MAINCNT0 MAINCNT7 MAINCNT6 MAINCNT5 MAINCNT4 MAINCNT3 MAINCNT2 MAINCNT1 MAINCNT0 0000 0000 73 0x227 MAINCNT1 MAINCNT15 MAINCNT14 MAINCNT13 MAINCNT12 MAINCNT11 MAINCNT10 MAINCNT9 MAINCNT8 0000 0000 73 0x228 MAINCNT2 MAINCNT23 MAINCNT22 MAINCNT21 MAINCNT20 MAINCNT19 MAINCNT18 MAINCNT17 MAINCNT16 0000 0000 74 0x229 MAINCNT3 STARTCNT r r r r r MAINCNT25 MAINCNT24 0000 0000 74 0x22A Reserved r r r r r r r r 0000 0000 — 0x22B Reserved r r r r r r r r 0000 0000 — 0x22C Reserved r r r r r r r r 0000 0000 — 0x22D Reserved r r r r r r r r 0000 0000 — 0x22E Reserved r r r r r r r r 0000 0000 — 0x22F TESTMODE r r r RSSIWAIT1 RSSIWAIT0 TESTMODE2 TESTMODE1 TESTMODE0 0000 0000 75 0x230 ASSOEADR0 ASSOEADR0<7:0> 0000 0000 76 0x231 ASSOEADR1 ASSOEADR1<15:8> 0000 0000 76 0x232 ASSOEADR2 ASSOEADR2<23:16> 0000 0000 77 0x233 ASSOEADR3 ASSOEADR3<31:24> 0000 0000 77 0x234 ASSOEADR4 ASSOEADR4<39:32> 0000 0000 78 0x235 ASSOEADR5 ASSOEADR5<47:40> 0000 0000 78 0x236 ASSOEADR6 ASSOEADR6<55:48> 0000 0000 79 0x237 ASSOEADR7 ASSOEADR7<63:56> 0000 0000 79 0x238 ASSOSADR0 ASSOSADR0<7:0> 0000 0000 80 0x239 ASSOSADR1 ASSOSADR1<15:8> 0000 0000 80 0x23A Reserved r r r r r r r r 0000 0000 — 0x23B Reserved r r r r r r r r 0000 0000 — 0x23C Unimple- — — — — — — — — ---- ---- — mented 0x23D Unimple- — — — — — — — — ---- ---- — mented 0x23E Unimple- — — — — — — — — ---- ---- — mented 0x23F Unimple- — — — — — — — — ---- ---- — mented 0x240 UPNONCE0 UPNONCE<7:0> 0000 0000 81 0x241 UPNONCE1 UPNONCE<15:8> 0000 0000 81 0x242 UPNONCE2 UPNONCE<23:16> 0000 0000 82 0x243 UPNONCE3 UPNONCE<31:24> 0000 0000 82 0x244 UPNONCE4 UPNONCE<39:32> 0000 0000 83 0x245 UPNONCE5 UPNONCE<47:40> 0000 0000 83 Legend: r = reserved Preliminary DS39776C-page 20 © 2010 Microchip Technology Inc.

MRF24J40 TABLE 2-7: LONG ADDRESS CONTROL REGISTER SUMMARY FOR MRF24J40 (CONTINUED) Details Value on Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR Page: 0x246 UPNONCE6 UPNONCE<55:48> 0000 0000 84 0x247 UPNONCE7 UPNONCE<63:56> 0000 0000 84 0x248 UPNONCE8 UPNONCE<71:64> 0000 0000 85 0x249 UPNONCE9 UPNONCE<79:72> 0000 0000 85 0x24A UPNONCE10 UPNONCE<87:80> 0000 0000 86 0x24B UPNONCE11 UPNONCE<95:88> 0000 0000 86 0x24C UPNONCE12 UPNONCE<103:96> 0000 0000 87 Legend: r = reserved Preliminary © 2010 Microchip Technology Inc. DS39776C-page 21

MRF24J40 2.15.3 SHORT ADDRESS CONTROL REGISTERS DETAIL REGISTER 2-1: RXMCR: RECEIVE MAC CONTROL REGISTER (ADDRESS: 0x00) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r r NOACKRSP r PANCOORD COORD ERRPKT PROMI bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Reserved: Maintain as ‘0’ bit 5 NOACKRSP: Automatic Acknowledgement Response bit 1 = Disables automatic Acknowledgement response 0 = Enables automatic Acknowledgement response. Acknowledgements are returned when they are requested (default). bit 4 Reserved: Maintain as ‘0’ bit 3 PANCOORD: PAN Coordinator bit 1 = Set device as PAN coordinator 0 = Device is not set as PAN coordinator (default) bit 2 COORD: Coordinator bit 1 = Set device as coordinator 0 = Device is not set as coordinator (default) bit 1 ERRPKT: Packet Error Mode bit 1 = Accept all packets including those with CRC error 0 = Accept only packets with good CRC (default) bit 0 PROMI: Promiscuous Mode bit 1 = Receive all packet types with good CRC 0 = Discard packet when there is a MAC address mismatch, illegal frame type, dPAN/sPAN or MAC short address mismatch (default) Preliminary DS39776C-page 22 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-2: PANIDL: PAN ID LOW BYTE REGISTER (ADDRESS: 0x01) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAN ID Low Byte (PANIDL<7:0>) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 PANIDL<7:0>: PAN ID Low Byte bits REGISTER 2-3: PANIDH: PAN ID HIGH BYTE REGISTER (ADDRESS: 0x02) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAN ID High Byte (PANIDH<15:8>) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 PANIDH<15:8>: PAN ID High Byte bits Preliminary © 2010 Microchip Technology Inc. DS39776C-page 23

MRF24J40 REGISTER 2-4: SADRL: SHORT ADDRESS LOW BYTE REGISTER (ADDRESS: 0x03) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Short Address Low Byte (SADRL<7:0>) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 SADRL<7:0>: Short Address Low Byte bits REGISTER 2-5: SADRH: SHORT ADDRESS HIGH BYTE REGISTER (ADDRESS: 0x04) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Short Address High Byte (SADRH<15:8>) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 SADRH<15:8>: Short Address High Byte bits Preliminary DS39776C-page 24 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-6: EADR0: EXTENDED ADDRESS 0 REGISTER (ADDRESS: 0x05) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 64-Bit Extended Address bits (EADR<7:0>) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EADR<7:0>: 64-Bit Extended Address bits REGISTER 2-7: EADR1: EXTENDED ADDRESS 1 REGISTER (ADDRESS: 0x06) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 64-Bit Extended Address bits (EADR<15:8>) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EADR<15:8>: 64-Bit Extended Address bits REGISTER 2-8: EADR2: EXTENDED ADDRESS 2 REGISTER (ADDRESS: 0x07) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 64-Bit Extended Address bits (EADR<23:16>) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EADR<23:16>: 64-Bit Extended Address bits Preliminary © 2010 Microchip Technology Inc. DS39776C-page 25

MRF24J40 REGISTER 2-9: EADR3: EXTENDED ADDRESS 3 REGISTER (ADDRESS: 0x08) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 64-Bit Extended Address bits (EADR<31:24>) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EADR<31:24>: 64-Bit Extended Address bits REGISTER 2-10: EADR4: EXTENDED ADDRESS 4 REGISTER (ADDRESS: 0x09) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 64-Bit Extended Address bits (EADR<39:32>) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EADR<39:32>: 64-Bit Extended Address bits REGISTER 2-11: EADR5: EXTENDED ADDRESS 5 REGISTER (ADDRESS: 0x0A) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 64-Bit Extended Address bits (EADR<47:40>) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EADR<47:40>: 64-Bit Extended Address bits Preliminary DS39776C-page 26 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-12: EADR6: EXTENDED ADDRESS 6 REGISTER (ADDRESS: 0x0B) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 64-Bit Extended Address bits (EADR<55:48>) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EADR<55:48>: 64-Bit Extended Address bits REGISTER 2-13: EADR7: EXTENDED ADDRESS 7 REGISTER (ADDRESS: 0x0C) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 64-Bit Extended Address bits (EADR<63:56>) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EADR<63:56>: 64-Bit Extended Address bits Preliminary © 2010 Microchip Technology Inc. DS39776C-page 27

MRF24J40 REGISTER 2-14: RXFLUSH: RECEIVE FIFO FLUSH REGISTER (ADDRESS: 0x0D) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 W-0 r WAKEPOL WAKEPAD r CMDONLY DATAONLY BCNONLY RXFLUSH bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Reserved: Maintain as ‘0’ bit 6 WAKEPOL: Wake Signal Polarity bit 1 = Wake signal polarity is active-high 0 = Wake signal polarity is active-low (default) bit 5 WAKEPAD: Wake I/O Pin Enable bit 1 = Enable wake I/O pin 0 = Disable wake I/O pin (default) bit 4 Reserved: Maintain as ‘0’ bit 3 CMDONLY: Command Frame Receive bit 1 = Only command frames are received, all other frames are filtered out 0 = All valid frames are received (default) bit 2 DATAONLY: Data Frame Receive bit 1 = Only data frames are received, all other frames are filtered out 0 = All valid frames are received (default) bit 1 BCNONLY: Beacon Frame Receive bit 1 = Only beacon frames are received, all other frames are filtered out 0 = All valid frames are received (default) bit 0 RXFLUSH: Reset Receive FIFO Address Pointer bit 1 = Resets the RXFIFO Address Pointer to zero. RXFIFO data is not modified. Bit is automatically cleared to ‘0’ by hardware. Preliminary DS39776C-page 28 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-15: ORDER: BEACON AND SUPERFRAME ORDER REGISTER (ADDRESS: 0x10) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 BO3(1) BO2(1) BO1(1) BO0(1) SO3(1) SO2(1) SO1(1) SO0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 BO<3:0>: Beacon Order bits (macBeaconOrder)(1) Specifies how often the coordinator will transmit a beacon.(2) 1111 = The coordinator will not transmit a beacon and the Superframe Order (SO) parameter value is ignored (default) 1110 = 1 4 • • • 0000 = 0 bit 3-0 SO<3:0>: Superframe Order bits (macSuperframeOrder)(1) Specifies the length of the active portion of the superframe, including the beacon frame.(2) 1111 = The superframe will not be active following the beacon (i.e., no active portion in the superframe (default)) 1110 = 1 4 • • • 0000 = 0 Note 1: Refer to IEEE 802.15.4™-2003 Standard, Section 7.5.1.1 “Superframe Structure”. 2: PANs that wish to use the superframe structure shall set macBeaconOrder to a value between 0 and 14 and macSuperframeOrder to a value between 0 and the value of macBeaconOrder (i.e., 0 ≤ SO ≤ BO ≤ 14). Preliminary © 2010 Microchip Technology Inc. DS39776C-page 29

MRF24J40 REGISTER 2-16: TXMCR: CSMA-CA MODE CONTROL REGISTER (ADDRESS: 0x11) R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 NOCSMA BATLIFEXT SLOTTED MACMINBE1 MACMINBE0 CSMABF2 CSMABF1 CSMABF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 NOCSMA: No Carrier Sense Multiple Access (CSMA) Algorithm bits 1 = Disable CSMA-CA algorithm when transmitting in Unslotted mode with GTSSWITCH (TXPEND 0x21<1>) bit set 0 = Enable CSMA-CA algorithm when transmitting in Unslotted mode with GTSSWITCH (TXPEND 0x21<1>) bit set (default) bit 6 BATLIFEXT: Battery Life Extension Mode bit (macBattLifeExt) 1 = Enable 0 = Disable (default) bit 5 SLOTTED: Slotted CSMA-CA Mode bit 1 = Enable Slotted CSMA-CA mode 0 = Disable Slotted CSMA-CA mode (default) bit 4-3 MACMINBE<1:0>: MAC Minimum Backoff Exponent bits (macMinBE) The minimum value of the backoff exponent in the CSMA-CA algorithm. Note that if this value is set to ‘0’, collision avoidance is disabled.(1) Default: 0x3. bit 2-0 CSMABF<2:0>: CSMA Backoff bits (macMaxCSMABackoff) The maximum number of backoffs the CSMA-CA algorithm will attempt before declaring a channel access failure.(1) 111 = Undefined 110 = Undefined 101 = 5 100 = 4 (default) 011 = 3 010 = 2 001 = 1 000 = 0 Note 1: Refer to IEEE 802.15.4™-2003 Standard, Table 71 – MAC PIB attributes. Preliminary DS39776C-page 30 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-17: ACKTMOUT: MAC ACK TIME-OUT DURATION REGISTER (ADDRESS: 0x12) R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 DRPACK MAWD6(1) MAWD5(1) MAWD4(1) MAWD3(1) MAWD2(1) MAWD1(1) MAWD0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DRPACK: Data Request Pending Acknowledgement bit(1) Sets or clears the frame pending bit in the Acknowledgement frame for a received data request MAC command. 1 = Sets frame pending bit 0 = Clears frame pending bit bit 6-0 MAWD<6:0>: macAckWaitDuration bits(2) The maximum number of symbols to wait for an Acknowledgment frame to arrive following a transmitted data or MAC command frame. Units: Symbol period (16 μs). Default value: 0x39. Note 1: Refer to IEEE 802.15.4™-2003 Standard, Section 5.4.2.2 “Data Transfer from a Coordinator” and Section 7.3 “MAC Command Frames”. 2: Refer to IEEE 802.15.4™-2003 Standard, Table 71: MAC PIB Attributes. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 31

MRF24J40 REGISTER 2-18: ESLOTG1: GTS1 AND CAP END SLOT REGISTER (ADDRESS: 0x13) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GTS1-3 GTS1-2 GTS1-1 GTS1-0 CAP3 CAP2 CAP1 CAP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 GTS1-<3:0>: End Slot of 1st GTS bits 1111 = 15 • • • 0000 = 0 (default) bit 3-0 CAP<3:0>: Contention Access Period (CAP) End Slot bits 1111 = 15 • • • 0000 = 0 (default) Preliminary DS39776C-page 32 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-19: SYMTICKL: SYMBOL PERIOD TICK LOW BYTE REGISTER (ADDRESS: 0x14) R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TICKP7 TICKP6 TICKP5 TICKP4 TICKP3 TICKP2 TICKP1 TICKP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 TICKP<7:0>: Symbol Period Tick bits Number of ticks to define a symbol period. Tick period is based on the system clock frequency of 20 MHz. TICKP is a 9-bit value. The TICKP8 bit is located in SYMTICKH<0>. Units: tick (50 ns). Default value = 0x140 (320 * 50 ns = 16 μs). REGISTER 2-20: SYMTICKH: SYMBOL PERIOD TICK HIGH BYTE REGISTER (ADDRESS: 0x15) R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 TXONT6(1) TXONT5(1) TXONT4(1) TXONT3(1) TXONT2(1) TXONT1(1) TXONT0(1) TICKP8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 TXONT<6:0>: Transmitter Enable On Time Tick bits(1) Transmitter on time before beginning of packet. TXONT is a 9-bit value. The TXONT<8:7> bits are located in PACON2<1:0>. Units: tick (50 ns). Default value = 0x028 (40 * 50 ns = 2 μs). bit 0 TICKP8: Symbol Period Tick bit Number of ticks to define a symbol period. Tick period is based on the system clock frequency of 20 MHz. TICKP is a 9-bit value. The TICKP<7:0> bits are located in SYMTICKL<7:0>. Units: tick (50 ns). Default value = 0x140 (320 * 50 ns = 16 μs). Note 1: Refer to Figure 4-4 for timing diagram. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 33

MRF24J40 REGISTER 2-21: PACON0: POWER AMPLIFIER CONTROL 0 REGISTER (ADDRESS: 0x16) R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 PAONT7(1) PAONT6(1) PAONT5(1) PAONT4(1) PAONT3(1) PAONT2(1) PAONT1(1) PAONT0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 PAONT<7:0>: Power Amplifier Enable On Time Tick bits(1) Power amplifier on time before beginning of packet. PAONT is a 9-bit value. The PAONT8 bit is located in PACON1<0>. Units: tick (50 ns). Default value = 0x029 (41 * 50 ns = 2.05 μs). Note 1: Refer to Figure 4-4 for timing diagram. REGISTER 2-22: PACON1: POWER AMPLIFIER CONTROL 1 REGISTER (ADDRESS: 0x17) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 r r r PAONTS3(1) PAONTS2(1) PAONTS1(1) PAONTS0(1) PAONT8(1) bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Reserved: Maintain as ‘0’ bit 4-1 PAONTS<3:0>: Power Amplifier Enable On Time Symbol bits(1) Power amplifier on time before beginning of packet. Units: symbol period (16 μs). Minimum value: 0x1 (default) (1 * 16 μs = 16 μs). bit 0 PAONT8: Power Amplifier Enable On Time Tick bit(1) Power amplifier on time before beginning of packet. PAONT is a 9-bit value. The PAONT<7:0> bits are located in PACON0<7:0>. Units: tick (50 ns). Default value = 0x029 (41 * 50 ns = 2.05 μs). Note 1: Refer to Figure 4-4 for timing diagram. Preliminary DS39776C-page 34 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-23: PACON2: POWER AMPLIFIER CONTROL 2 REGISTER (ADDRESS: 0x18) R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 FIFOEN r TXONTS3(1) TXONTS2(1) TXONTS1(1) TXONTS0(1) TXONT8(1) TXONT7(1) bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 FIFOEN: FIFO Enable bit 1 = Enabled (default). Always maintain this bit as a ‘1’. bit 6 Reserved: Maintain as ‘0’ bit 5-2 TXONTS<3:0>: Transmitter Enable On Time Symbol bits(1) Transmitter on time before beginning of packet. Units: symbol period (16 μs). Minimum value: 0x1. Default value: 0x2 (2 * 16 μs = 32 μs). Recommended value: 0x6 (6 * 16 μs = 96 μs). bit 1-0 TXONT<8:7>: Transmitter Enable On Time Tick bits(1) Transmitter on time before beginning of packet. TXONT is a 9-bit value. TXONT<6:0> bits are located in SYMTICKH<7:1>. Units: tick (50 ns). Default value = 0x028 (40 * 50 ns = 2 μs). Note 1: Refer to Figure 4-4 for timing diagram. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 35

MRF24J40 REGISTER 2-24: TXBCON0: TRANSMIT BEACON FIFO CONTROL 0 REGISTER (ADDRESS: 0x1A) R-0 R-0 R-0 R-0 R-0 R-0 R/W-0 W-0 r r r r r r TXBSECEN TXBTRIG bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Reserved: Maintain as ‘0’ bit 1 TXBSECEN: TX Beacon FIFO Security Enabled bit 1 = Security enabled 0 = Security disabled (default) bit 0 TXBTRIG: Transmit Frame in TX Beacon FIFO bit 1 = Transmit the frame in the TX Beacon FIFO; bit is automatically cleared by hardware Preliminary DS39776C-page 36 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-25: TXNCON: TRANSMIT NORMAL FIFO CONTROL REGISTER (ADDRESS: 0x1B) R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 W-0 r r r FPSTAT(1) INDIRECT(4) TXNACKREQ(2,4) TXNSECEN(3,4) TXNTRIG bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Reserved: Maintain as ‘0’ bit 4 FPSTAT: Frame Pending Status bit(1) Status of the frame pending bit in the received Acknowledgement frame. 1 = Sets frame pending bit 0 = Clears frame pending bit bit 3 INDIRECT: Activate Indirect Transmission bit (coordinator only)(4) 1 = Indirect transmission enabled 0 = Indirect transmission disabled (default) bit 2 TXNACKREQ: TX Normal FIFO Acknowledgement Request bit(2,4) Transmit a frame with Acknowledgement frame expected. If Acknowledgement is not received, retransmit. 1 = Acknowledgement requested 0 = No Acknowledgement requested (default) bit 1 TXNSECEN: TX Normal FIFO Security Enabled bit(3,4) 1 = Security enabled 0 = Security disabled (default) bit 0 TXNTRIG: Transmit Frame in TX Normal FIFO bit 1 = Transmit the frame in the TX Normal FIFO; bit is automatically cleared by hardware Note 1: Refer to IEEE 802.15.4™-2003 Standard, Section 7.2.1.1.3 “Frame Pending Subfield”. 2: Refer to IEEE 802.15.4-2003 Standard, Section 7.2.1.1.4 “Acknowledgement Request Subfield”. 3: Refer to IEEE 802.15.4-2003 Standard, Section 7.2.1.1.2 “Security Enabled Subfield”. 4: Bit is cleared at the next triggering of TXN FIFO. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 37

MRF24J40 REGISTER 2-26: TXG1CON: GTS1 FIFO CONTROL REGISTER (ADDRESS: 0x1C) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 W-0 TXG1RETRY1 TXG1RETRY0 TXG1SLOT2 TXG1SLOT1 TXG1SLOT0 TXG1ACKREQ TXG1SECEN TXG1TRIG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 TXG1RETRY<1:0>: TX GTS1 FIFO Retry Times bits Write: retry times of packet Read: number of retry times of the successfully transmitted packet bit 5-3 TXG1SLOT<2:0>: GTS Slot that TX GTS1 FIFO Occupies bits bit 2 TXG1ACKREQ: TX GTS1 FIFO Acknowledgement Request bit Transmit a frame with Acknowledgement frame expected. If Acknowledgement is not received, retransmit. 1 = Acknowledgement requested 0 = No Acknowledgement requested (default) bit 1 TXG1SECEN: TX GTS1 FIFO Security Enabled bit 1 = Security enabled 0 = Security disabled (default) bit 0 TXG1TRIG: Transmit Frame in TX GTS1 FIFO bit 1 = Transmit the frame in the TX GTS1 FIFO; bit is automatically cleared by hardware REGISTER 2-27: TXG2CON: GTS2 FIFO CONTROL REGISTER (ADDRESS: 0x1D) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 W-0 TXG2RETRY1 TXG2RETRY0 TXG2SLOT2 TXG2SLOT1 TXG2SLOT0 TXG2ACKREQ TXG2SECEN TXG2TRIG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 TXG2RETRY<1:0>: TX GTS2 FIFO Retry Times bits Write: retry times of packet Read: number of retry times of the successfully transmitted packet bit 5-3 TXG2SLOT<2:0>: GTS Slot that TX GTS2 FIFO Occupies bits bit 2 TXG2ACKREQ: TX GTS2 FIFO Acknowledgement Request bit Transmit a frame with Acknowledgement frame expected. If Acknowledgement is not received, retransmit. 1 = Acknowledgement requested 0 = No Acknowledgement requested (default) bit 1 TXG2SECEN: TX GTS2 FIFO Security Enabled bit 1 = Security enabled 0 = Security disabled (default) bit 0 TXG2TRIG: Transmit Frame in TX GTS2 FIFO bit 1 = Transmit the frame in the TX GTS2 FIFO; bit is automatically cleared by hardware Preliminary DS39776C-page 38 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-28: ESLOTG23: END SLOT OF GTS3 AND GTS2 REGISTER (ADDRESS: 0x1E) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GTS3-3 GTS3-2 GTS3-1 GTS3-0 GTS2-3 GTS2-2 GTS2-1 GTS2-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 GTS3-<3:0>: End Slot of 3rd GTS bits bit 3-0 GTS2-<3:0>: End Slot of 2nd GTS bits REGISTER 2-29: ESLOTG45: END SLOT OF GTS5 AND GTS4 REGISTER (ADDRESS: 0x1F) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GTS5-3 GTS5-2 GTS5-1 GTS5-0 GTS4-3 GTS4-2 GTS4-1 GTS4-0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 GTS5-<3:0>: End Slot of 5th GTS bits bit 3-0 GTS4-<3:0>: End Slot of 4th GTS bits REGISTER 2-30: ESLOTG67: END SLOT OF GTS6 REGISTER (ADDRESS: 0x20) R-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 r r r r GTS6-3 GTS6-2 GTS6-1 GTS6-0 bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Reserved: Maintain as ‘0’ bit 3-0 GTS6-<3:0>: End Slot of 6th GTS bits If 7th GTS exists, the end slot must be 15. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 39

MRF24J40 REGISTER 2-31: TXPEND: TX DATA PENDING REGISTER (ADDRESS: 0x21) R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 MLIFS5 MLIFS4 MLIFS3 MLIFS2 MLIFS1 MLIFS0 GTSSWITCH FPACK(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 MLIFS<5:0>: Minimum Long Interframe Spacing bits The minimum number of symbols forming a Long Interframe Spacing (LIFS) period. Refer to IEEE 802.15.4™-2003 Standard, Section 7.5.1.2 “IFS” and Table 70: MAC Sublayer Constants. MLIFS + RFSTBL = aMinLIFSPeriod = 40 symbols. Units: symbol period (16 μs). Default value: 0x21. Recommended values: MLIFS = 0x1F and RFSTBL = 0x9. bit 1 GTSSWITCH: Continue TX GTS FIFO Switch in CFP bit 1 = GTS1 and GTS2 FIFO will toggle with each other during CFP 0 = GTS1 and GTS2 FIFO will stop toggling with each other if the transmission fails (default) bit 0 FPACK: Frame Pending bit in the Acknowledgement Frame bit(1) Sets or clears the frame pending bit in the Acknowledgement frame. 1 = Sets frame pending bit 0 = Clears frame pending bit Note 1: Refer to IEEE 802.15.4™-2003 Standard, Section 7.2.1.1.3 “Frame Pending Subfield” and Section 7.2.2.3.1 “Acknowledgement Frame MHR Fields”. Preliminary DS39776C-page 40 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-32: WAKECON: WAKE CONTROL REGISTER (ADDRESS: 0x22) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IMMWAKE REGWAKE INTL INTL INTL INTL INTL INTL bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IMMWAKE: Immediate Wake-up Mode Enable bit 1 = Enable Immediate Wake-up mode 0 = Disable Immediate Wake-up mode (default) bit 6 REGWAKE: Register Wake-up Signal bit Host processor should set to ‘1’, then clear to ‘0’, to perform wake-up. bit 5-0 INTL<5:0>: Interval to Start Beacon(1) For Beacon-Enabled mode the timing interval between triggering slotted mode and the first time to transmit beacon. Default Value: 0x00. Note 1: Refer to Section 3.8.1.4 “Configuring Beacon-Enabled PAN Coordinator” for more information. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 41

MRF24J40 REGISTER 2-33: FRMOFFSET: SUPERFRAME COUNTER OFFSET TO ALIGN BEACON REGISTER (ADDRESS: 0x23) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OFFSET7(1) OFFSET6(1) OFFSET5(1) OFFSET4(1) OFFSET3(1) OFFSET2(1) OFFSET1(1) OFFSET0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 OFFSET<7:0>: Superframe Counter Offset for Align Air Slot Boundary bits(1) For Beacon-Enabled mode device. Default value: 0x00. Recommended value: 0x15. Note 1: Refer to Section 3.8.1.6 “Configuring Beacon-Enabled Device” for more information. Preliminary DS39776C-page 42 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-34: TXSTAT: TX MAC STATUS REGISTER (ADDRESS: 0x24) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TXNRETRY1 TXNRETRY0 CCAFAIL TXG2FNT TXG1FNT TXG2STAT TXG1STAT TXNSTAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 TXNRETRY<1:0>: TX Normal FIFO Retry Times bits Number of retries of the most recent TX Normal FIFO transmission. bit 5 CCAFAIL: Clear Channel Assessment (CCA) Status of Last Transmission bit 1 = Channel busy 0 = Channel Idle bit 4 TXG2FNT: TX GTS2 FIFO Transmission failed due to not enough time before the end of GTS bit 1 = Failed 0 = Succeeded bit 3 TXG1FNT: TX GTS1 FIFO Transmission failed due to not enough time before the end of GTS bit 1 = Failed 0 = Succeeded bit 2 TXG2STAT: TX GTS2 FIFO Release Status bit 1 = Failed, retry count exceeded 0 = Succeeded bit 1 TXG1STAT: TX GTS2 FIFO Release Status bit 1 = Failed, retry count exceeded 0 = Succeeded bit 0 TXNSTAT: TX Normal FIFO Release Status bit 1 = Failed, retry count exceeded 0 = Succeeded Preliminary © 2010 Microchip Technology Inc. DS39776C-page 43

MRF24J40 REGISTER 2-35: TXBCON1: TRANSMIT BEACON CONTROL 1 REGISTER (ADDRESS: 0x25) R/W-0 R-0 R/W-1 R/W-1 R-0 R-0 R-0 R-0 TXBMSK WU/BCN RSSINUM1 RSSINUM0 r r r r bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TXBMSK: TX Beacon FIFO Interrupt Mask bit 1 = TX Beacon FIFO interrupt is masked 0 = TX Beacon FIFO interrupt is not masked (default) bit 6 WU/BCN: Wake-up/Beacon Interrupt Status bit Indicates if the WAKEIF interrupt was due to beacon start or wake-up. 1 = Beacon start interrupt 0 = Wake-up interrupt bit 5-4 RSSINUM<1:0>: RSSI Average Symbols bits 11 = 8 symbols (default) 10 = 4 symbols 01 = 2 symbols 00 = 1 symbol bit 3-0 Reserved: Maintain as ‘0’ Preliminary DS39776C-page 44 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-36: GATECLK: GATED CLOCK CONTROL REGISTER (ADDRESS: 0x26) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r r r r GTSON r r r bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Reserved: Maintain as ‘0’ bit 3 GTSON: GTS FIFO Clock Enable bit 1 = Enabled 0 = Disabled (default) bit 2-0 Reserved: Maintain as ‘0’ Preliminary © 2010 Microchip Technology Inc. DS39776C-page 45

MRF24J40 REGISTER 2-37: TXTIME: TX TURNAROUND TIME REGISTER (ADDRESS: 0x27) R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 TURNTIME3 TURNTIME2 TURNTIME1 TURNTIME0 r r r r bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 TURNTIME<3:0>: Turnaround Time bits Transmission to reception and reception to transmission turnaround time. Refer to IEEE 802.15.4™-2003 Standard, Table 18: PHY Constants and Section 7.5.6.4.2 “Acknowledgment”. TURNTIME + RFSTBL = aTurnaroundTime = 12 symbols. Units: symbol period (16 μs). Default value: 0x4. Minimum value: 0x2. Recommended values: TURNTIME = 0x3 and RFSTBL = 0x9. bit 3-0 Reserved: Maintain as 0x8 Preliminary DS39776C-page 46 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-38: HSYMTMRL: HALF SYMBOL TIMER LOW BYTE REGISTER (ADDRESS: 0x28) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HSYMTMR7 HSYMTMR6 HSYMTMR5 HSYMTMR4 HSYMTMR3 HSYMTMR2 HSYMTMR1 HSYMTMR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 HSYMTMR<7:0>: Half Symbol Timer Low Byte bits Units: 8 μs. REGISTER 2-39: HSYMTMRH: HALF SYMBOL TIMER HIGH BYTE REGISTER (ADDRESS: 0x29) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HSYMTMR15 HSYMTMR14 HSYMTMR13 HSYMTMR12 HSYMTMR11 HSYMTMR10 HSYMTMR09 HSYMTMR08 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 HSYMTMR<15:8>: Half Symbol Timer High Byte bits Units: 8 μs. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 47

MRF24J40 REGISTER 2-40: SOFTRST: SOFTWARE RESET REGISTER (ADDRESS: 0x2A) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 W-0 W-0 W-0 r r r r r RSTPWR RSTBB RSTMAC bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Reserved: Maintain as ‘0’ bit 2 RSTPWR: Power Management Reset bit 1 = Reset power management circuitry (bit is automatically cleared to ‘0’ by hardware) bit 1 RSTBB: Baseband Reset bit 1 = Reset baseband circuitry (bit is automatically cleared to ‘0’ by hardware) bit 0 RSTMAC: MAC Reset bit 1 = Reset MAC circuitry (bit is automatically cleared to ‘0’ by hardware) Preliminary DS39776C-page 48 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-41: SECCON0: SECURITY CONTROL 0 REGISTER (ADDRESS: 0x2C) W-0 W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SECIGNORE SECSTART RXCIPHER2 RXCIPHER1 RXCIPHER0 TXNCIPHER2 TXNCIPHER1 TXNCIPHER0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SECIGNORE: RX Security Decryption Ignore bit 1 = Ignore decryption process bit 6 SECSTART: RX Security Decryption Start bit 1 = Start decryption process bit 5-3 RXCIPHER<2:0>: RX FIFO Security Suite Select bits 111 = AES-CBC-MAC-32 110 = AES-CBC-MAC-64 101 = AES-CBC-MAC-128 100 = AES-CCM-32 011 = AES-CCM-64 010 = AES-CCM-128 001 = AES-CTR 000 = None (default) bit 2-0 TXNCIPHER<2:0>: TX Normal FIFO Security Suite Select bits 111 = AES-CBC-MAC-32 110 = AES-CBC-MAC-64 101 = AES-CBC-MAC-128 100 = AES-CCM-32 011 = AES-CCM-64 010 = AES-CCM-128 001 = AES-CTR 000 = None (default) Preliminary © 2010 Microchip Technology Inc. DS39776C-page 49

MRF24J40 REGISTER 2-42: SECCON1: SECURITY CONTROL 1 REGISTER (ADDRESS: 0x2D) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r TXBCIPHER2 TXBCIPHER1 TXBCIPHER0 r r DISDEC DISENC bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Reserved: Read as ‘0’ bit 6-4 TXBCIPHER<2:0>: TX Beacon FIFO Security Suite Select bits 111 = AES-CBC-MAC-32 110 = AES-CBC-MAC-64 101 = AES-CBC-MAC-128 100 = AES-CCM-32 011 = AES-CCM-64 010 = AES-CCM-128 001 = AES-CTR 000 = None (default) bit 3-2 Reserved: Read as ‘0’ bit 1 DISDEC: Disable Decryption Function bit 1 = Will not generate a security interrupt if security enabled bit is set in the MAC header bit 0 DISENC: Disable Encryption Function bit 1 = Will not encrypt packet if transmit security is enabled Preliminary DS39776C-page 50 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-43: TXSTBL: TX STABILIZATION REGISTER (ADDRESS: 0x2E) R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 R/W-0 R/W-1 RFSTBL3 RFSTBL2 RFSTBL1 RFSTBL0 MSIFS3 MSIFS2 MSIFS1 MSIFS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 RFSTBL<3:0>: VCO Stabilization Period bits Units: symbol period (16 μs). Default value: 0x7. Recommended value: 0x9. bit 3-0 MSIFS<3:0>: Minimum Short Interframe Spacing bits The minimum number of symbols forming a Short Interframe Spacing (SIFS) period. Refer to IEEE 802.15.4™-2003 Standard, Section 7.5.1.2 “IFS” and Table 70: MAC Sublayer Constants. MSIFS + RFSTBL = aMinSIFSPeriod = 12 symbols. Units: symbol period (16 μs). Default value: 0x5. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 51

MRF24J40 REGISTER 2-44: RXSR: RX MAC STATUS REGISTER (ADDRESS: 0x30) R-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R/W-0 r UPSECERR BATIND(1) r r SECDECERR r r bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Reserved: Read as ‘0’ bit 6 UPSECERR: MIC Error in Upper Layer Security Mode bit 1 = MIC error occurred. Write ‘1’ to clear 0 = MIC error did not occur bit 5 BATIND: Battery Low-Voltage Indicator bit(1) 1 = Supply voltage is lower than battery low-voltage threshold 0 = Supply voltage is greater than battery low-voltage threshold bit 4-3 Reserved: Maintain as ‘0’ bit 2 SECDECERR: Security Decryption Error 1 = Security decryption error occurred 0 = Security decryption error did not occur bit 1-0 Reserved: Maintain as ‘0’ Note 1: Battery low-voltage threshold (BATTH) value set in the RFCON5 (0X205<7:4>) register and the Battery Monitor Enable (BATEN) bit located in the RFCON6 (0x206<3>) register. Preliminary DS39776C-page 52 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-45: INTSTAT: INTERRUPT STATUS REGISTER (ADDRESS: 0x31) RC-0 RC-0 RC-0 RC-0 RC-0 RC-0 RC-0 RC-0 SLPIF(1) WAKEIF(1) HSYMTMRIF(1) SECIF(1) RXIF(1) TXG2IF(1) TXG1IF(1) TXNIF(1) bit 7 bit 0 Legend: RC = Read to clear bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SLPIF: Sleep Alert Interrupt bit(1) 1 = Sleep alert interrupt occurred 0 = No Sleep alert interrupt occurred bit 6 WAKEIF: Wake-up Alert Interrupt bit(1) 1 = A wake-up alert interrupt occurred 0 = No wake-up alert interrupt occurred bit 5 HSYMTMRIF: Half Symbol Timer Interrupt bit(1) 1 = A half symbol timer interrupt occurred 0 = No half symbol timer interrupt occurred bit 4 SECIF: Security Key Request Interrupt bit(1) 1 = A security key request interrupt occurred 0 = No security key request interrupt occurred bit 3 RXIF: RX FIFO Reception Interrupt bit(1) 1 = An RX FIFO reception interrupt occurred 0 = No RX FIFO reception interrupt occurred bit 2 TXG2IF: TX GTS2 FIFO Transmission Interrupt bit(1) 1 = A TX GTS2 FIFO transmission interrupt occurred 0 = No TX GTS2 FIFO transmission interrupt occurred bit 1 TXG1IF: TX GTS1 FIFO Transmission Interrupt bit(1) 1 = A TX GTS1 FIFO transmission interrupt occurred 0 = No TX GTS1 FIFO transmission interrupt occurred bit 0 TXNIF: TX Normal FIFO Release Interrupt bit(1) 1 = A TX Normal FIFO transmission interrupt occurred 0 = No TX Normal FIFO transmission interrupt occurred Note 1: Interrupt bits are cleared to ‘0’ when the INTSTAT register is read. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 53

MRF24J40 REGISTER 2-46: INTCON: INTERRUPT CONTROL REGISTER (ADDRESS: 0x32) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SLPIE WAKEIE HSYMTMRIE SECIE RXIE TXG2IE TXG1IE TXNIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SLPIE: Sleep Alert Interrupt Enable bit 1 = Disables the Sleep alert interrupt (default) 0 = Enables the Sleep alert interrupt bit 6 WAKEIE: Wake-up Alert Interrupt Enable bit 1 = Disables the wake-up alert interrupt (default) 0 = Enables the wake-up alert interrupt bit 5 HSYMTMRIE: Half Symbol Timer Interrupt Enable bit 1 = Disables the half symbol timer interrupt (default) 0 = Enables the half symbol timer interrupt bit 4 SECIE: Security Key Request Interrupt Enable bit 1 = Disables the security key request interrupt (default) 0 = Enable security key request interrupt bit 3 RXIE: RX FIFO Reception Interrupt Enable bit 1 = Disables the RX FIFO reception interrupt (default) 0 = Enables the RX FIFO reception interrupt bit 2 TXG2IE: TX GTS2 FIFO Transmission Interrupt Enable bit 1 = Disables the TX GTS2 FIFO transmission interrupt (default) 0 = Enables the TX GTS2 FIFO transmission interrupt bit 1 TXG1IE: TX GTS1 FIFO Transmission Interrupt Enable bit 1 = Disables the TX GTS1 FIFO transmission interrupt (default) 0 = Enables the TX GTS1 FIFO transmission interrupt bit 0 TXNIE: TX Normal FIFO Transmission Interrupt Enable bit 1 = Disables the TX Normal FIFO transmission interrupt (default) 0 = Enables the TX Normal FIFO transmission interrupt Preliminary DS39776C-page 54 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-47: GPIO: GPIO PORT REGISTER (ADDRESS: 0x33) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r r GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Reserved: Maintain as ‘0’ bit 5 GPIO5: General Purpose I/O GPIO5 bit bit 4 GPIO4: General Purpose I/O GPIO4 bit bit 3 GPIO3: General Purpose I/O GPIO3 bit bit 2 GPIO2: General Purpose I/O GPIO2 bit bit 1 GPIO1: General Purpose I/O GPIO1 bit bit 0 GPIO0: General Purpose I/O GPIO0 bit REGISTER 2-48: TRISGPIO: GPIO PIN DIRECTION REGISTER (ADDRESS: 0x34) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r r TRISGP5 TRISGP4 TRISGP3 TRISGP2 TRISGP1 TRISGP0 bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Reserved: Maintain as ‘0’ bit 5 TRISGP5: General Purpose I/O GPIO5 Direction bit 1 = Output 0 = Input (default) bit 4 TRISGP4: General Purpose I/O GPIO4 Direction bit 1 = Output 0 = Input (default) bit 3 TRISGP3: General Purpose I/O GPIO3 Direction bit 1 = Output 0 = Input (default) bit 2 TRISGP2: General Purpose I/O GPIO2 Direction bit 1 = Output 0 = Input (default) bit 1 TRISGP1: General Purpose I/O GPIO1 Direction bit 1 = Output 0 = Input (default) bit 0 TRISGP0: General Purpose I/O GPIO0 Direction bit 1 = Output 0 = Input (default) Preliminary © 2010 Microchip Technology Inc. DS39776C-page 55

MRF24J40 REGISTER 2-49: SLPACK: SLEEP ACKNOWLEDGEMENT AND WAKE-UP COUNTER REGISTER (ADDRESS: 0x35) W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SLPACK WAKECNT6 WAKECNT5 WAKECNT4 WAKECNT3 WAKECNT2 WAKECNT1 WAKECNT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SLPACK: Sleep Acknowledge bit 1 = Places the MRF24J40 to Sleep (automatically cleared to ‘0’ by hardware) bit 6-0 WAKECNT<6:0>: Wake Count bits Main oscillator (20 MHz) start-up timer counter bits. WAKECNT is a 9-bit value. WAKECNT<8:7> bits are located in RFCTL<4:3>. Units: Sleep clock (SLPCLK) period.(1) Default value: 0x00. Recommended value: 0x05F. Note 1: Sleep Clock (SLPCLK) period depends on the Sleep Clock Selection (SLPCLKSEL) RFCON7<7:6> and Sleep Clock Divisor (SLPCLKDIV) SLPCON1<4:0>. Preliminary DS39776C-page 56 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-50: RFCTL: RF MODE CONTROL REGISTER (ADDRESS: 0x36) W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r r r WAKECNT8 WAKECNT7 RFRST(2) RFTXMODE RFRXMODE bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Reserved: Maintain as ‘0’ bit 4-3 WAKECNT<8:7>: Wake Count bits Main oscillator (20 MHz) start-up timer counter bits. WAKECNT is a 9-bit value. WAKECNT<6:0> bits are located in SLPACK<6:0>. Units: Sleep clock (SLPCLK) period.(1) Default value: 0x00. Recommended value: 0x05F bit 2 RFRST: RF State Machine Reset bit(2) 1 = Hold RF state machine in Reset 0 = Normal operation of RF state machine bit 1 RFTXMODE: Forces RF Control State Machine to transmit State(3) bit 0 RFRXMODE: Forces RF Control State Machine to receive State Note 1: Sleep clock (SLPCLK) period depends on the Sleep clock selection (SLPCLKSEL) RFCON7<7:6> and Sleep clock divisor (SLPCLKDIV) SLPCON1<4:0>. 2: Perform RF Reset by setting RFRST = 1 and then RFRST = 0. Delay at least 192 μs after performing to allow RF circuitry to calibrate. 3: Recommended sequence RFCTL = 0x06 (reset mode) then RFCTL = 0x02 (transmit mode). Preliminary © 2010 Microchip Technology Inc. DS39776C-page 57

MRF24J40 REGISTER 2-51: SECCR2: SECURITY CONTROL 2 REGISTER (ADDRESS: 0x37) W-0 W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPDEC UPENC TXG2CIPHER2 TXG2CIPHER1 TXG2CIPHER0 TXG1CIPHER2 TXG1CIPHER1 TXG1CIPHER0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UPDEC: Upper Layer Security Decryption Mode bit 1 = Perform upper layer decryption using TX Normal FIFO. Automatically cleared to ‘0’ when finished. bit 6 UPENC: Upper Layer Security Encryption Mode bit 1 = Perform upper layer encryption using TX Normal FIFO. Automatically cleared to ‘0’ when finished. bit 5-3 TXG2CIPHER-<2:0>: TX GTS2 FIFO Security Suite Select bits 111 = AES-CBC-MAC-32 110 = AES-CBC-MAC-64 101 = AES-CBC-MAC-128 100 = AES-CCM-32 011 = AES-CCM-64 010 = AES-CCM-128 001 = AES-CTR 000 = None (default) bit 2-0 TXG1CIPHER-<2:0>: TX GTS1 FIFO Security Suite Select bits 111 = AES-CBC-MAC-32 110 = AES-CBC-MAC-64 101 = AES-CBC-MAC-128 100 = AES-CCM-32 011 = AES-CCM-64 010 = AES-CCM-128 001 = AES-CTR 000 = None (default) Preliminary DS39776C-page 58 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-52: BBREG0: BASEBAND 0 REGISTER (ADDRESS: 0x38) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r r r r r r r TURBO bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 Reserved: Maintain as ‘0’ bit 0 TURBO: Turbo Mode Enable bit 1 = Turbo mode (625 kbps) 0 = IEEE 802.15.4™ mode (250 kbps) REGISTER 2-53: BBREG1: BASEBAND 1 REGISTER (ADDRESS: 0x39) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r r r r r RXDECINV r r bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Reserved: Maintain as ‘0’ bit 2 RXDECINV: RX Decode Inversion bit 1 = RX decode symbol sign inverted 0 = RX decode symbol sign not inverted (default) bit 1-0 Reserved: Maintain as ‘0’ Preliminary © 2010 Microchip Technology Inc. DS39776C-page 59

MRF24J40 REGISTER 2-54: BBREG2: BASEBAND 2 REGISTER (ADDRESS: 0x3A) R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 CCAMODE1 CCAMODE0 CCACSTH3 CCACSTH2 CCATCSH1 CCACSTH0 r r bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CCAMODE<1:0>: Clear Channel Assessment (CCA) Mode bits 11 = CCA Mode 3: Carrier sense with energy above threshold. CCA shall report a busy medium only upon the detection of a signal with the modulation and spreading characteristics of IEEE 802.15.4™ with energy above the Energy Detection (ED) threshold. 10 = CCA Mode 1: Energy above threshold. CCA shall report a busy medium upon detecting any energy above the Energy Detection (ED) threshold. 01 = CCA Mode 2: Carrier sense only. CCA shall report a busy medium only upon the detection of a signal with the modulation and spreading characteristics of IEEE 802.15.4. This signal may be above or below the Energy Detection (ED) threshold (default). 00 = Reserved bit 5-2 CCACSTH<3:0>: Clear Channel Assessment (CCA) Carrier Sense (CS) Threshold bits 1111 = 1110 = Recommended value 1101 = • • • 0010 = (default) 0001 = 0000 = bit 1-0 Reserved: Maintain as ‘0’ REGISTER 2-55: BBREG3: BASEBAND 3 REGISTER (ADDRESS: 0x3B) R/W-1 R/W-1 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 PREVALIDTH3 PREVALIDTH2 PREVALIDTH1 PREVALIDTH0 PREDETTH2 PREDETTH1 PREDETTH0 r bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 PREVALIDTH<3:0>: Preamble Search Energy Valid Threshold bits 1101 = IEEE 802.15.4™ (250 kbps) optimized value (default) 0011 = Turbo mode (625 kbps) optimized value bit 3-1 PREDETTH<2:0>: Preamble Search Energy Detection Threshold bits Default value: 0x4. bit 0 Reserved: Maintain as ‘0’ Preliminary DS39776C-page 60 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-56: BBREG4: BASEBAND 4 REGISTER (ADDRESS: 0x3C) R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 CSTH2 CSTH1 CSTH0 PRECNT2 PRECNT1 PRECNT0 r r bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 CSTH<2:0>: Carrier Sense Threshold bits 100 = IEEE 802.15.4™ (250 kbps) optimized value (default) 010 = Turbo mode (625 kbps) optimized value bit 4-2 PRECNT<2:0>: Preamble Counter Threshold bits 111 = Optimized value (default) bit 1-0 Reserved: Maintain as ‘0’ REGISTER 2-57: BBREG6: BASEBAND 6 REGISTER (ADDRESS: 0x3E) W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 RSSIMODE1 RSSIMODE2 r r r r r RSSIRDY bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RSSIMODE1: RSSI Mode 1 bit 1 = Initiate RSSI calculation (bit is automatically cleared to ‘0’ by hardware) bit 6 RSSIMODE2: RSSI Mode 2 bit 1 = Calculate RSSI for each received packet. The RSSI value is stored in RXFIFO 0 = RSSI calculation is not performed for each received packet (default) bit 5-1 Reserved: Maintain as ‘0’ bit 0 RSSIRDY: RSSI Ready Signal for RSSIMODE1 bit If RSSIMODE1 = 1, then 1 = RSSI calculation has finished and the RSSI value is ready 0 = RSSI calculation in progress Preliminary © 2010 Microchip Technology Inc. DS39776C-page 61

MRF24J40 REGISTER 2-58: CCAEDTH: ENERGY DETECTION THRESHOLD FOR CCA REGISTER (ADDRESS: 0x3F) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCAEDTH7 CCAEDTH6 CCAEDTH5 CCAEDTH4 CCAEDTH3 CCAEDTH2 CCAEDTH1 CCAEDTH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 CCAEDTH<7:0>: Clear Channel Assessment (CCA) Energy Detection (ED) Mode bits If the in-band signal strength is greater than the threshold, the channel is busy. The 8-bit value can be mapped to a power level according to RSSI. Refer to Section 3.6 “Received Signal Strength Indicator (RSSI)/Energy Detection (ED)”. Default value: 0x00. Recommended value: 0x60 (approximately -69 dBm). Preliminary DS39776C-page 62 © 2010 Microchip Technology Inc.

MRF24J40 2.15.4 LONG ADDRESS CONTROL REGISTERS DETAIL REGISTER 2-59: RFCON0: RF CONTROL 0 REGISTER (ADDRESS: 0x200) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHANNEL3 CHANNEL2 CHANNEL1 CHANNEL0 RFOPT3 RFOPT2 RFOPT1 RFOPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 CHANNEL<3:0>: Channel Number bits 0000 = Channel 11 (2405 MHz) (default) 0001 = Channel 12 (2410 MHz) 0010 = Channel 13 (2415 MHz) … 1111 = Channel 26 (2480 MHz) bit 3-0 RFOPT<3:0>: RF Optimize Control bits Default value: 0x0. Recommended value: 0x3. REGISTER 2-60: RFCON1: RF CONTROL 1 REGISTER (ADDRESS: 0x201) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VCOOPT7 VCOOPT6 VCOOPT5 VCOOPT4 VCOOPT3 VCOOPT2 VCOOPT1 VCOOPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 VCOOPT<7:0>: VCO Optimize Control bits Default value: 0x0. Recommended value: 0x2. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 63

MRF24J40 REGISTER 2-61: RFCON2: RF CONTROL 2 REGISTER (ADDRESS: 0x202) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PLLEN(1) r r r r r r r bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PLLEN: PLL Enable bit(1) 1 = Enabled 0 = Disabled (default) bit 6-0 Reserved: Maintain as ‘0’ Note 1: PLL must be enabled for RF reception or transmission. REGISTER 2-62: RFCON3: RF CONTROL 3 REGISTER (ADDRESS: 0x203) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXPWRL1 TXPWRL0 TXPWRS2 TXPWRS1 TXPWRS0 r r r bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 TXPWRL<1:0>: Large Scale Control for TX Power bits 11 = -30 dB 10 = -20 dB 01 = -10 dB 00 = 0 dB bit 5-3 TXPWRS<2:0>: Small Scale Control for TX Power bits 111 = -6.3 dB 110 = -4.9 dB 101 = -3.7 dB 100 = -2.8 dB 011 = -1.9 dB 010 = -1.2 dB 001 = -0.5 dB 000 = 0 dB bit 2-0 Reserved: Maintain as ‘0’ Preliminary DS39776C-page 64 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-63: RFCON5: RF CONTROL 5 REGISTER (ADDRESS: 0x205) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BATTH3(1) BATTH2(1) BATTH1(1) BATTH0(1) r r r r bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 BATTH<3:0>: Battery Low-Voltage Threshold bits(1) 1110 = 3.5V 1101 = 3.3V 1100 = 3.2V 1011 = 3.1V 1010 = 2.8V 1001 = 2.7V 1000 = 2.6V 0111 = 2.5V 0110 = Undefined ... 0000 = Undefined bit 3-0 Reserved: Maintain as ‘0’ Note 1: The Battery Low-Voltage Indicator (BATIND) bit is located in the RXSR (0x30<5>) register and the Battery Monitor Enable (BATEN) bit is located in the RFCON6 (0x206<3>) register. REGISTER 2-64: RFCON6: RF CONTROL 6 REGISTER (ADDRESS: 0x206) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXFIL r r 20MRECVR BATEN(1) r r r bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TXFIL: TX Filter Control bit Default value: ‘0’. Recommended value: ‘1’. bit 6-5 Reserved: Maintain as ‘0’ bit 4 20MRECVR: 20 MHz Clock Recovery Control bits Recovery from Sleep control. 1 = Less than 1 ms (recommended) 0 = Less than 3 ms (default) bit 3 BATEN: Battery Monitor Enable bit(1) 1 = Enabled 0 = Disabled (default) bit 2-0 Reserved: Maintain as ‘0’ Note 1: The Battery Low-Voltage Threshold (BATTH) bits are located in the RFCON5 (0x205<7:4>) register and the Battery Low-Voltage Indicator (BATIND) bit is located in the RXSR (0x30<5>) register. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 65

MRF24J40 REGISTER 2-65: RFCON7: RF CONTROL 7 REGISTER (ADDRESS: 0x207) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SLPCLKSEL1 SLPCLKSEL0 r r r r r r bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 SLPCLKSEL<1:0>: Sleep Clock Selection bits 10 = 100 kHz internal oscillator 01 = 32 kHz external crystal oscillator bit 5-0 Reserved: Maintain as ‘0’ REGISTER 2-66: RFCON8: RF CONTROL 8 REGISTER (ADDRESS: 0x208) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RFVCO — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Reserved: Maintain as ‘0’ bit 4 RFVCO: VCO Control bit Default value: ‘0’. Recommended value: ‘1’. bit 3-0 Reserved: Maintain as ‘0’ Preliminary DS39776C-page 66 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-67: SLPCAL0: SLEEP CALIBRATION 0 REGISTER (ADDRESS: 0x209) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 SLPCAL7 SLPCAL6 SLPCAL5 SLPCAL4 SLPCAL3 SLPCAL2 SLPCAL1 SLPCAL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 SLPCAL<7:0>: Sleep Calibration Counter bits 20-bit counter to calibrate the Sleep Clock (SLPCLK) period. The counter contains the count of 16 SLPCLK periods. The SLPCLK period depends on the Sleep Clock Selection (SLPCLKSEL), RFCON7<7:6> and Sleep Clock Divisor (SLPCLKDIV) SLPCON1<4:0> bits. Units: tick (50 ns). REGISTER 2-68: SLPCAL1: SLEEP CALIBRATION 1 REGISTER (ADDRESS: 0x20A) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 SLPCAL15 SLPCAL14 SLPCAL13 SLPCAL12 SLPCAL11 SLPCAL10 SLPCAL9 SLPCAL8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 SLPCAL<15:8>: Sleep Calibration Counter bits 20-bit counter to calibrate the Sleep Clock (SLPCLK) period. The counter contains the count of 16 SLPCLK periods. The SLPCLK period depends on the Sleep Clock Selection (SLPCLKSEL), RFCON7<7:6> and Sleep Clock Divisor (SLPCLKDIV) SLPCON1<4:0> bits. Units: tick (50 ns). Preliminary © 2010 Microchip Technology Inc. DS39776C-page 67

MRF24J40 REGISTER 2-69: SLPCAL2: SLEEP CALIBRATION 2 REGISTER (ADDRESS: 0x20B) R-0 R/W-0 R/W-0 W-0 R-0 R-0 R-0 R-0 SLPCALRDY r r SLPCALEN SLPCAL19 SLPCAL18 SLPCAL17 SLPCAL16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SLPCALRDY: Sleep Calibration Ready bit 1 = Sleep calibration count is complete bit 6-5 Reserved: Maintain as ‘0’ bit 4 SLPCALEN: Sleep Calibration Enable bit 1 = Starts the Sleep calibration counter. Automatically cleared to ‘0’ by hardware bit 3-0 SLPCAL<19:16>: Sleep Calibration Counter bits 20-bit counter to calibrate the Sleep Clock (SLPCLK) period. The counter contains the count of 16 SLPCLK periods. The SLPCLK period depends on the Sleep Clock Selection (SLPCLKSEL), RFCON7<7:6> and Sleep Clock Divisor (SLPCLKDIV) SLPCON1<4:0> bits. Units: tick (50 ns). Preliminary DS39776C-page 68 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-70: RFSTATE: RF STATE REGISTER (ADDRESS: 0x20F) R-0 R-0 R-0 U-0 U-0 U-0 U-0 U-0 RFSTATE2 RFSTATE1 RFSTATE0 — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 RFSTATE<2:0>: RF State Machine bits 111 = RTSEL2 110 = RTSEL1 101 = RX 100 = TX 011 = CALVCO 010 = SLEEP 001 = CALFIL 000 = RESET bit 4-0 Reserved: Maintain as ‘0’ REGISTER 2-71: RSSI: AVERAGED RSSI VALUE REGISTER (ADDRESS: 0x210) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RSSI7(1) RSSI6(1) RSSI5(1) RSSI4(1) RSSI3(1) RSSI2(1) RSSI1(1) RSSI0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 RSSI<7:0>: Averaged RSSI Value bits(1) Note 1: The number of RSSI samples averaged, set by RSSINUMx (0x25<5:4>) bits. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 69

MRF24J40 REGISTER 2-72: SLPCON0: SLEEP CLOCK CONTROL 0 REGISTER (ADDRESS: 0x211) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r r r r r r INTEDGE(1) SLPCLKEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Reserved: Maintain as ‘0’ bit 1 INTEDGE: Interrupt Edge Polarity bit(1) 1 = Rising edge 0 = Falling edge (default) bit 0 SLPCLKEN: Sleep Clock Enable bit 1 = Disabled 0 = Enabled (default) Note 1: Ensure that the interrupt polarity matches the interrupt pin polarity on the host microcontroller. REGISTER 2-73: SLPCON1: SLEEP CLOCK CONTROL 1 REGISTER (ADDRESS: 0x220) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r r CLKOUTEN SLPCLKDIV4 SLPCLKDIV3 SLPCLKDIV2 SLPCLKDIV1 SLPCLKDIV0 bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Reserved: Maintain as ‘0’ bit 5 CLKOUTEN: CLKOUT Pin Enable bit The CLKOUT pin 26 feature has been discontinued. It is recommended that it be disabled. 1 = Disable (recommended) 0 = Enable (default) bit 4-0 SLPCLKDIV<4:0>: Sleep Clock Divisor bits Sleep clock is divided by 2n, where n = SLPCLKDIV.(1) Default value: 0x00. Note 1: If the Sleep Clock Selection, SLPCLKSEL (0x207<7:6), is the internal oscillator (100 kHz), set SLPCLKDIV to a minimum value of 0x01. Preliminary DS39776C-page 70 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-74: WAKETIMEL: WAKE-UP TIME MATCH VALUE LOW REGISTER (ADDRESS: 0x222) R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 WAKETIME7(1) WAKETIME6(1) WAKETIME5(1) WAKETIME4(1) WAKETIME3(1)WAKETIME2(1) WAKETIME1(1) WAKETIME0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 WAKETIME<7:0>: Wake Time Match Value bits(1) WAKETIME is an 11-bit value that is compared with the Main Counter (MAINCNT) to signal the time to enable (wake-up) the 20 MHz main oscillator when the MRF24J40 is using the Sleep mode timers. Default value: 0x00A. Minimum value: 0x001. Note 1: Rule: WAKETIME > WAKECNT. REGISTER 2-75: WAKETIMEH: WAKE-UP TIME MATCH VALUE HIGH REGISTER (ADDRESS: 0x223) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r r r r r WAKETIME10(1) WAKETIME9(1) WAKETIME8(1) bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Reserved: Maintain as ‘0’ bit 2-0 WAKETIME<10:8>: Wake-up Time Counted by SLPCLK bits(1) WAKETIME is an 11-bit value that is compared with the Main Counter (MAINCNT) to signal the time to enable (wake-up) the 20 MHz main oscillator when the MRF24J40 is using the Sleep mode timers. Default value: 0x00A. Minimum value: 0x001. Note 1: Rule: WAKETIME > WAKECNT. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 71

MRF24J40 REGISTER 2-76: REMCNTL: REMAIN COUNTER LOW REGISTER (ADDRESS: 0x224) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 REMCNT7 REMCNT6 REMCNT5 REMCNT4 REMCNT3 REMCNT2 REMCNT1 REMCNT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 REMCNT<7:0>: Remain Counter bits Remain counter is a 16-bit counter. Together with the main counter times events: Beacon Interval (BI) and inactive period for beacon-enabled devices and Sleep interval for nonbeacon-enabled devices. Units: tick (50 ns). REGISTER 2-77: REMCNTH: REMAIN COUNTER HIGH REGISTER (ADDRESS: 0x225) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 REMCNT15 REMCNT14 REMCNT13 REMCNT12 REMCNT11 REMCNT10 REMCNT9 REMCNT8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 REMCNT<15:8>: Remain Counter bits Remain counter is a 16-bit counter. Together with the main counter times events: Beacon Interval (BI) and inactive period for beacon-enabled devices and Sleep interval for nonbeacon-enabled devices. Units: tick (50 ns). Preliminary DS39776C-page 72 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-78: MAINCNT0: MAIN COUNTER 0 REGISTER (ADDRESS: 0x226) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MAINCNT7 MAINCNT6 MAINCNT5 MAINCNT4 MAINCNT3 MAINCNT2 MAINCNT1 MAINCNT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 MAINCNT<7:0>: Main Counter bits Main counter is a 26-bit counter. Together with the remain counter times events: Beacon Interval (BI) and inactive period for beacon-enabled devices and Sleep interval for nonbeacon-enabled devices. Units: SLPCLK.(1) Note 1: Sleep Clock (SLPCLK) period depends on the Sleep Clock Selection (SLPCLKSEL) RFCON<7:6> and Sleep Clock Divisor (SLPCLKDIV) CLKCON<4:0> bits. REGISTER 2-79: MAINCNT1: MAIN COUNTER 1 REGISTER (ADDRESS: 0x227) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MAINCNT15 MAINCNT14 MAINCNT13 MAINCNT12 MAINCNT11 MAINCNT10 MAINCNT9 MAINCNT8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 MAINCNT<15:8>: Main Counter bits Main counter is a 26-bit counter. Together with the remain counter times events: Beacon Interval (BI) and inactive period for beacon-enabled devices and Sleep interval for nonbeacon-enabled devices. Units: SLPCLK.(1) Note 1: Sleep Clock (SLPCLK) period depends on the Sleep Clock Selection (SLPCLKSEL) RFCON<7:6> and Sleep Clock Divisor (SLPCLKDIV) CLKCON<4:0> bits. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 73

MRF24J40 REGISTER 2-80: MAINCNT2: MAIN COUNTER 2 REGISTER (ADDRESS: 0x228) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MAINCNT23 MAINCNT22 MAINCNT21 MAINCNT20 MAINCNT19 MAINCNT18 MAINCNT17 MAINCNT16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 MAINCNT<23:16>: Main Counter bits Main counter is a 26-bit counter. Together with the remain counter times events: Beacon Interval (BI) and inactive period for beacon-enabled devices and Sleep interval for nonbeacon-enabled devices. Units: SLPCLK.(1) Note 1: Sleep Clock (SLPCLK) period depends on the Sleep Clock Selection (SLPCLKSEL) RFCON<7:6> and Sleep Clock Divisor (SLPCLKDIV) CLKCON<4:0> bits. REGISTER 2-81: MAINCNT3: MAIN COUNTER 3 REGISTER (ADDRESS: 0x229) W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STARTCNT r r r r r MAINCNT25 MAINCNT24 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STARTCNT: Start Sleep Mode Counters bits 1 = Trigger Sleep mode for Nonbeacon Enable mode (BO = 0xF and Slotted = 0). Bit automatically clears to ‘0’. bit 6-2 Reserved: Maintain as ‘0’ bit 1-0 MAINCNT<25:24>: Main Counter bits Main counter is a 26-bit counter. Together with the remain counter times events: Beacon Interval (BI) and inactive period for beacon-enabled devices and Sleep interval for nonbeacon-enabled devices. Units: SLPCLK.(1) Note 1: Sleep Clock (SLPCLK) period depends on the Sleep Clock Selection (SLPCLKSEL) RFCON<7:6> and Sleep Clock Divisor (SLPCLKDIV) CLKCON<4:0> bits. Preliminary DS39776C-page 74 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-82: TESTMODE: TEST MODE REGISTER (ADDRESS: 0x22F) R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 r r r RSSIWAIT1 RSSIWAIT0 TESTMODE2 TESTMODE1 TESTMODE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Reserved: Maintain as ‘0’ bit 4-3 RSSIWAIT<1:0>: RSSI State Machine Parameter bits 01 = Optimized value (default) bit 2-0 TESTMODE<2:0>: Test Mode bits 111 = GPIO0, GPIO1 and GPIO2 are configured to control an external PA and/or LNA(1) 101 = Single Tone Test mode 000 = Normal operation (default) Note 1: Refer to Section 4.2 “External PA/LNA Control” for more information. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 75

MRF24J40 REGISTER 2-83: ASSOEADR0: ASSOCIATED COORDINATOR EXTENDED ADDRESS 0 REGISTER (ADDRESS: 0x230) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ASSOEADR7 ASSOEADR6 ASSOEADR5 ASSOEADR4 ASSOEADR3 ASSOEADR2 ASSOEADR1 ASSOEADR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ASSOEADR<7:0>: 64-Bit Extended Address of Associated Coordinator bits REGISTER 2-84: ASSOEADR1: ASSOCIATED COORDINATOR EXTENDED ADDRESS 1 REGISTER (ADDRESS: 0x231) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ASSOEADR15 ASSOEADR14 ASSOEADR13 ASSOEADR12 ASSOEADR11 ASSOEADR10 ASSOEADR9 ASSOEADR8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ASSOEADR<15:8>: 64-Bit Extended Address of Associated Coordinator bits Preliminary DS39776C-page 76 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-85: ASSOEADR2: ASSOCIATED COORDINATOR EXTENDED ADDRESS 2 REGISTER (ADDRESS: 0x232) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ASSOEADR23 ASSOEADR22 ASSOEADR21 ASSOEADR20 ASSOEADR19 ASSOEADR18 ASSOEADR17 ASSOEADR16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ASSOEADR<23:16>: 64-Bit Extended Address of Associated Coordinator bits REGISTER 2-86: ASSOEADR3: ASSOCIATED COORDINATOR EXTENDED ADDRESS 3 REGISTER (ADDRESS: 0x233) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ASSOEADR31 ASSOEADR30 ASSOEADR29 ASSOEADR28 ASSOEADR27 ASSOEADR26 ASSOEADR25 ASSOEADR24 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ASSOEADR<31:24>: 64-Bit Extended Address of Associated Coordinator bits Preliminary © 2010 Microchip Technology Inc. DS39776C-page 77

MRF24J40 REGISTER 2-87: ASSOEADR4: ASSOCIATED COORDINATOR EXTENDED ADDRESS 4 REGISTER (ADDRESS: 0x234) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ASSOEADR39 ASSOEADR38 ASSOEADR37 ASSOEADR36 ASSOEADR35 ASSOEADR34 ASSOEADR33 ASSOEADR32 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ASSOEADR<39:32>: 64-Bit Extended Address of Associated Coordinator bits REGISTER 2-88: ASSOEADR5: ASSOCIATED COORDINATOR EXTENDED ADDRESS 5 REGISTER (ADDRESS: 0x235) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ASSOEADR47 ASSOEADR46 ASSOEADR45 ASSOEADR44 ASSOEADR43 ASSOEADR42 ASSOEADR41 ASSOEADR40 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ASSOEADR<47:40>: 64-Bit Extended Address of Associated Coordinator bits Preliminary DS39776C-page 78 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-89: ASSOEADR6: ASSOCIATED COORDINATOR EXTENDED ADDRESS 6 REGISTER (ADDRESS: 0x236) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ASSOEADR55 ASSOEADR54 ASSOEADR53 ASSOEADR52 ASSOEADR51 ASSOEADR50 ASSOEADR49 ASSOEADR48 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ASSOEADR<55:48>: 64-Bit Extended Address of Associated Coordinator bits REGISTER 2-90: ASSOEADR7: ASSOCIATED COORDINATOR EXTENDED ADDRESS 7 REGISTER (ADDRESS: 0x237) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ASSOEADR63 ASSOEADR62 ASSOEADR61 ASSOEADR60 ASSOEADR59 ASSOEADR58 ASSOEADR57 ASSOEADR56 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ASSOEADR<63:56>: 64-Bit Extended Address of Associated Coordinator bits Preliminary © 2010 Microchip Technology Inc. DS39776C-page 79

MRF24J40 REGISTER 2-91: ASSOSADR0: ASSOCIATED COORDINATOR SHORT ADDRESS 0 REGISTER (ADDRESS: 0x238) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ASSOSADR7 ASSOSADR6 ASSOSADR5 ASSOSADR4 ASSOSADR3 ASSOSADR2 ASSOSADR1 ASSOSADR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ASSOSADR<7:0>: 16-Bit Short Address of Associated Coordinator bits REGISTER 2-92: ASSOSADR1: ASSOCIATED COORDINATOR SHORT ADDRESS 1 REGISTER (ADDRESS: 0x239) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ASSOSADR15 ASSOSADR14 ASSOSADR13 ASSOSADR12 ASSOSADR11 ASSOSADR10 ASSOSADR9 ASSOSADR8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ASSOSADR<15:8>: 16-Bit Short Address of Associated Coordinator bits Preliminary DS39776C-page 80 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-93: UPNONCE0: UPPER NONCE SECURITY 0 REGISTER (ADDRESS: 0x240) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE7 UPNONCE6 UPNONCE5 UPNONCE4 UPNONCE3 UPNONCE2 UPNONCE1 UPNONCE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 UPNONCE<7:0>: Upper Nonce bits 13-byte nonce value used in security. REGISTER 2-94: UPNONCE1: UPPER NONCE SECURITY 1 REGISTER (ADDRESS: 0x241) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE15 UPNONCE14 UPNONCE13 UPNONCE12 UPNONCE11 UPNONCE10 UPNONCE9 UPNONCE8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 UPNONCE<15:8>: Upper Nonce bits 13-byte nonce value used in security. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 81

MRF24J40 REGISTER 2-95: UPNONCE2: UPPER NONCE SECURITY 2 REGISTER (ADDRESS: 0x242) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE23 UPNONCE22 UPNONCE21 UPNONCE20 UPNONCE19 UPNONCE18 UPNONCE17 UPNONCE16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 UPNONCE<23:16>: Upper Nonce bits 13-byte nonce value used in security. REGISTER 2-96: UPNONCE3: UPPER NONCE SECURITY 3 REGISTER (ADDRESS: 0x243) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE31 UPNONCE30 UPNONCE29 UPNONCE28 UPNONCE27 UPNONCE26 UPNONCE25 UPNONCE24 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 UPNONCE<31:24>: Upper Nonce bits 13-byte nonce value used in security. Preliminary DS39776C-page 82 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-97: UPNONCE4: UPPER NONCE SECURITY 4 REGISTER (ADDRESS: 0x244) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE39 UPNONCE38 UPNONCE37 UPNONCE36 UPNONCE35 UPNONCE34 UPNONCE33 UPNONCE32 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 UPNONCE<39:32>: Upper Nonce bits 13-byte nonce value used in security. REGISTER 2-98: UPNONCE5: UPPER NONCE SECURITY 5 REGISTER (ADDRESS: 0x245) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE47 UPNONCE46 UPNONCE45 UPNONCE44 UPNONCE43 UPNONCE42 UPNONCE41 UPNONCE40 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 UPNONCE<47:40>: Upper Nonce bits 13-byte nonce value used in security. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 83

MRF24J40 REGISTER 2-99: UPNONCE6: UPPER NONCE SECURITY 6 REGISTER (ADDRESS: 0x246) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE55 UPNONCE54 UPNONCE53 UPNONCE52 UPNONCE51 UPNONCE50 UPNONCE49 UPNONCE48 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 UPNONCE<55:48>: Upper Nonce bits 13-byte nonce value used in security. REGISTER 2-100: UPNONCE7: UPPER NONCE SECURITY 7 REGISTER (ADDRESS: 0x247) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE63 UPNONCE62 UPNONCE61 UPNONCE60 UPNONCE59 UPNONCE58 UPNONCE57 UPNONCE56 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 UPNONCE<63:56>: Upper Nonce bits 13-byte nonce value used in security. Preliminary DS39776C-page 84 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-101: UPNONCE8: UPPER NONCE SECURITY 8 REGISTER (ADDRESS: 0x248) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE71 UPNONCE70 UPNONCE69 UPNONCE68 UPNONCE67 UPNONCE66 UPNONCE65 UPNONCE64 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 UPNONCE<71:64>: Upper Nonce bits 13-byte nonce value used in security. REGISTER 2-102: UPNONCE9: UPPER NONCE SECURITY 9 REGISTER (ADDRESS: 0x249) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE79 UPNONCE78 UPNONCE77 UPNONCE76 UPNONCE75 UPNONCE74 UPNONCE73 UPNONCE72 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 UPNONCE<79:72>: Upper Nonce bits 13-byte nonce value used in security. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 85

MRF24J40 REGISTER 2-103: UPNONCE10: UPPER NONCE SECURITY 10 REGISTER (ADDRESS: 0x24A) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE87 UPNONCE86 UPNONCE85 UPNONCE84 UPNONCE83 UPNONCE82 UPNONCE81 UPNONCE80 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 UPNONCE<87:80>: Upper Nonce bits 13-byte nonce value used in security. REGISTER 2-104: UPNONCE11: UPPER NONCE SECURITY 11 REGISTER (ADDRESS: 0x24B) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE95 UPNONCE94 UPNONCE93 UPNONCE92 UPNONCE91 UPNONCE90 UPNONCE89 UPNONCE88 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 UPNONCE<95:88>: Upper Nonce bits 13-byte nonce value used in security. Preliminary DS39776C-page 86 © 2010 Microchip Technology Inc.

MRF24J40 REGISTER 2-105: UPNONCE12: UPPER NONCE SECURITY 12 REGISTER (ADDRESS: 0x24C) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE103 UPNONCE102 UPNONCE101 UPNONCE100 UPNONCE99 UPNONCE98 UPNONCE97 UPNONCE96 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 UPNONCE<103:96>: Upper Nonce bits 13-byte nonce value used in security. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 87

MRF24J40 NOTES: Preliminary DS39776C-page 88 © 2010 Microchip Technology Inc.

MRF24J40 3.0 FUNCTIONAL DESCRIPTION • Software Reset – A Software Reset can be performed by the host microcontroller. The power management circuitry is reset by setting the 3.1 Reset RSTPWR (0x2A<2>) bit to ‘1’. The control The MRF24J40 has four Reset types: registers retain their values. The baseband circuitry is reset by setting the RSTBB (0x2A<1>) • Power-on Reset – The MRF24J40 has built-in bit to ‘1’. The control registers retain their values. Power-on Reset circuitry that will automatically The MAC circuitry is reset by setting the RSTMAC reset all control registers when power is applied. It (0x2A<0>) bit to ‘1’. All control registers will be is recommended to delay 2 ms after a Reset reset. The Resets can be performed individually before accessing the MRF24J40 to allow the RF or together. The bit(s) will be automatically circuitry to start up and stabilize. cleared to ‘0’ by hardware. No delay is necessary • RESET Pin – The MRF24J40 can be reset by the after a Software Reset. host microcontroller by asserting the RESET pin • RF State Machine Reset – Perform an RF State 13 low. All control registers will be reset. The Machine Reset by setting to ‘1’ the RFRST MRF24J40 will be released from Reset approxi- (RFCTL 0x36<2>) bit and then clearing to ‘0’. mately 250 μs after RESET is released. The Delay at least 192 μs after performing to allow the RESET pin has an internal weak pull-up resistor. RF circuitry to calibrate. The control registers It is recommended to delay 2 ms after a Reset retain their values. before accessing the MRF24J40 to allow the RF circuitry to start up and stabilize. Note: The RF state machine should be Reset after the frequency channel has been changed (RFCON0 0x200). TABLE 3-1: REGISTERS ASSOCIATED WITH RESET Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x2A SOFTRST r r r r r RSTPWR RSTBB RSTMAC 0x36 RFCTL r r r WAKECNT8 WAKECNT7 RFRST RFTXMODE RFRXMODE Preliminary © 2010 Microchip Technology Inc. DS39776C-page 89

MRF24J40 3.2 Initialization Certain control register values must be initialized for basic operations. These values differ from the Power-on Reset values and provide improved opera- tional parameters. These settings are normally made once after a Reset. After initialization, MRF24J40 features can be configured for the application. The steps for initialization are shown in Example 3-1. EXAMPLE 3-1: INITIALIZING THE MRF24J40 Example steps to initialize the MRF24J40: 1. SOFTRST (0x2A) = 0x07 – Perform a software Reset. The bits will be automatically cleared to ‘0’ by hardware. 2. PACON2 (0x18) = 0x98 – Initialize FIFOEN = 1 and TXONTS = 0x6. 3. TXSTBL (0x2E) = 0x95 – Initialize RFSTBL = 0x9. 4. RFCON0 (0x200) = 0x03 – Initialize RFOPT = 0x03. 5. RFCON1 (0x201) = 0x01 – Initialize VCOOPT = 0x02. 6. RFCON2 (0x202) = 0x80 – Enable PLL (PLLEN = 1). 7. RFCON6 (0x206) = 0x90 – Initialize TXFIL = 1 and 20MRECVR = 1. 8. RFCON7 (0x207) = 0x80 – Initialize SLPCLKSEL = 0x2 (100 kHz Internal oscillator). 9. RFCON8 (0x208) = 0x10 – Initialize RFVCO = 1. 10. SLPCON1 (0x220) = 0x21 – Initialize CLKOUTEN = 1 and SLPCLKDIV = 0x01. Configuration for nonbeacon-enabled devices (see Section 3.8 “Beacon-Enabled and Nonbeacon-Enabled Networks”): 11. BBREG2 (0x3A) = 0x80 – Set CCA mode to ED. 12. CCAEDTH = 0x60 – Set CCA ED threshold. 13. BBREG6 (0x3E) = 0x40 – Set appended RSSI value to RXFIFO. 14. Enable interrupts – See Section 3.3 “Interrupts”. 15. Set channel – See Section 3.4 “Channel Selection”. Note: Maintain 0x200<3:0> = 0x03 16. Set transmitter power - See “REGISTER 2-62: RF CONTROL 3 REGISTER (ADDRESS: 0x203)”. 17. RFCTL (0x36) = 0x04 – Reset RF state machine. 18. RFCTL (0x36) = 0x00. 19. Delay at least 192 μs. TABLE 3-2: REGISTERS ASSOCIATED WITH INITIALIZATION Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x18 PACON2 FIFOEN r TXONTS3 TXONTS2 TXONTS1 TXONTS0 TXONT8 TXONT7 0x2A SOFTRST r r r r r RSTPWR RSTBB RSTMAC 0x2E TXSTBL RFSTBL3 RFSTBL2 RFSTBL1 RFSTBL0 MSIFS3 MSIFS2 MSIFS1 MSIFS0 0x201 RFCON1 VCOOPT7 VCOOPT6 VCOOPT5 VCOOPT4 VCOOPT3 VCOOPT2 VCOOPT1 VCOOPT0 0x202 RFCON2 PLLEN r r r r r r r 0x206 RFCON6 TXFIL r r 20MRECVR BATEN r r r 0x207 RFCON7 SLPCLKSEL1 SLPSCKSEL0 r r r r r r 0x208 RFCON8 r r r RFVCO r r r r 0x220 SLPCON1 r r CLKOUTEN SLPCLKDIV4 SLPCLKDIV3 SLPCLKDIV2 SLPCLKDIV1 SLPCLKDIV0 Preliminary DS39776C-page 90 © 2010 Microchip Technology Inc.

MRF24J40 3.3 Interrupts interrupt until the INTSTAT register is read. The edge polarity of the INT pin is configured via the INTEDGE The MRF24J40 has one interrupt (INT) pin 16 that bit in the SLPCON0 (0x211<1>) register. signals one of eight interrupt events to the host microcontroller. The interrupt structure is shown in Note1: The INTEDGE polarity defaults to: Figure 3-1. Interrupts are enabled via the INTCON 0 = Falling Edge. Ensure that the inter- (0x32) register. Interrupt flags are located in the rupt polarity matches the interrupt pin INTSTAT (0x31) register. The INTSTAT register polarity of the host microcontroller. clears-to-zero upon read. Therefore, the host 2: The INT pin will remain high or low, microcontroller should read and store the INTSTAT depending on INTEDGE polarity setting, register and check the bits to determine which interrupt until INTSTAT register is read. occurred. The INT pin will continue to signal an FIGURE 3-1: MRF24J40 INTERRUPT LOGIC INTSTAT.SLPIF INTCON.SLPIE INTSTAT.WAKEIF INTCON.WAKEIE INTSTAT.HSYMTMRIF INTCON.HSYMTMRIE SLPCON0.INTEDGE INTSTAT.SECIF INTCON.SECIE INT INTSTAT.RXIF INTCON.RXIE INTSTAT.TXG2IF INTCON.TXG2IE INTSTAT.TXG1IF INTCON.TXG1IE INTSTAT.TXNIF INTCON.TXNIE TABLE 3-3: REGISTERS ASSOCIATED WITH INTERRUPTS Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x31 INTSTAT SLPIF WAKEIF HSYMTMRIF SECIF RXIF TXG2IF TXG1IF TXNIF 0x32 INTCON SLPIE WAKEIE HSYMTMRIE SECIE RXIE TXG2IE TXG1IE TXNIE 0x211 SLPCON0 r r r r r r INTEDGE SLPCKEN Preliminary © 2010 Microchip Technology Inc. DS39776C-page 91

MRF24J40 3.4 Channel Selection TABLE 3-4: CHANNEL SELECTION RFCON0 (0x200) REGISTER The MRF24J40 is capable of selecting one of sixteen SETTING channel frequencies in the 2.4 GHz band. The desired channel is selected by configuring the CHANNEL bits Channel Frequency Set Value in the RFCON0 (0x200<7:4>) register. See Table 3-4 Number for the RFCON0 register setting for channel number 11 2.405 GHz 0x03 and frequency. 12 2.410 GHz 0x13 Note: Perform an RF State Machine Reset (see 13 2.415 GHz 0x23 Section 3.1 “Reset”) after a channel 14 2.420 GHz 0x33 frequency change. Then, delay at least 192 μs after the RF State Machine Reset, 15 2.425 GHz 0x43 to allow the RF circuitry to calibrate. 16 2.430 GHz 0x53 17 2.435 GHz 0x63 18 2.440 GHz 0x73 19 2.445 GHz 0x83 20 2.450 GHz 0x93 21 2.455 GHz 0xA3 22 2.460 GHz 0xB3 23 2.465 GHz 0xC3 24 2.470 GHz 0xD3 25 2.475 GHz 0xE3 26 2.480 GHz 0xF3 TABLE 3-5: REGISTERS ASSOCIATED WITH CHANNEL SELECTION Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x36 RFCTL r r r WAKECNT8 WAKECNT7 RFRST RFTX- RFRX- MODE MODE 0x200 RFCON0 CHANNEL3 CHANNEL2 CHANNEL1 CHANNEL0 RFOPT3 RFOPT2 RFOPT1 RFOPT0 Preliminary DS39776C-page 92 © 2010 Microchip Technology Inc.

MRF24J40 3.5 Clear Channel Assessment (CCA) 3.5.3 CCA MODE 3: CARRIER SENSE WITH ENERGY ABOVE The CCA signal is an indication to the MAC layer from THRESHOLD the PHY layer as to whether the medium is busy or idle. CCA reports a busy medium only upon detection of a The MRF24J40 provides three methods of performing signal with modulation or spreading characteristics of CCA. Refer to IEEE 802.15.4-2003 Standard, IEEE 802.15.4 with energy above the ED threshold. Section 6.7.9 “CCA”. 1. Program CCAMODE 0x3A<7:6> to the value, 3.5.1 CCA MODE 1: ENERGY ABOVE ‘11’. THRESHOLD 2. Program CCACSTH 0x3A<5:2> with the CCA CCA reports a busy medium upon detecting energy carrier sense threshold. above the Energy Detection (ED) threshold. 3. Program CCAEDTH 0x3F<7:0> with the CCA ED threshold (RSSI value). 1. Program CCAMODE 0x3A<7:6> to the value, ‘10’. 2. Program CCAEDTH 0x3F<7:0> with CCA ED The 8-bit CCAEDTH threshold can be mapped threshold value (RSSI value). to a power level according to RSSI. Refer to Section 3.6 “Received Signal Strength The 8-bit CCAEDTH threshold can be mapped Indicator (RSSI)/Energy Detection (ED)”. to a power level according to RSSI. Refer to Section 3.6 “Received Signal Strength Indicator (RSSI)/Energy Detection (ED)”. 3.5.2 CCA MODE 2: CARRIER SENSE ONLY CCA reports a busy medium only upon detection of a signal with the modulation and spreading characteris- tics of IEEE 802.15.4. This signal may or may not be above the ED threshold. 1. Program CCAMODE 0x3A<7:6> to the value, ‘01’. 2. Program CCACSTH 0x3A<5:2> with the CCA carrier sense threshold (units). TABLE 3-6: REGISTERS ASSOCIATED WITH CCA Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x3A BBREG2 CCAMODE1 CCAMODE0 CCACSTH3 CCACSTH2 CCACSTH1 CCACSTH0 r r 0x3F CCAEDTH CCAEDTH7 CCAEDTH6 CCAEDTH5 CCAEDTH4 CCAEDTH3 CCAEDTH2 CCAEDTH1 CCAEDTH0 Preliminary © 2010 Microchip Technology Inc. DS39776C-page 93

MRF24J40 3.6 Received Signal Strength 3.6.1 RSSI FIRMWARE REQUEST (RSSI Indicator (RSSI)/Energy Detection MODE1) (ED) In this mode, the host microcontroller sends a request to calculate RSSI, then waits until it is done and then RSSI/ED are an estimate of the received signal power reads the RSSI value. The steps are: within the bandwidth of an IEEE 802.15.4 channel. The RSSI value is an 8-bit value ranging from 0-255. The 1. Set RSSIMODE1 0x3E<7> – Initiate RSSI mapping between the RSSI values with the received calculation. power level is shown in Figure 3-3 and is shown in 2. Wait until RSSIRDY 0x3E<0> is set to ‘1’ – RSSI tabular form in Table 3-8. The number of symbols to calculation is complete. average can be changed by programming the 3. Read RSSI 0x210<7:0> – The RSSI register RSSINUM (TXBCON1 0x25<5:4>) bits. contains the averaged RSSI received power The programmer can obtain the RSSI/ED value in one level for 8 symbol periods. of two methods. 3.6.2 APPENDED RSSI TO THE RECEIVED PACKET (RSSI MODE 2) The RSSI value is appended at the end of each successfully received packet. To enable RSSI Mode 2, set RSSIMODE2 = 1 (0x3E<6>). The RSSI value will be appended to the RXFIFO as shown in Figure 3-2. FIGURE 3-2: PACKET FORMAT IN RX FIFO 1 Octet N Octets M Octets 2 Octets 1 Octet 1 Octet Frame Length Header Payload FCS LQI RSSI TABLE 3-7: REGISTERS ASSOCIATED WITH RSSI/ED Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x25 TXBCON1 TXBMSK WU/BCN RSSINUM1 RSSINUM0 r r r r 0x3E BBREG6 RSSIMODE1 RSSIMODE2 r r r r r RSSIRDY 0x210 RSSI RSSI7 RSSI6 RSSI5 RSSI4 RSSI3 RSSI2 RSSI1 RSSI0 Preliminary DS39776C-page 94 © 2010 Microchip Technology Inc.

MRF24J40 FIGURE 3-3: RSSI vs. RECEIVED POWER (dBm) 300 250 200 150 RSSI 100 50 0 -120 -100 -80 -60 -40 -20 0 -50 Received Power (dBm) Preliminary © 2010 Microchip Technology Inc. DS39776C-page 95

MRF24J40 RSSI versus received power (dB) is shown in tabular TABLE 3-8: RSSI vs. RECEIVED POWER form in Table 3-8. (dB) (CONTINUED) TABLE 3-8: RSSI vs. RECEIVED POWER Received Power RSSI Value RSSI Value (dB) (dBm) (hex) (dec) Received Power RSSI Value RSSI Value -59 0x8F 143 (dBm) (hex) (dec) -58 0x94 148 -100 0x0 0 -57 0x99 153 -99 0x0 0 -56 0x9F 159 -98 0x0 0 -55 0xA5 165 -97 0x0 0 -54 0xAA 170 -96 0x0 0 -53 0xB0 176 -95 0x0 0 -52 0xB7 183 -94 0x0 0 -51 0xBC 188 -93 0x0 0 -50 0xC1 193 -92 0x0 0 -49 0xC6 198 -91 0x0 0 -48 0xCB 203 -90 0x0 0 -47 0xCF 207 -89 0x1 1 -46 0xD4 212 -88 0x2 2 -45 0xD8 216 -87 0x5 5 -44 0xDD 221 -86 0x9 9 -43 0xE1 225 -85 0x0D 13 -42 0xE4 228 -84 0x12 18 -41 0xE9 233 -83 0x17 23 -40 0xEF 239 -82 0x1B 27 -39 0xF5 245 -81 0x20 32 -38 0xFA 250 -80 0x25 37 -37 0xFD 253 -79 0x2B 43 -36 0xFE 254 -78 0x30 48 -35 0xFF 255 -77 0x35 53 -34 0xFF 255 -76 0x3A 58 -33 0xFF 255 -75 0x3F 63 -32 0xFF 255 -74 0x44 68 -31 0xFF 255 -73 0x49 73 -30 0xFF 255 -72 0x4E 78 -29 0xFF 255 -71 0x53 83 -28 0xFF 255 -70 0x59 89 -27 0xFF 255 -69 0x5F 95 -26 0xFF 255 -68 0x64 100 -25 0xFF 255 -67 0x6B 107 -24 0xFF 255 -66 0x6F 111 -23 0xFF 255 -65 0x75 117 -22 0xFF 255 -64 0x79 121 -21 0xFF 255 -63 0x7D 125 -20 0xFF 255 -62 0x81 129 -61 0x85 133 -60 0x8A 138 Preliminary DS39776C-page 96 © 2010 Microchip Technology Inc.

MRF24J40 3.7 Link Quality Indication (LQI) 3.8 Beacon-Enabled and Nonbeacon-Enabled Networks Link Quality Indication (LQI) is a characterization of strength or quality of a received packet. Several The IEEE 802.15.4 Standard defines two modes of metrics, for example, RSSI, Signal to Noise Ratio operation: (SNR), RSSI combined with SNR, etc., can be used for • Beacon-enabled network measuring link quality. Using RSSI or SNR alone may not be the best way to estimate the quality of a link. The • Nonbeacon-enabled network received RSSI value will be a very high value if a packet 3.8.1 BEACON-ENABLED NETWORK is received with greater signal strength or even if an interferer is present in the channel. Hence, for better In a beacon-enabled network, beacons will be transmit- approximation of link quality, the MRF24J40 reports the ted periodically by the PAN coordinator. These correlation degree between spreading sequences and beacons are mainly used to provide synchronization the incoming chips during the reception of a packet. services between all the devices in the PAN and also to This correlation value is directly mapped to a range of support other extended features, like Guaranteed Time 0-255 (256 values), where an LQI value of 0 indicates Slots (GTS), a Quality of Service (QoS) mechanism for that the quality of the link is very low, and an LQI value the IEEE 802.15.4 Standard. The PAN coordinator of 255 indicates the quality of the link is very high. The defines the structure of the superframe using beacons. correlation degree between spreading sequences and incoming chips is computed over a period of 3 symbol periods during the reception of the preamble of a packet. The LQI is reported along with each received packet in the RX FIFO as shown in Figure 3-2. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 97

MRF24J40 3.8.1.1 Superframe Structure on the values of Beacon Order (BO) and Superframe Order (SO). The CFP, if present, follows immediately The superframe structure is shown in Figure 3-4. A after the CAP and extends to the end of active portion superframe is bounded by the transmission of a of the superframe. Any allocated GTSs shall be located beacon frame and can have an active and inactive in the CFP of the active portion of the superframe. portion. The coordinator will interact with its PAN only during the active portion of the superframe, and during All the frames transmitted in the CAP, except the inactive portion of the superframe, the coordinator Acknowledgement frames and data frames that imme- can go to a low-power mode. The active portion of the diately follow the data request command, must use superframe is divided into 16 equally spaced slots and slotted CSMA-CA. Refer to Section 3.9 “Carrier is composed of three parts: a beacon, a Contention Sense Multiple Access-Collision Avoidance Access Period (CAP) and an optional Contention Free (CSMA-CA) Algorithm” for more information. Period (CFP). The structure of the superframe depends FIGURE 3-4: SUPERFRAME STRUCTURE Backoff Period (aUnitBackoffPeriod = 20 symbols) CAP End Slot = ESLOTG1 (0x13<3:0>) Beacon Beacon GTS End Slots = ESLOTG23 (0x1E), ESLOTG45 (0x1F), ESLOT67 (0x20) Slot G T 0 1 2 3 4 5 6 7 8 GTS1 GTS3 Inactive Portion S 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CAP CFP Active Portion Inactive Portion Superframe Duration (SD) = aBaseSuperframeDuration * 2SO symbols (SO – ORDER 0x10<3:0>) SD Beacon Interval (BI) = aBaseSuperframeDuration * 2BO symbols (BO – ORDER 0x10<7:4>) BI Preliminary DS39776C-page 98 © 2010 Microchip Technology Inc.

MRF24J40 3.8.1.2 BO and SO 3.8.1.3 GTS Values of Beacon Order (BO) and Superframe Order If a device wants to transmit or receive during CFP, it (SO) determine the Beacon Interval (BI) and sends out a “GTS request” in the CAP to the PAN coor- Superframe Duration (SD). dinator. The PAN coordinator broadcasts the address of the device number for that device in the beacon Beacon Interval (BI) in terms of BO can be expressed as: frame if resources are available. BI = aBaseSuperframeduration * 2BO To support GTS operation, MRF24J40 uses Similarly, Superframe Duration (SD) in terms of SO can TXGTS1FIFO and TXGTS2FIFO. The TXGTS1FIFO be expressed as: and TXGTS2FIFO are ping-pong FIFOs and can be SD = aBaseSuperframeduration * 2SO assigned to different GTS slots or to the same slots. If both are assigned to the same slot, they take turns for where aBaseSuperframeduration = 960 symbols. transmission within that slot. TXGTS1FIFO and BO and SO can be configured by programming the BO TXGTS2FIFO can be triggered ahead of their slot time, (0x10<7:4>) bits and SO (0x10<3:0>) bits in the ORDER but transmission from the FIFO will take place exactly register. For beacon-enabled networks, the values of BO at the assigned slot time. and SO should be in the range, 0 ≤ SO ≤ BO ≤ 14. If the Refer to Section 3.12 “Transmission” for information values of BO and SO are equal, then the superframe on how to transmit a data frame using the does not have any inactive portion. A Beacon Interval TXGTSxFIFOs. can be as short as 15 ms or a long as 251 seconds based on the values of BO and SO. FIGURE 3-5: GTSFIFO STATE DIAGRAM GTSSWITCH = 1 GTSSWITCH = 0 Switch TXGTSxFIFO Hold and wait TXGTSxFIFO if Transmit Error if Transmit Error Wait for GTS Slot Wait for GTS Slot Transmit Error (clear TXG1TRIG and TXG2TRIG) TXGTS1FIFO TXGTS1FIFO Transmit Complete Transmit Complete or or Transmit Transmit Hold and Wait Transmit Error Transmit Error Complete Complete until Next GTS (clear TXG1TRIG) (clear TXG2TRIG) TXGTS2FIFO TXGTS2FIFO Transmit Error (clear TXG1TRIG Wait for GTS Slot Wait for GTS Slot and TXG2TRIG) Preliminary © 2010 Microchip Technology Inc. DS39776C-page 99

MRF24J40 3.8.1.4 Configuring Beacon-Enabled PAN 3.8.1.5 Configuring Beacon-Enabled GTS Coordinator Settings for PAN Coordinator The following steps configure the MRF24J40 as a The following steps configure the MRF24J40 as a coordinator in a beacon-enabled network: coordinator in a beacon-enabled network with Guaranteed Time Slots: 1. Set the PANCOORD (RXMCR 0x00<3>) bit = 1 to configure as PAN coordinator. 1. Set the GTSON (GATECLK 0x26 <3>) bit = 1 to 2. Set the SLOTTED (TXMCR 0x11<5>) bit = 1 to enable the GTS FIFO clock. use Slotted CSMA-CA mode. 2. Based on the number of GTSs that are active for 3. Load the beacon frame into the TXBFIFO the current superframe, program the end slot (0x080-0x0FF). value of each GTS into the ESLOT registers as shown in Table 3-9. 4. Set the TXBMSK (TXBCON1 0x25<7>) bit = 1 to mask the beacon interrupt mask. TABLE 3-9: PROGRAMMING END SLOT 5. Set INTL (WAKECON 0x22<5:0>) value to VALUES 0x03. 6. Program the CAP end slot (ESLOTG1 GTS Number Register 0x13<3:0>) value. If the coordinator supports CAP ESLOTG1 0x13<3:0> Guaranteed Time Slot operation, refer to Section 3.8.1.5 “Configuring Beacon-Enabled GTS1 ESLOTG1 0x13<7:4> GTS Settings for PAN Coordinator” below. GTS2 ESLOTG23 0x1E<3:0> 7. Calibrate the Sleep Clock (SLPCLK) frequency. GTS3 ESLOTG23 0x1E<7:4> Refer to Section 3.15.1.2 “Sleep Clock GTS4 ESLOTG45 0x1F<3:0> Calibration”. GTS5 ESLOTG45 0x1F<7:4> 8. Set WAKECNT (SLPACK 0x35<6:0>) GTS6 ESLOTG67 0x20<3:0> value = 0x5F to set the main oscillator (20 MHz) start-up timer value. GTS7 If 7th GTS exists, the end slot must 9. Program the Beacon Interval into the Main Coun- be 15 ter, MAINCNT (0x229<1:0>, 0x228, 0x227, 0x226), and Remain Counter, REMCNT (0x225, 3. Set the GTSSWITCH (TXPEND 0x21<1>) bit = 1 0x224), according to BO and SO values. Refer to so that if a TXGTS1FIFO or TXGTS2FIFO trans- Section 3.15.1.3 “Sleep Mode Counters”. mission error occurs, it will switch to another 10. Configure the BO (ORDER 0x10<7:4>) and SO TXGTSxFIFO. (ORDER 0x10<3:0>) values. After configuring BO and SO, the beacon frame will be sent immediately. Preliminary DS39776C-page 100 © 2010 Microchip Technology Inc.

MRF24J40 3.8.1.6 Configuring Beacon-Enabled Device 3.8.2 NONBEACON-ENABLED NETWORK The following steps configure the MRF24J40 as a A nonbeacon-enabled network does not transmit a device in a beacon-enabled network: beacon unless it receives a beacon request, and hence, does not have any superframe structure. A 1. Set the SLOTTED (TXMCR 0x11<5>) bit = 1 to nonbeacon-enabled network uses unslotted CSMA-CA use Slotted CSMA-CA mode. to access the medium. The unslotted CSMA-CA is 2. Set the OFFSET (FRMOFFSET 0x23<7:0>) explained in Section 3.9 “Carrier Sense Multiple value = 0x15 for optimum timing alignment. Access-Collision Avoidance (CSMA-CA) Algo- 3. Calibrate the Sleep Clock (SLPCLK) fre- rithm”. For nonbeacon-enabled networks, both BO and quency. Refer to Section 3.15.1.2 “Sleep SO are set to 15. Guaranteed Time Slots (GTS) are not Clock Calibration”. supported, and generally, devices require less comput- 4. Program the associated coordinator’s 64-bit ing power as there are no strict timing requirements that extended address to the ASSOEADR registers need to be met. (0x230-0x237). 3.8.2.1 Configuring Nonbeacon-Enabled 5. Program the associated coordinator’s 16-bit short address to the ASSOSADR registers PAN Coordinator (0x238-0x239). The following steps configure the MRF24J40 as a Note: The device will align its beacon frame with coordinator in a nonbeacon-enabled network: the associated coordinator’s beacon 1. Set the PANCOORD (RXMCR 0x00<3>) bit = 1 frame only when the source address to configure as the PAN coordinator. matches the ASSOEADR or ASSOSADR 2. Clear the SLOTTED (TXMCR 0x11<5>) bit = 0 value. to configure Unslotted CSMA-CA mode. 6. Parse the received associated coordinator’s 3. Configure BO (ORDER 0x10<7:4>) value = 0xF. beacon frame and extract the values of BO and 4. Configure SO (ORDER 0x10<3:0>) value = 0xF. SO. Calculate the inactive period and program the Main Counter, MAINCNT (0x229<1:0>, 3.8.2.2 Configuring Nonbeacon-Enabled 0x228, 0x227, 0x226), and Remain Counter, Device REMCNT (0x225, 0x224), according to the BO and SO values. Refer to Section 3.15.1.3 The following steps configure the MRF24J40 as a “Sleep Mode Counters”. device in a nonbeacon-enabled network: 7. Program the CAP end slot (ESLOTG1 1. Clear the PANCOORD (RXMCR 0x00<3>) bit = 0 0x13<3:0>) value. to configure as device. 2. Clear the SLOTTED (TXMCR 0x11<5>) bit = 0 3.8.1.7 Configuring Beacon-Enabled GTS to use Unslotted CSMA-CA mode. Settings for Device The following steps configure the MRF24J40 as a device in a beacon-enabled network with Guaranteed Time Slots: 1. Set the GTSON (GATECLK 0x26<3>) bit = 1 to enable the GTS FIFO clock. 2. Parse the received beacon frame and obtain the GTS allocation information. Program the end slot value of the CAP and each GTS into the ESLOT registers, as shown in Table 3-9. 3. Set the GTSSWITCH (TXPEND 0x21<1>) bit = 1 so that if a TXGTS1FIFO or TXGTS2FIFO trans- mission error occurs, it will switch to another TXGTSxFIFO. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 101

MRF24J40 TABLE 3-10: REGISTERS ASSOCIATED WITH SETTING UP BEACON-ENABLED AND NONBEACON-ENABLED NETWORKS Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00 RXMCR r r NOACKRSP r PANCOORD COORD ERRPKT PROMI 0x10 ORDER BO3 BO2 BO1 BO0 SO3 SO2 SO1 SO0 0x11 TXMCR NOCSMA BATLIFEXT SLOTTED MACMINBE1 MACMINB0 CSMABF2 CSMABF1 CSMABF0 0x13 ESLOTG1 GTS1-3 GTS1-2 GTS1-1 GTS1-0 CAP3 CAP2 CAP1 CAP0 0x1E ESLOTG23 GTS3-3 GTS3-2 GTS3-1 GTS3-0 GTS2-3 GTS2-2 GTS2-1 GTS2-0 0x1F ESLOTG45 GTS5-3 GTS5-2 GTS5-1 GTS5-0 GTS4-3 GTS4-2 GTS4-1 GTS4-0 0x20 ESLOTG67 r r r r GTS6-3 GTS6-2 GTS6-1 GTS6-0 0x21 TXPEND MLIFS5 MLIFS4 MLIFS3 MLIFS2 MLIFS1 MLIFS0 GTSSWITCH FPACK 0x22 WAKECON IMMWAKE REGWAKE INTL INTL INTL INTL INTL INTL 0x23 FRMOFFSET OFFSET7 OFFSET6 OFFSET5 OFFSET4 OFFSET3 OFFSET2 OFFSET1 OFFSET0 0x25 TXBCON1 TXBMSK WU/BCN RSSINUM1 RSSINUM0 r r r r 0x26 GATECLK r r r r GTSON r r r 0x35 SLPACK SLPACK WAKECNT6 WAKECNT5 WAKECNT4 WAKECNT3 WAKECNT2 WAKECNT1 WAKECNT0 0x224 REMCNTL REMCNT7 REMCNT6 REMCNT5 REMCNT4 REMCNT3 REMCNT2 REMCNT1 REMCNT0 0x225 REMCNTH REMCNT15 REMCNT14 REMCNT13 REMCNT12 REMCNT11 REMCNT10 REMCNT9 REMCNT8 0x226 MAINCNT0 MAINCNT7 MAINCNT6 MAINCNT5 MAINCNT4 MAINCNT3 MAINCNT2 MAINCNT1 MAINCNT0 0x227 MAINCNT1 MAINCNT15 MAINCNT14 MAINCNT13 MAINCNT12 MAINCNT11 MAINCNT10 MAINCNT9 MAINCNT8 0x228 MAINCNT2 MAINCNT23 MAINCNT22 MAINCNT21 MAINCNT20 MAINCNT19 MAINCNT18 MAINCNT17 MAINCNT16 0x229 MAINCNT3 STARTCNT r r r r r MAINCNT25 MAINCNT24 0x230 ASSOEADR0 ASSOEADR7 ASSOEADR6 ASSOEADR5 ASSOEADR4 ASSOEADR3 ASSOEADR2 ASSOEADR1 ASSOEADR0 0x231 ASSOEADR1 ASSOEADR15 ASSOEADR14 ASSOEADR13 ASSOEADR12 ASSOEADR11 ASSOEADR10 ASSOEADR9 ASSOEADR8 0x232 ASSOEADR2 ASSOEADR23 ASSOEADR22 ASSOEADR21 ASSOEADR20 ASSOEADR19 ASSOEADR18 ASSOEADR17 ASSOEADR16 0x233 ASSOEADR3 ASSOEADR31 ASSOEADR30 ASSOEADR29 ASSOEADR28 ASSOEADR27 ASSOEADR26 ASSOEADR25 ASSOEADR24 0x234 ASSOEADR4 ASSOEADR39 ASSOEADR38 ASSOEADR37 ASSOEADR36 ASSOEADR35 ASSOEADR34 ASSOEADR33 ASSOEADR32 0x235 ASSOEADR5 ASSOEADR47 ASSOEADR46 ASSOEADR45 ASSOEADR44 ASSOEADR43 ASSOEADR42 ASSOEADR41 ASSOEADR40 0x236 ASSOEADR6 ASSOEADR55 ASSOEADR54 ASSOEADR53 ASSOEADR52 ASSOEADR51 ASSOEADR50 ASSOEADR49 ASSOEADR48 0x237 ASSOEADR7 ASSOEADR63 ASSOEADR62 ASSOEADR61 ASSOEADR60 ASSOEADR59 ASSOEADR58 ASSOEADR57 ASSOEADR56 0x238 ASSOSADR0 ASSOSADR7 ASSOSADR6 ASSOSADR5 ASSOSADR4 ASSOSADR3 ASSOSADR2 ASSOSADR1 ASSOSADR0 0x239 ASSOSADR1 ASSOSADR15 ASSOSADR14 ASSOSADR13 ASSOSADR12 ASSOSADR11 ASSOSADR10 ASSOSADR9 ASSOSADR8 Preliminary DS39776C-page 102 © 2010 Microchip Technology Inc.

MRF24J40 3.9 Carrier Sense Multiple IEEE 802.15.4-2003, Section 7.5.1.3 “The CSMA-CA Access-Collision Avoidance Algorithm” for more information. This section covers the two modes and their settings. (CSMA-CA) Algorithm Note: Acknowledgment and beacon frames are MRF24J40 supports both unslotted and slotted sent without using a CSMA-CA CSMA-CA mechanisms, as defined in the mechanism. IEEE 802.15.4 Standard. In both modes, the CSMA-CA algorithm is implemented using units of time 3.9.1 UNSLOTTED CSMA-CA MODE called backoff periods. In slotted CSMA-CA, the back- off period boundaries of every device on the PAN shall Figure 3-6 shows the unslotted CSMA-CA algorithm. be aligned with the superframe slot boundaries of the This mode is used in a nonbeacon-enabled network PAN coordinator. In unslotted CSMA-CA, the backoff where the backoff periods of one device are not related periods of one device are not related in time to the in time to the backoff periods of any other device in the backoff periods of any other device in the PAN. Refer to network. Refer to IEEE 802.15.4-2003, Section 7.5.1.3 “The CSMA-CA Algorithm” for more information. Configuring the MRF24J40 for nonbeacon-enabled network operation is covered in Section 3.8.2 “Nonbeacon-Enabled Network”. FIGURE 3-6: UNSLOTTED CSMA-CA ALGORITHM Start macMinBE NB = 0, BE = macMinBE MACMINBE (TXMCR 0x11<4:3>) Delay for Random (2BE – 1) Backoff Periods Perform CCA Y Channel Idle? N NB = NB + 1, BE = min(BE + 1, aMaxBE) N NB > macMaxCSMABackoffs macMaxCSMABackoffs CSMABF (TXMCR 0x11<2:0>) Y FAILURE SUCCESS (Report Channel Access Failure (Transmit Pending Packet) to Host Microcontroller) TXNSTAT (TXSTAT 0x24<0>) CCAFAIL (TXSTAT 0x24<5>) Preliminary © 2010 Microchip Technology Inc. DS39776C-page 103

MRF24J40 To configure the MRF24J40 for Unslotted CSMA-CA 3.9.2 SLOTTED CSMA-CA MODE mode, clear SLOTTED (TXMCR 0x11<5>) bit = 0. Figure 3-7 shows the slotted CSMA-CA algorithm. This The macMinBE and macMaxCSMABackoff values in mode is used on a beacon-enabled network where the the MRF24J40 are set to the IEEE 802.15.4 Standard backoff period boundaries of every device on the network defaults. To program their values: shall be aligned with the superframe slot boundaries of • macMinBE – Program MACMINBE (TXMCR the PAN coordinator. Refer to IEEE 802.15.4-2003, Section 7.5.1.3 “The CSMA-CA Algorithm” for more infor- 0x11<4:3>) bits to a value between 0 and 3 (the mation. IEEE 802.15.4 Standard default is 3). • macMaxCSMABackoff – Program CSMABF Configuring the MRF24J40 for beacon-enabled (TXMCR 0x11<2:0>) bits to a value between 0 network operation is covered in Section 3.8.1 and 5 (the IEEE 802.15.4 Standard default is 4). “Beacon-Enabled Network”. FIGURE 3-7: SLOTTED CSMA-CA ALGORITHM Start Start NB = 0, CW = 2 NB = 0, CW = 2 Y BATBBLaIaFtttEteeXrryyT LL(TiiffXee M EECxxtRtee nn0ssxi1ioo1nn<6>) BEBxaatttteteenrrsyyi oLLniiff?ee Y BBEE == lleesssseerr((22,, mmaaccMMiinnBBEE)) BATLIFEXT (TXMCR 0x11<6>) Extension? N N macMinBE MACMINBEm (aTcXMMiCnBRE 0x11<4:3>) BBEE == mmaaccMMiinnBBEE MACMINBE (TXMCR 0x11<4:3>) Locate for Backoff Period Boundary Locate for Backoff Period Boundary Delay for Random (2BE – 1) Unit Backoff Periods Delay for Random (2BE – 1) Unit Backoff Periods Perform CCA on Backoff Period Boundary Perform CCA on Backoff Period Boundary Y Channel Idle? Y Channel Idle? N N CW = 2, NB = NB + 1, BE = min(BE+1, aMaxBE) CW = CW – 1 CW = 2, NB = NB + 1, BE = min(BE+1, aMaxBE) CW = CW – 1 N N N NB > macMaxCSMABackoffs? CW = 0? N NB > macMaxCSMABackoffs? CW = 0? macMaxCSMABackoffs CSMmaAcBMFa (xTCXSMMCABRa 0cxk1o1f<f2s:0>) Y CSMABF (TXMCR 0x11<2:0>) Y Y Y FAILURE SUCCESS (Report CFhAaInLnUeRl EAccess (Transm iSt UPCenCdEinSgS Packet) (ReFpaoirltu Creh taon Hneols Atccess (TTraXnNsmSTit APTen (dTinXgS PTaAckTe t) MMiFcaircoirlcuoorceno tntrootr lHolelolre)srt) TXNS0xT2A4T< (0T>X)STAT CCAFAIL (TXSTAT 0x24<5>) 0x24<0>) CCAFAIL (TXSTAT 0x24<5>) Preliminary DS39776C-page 104 © 2010 Microchip Technology Inc.

MRF24J40 To configure the MRF24J40 for Slotted CSMA-CA The macMinBE and macMaxCSMABackoff values are mode, set SLOTTED (TXMCR 0x11<5>) bit = 1. set to the IEEE 802.15.4 Standard defaults. To change their values: To program the battery life extension bit in the Slotted CSMA-CA mode, set BATLIFEXT (TXMCR 0x11<6>) • macMinBE – Program MACMINBE (TXMCR bit = 1. 0x11<4:3>) bits to a value between 0 and 3 (the default is 3). • macMaxCSMABackoff – Program CSMABF (TXMCR 0x11<2:0>) bits to a value between 0 and 5 (the default is 4). TABLE 3-11: REGISTERS ASSOCIATED WITH CSMA-CA Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x11 TXMCR NOCSMA BATLIFEXT SLOTTED MACMINBE1 MACMINB0 CSMABF2 CSMABF1 CSMABF0 Preliminary © 2010 Microchip Technology Inc. DS39776C-page 105

MRF24J40 3.10 Interframe Spacing (IFS) by the MSIFS (TXSTBL 0x2E<3:0>) and RFSTBL (TXSTBL 0x2E<7:4>) bits, where aMinSIFSPeriod = Interframe Spacing (IFS) allows the MAC sublayer time MSIFS + RFSTBL. to process data received by the PHY. The length of the The IEEE 802.15.4 Specification defines IFS period depends on the size of the frame that is to be aMinLIFSPeriod as a constant value of 40 symbol transmitted. Frames up to aMaxSIFSFrameSize periods. The aMinLIFSPeriod can be programmed (18 octets) in length shall be followed by a SIFS period by the MLIFS (TXPEND 0x21<7:2>) and RFSTBL of at least aMinSIFSPeriod (12) symbols. Frames with (TXSTBL 0x2E<7:4>) bits, where aMinLIFSPeriod = lengths greater than aMaxSIFSFrameSize shall be fol- MLFS + RFSTBL. lowed by a LIFS period of at least aMinLIFSPeriod (40) symbols. If the transmission requires an Acknowl- The IEEE 802.15.4 Specification defines aTurn- edgment, the IFS shall follow the Acknowledgment aroundTime as a constant value of 12 symbol frame. Figure 3-8 shows the relationship between periods. The aTurnaroundTime can be programmed frames and IFS periods. Refer to IEEE 802.15.4-2003, by the TURNTIME (TXTIME 0x27<7:4>) and RFSTBL Section 7.5.1.2 “IFS” for more information. (TXSTBL 0x2E<7:4>) bits, where aTurnaroundTime = TURNTIME + RFSTBL. The IEEE 802.15.4 Specification defines aMinSIFSPeriod as a constant value of 12 symbol periods. The aMinSIFSPeriod can be programmed FIGURE 3-8: INTERFRAME SPACING (IFS) Acknowledged Transmission: Long Frame ACK Short Frame ACK t LIFS t SIFS ack ack Unacknowledged Transmission: Long Frame Short Frame LIFS SIFS Where aTurnaroundTime ≤= t =≤ (aTurnaroundTime + aUnitBackoffPeriod) ack TABLE 3-12: REGISTERS ASSOCIATED WITH INTERFRAME SPACING Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x21 TXPEND MLIFS5 MLIFS4 MLIFS3 MLIFS2 MLIFS1 MLIFS0 GTSSWITCH FPACK 0x27 TXTIME TURNTIME3 TURNTIME2 TURNTIME1 TURNTIME0 r r r r 0x2E TXSTBL RFSTBL3 RFSTBL2 RFSTBL1 RFSTBL0 MSIFS3 MSIFS2 MSIFS1 MSIFS0 Preliminary DS39776C-page 106 © 2010 Microchip Technology Inc.

MRF24J40 3.11 Reception demodulated and the CRC is calculated and checked. The packet is accepted or rejected depending on the An IEEE 802.15.4 compliant packet is prefixed with a reception mode and frame filter, and placed in the Synchronization Header (SHR) containing the RXFIFO buffer. When the packet is placed in the preamble sequence and Start-of-Frame Delimiter RXFIFO, a Receive Interrupt (RXIF 0x31<3>) is issued. (SFD) fields. The preamble sequence enables the The RXFIFO address mapping is shown in Figure 3-9. receiver to achieve symbol synchronization. The following sections detail the reception operation of The MRF24J40 monitors incoming signals and looks the MRF24J40. for the preamble of IEEE 802.15.4 packets. When a valid synchronization is obtained, the entire packet is FIGURE 3-9: PACKET RECEPTION From On Air PPDU Air Packet 4 1 1 5 -127 1 1 octets PackePt SHtYru cture Preamble SFD LFeranmgteh PSDU RSSI RSSI SHR PHR PHY Payload Packet to RXMAC 1 m n 2 1 1 octets To Frame RXFIFO RXFIFO (mLe+nng+th2) Header (MHR) Data Payload (MSDU) FCS LQI RSSI RXFIFO Address: 0x300 0x301 to (0x301 + m – 1) (0x301 + m) to (0x301 + m + n – 1) (0x301 + m + n + 3) (0x301 + m + n + 2) (0x301 + m + n) to (0x301 + m + n + 1) Fields appended by RXMAC Fields removed by RXMAC Preliminary © 2010 Microchip Technology Inc. DS39776C-page 107

MRF24J40 3.11.1 RECEPTION MODES TABLE 3-14: FRAME FORMAT FILTER The MRF24J40 can be configured for one of three Filter Mode RXFLUSH (0x0D<3:1>) different Reception modes as shown in Table 3-13. An All Frames 000 (default) explanation of each of the modes follows. Command Only 100 TABLE 3-13: RECEPTION MODES Data Only 010 Beacon Only 001 Receive Mode RXMCR (0x00<1:0>) Normal 00 (default) 3.11.3 ACKNOWLEDGMENT REQUEST Error 10 If the received packet has the Acknowledgment Promiscuous 01 request bit set to ‘1’ (bit 5 of the Frame Control Field – refer to IEEE 802.15.4 Standard, Section 7.2.1.1 3.11.1.1 Normal Mode “Frame Control Field”), the TXMAC circuitry will send an Acknowledgment packet automatically. This feature Normal mode accepts only packets with a good CRC minimizes the processing duties of the host micro- and satisfies the requirements of the IEEE 802.15.4 controller and keeps the Acknowledgment timing within Specification, Section 7.5.6.2 “Reception and Rejection”: the IEEE 802.15.4 Specification. 1. The frame type subfield of the frame control field The sequence number field of the Acknowledgment shall not contain an illegal frame type. frame will contain the value of the sequence number of the received frame for which the Acknowledgment is to 2. If the frame type indicates that the frame is a be sent. beacon frame, the source PAN identifier shall match macPANId unless macPANID is equal to Refer to Section 3.13 “Acknowledgement” for more 0xFFFF, in which case, the beacon frame will be information. accepted regardless of the source PAN 3.11.4 RECEIVE INTERRUPT identifier. 3. If a destination PAN identifier is included in the Once the packet is accepted, depending on the Recep- frame, it shall match macPANId or shall be the tion mode (Normal, Error or Promiscuous) and frame broadcast PAN identifier (0xFFFF). format (all, command, data or beacon), it is placed in 4. If a short destination address is included in the the RXFIFO buffer and a Receive Interrupt (RXIF frame, it shall match either macShortAddress 0x31<3>) is issued. or the broadcast address (0xFFFF). Otherwise, Note: The INTSTAT (0x31) register if an extended destination address is included in clears-to-zero upon read. Therefore, the the frame, it shall match aExtendedAddress. host microcontroller should read and store 5. If only source addressing fields are included in a the INTSTAT register and check the bits to data or MAC command frame, the frame shall determine which interrupt occurred. Refer be accepted only if the device is a PAN to Section 3.3 “Interrupts” for more coordinator and the source PAN identifier information. matches macPANId. Data is placed into the RXFIFO buffer as shown in 3.11.1.2 Error Mode Figure 3-9. The host processor reads the RXFIFO via the SPI port by reading addresses, 0x300-0x38F. Error mode accepts packets with good or bad CRC. Address, 0x300, contains the received packet frame length which includes the header length, data payload 3.11.1.3 Promiscuous Mode length, plus 2 for the FCS bytes. An LQI and RSSI value Promiscuous mode accepts all packets with a good comes after the FCS. Refer to Section 3.6 “Received CRC. Signal Strength Indicator (RSSI)/Energy Detection (ED)” and Section 3.7 “Link Quality Indication (LQI)” 3.11.2 FRAME FORMAT FILTER for more information. Once the packet has been accepted, depending on the Reception mode above, the frame format is filtered according to Table 3-14. Command, data or beacon only frames can be filtered and placed in the RXFIFO buffer. All frames (default) can be selected placing all frame formats (command, data and beacon) in the RXFIFO. Preliminary DS39776C-page 108 © 2010 Microchip Technology Inc.

MRF24J40 The RXFIFO is a 128-byte dual port buffer. The The RXFIFO can only hold one packet at a time. It is RXMAC circuitry places the packet into the RXFIFO highly recommended that the host microcontroller read sequentially, byte by byte, using an internal pointer. the entire RXFIFO without interruption so that received The internal pointer is reset one of three ways: packets are not missed. 1. When the host microcontroller reads the first Note: When the first byte of the RXFIFO is read, byte of the packet. the MRF24J40 is ready to receive the next 2. Manually by setting the RXFLUSH (0x0D<0>) packet. To avoid receiving a packet while bit. The bit is automatically cleared to ‘0’ by the RXFIFO is being read, set the Receive hardware. Decode Inversion (RXDECINV) bit 3. Software Reset (see Section 3.1 “Reset” for (0x39<2>) to ‘1’ to disable the MRF24J40 more information). from receiving a packet off the air. Once the data is read from the RXFIFO, the RXDECINV should be cleared to ‘0’ to enable packet reception. Example 3-2 shows example steps to read the RXFIFO. EXAMPLE 3-2: STEPS TO READ RXFIFO Example steps to read the RXFIFO: 1. Receive RXIF interrupt. 2. Disable host microcontroller interrupts. 3. Set RXDECINV = 1; disable receiving packets off air. 4. Read address, 0x300; get RXFIFO frame length value. 5. Read RXFIFO addresses, 0x301 through (0x300 + Frame Length + 2); read packet data plus LQI and RSSI. 6. Clear RXDECINV = 0; enable receiving packets. 7. Enable host microcontroller interrupts. 3.11.5 SECURITY Security Interrupt (SECIF 0x31<4>) is issued. The host microcontroller can then decide to decrypt or ignore the If the received packet has the security enabled bit set to packet. See Section 3.17 “Security” for more ‘1’ (bit 3 of the frame control field; refer to IEEE 802.15.4 information. Standard, Section 7.2.1.1 “Frame Control Field”) a TABLE 3-15: REGISTERS ASSOCIATED WITH RECEPTION Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00 RXMCR r r NOACKRSP r PANCOORD COORD ERRPKT PROMI 0x0D RXFLUSH r WAKEPOL WAKEPAD r CMDONLY DATAONLY BCNONLY RXFLUSH 0x2A SOFTRST r r r r r RSTPWR RSTBB RSTMAC 0x31 INSTAT SLPIF WAKEIF HSYMTMRIF SECIF RXIF TXG2IF TXG1IF TXNIF 0x32 INTCON SLPIE WAKEIE HSYMTMRIE SECIE RXIE TXG2IE TXG1IE TXNIE 0x39 BBREG1 r r r r r RXDECINV r r Preliminary © 2010 Microchip Technology Inc. DS39776C-page 109

MRF24J40 3.12 Transmission Figure 3-10 summarizes the memory map for each of the TX FIFOs. Each TX FIFO occupies 128 bytes of IEEE 802.15.4 Standard defines four frame types: memory and can hold one frame at a time. Acknowledgment, Data, Beacon and MAC Command Figure 3-11 shows the flow of data from the TX FIFO to frame. The transmission of the Acknowledgment frame on air packet and summarizes the data, beacon and is handled automatically in hardware by the MRF24J40 MAC command frames. and is covered in Section 3.13 “Acknowledgement”. Hardware management of the transmission of data, FIGURE 3-10: MEMORY MAP OF TX beacon and MAC command frames are handled in four transmit (TX) FIFOs. FIFOS Each TX FIFO has a specific purpose depending on if the Long Address MRF24J40 is configured for Beacon or Non- Memory Space beacon-Enabled mode. Configuring the MRF24J40 for beacon-enabled network operation is covered in 0x000 Section 3.8.1 “Beacon-Enabled Network”. Configuring TX Normal FIFO 128 bytes the MRF24J40 for nonbeacon-enabled network operation is covered in Section 3.8.2 “Nonbeacon-Enabled 0x07F Network”. 0x080 The four TX FIFOs are: TX Beacon FIFO 128 bytes TX Normal FIFO – Used for the transmission of data 0x0FF and MAC command frames during the Contention 0x100 Access Phase (CAP) of the superframe if the device is TX GTS1 FIFO 128 bytes operating in Beacon-Enabled mode and for all transmissions when the device is operating in 0x17F Nonbeacon-Enabled mode. 0x180 TX Beacon FIFO – Used for the transmission of the TX GTS2 FIFO 128 bytes beacon frames. 0x1FF TX GTS1 FIFO and TX GTS2 FIFO – Used for the transmission of data during the Contention Free Period (CFP) of the superframe if the device is operating in Beacon-Enabled mode. Refer to Section 3.8.1 “Beacon-Enabled Network” for more information about guaranteed time slots in Beacon-Enabled mode. Preliminary DS39776C-page 110 © 2010 Microchip Technology Inc.

MRF24J40 FIGURE 3-11: PACKET TRANSMISSION 1 1 m n octets From Header Frame TX FIFO TX FIFO Length Length HHeeaaddeerr DPaatyalo Paadyload (m) (m + n) 2 1 4 – 20 n 2 octets DaFtao rFmraamte CForanmtroel SNeuqmuebnecre AdFdrieelsdssing Data Payload FCS MHR MSDU MFR 2 1 4 – 20 1 n – 1 2 octets MAC CoFmomrmaantd Frame CForanmtroel SNeuqmuebnecre AdFdrieelsdssing CoTmympeand Command Payload FCS MHR MSDU MFR 2 1 4 – 10 2 k m n – m – k – 2 2 octets BeaFcoonrm Fartame CForanmtroel SNeuqmuebnecre AdFdrieelsdssing SSpuepceifrifcraamtioen FGieTldSs PAFedindedrldeinssgs Beacon Payload FCS MHR MSDU MFR 4 1 1 8 – 127 octets PackePt SHtYru cture Preamble SFD LFeranmgteh PSDU SHR PHR PHY Payload AToir POanc kAeirt PPDU Fields appended by TXMAC Fields appended by TX baseband Preliminary © 2010 Microchip Technology Inc. DS39776C-page 111

MRF24J40 3.12.1 TX FIFOs FRAME STRUCTURE transmitted using in-line security, the Message Integrity Code (MIC) will be appended in the data payload by the The TX FIFOs are divided into four fields: MRF24J40. Refer to Section 3.17 “Security” for more Header length – Used primarily in Security mode and information about transmitting and receiving data in contains the length, in octets (bytes), of the MAC Security mode. In Beacon-Enabled mode, the Header (MHR). In Unsecure mode, this field is ignored. MRF24J40 will handle superframe timing, transmission of the beacon and data packets during CAP and CFP. Note: The header length field as implemented in the MRF24J40 is 5-bits long. Therefore, 3.12.2 TX NORMAL FIFO the header length maximum value is 31 octets (bytes). In Beacon-Enabled mode, the TX Normal FIFO is used for the transmission of data and MAC command frames Frame length – Contains the length, in octets (bytes), during the Contention Access Phase (CAP) of the of the MAC Header (MHR) and data payload. superframe. Header – Contains the MAC Header (MHR). In Nonbeacon-Enabled mode, the TX Normal FIFO is Payload – Contains the data payload. used for all transmissions. When the individual TX FIFO is triggered, the To transmit a packet in the TX Normal FIFO, perform MRF24J40 will handle transmitting the packet using the the following steps: CSMA-CA algorithm, Acknowledgment of the packet 1. The host processor loads the TX Normal FIFO (optional), retransmit if Acknowledgment not received with IEEE 802.15.4 compliant data or MAC within required time period and interframe spacing. The command frame using the format shown in MRF24J40 will add the Synchronization Header Figure 3-12. (SHR), PHY Header (PHR) and Frame Check Sequence (FCS) automatically. If a packet is to be FIGURE 3-12: TX NORMAL FIFO FORMAT octets 1 1 m n Header Frame Packet Structure Length Length Header Payload (m) (m + n) TX Normal FIFO 0x000 0x001 0x002 – (0x002 + m – 1) (0x002 + m) – (0x002 + m + n – 1) Memory Address 2. If the packet requires an Acknowledgment, the 4. Transmit the packet by setting the TXNTRIG Acknowledgment request bit in the frame control (TXNCON 0x1B<0>) bit = 1. The bit will be field should be set to ‘1’ in the MAC Header automatically cleared by hardware. (MHR) when the host microcontroller loads the TX 5. A TXNIF (INTSTAT 0x31<0>) interrupt will be Normal FIFO, and set the TXNACKREQ issued. The TXNSTAT (TXSTAT 0x24<0>) bit (TXNCON 0x1B<2>) bit = 1. Refer to indicates the status of the transmission: Section 3.13 “Acknowledgement” for more TXNSTAT = 0: Transmission was successful information about Acknowledgment configuration. TXNSTAT = 1: Transmission failed, retry count 3. If the frame is to be encrypted, the security exceeded enabled bit in the frame control field should be set to ‘1’ in the MAC Header (MHR) when the The number of retries of the most recent host microcontroller loads the TX Normal FIFO, transmission is contained in the TXNRETRY and set the TXNSECEN (TXNCON 0x1B<1>) (TXSTAT 0x24<7:6>) bits. The CCAFAIL bit = 1. Refer to Section 3.17 “Security” for (TXSTAT 0x24<5>) bit = 1 indicates if the failed more information about Security modes. transmission was due to the channel busy (CSMA-CA timed out). Preliminary DS39776C-page 112 © 2010 Microchip Technology Inc.

MRF24J40 3.12.3 TX BEACON FIFO To transmit a packet in the TX Beacon FIFO, perform the following steps: In Beacon-Enabled mode, the TX Beacon FIFO is used for the transmission of beacon frames during the 1. The host processor loads the TX Beacon FIFO beacon slot of the superframe. with an IEEE 802.15.4 compliant beacon frame using the format shown in Figure 3-13. In Nonbeacon-Enabled mode, the TX Beacon FIFO is used for the transmission of a beacon frame at the time it is triggered (transmitted). FIGURE 3-13: TX BEACON FIFO FORMAT octets 1 1 m n Header Frame Packet Structure Length Length Header Payload (m) (m + n) TX Beacon FIFO 0x080 0x081 0x082 – (0x082 + m – 1) (0x082 + m) – (0x082 + m + n – 1) Memory Address 2. If the beacon frame is to be encrypted, the 3. Transmit the packet by setting the TXBTRIG security enabled bit in the frame control field (TXBCON 0x1A<0>) bit = 1. The bit will be auto- should be set to ‘1’ in the MAC Header (MHR) matically cleared by hardware. If the MRF24J40 when the host microcontroller loads the TX is configured for Beacon-Enabled mode, the Beacon FIFO, and set the TXBSECEN beacon frame will be transmitted at the beacon (TXBCON 0x1A<1>) bit = 1. Refer to slot time at the beginning of the superframe. In Section 3.17 “Security” for more information Nonbeacon-Enabled mode, the beacon frame is about Security modes. transmitted at the time of triggering. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 113

MRF24J40 3.12.4 TX GTSx FIFO To transmit a packet in the TX GTSx FIFO, perform the following steps: In Beacon-Enabled mode, the TX GTSx FIFOs are used for the transmission of data or MAC command 1. The host processor loads the respective TX frames during the CFP of the superframe. Refer to GTSx FIFO with an IEEE 802.15.4 compliant Section 3.8.1 “Beacon-Enabled Network” for more data or MAC command frame using the format information about guaranteed time slots in shown in Figure 3-14. Beacon-Enabled mode. FIGURE 3-14: TX GTS1 AND GTS2 FIFOS FORMAT octets 1 1 m n Header Frame Packet Structure Length Length Header Payload (m) (m + n) TX GTS1 FIFO 0x100 0x101 0x102 – (0x102 + m – 1) (0x102 + m) – (0x102 + m + n – 1) Memory Address TX GTS2 FIFO 0x180 0x181 0x182 – (0x182 + m – 1) (0x182 + m) – (0x182 + m + n – 1) Memory Address 2. If the packet requires an Acknowledgment, the 6. Transmit the packet in the respective TX GTSx Acknowledgment request bit in the frame control FIFO by setting the TXG1TRIG (TXG1CON field should be set to ‘1’ in the MAC Header 0x1C<0>) or TXG2TRIG (TXG2CON 0x1D<0>) (MHR) when the host microcontroller loads the bit = 1. The bit will be automatically cleared by respective TX GTSx FIFO, and set the hardware. The packet will be transmitted at the TXG1ACKREQ (TXG1CON 0x1C<2>) or corresponding slot time of the superframe. TXG2ACKREQ (TXG2CON 0x1D<2>) bit = 1. 7. A TXG1IF (INTSTAT 0x31<1>) or TXG2IF Refer to Section 3.13 “Acknowledgement” for (INTSTAT 0x31<2>) interrupt will be issued. The more information about Acknowledgment TXG1STAT (TXSTAT 0x24<1>) or TXG2STAT configuration. (TXSTAT 0x24<2>) bit indicates the status of the 3. Program the number of retry times for the transmission: respective TX GTSx FIFO in the TXG1RETRY TXGxSTAT = 0: Transmission was successful (TXG1CON 0x1C<7:6>) or TXG2RETRY TXGxSTAT = 1: Transmission failed, retry (TXG2CON 0x1D<7:6>) bits. count exceeded 4. If the frame is to be encrypted, the security The number of retries of the most recent enabled bit in the frame control field should be transmission is contained in the TXG1RETRY set to ‘1’ in the MAC Header (MHR) when the (TXG1CON 0x1C<7:6>) or TXG2RETRY host microcontroller loads the TX GTSx FIFO, (TXG2CON 0x1D<7:6>) bits. The CCAFAIL and set the TXG1SECEN (TXG1CON (TXSTAT 0x24<5>) bit = 1 indicates if the failed 0x1C<1>) or TXG2SECEN (TXG2CON transmission was due to the channel busy 0x1D<1>) bit = 1. Refer to Section 3.17 “Secu- (CSMA-CA timed out). The TXG1FNT (TXSTAT rity” for more information about Security 0x24<3>) or TXG2FNT (TXSTAT 0x24<4>) modes. bit = 1 indicates if the TX GTSx FIFO transmis- 5. Program the slot number for the respective TX sion failed due to not enough time to transmit in GTSx FIFO in the TXG1SLOT (TXG1CON the guaranteed time slot. 0x1C<5:3> or TXG2SLOT (TXG2CON 0x1D<5:3>) bits. Preliminary DS39776C-page 114 © 2010 Microchip Technology Inc.

MRF24J40 TABLE 3-16: REGISTERS ASSOCIATED WITH TRANSMISSION Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x1A TXBCON0 r r r r r r TXBSECEN TXBTRIG 0x1B TXNCON r r r FPSTAT INDIRECT TXNACKREQ TXNSECEN TXNTRIG 0x1C TXG1CON TXG1RETRY1 TXG1RETRY0 TXG1SLOT2 TXG1SLOT1 TXG1SLOT0 TXG1ACKREQ TXG1SECEN TXG1TRIG 0x1D TXG2CON TXG2RETRY1 TXG2RETRY0 TXG2SLOT2 TXG2SLOT1 TXG2SLOT0 TXG2ACKREQ TXG2SECEN TXG2TRIG 0x24 TXSTAT TXNRETRY1 TXNRETRY0 CCAFAIL TXG2FNT TXG1FNT TXG2STAT TXG1STAT TXNSTAT 0x31 INTSTAT SLPIF WAKEIF HSYMTMRIF SECIF RXIF TXG2IF TXG1IF TXNIF 0x32 INTCON SLPIE WAKEIE HSYMTMRIE SECIE RXIE TXG2IE TXG1IE TXNIE Preliminary © 2010 Microchip Technology Inc. DS39776C-page 115

MRF24J40 3.13 Acknowledgement The MRF24J40 features hardware retransmit. It will automatically retransmit the packet if an Acknowledg- An Acknowledgment frame is used for confirming ment has not been received. The Acknowledgment successful frame reception. The successful reception of request bit in the frame control field should be pro- a data or MAC command frame can be optionally grammed into the transmit FIFO of interest and the confirmed with an Acknowledgment frame. If the applicable xACKREQ bit should be set: originator does not receive an Acknowledgment after, at • TXNACKREQ (TXNCON 0x1B<2>) – When the most macAckWaitDuration (54) symbols, it assumes TX Normal FIFO transmits a frame, an that the transmission was unsuccessful and retries the Acknowledgment frame is expected. If an frame transmission. The turnaround time from the Acknowledgment is not received, retransmit. reception of the packet to the transmission of the Acknowledgment shall be less than aTurnaroundTime • TXG1ACKREQ (TXG1CON 0x1C<2>) – When (12) symbols. Acknowledgment frames are sent without the TX GTS1 FIFO transmits a frame, an using a CSMA-CA mechanism. Refer to Acknowledgment frame is expected. If an IEEE 802.15.4-2003 Standard, Section 7.5.6.4 “Use of Acknowledgment is not received, retransmit. Acknowledgments” for more information. • TXG2ACKREQ (TXG2CON 0x1D<2>) – When the TX GTS2 FIFO transmits a frame, an The MRF24J40 provides hardware support for: Acknowledgment frame is expected. If an • Acknowledgment Request – Originator Acknowledgment is not received, retransmit. • Acknowledgment Request – Recipient When the frame is transmitted, the MRF24J40 will • Reception of Acknowledgment with Frame expect an Acknowledgment frame within Pending bit macAckWaitDuration. If an Acknowledgment is not • Transmission of Acknowledgment with Frame received, it will retransmit aMaxFrameRetries. Pending bit The macAckWaitDuration value can be programmed These features are explained below. by the MAWD (ACKTMOUT 0x12<6:0>) bits. The aMaxFrameRetries value is a constant and not 3.13.1 ACKNOWLEDGMENT REQUEST – configurable. The number of retry times of the most ORIGINATOR recent TXNFIFO transmission can be read in the A data or MAC command frame, transmitted by an TXNRETRY (TXSTAT 0x24<7:6>) bits. The number of originator with the Acknowledgment request subfield in retry times for the TX GTS1 FIFO and TX GTS2 FIFO its frame control field set to ‘1’, shall be Acknowledged can be programmed or read in the TXG1RETRY by the recipient. The originator shall wait for at most (TXG1CON 0x1C<7:6>) and TXG2RETRY (TXG2CON macAckWaitDuration (54) symbols for the 0x1D<7:6>) bits. corresponding Acknowledgment frame to be received. If an Acknowledgment is received, the transmission is successful. If an Acknowledgment is not received, the originator shall conclude that the transmission failed. If the transmission was direct, the originator shall retrans- mit the data or MAC command frame and wait. If an Acknowledgment is not received after aMaxFrameRetries (3) transmissions, the originator shall assume the transmission has failed and notify the upper layers of the failure. Preliminary DS39776C-page 116 © 2010 Microchip Technology Inc.

MRF24J40 3.13.2 ACKNOWLEDGMENT REQUEST – by the TURNTIME (TXTIME 0x27<7:4>) and RFSTBL RECIPIENT (TXSTBL 0x2E<7:4>) bits where aTurnaroundTime = TURNTIME + RFSTBL. The MRF24J40 features hardware automatic Acknowl- edgment. It will automatically Acknowledge a frame if 3.13.3 RECEPTION OF the received frame has the Acknowledgment request ACKNOWLEDGMENT WITH FRAME subfield in the frame control field set to ‘1’. This will PENDING BIT maintain the RX-TX timing requirements of the IEEE 802.15.4 Specification. The status of the frame pending bit in the frame control field of the received Acknowledgment frame is reflected Automatic Acknowledgment is enabled by clearing the in the FPSTAT (TXNCON 0x1B<4>) bit. NOACKRSP (RXMCR 0x00<5>) bit = 0. To disable automatic Acknowledgment, set the NOACKRSP 3.13.4 TRANSMISSION OF (RXMCR 0x00<5>) bit = 1. ACKNOWLEDGMENT WITH FRAME The transmission of an Acknowledgment frame in a PENDING BIT nonbeacon-enabled network, or in the CFP, shall The frame pending bit in the frame control field of an commence aTurnaroundTime (12) symbols after the Acknowledgment frame indicates that a device has reception of the data or MAC command frame. The additional data to send to the recipient following the transmission of an Acknowledgment frame in the CAP current transfer. Refer to IEEE 802.15.4-2003 shall commence at a backoff slot boundary. In this Standard, Section 7.2.1.1.3 “Frame Pending Subfield”. case, the transmission of an Acknowledgment frame shall commence between aTurnaroundTime and Acknowledgment of a data request MAC command – In (aTurnaroundTime + aUnitBackoffPeriod) response to a data request MAC command, if the symbols after the reception of the data or MAC MRF24J40 has additional (pending) data, it can set the command frame. frame pending bit of the Acknowledgment frame by set- ting DRPACK (ACKTMOUT 0x12<7>) = 1. This will The IEEE 802.15.4 Specification defines only set the frame pending bit for an Acknowledgment aTurnaroundTime as a constant value of 12 symbol of a data request MAC command. periods. The aTurnaroundTime can be programmed TABLE 3-17: REGISTERS ASSOCIATED WITH ACKNOWLEDGEMENT Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00 RXMCR r r NOACKRSP r PANCOORD COORD ERRPKT PROMI 0x12 ACKTMOUT DRPACK MAWD6 MAWD5 MAWD4 MAWD3 MAWD2 MAWD1 MAWD0 0x1B TXNCON r r r FPSTAT INDIRECT TXNACKREQ TXNSECEN TXNTRIG 0x1C TXG1CON TXG1RETRY1 TXG1RETRY0 TXG1SLOT2 TXG1SLOT1 TXG1SLOT0 TXG1ACKREQ TXG1SECEN TXG1TRIG 0x1D TXG2CON TXG2RETRY1 TXG2RETRY0 TXG2SLOT2 TXG2SLOT1 TXG2SLOT0 TXG2ACKREQ TXG2SECEN TXG2TRIG 0x21 TXPEND MLIFS5 MLIFS4 MLIFS3 MLIFS2 MLIFS1 MLIFS0 GTSSWITCH FPACK 0x24 TXSTAT TXNRETRY1 TXNRETRY0 CCAFAIL TXG2FNT TXG1FNT TXG2STAT TXG1STAT TXNSTAT 0x27 TXTIME TURNTIME3 TURNTIME2 TURNTIME1 TURNTIME0 r r r r 0x2E TXSTBL RFSTBL3 RFSTBL2 RFSTBL1 RFSTBL0 MSIFS3 MSIFS2 MSIFS1 MSIFS0 Preliminary © 2010 Microchip Technology Inc. DS39776C-page 117

MRF24J40 3.14 Battery Monitor 1. Set the battery monitor threshold (BATTH) voltage in the RFCON5 (0x205<7:4>) register. The MRF24J40 provides a battery monitor feature to 2. Enable battery monitoring by setting BATEN = 1 monitor the system supplied voltage. A threshold volt- in the RFCON6 (0x206<3>) register. age level (BATTH) can be set and the system supplied 3. Periodically, monitor the Battery Low Indicator voltage can be monitored by the Battery Low Indicator (BATIND) bit in the RXSR (0x30<5>) register to (BATIND) to determine if the voltage is above or below determine if the system supply voltage is above the threshold. The following steps set the threshold and or below the battery monitor threshold (BATTH). enable battery monitoring: TABLE 3-18: REGISTERS ASSOCIATED WITH POWER MANAGEMENT Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x30 RXSR r UPSECERR BATIND r r SECDECERR r r 0x205 RFCON5 BATTH3 BATTH2 BATTH1 BATTH0 r r r r 0x206 RFCON6 TXFIL r r 20MRECVR BATEN r r r Preliminary DS39776C-page 118 © 2010 Microchip Technology Inc.

MRF24J40 3.15 Sleep 3.15.1.1 Sleep Clock Generation The MRF24J40 can be placed into a low-current Sleep Figure 3-15 shows the Sleep clock generation circuitry. mode. During Sleep, the 20 MHz main oscillator is turned The Sleep Clock (SLPCLK) frequency is selectable off, disabling the RF, baseband and MAC circuitry. Data between a 100 kHz internal oscillator or a 32 kHz external crystal oscillator. The Sleep Clock Enable is retained in the control and FIFO registers and the (SLPCLKEN) bit in the SLPCON0 (0x211<0>) register MRF24J40 is accessible via the SPI port. There are two can enable (SLPCLKEN = 0; default setting) or disable Sleep modes: (SLPCLKEN = 1) the Sleep clock oscillators. The • Timed Sleep Mode SLPCLK frequency can be further divided by the Sleep • Immediate Sleep and Wake Mode Clock Divisor (SLPCLKDIV) 0x220<4:0> bits. The SLPCLK frequency can be calibrated; the procedure is 3.15.1 TIMED SLEEP MODE listed in Section 3.15.1.2 “Sleep Clock Calibration” The Timed Sleep Mode uses several counters to time below. events for the Sleep and wake-up of the MRF24J40. The following sections cover Sleep clock generation, calibration and counters. FIGURE 3-15: SLEEP CLOCK GENERATION SLPCALEN SLPCALRDY (SLPCAL2 0x20B<4>) (SLPCAL2 0x20B<7>) MAINCLK Sleep Calibration Counter (SLPCAL<19:0>) LPOSC2 32 kHz External Oscillator LPOSC1 EN Count 16 SLPCLK Periods 01 Sleep Clock Divisor SLPCLK (SLPCLKDIV<4:0>) 100 kHz 10 Internal Oscillator EN SLPCLKSEL (RFCON7 0x207<7:6>) SLPCLKEN (SLPCON0 0x211<0>) The 100 kHz internal oscillator requires no external The 32 kHz external crystal oscillator provides better components. However, it is not as accurate or stable as frequency accuracy and stability than the 100 kHz the 32 kHz external crystal oscillator. It is recom- internal oscillator. The 32 kHz external crystal oscillator mended that it be calibrated before use. See external circuitry is explained in detail in Section 2.7 Section 3.15.1.2 “Sleep Clock Calibration” below for “32 kHz External Crystal Oscillator”. the Sleep clock calibration procedure. To select the 32 kHz external crystal oscillator as the To select the 100 kHz internal oscillator as the source source of SLPCLK, set the SLPCLKSEL bits (RFCON7 of SLPCLK, set the SLPCLKSEL bits (RFCON7 0x207<7:6>) to ‘01’. 0x207<7:6> to ‘10’) Preliminary © 2010 Microchip Technology Inc. DS39776C-page 119

MRF24J40 3.15.1.2 Sleep Clock Calibration Wake Time (0x223<2:0>, 0x222) – An 11-bit value that is compared with the main counter value to signal the The SLPCLK frequency is calibrated by a 20-bit time to enable (wake-up) the 20 MHz main oscillator. SLPCAL register clocked by the 20 MHz main oscillator Table 3-20 gives the recommended values for (50 ns period). Sixteen samples of the SLPCLK are WAKETIME depending on the SLPCLK frequency. counted and stored in the SLPCAL register. To perform SLPCLK calibration: Wake Count (0x36<4:3>, 0x35<6:0>) – A 9-bit counter clocked by SLPCLK. During the time the wake counter 1. Select the source of SLPCLK. is counting, the 20 MHz main oscillator is starting up, 2. Begin calibration by setting the SLPCALEN bit stabilizing and disabled to the RF, baseband and MAC (SLPCAL2 0x20B<4>) to ‘1’. Sixteen samples of circuitry. The recommended wake count period is 2 ms the SLPCLK are counted and stored in the to allow the 20 MHz main oscillator to stabilize. SLPCAL register. Table 3-20 gives the recommended values for 3. Calibration is complete when the SLPCALRDY WAKECNT depending on the SLPCLK frequency. bit (SLPCAL2 0x20B<7>) is set to ‘1’. The 20-bit SLPCAL value is contained in registers, TABLE 3-19: MAIN AND REMAIN COUNTER SLPCAL2, SLPCAL1 and SLPCAL0 (0x20B<3:0>, TIMED EVENTS 0x20A and 0x209). The Sleep clock period is calculated Mode Timed Event as shown in Equation 3-1. Beacon-Enabled Beacon Interval (BI) EQUATION 3-1: Coordinator Beacon-Enabled Device Inactive Period P = SLPCAL * 50 ns/16 SLPCAL Nonbeacon-Enabled Sleep Interval The SLPCLK frequency can be slowed by setting the Coordinator or Device Sleep Clock Division (SLPCLKDIV) bits (SLPCON1 0x220<4:0>). TABLE 3-20: WAKE TIME AND WAKE COUNT RECOMMENDED 3.15.1.3 Sleep Mode Counters VALUES Figure 3-16 shows the Sleep mode counters. A SLPCLK WAKETIME WAKECNT summary of the counters are: SLPCLKDIV Source (2.1 ms) (2 ms) Main Counter (0x229<1:0>, 0x228, 0x227, 0x226) – A 100 kHz 0x01 0x0D2 0x0C8 26-bit counter clocked by SLPCLK. Together with the Remain Counter times events as listed in Table 3-19. 32 kHz 0x00 0x045 0x042 Remain Counter (0x225, 0x224) – A 16-bit counter clocked by MAINCLK. Together with the Main Counter times events as listed in Table 3-19. Preliminary DS39776C-page 120 © 2010 Microchip Technology Inc.

MRF24J40 FIGURE 3-16: SLEEP MODE COUNTERS OSC1 OSC2 Wake Time (WAKETIME<10:0>) Compare EN 20 MHz Main Oscillator MAINCLK EN Main Counter MAINCNT = 0 SLPCLK (MAINCNT<25:0>) EN Wake Count WAKECNT = 0 SLPCLK (WAKECNT<8:0>) WAKEIF WAKEIFIE EN Remain Counter REMCNT = 0 MAINCLK (REMCNT<15:0>) Beacon Interval (Beacon-Enabled Coordinator) Inactive Period (Beacon-Enabled Device) Beacon-Enabled mode (BO ≠? 15, SLOTTED = 1) SLPACK (SLPACK 0x35<7>) Nonbeacon-Enabled mode (BO = 15, SLOTTED = 0) STARTCNT (MAINCNT3 0x229<7>) Preliminary © 2010 Microchip Technology Inc. DS39776C-page 121

MRF24J40 Beacon-Enabled Coordinator mode – Figure 3-17 The MRF24J40 alerts the host processor on the bound- shows the Sleep time line for Beacon-Enabled Coordi- ary of the active and inactive portion via a Sleep Alert nator mode. In this mode, the sum of the main and Interrupt (SLPIF 0x31<7>). The host microcontroller remain counters is the Beacon Interval (BI) of the Acknowledges the interrupt (SLPACK 0x35<7>), at superframe. The MRF24J40 will transmit a beacon which time, the MRF24J40 turns off the 20 MHz main packet as per Beacon Interval shown in Equation 3-2. oscillator. As the main counter counts, when WAKETIME = MAINCNT, the 20 MHz main oscillator is EQUATION 3-2: turned on. The wake counter counts as the 20 MHz main oscillator stabilizes and MAINCLK is disabled. The Beacon Interval = (MAINCNT * SLPCLK Period) + MRF24J40 alerts the host processor with a wake-up alert (REMCNT * 50 ns) interrupt (0x31<6>). FIGURE 3-17: BEACON-ENABLED COORDINATOR SLEEP TIME LINE Beacon Time Beacon Beacon Interval (BI) Active Portion Inactive Portion Superframe Duration (SD) Sleep Acknowledge Sleep Alert Interrupt SLPACK Wake-up Alert Interrupt SLPIF (0x31<7>) (0x35<7>) WAKEIF (0x31<6>) Remain Remain Counter Main Counter Counts Counter Counts Counts Wake Counter Counts (~2 ms) 20 MHz Main Oscillator Turned OFF WAKETIME = MAINCNT 20 MHz Main 20 MHz Main Oscillator Oscillator Stable Turned ON Low-Current Sleep Period Preliminary DS39776C-page 122 © 2010 Microchip Technology Inc.

MRF24J40 Beacon-Enabled Device mode – Figure 3-18 shows The MRF24J40 alerts the host processor on the bound- the Sleep time line for Beacon-Enabled Device mode. ary of the active and inactive portion via a Sleep Alert In this mode, the sum of the main and remain counters Interrupt (SLPIF 0x31<7>). The host microcontroller is the inactive period of the superframe. The Acknowledges the interrupt (SLPACK 0x35<7>), at MRF24J40 will time the inactive period as shown in which time, the MRF24J40 turns off the 20 MHz main Equation 3-3. oscillator. As the main counter counts, when WAKETIME = MAINCNT, the 20 MHz main oscillator is EQUATION 3-3: turned on. The wake counter counts as the 20 MHz main oscillator stabilizes. The MRF24J40 alerts the host Inactive Period = (MAINCNT * SLPCLK Period) + processor with a wake-up alert interrupt (0x31<6>). (REMCNT * 50 ns) FIGURE 3-18: BEACON-ENABLED DEVICE SLEEP TIME LINE Beacon Time Beacon Beacon Interval (BI) Active Portion Inactive Portion Superframe Duration (SD) Sleep Acknowledge Sleep Alert Interrupt SLPACK Wake-up Alert Interrupt SLPIF (0x31<7>) (0x35<7>) WAKEIF (0x31<6>) Remain Remain Counter Main Counter Counts Counter Counts Counts Wake Counter Counts (~2 ms) 20 MHz Main Oscillator Turned OFF WAKETIME = MAINCNT 20 MHz Main 20 MHz Main Oscillator Oscillator Stable Turned ON Low-Current Sleep Period Preliminary © 2010 Microchip Technology Inc. DS39776C-page 123

MRF24J40 Nonbeacon-Enabled (Coordinator or Device) mode – EQUATION 3-4: Figure 3-19 shows the Sleep time line for Non- Sleep Interval = (MAINCNT * SLPCLK Period) – beacon-Enabled (Coordinator or Device) mode. In this WAKETIME + [(REMCNT * 50 ns)/2] mode, the host processor puts the MRF24J40 to Sleep by setting the STARTCNT (0x229<7>) bit. At the end of the Sleep interval, the MRF24J40 alerts the host processor with a wake-up alert interrupt (0x31<6>). FIGURE 3-19: NONBEACON-ENABLED (COORDINATOR OR DEVICE) SLEEP TIME LINE Time Wake-up Alert Interrupt WAKEIF (0x31<6>) Remain Remain Counter Main Counter Counts Counter Counts Counts Wake Counter Counts (~2 ms) 20 MHz Main Oscillator Turned OFF WAKETIME = MAINCNT 20 MHz Main 20 MHz Main Oscillator Oscillator Stable Turned ON Low-Current Sleep Period Preliminary DS39776C-page 124 © 2010 Microchip Technology Inc.

MRF24J40 3.15.2 IMMEDIATE SLEEP AND WAKE-UP Wake-up can be performed in one of two methods: MODE 1. Wake-up on WAKE pin 15. To enable the WAKE In the Immediate Sleep and Wake-up mode, the host pin, set the WAKEPAD (0x0D<5>) bit to ‘1’ and microcontroller places the MRF24J40 to Sleep and set the WAKE pin polarity. Set the WAKEPOL wakes it up. (0x0D<7>) bit to ‘1’ for active-high signal, or clear to ‘0’ for active-low signal. To enable the Immediate Wake-up mode, set the or IMMWAKE (0x22<7>) bit to ‘1’. 2. Wake-up on register. To wake up the MRF24J40 To place the MRF24J40 to Sleep immediately, perform from Sleep via the SPI port, set the REGWAKE the following two steps: (0x22<6>) bit to ‘1’ and then clear to ‘0’. 1. Perform a Power Management Reset by setting After wake-up, delay at least 2 ms to allow 20 MHz main the RSTPWR (0x2A<2>) bit to ‘1’. The bit will be oscillator time to stabilize before transmitting or receiving. automatically cleared to ‘0’ by hardware. Example 3-3 summarizes the steps to prepare the 2. Put the MRF24J40 to Sleep immediately by set- MRF24J40 for wake-up on WAKE pin and placing to ting the SLPACK (0x35<7>) bit to ‘1’. The bit will Sleep. be automatically cleared to ‘0’ by hardware. EXAMPLE 3-3: IMMEDIATE SLEEP AND WAKE The steps to prepare the MRF24J40 for immediate sleep and wake up on WAKE pin Prepare WAKE pin: 1. WAKE pin = low 2. RXFLUSH (0x0D) = 0x60 – Enable WAKE pin and set polarity to active-high 3. WAKECON (0x22) = 0x80 – Enable Immediate Wake-up mode Put to Sleep: 4. SOFTRST (0x2A) = 0x04 – Perform a Power Management Reset 5. SLPACK (0x35) = 0x80 – Put MRF24J40 to Sleep immediately To Wake: 6. WAKE pin = high – Wake-up 7. RFCTL (0x36) = 0x04 - RF State Machine reset 8. RFCTL (0x36) = 0x00 9. Delay 2 ms to allow 20 MHz main oscillator time to stabilize before transmitting or receiving. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 125

MRF24J40 TABLE 3-21: REGISTERS ASSOCIATED WITH SLEEP Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0D RXFLUSH r WAKEPLOL WAKEPAD r CMDONLY DATAONLY BCNONLY RXFLUSH 0x22 WAKECON IMMWAKE REGWAKE INTL INTL INTL INTL INTL INTL 0x2A SOFTRST r r r r r RSTPWR RSTBB RSTMAC 0x31 INSTAT SLPIF WAKEIF HSYMTMRIF SECIF RXIF TXG2IF TXG1IF TXNIF 0x32 INTCON SLPIE WAKEIE HSYMTMRIE SECIE RXIE TXG2IE TXG1IE TXNIE 0x35 SLPACK SLPACK WAKECNT6 WAKECNT5 WAKECNT4 WAKECNT3 WAKECNT2 WAKECNT1 WAKECNT0 0x36 RFCTL r r r WAKECNT8 WAKECNT7 RFRST RFTXMODE RFRXMODE 0x207 RFCON7 SLPCLKSEL1 SLPCLKSEL0 r r r r r r 0x20B SLPCAL2 SLPCALRDY r r SLPCALEN SLPCAL19 SLPCAL18 SLPCAL17 SLPCAL16 0x211 SLPCON0 r r r r r r INTEDGE SLPCLKEN 0x220 SLPCON1 r r CLKOUTEN SLPCLKDIV4 SLPCLKDIV3 SLPCLKDIV2 SLPCLKDIV1 SLPCLKDIV0 0x223 WAKETIMEH r r r r r WAKETIME10 WAKETIME9 WAKETIME8 0x224 REMCNTL REMCNT7 REMCNT6 REMCNT5 REMCNT4 REMCNT3 REMCNT2 REMCNT1 REMCNT0 0x225 REMCNTH REMCNT15 REMCNT14 REMCNT13 REMCNT12 REMCNT11 REMCNT10 REMCNT9 REMCNT8 0x226 MAINCNT0 MAINCNT7 MAINCNT6 MAINCNT5 MAINCNT4 MAINCNT3 MAINCNT2 MAINCNT1 MAINCNT0 0x227 MAINCNT1 MAINCNT15 MAINCNT14 MAINCNT13 MAINCNT12 MAINCNT11 MAINCNT10 MAINCNT9 MAINCNT8 0x228 MAINCNT2 MAINCNT23 MAINCNT22 MAINCNT21 MAINCNT20 MAINCNT19 MAINCNT18 MAINCNT17 MAINCNT16 0x229 MAINCNT3 STARTCNT r r r r r MAINCNT25 MAINCNT24 Preliminary DS39776C-page 126 © 2010 Microchip Technology Inc.

MRF24J40 3.16 MAC Timer multiples of 8 μs. The MAC timer begins counting down when a value is written to the HSYMTMRH (0x29) reg- Many features of the IEEE 802.15.4-2003 Standard are ister. A HSYMTMRIF (0x31<5>) interrupt is generated based on a symbol period of 16 μs. A 16-bit MAC timer when the count reaches zero. is provided to generate interrupts configurable in TABLE 3-22: REGISTERS ASSOCIATED WITH THE MAC TIMER Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x28 HSYMTMRL HSYMTMR7 HSYMTMR6 HSYMTMR5 HSYMTMR4 HSYMTMR3 HSYMTMR2 HSYMTMR1 HSYMTMR0 0x29 HSYMTMRH HSYMTMR15 HSYMTMR14 HSYMTMR13 HSYMTMR12 HSYMTMR11 HSYMTMR10 HSYMTMR9 HSYMTMR8 0x31 INSTAT SLPIF WAKEIF HSYMTMRIF SECIF RXIF TXG2IF TXG1IF TXNIF 0x32 INTCON SLPIE WAKEIE HSYMTMRIE SECIE RXIE TXG2IE TXG1IE TXNIE Preliminary © 2010 Microchip Technology Inc. DS39776C-page 127

MRF24J40 3.17 Security FIGURE 3-20: MEMORY MAP OF SECURITY KEY FIFO The MRF24J40 provides a hardware security engine that implements the Advanced Encryption Standard, Long Address 128-bit (AES-128) according to the IEEE 802.15.4-2003 Memory Space Standard. The MRF24J40 supports seven security suites which provide a group of security operations 0x280 TX Normal FIFO designed to provide security services on MAC and upper 16 bytes Security Key layer frames. 0x28F • AES-CTR 0x290 TX GTS1 FIFO • AES-CCM-128 16 bytes Security Key • AES-CCM-64 0x29F • AES-CCM-32 0x2A0 TX GTS2 FIFO/ • AES-CRC-MAC-128 TX Beacon FIFO 16 bytes • AES-CRC-MAC-64 0x2AF Security Key • AES-CRC-MAC-32 0x2B0 RX FIFO Security keys are stored in the Security Key FIFO. Four 16 bytes Security Key security keys, three for encryption and one for decryption, 0x2BF are stored in the memory locations shown in Figure 3-20. The security engine can be used for the encryption and decryption of MAC sublayer frames for transmission Note: The TX GTS2 FIFO and TX Beacon FIFO and reception of secured frames and provide security share the same security key memory encryption and decryption services to the upper layers. location. These functions are described in the following subsections. 3.17.1 MAC SUBLAYER TRANSMIT ENCRYPTION A frame can be encrypted and transmitted from each of the TX FIFOs. Table 3-23 lists the TX FIFO and associ- ated security key memory address and control register bits. TABLE 3-23: ENCRYPTION SECURITY KEY AND CONTROL REGISTER BITS Security Key Security Suite TX FIFO Security Enable Bits Trigger Bit Memory Address Select Bits TX Normal FIFO 0x280-0x28F TXNCIPHER TXNSECEN TXNTRIG (SECCON0 0x2C<2:0>) (TXNCON 0x1B<1>) (TXNCON 0x1B<0>) TX GTS1 FIFO 0x290-0x29F TXG1CIPHER TXG1SECEN TXG1TRIG (SECCR2 0x37<2:0>) (TXG1CON 0x1C<1>) (TXG1CON 0x1C<0>) TX GTS2 FIFO 0x2A0-0x2AF TXG2CIPHER TXG2SECEN TXG2TRIG (SECCR2 0x37<5:3>) (TXG2CON 0x1D<1>) (TXG2CON 0x1D<0>) TX Beacon FIFO 0x2A0-0x2AF TXBCIPHER TXBCNSECEN TXBCNTRIG (SECCON1 0x2D<6:4>) (TXBCON 0x1A<1>) (TXBCON 0x1A<0>) Note: The TX GTS2 FIFO and TX Beacon FIFO share the same security key memory location. Preliminary DS39776C-page 128 © 2010 Microchip Technology Inc.

MRF24J40 To transmit a secured frame, perform the following steps: 1. The host processor loads one of the four TX FIFOs with an IEEE 802.15.4 compliant frame to be encrypted using the format shown in Figure 3-21. FIGURE 3-21: SECURITY TX FIFO FORMAT 1 1 m n octets Header Frame TX FIFO Length Length HHeeaaddeerr Data Payload (m) (m + n) 2 1 4 – 20 4 1 n – 5 4/8/16 2 octets EncMryApCtio Sn u(bTlraaynesrm it) CForanmtroel SNeuqmuebnecre AdFdrieelsdssing CForuamnteer SCeoqKuueneytnecre Encrypted Payload InCteogdreity FCS MHR MSDU MFR Fields appended by TXMAC 2. Program the corresponding TX FIFO 128-bit TX Normal FIFO – A TXNIF (INTSTAT 0x31<0>) inter- security key into the Security Key FIFO memory rupt will be issued. The TXNSTAT (TXSTAT 0x24<0>) address, as shown in Table 3-23. bit indicates the status of the transmission: 3. Select the security suite for the corresponding TXNSTAT = 0: Transmission was successful TX FIFO and program the security select bits as TXNSTAT = 1: Transmission failed, retry count shown in Table 3-23. The security suite exceeded selection values are shown in Table 3-24. The number of retries of the most recent transmission TABLE 3-24: SECURITY SUITE is contained in the TXNRETRY (TXSTAT 0x24<7:6>) SELECTION VALUE bits. The CCAFAIL (TXSTAT 0x24<5>) bit = 1 indicates if the failed transmission was due to the channel busy Security Suite Select Bits (CSMA-CA timed out). Mode (see Table 3-23) TX GTSx FIFO – A TXG1IF (INTSTAT 0x31<1>) or None 000 TXG2IF (INTSTAT 0x31<2>) interrupt will be issued. AES-CTR 001 The TXG1STAT (TXSTAT 0x24<1>) or TXG2STAT (TXSTAT 0x24<2>) bit indicates the status of the AES-CCM-128 010 transmission: AES-CCM-64 011 TXGxSTAT = 1: Transmission was successful AES-CCM-32 100 TXGxSTAT = 0: Transmission failed, retry count AES-CBC-MAC-128 101 exceeded AES-CBC-MAC-64 110 The number of retries of the most recent transmission AES-CBC-MAC-32 111 is contained in the TXG1RETRY (TXG1CON 0x1C<7:6>) or TXG2RETRY (TXG2CON 0x1D<7:6>) 4. Encrypt and transmit the packet by setting the bits. The CCAFAIL (TXSTAT 0x24<5>) bit = 1 indicates Security Enable (TXxSECEN) = 1 and Trigger if the failed transmission was due to the channel busy (TXxTRIG) bits = 1 for the respective TX FIFO, (CSMA-CA timed out). The TXG1FNT (TXSTAT as shown in Table 3-23. 0x24<3>) or TXG2FNT (TXSTAT 0x24<4>) bit = 1 5. Depending on which TX FIFO the secure packet indicates if TX GTSx FIFO transmission failed due to was transmit from, the status of the transmission not enough time to transmit in the guaranteed time slot. is read as, Preliminary © 2010 Microchip Technology Inc. DS39776C-page 129

MRF24J40 3.17.2 MAC SUBLAYER RECEIVE MRF24J40 issues a Security Interrupt, SECIF DECRYPTION (INTSTAT 0x31<4>). The Security Interrupt indicates to the host microcontroller that the To receive and decrypt a secured frame from the received frame was secured. The host micro- RXFIFO, perform the following steps: controller can choose to decrypt or ignore the 1. When a packet is received and the security frame. The format of the received frame is enable bit = 1 in the frame control field, the shown in Example 3-22. FIGURE 3-22: SECURITY RX FIFO FORMAT 1 m n 2 1 1 octets Frame RXFIFO Length Header (MHR) Data Payload (MSDU) FCS LQI RSSI (m+n+2) RXFIFO Address: 0x300 0x301 to (0x301 + m – 1) (0x301 + m) to (0x301 + m + n – 1) (0x301 + m + n + 3) (0x301 + m + n + 2) (0x301 + m + n) to (0x301 + m + n + 1) 2. If the decryption should be ignored, set the 4. Select the security suite and program the SECIGNORE (SECCON0 0x2C<7>) bit = 1. RXCIPHER (SECCON0 0x2C<5:3>) bits. The The encrypted packet can be discarded or read security suite selection values are shown in from the RXFIFO and processed in the upper Table 3-24. layers. 5. Start the decryption by setting the SECSTART 3. The host microcontroller loads the security key (SECCON0 0x2C<6>) bit = 1. into the RX FIFO Security Key memory location 6. When the decryption process is complete, a as shown in Table 3-25. Receive Interrupt (RXIF 0x31<3>) is issued. 7. Check the decryption status by reading TABLE 3-25: DECRYPTION SECURITY KEY SECDECERR (RXSR 0x30<2>) AND CONTROL REGISTER SECDECERR = 0: No Decryption Error BITS SECDECERR = 1: Decryption Error Security Key Memory Note: If decryption error has occurred and the FIFO Address packet in the FIFO needs to be discarded, then set RXFLUSH (RXFLUSH 0x0D<0>) RX FIFO 0x2B0-0x2BF bit = 1. Preliminary DS39776C-page 130 © 2010 Microchip Technology Inc.

MRF24J40 3.17.3 UPPER LAYER ENCRYPTION Note: The header length field, as implemented in To encrypt an upper layer frame, perform the following the MRF24J40, is 5 bits long. Therefore, steps: the header length maximum value is 31 octets (bytes). This conforms to the 1. The host microcontroller loads the TXNFIFO IEEE 802.15.4-2003 Specification. How- with the upper layer frame for encryption into the ever, it does not conform to the TXNFIFO using the format shown in IEEE 802.15.4-2006 Standard. The work Figure 3-23. The header length field indicates around is to: the number of octets (bytes) that is not encrypted. - Use a header length no longer than 31 octets (bytes) - Implement a security algorithm in the upper layers FIGURE 3-23: UPPER LAYER ENCRYPTION AND DECRYPTION FORMAT 1 1 m n octets Header Frame TX FIFO Length Length HHeeaaddeerr Data Payload (m) (m + n) m n octets Upper Layer Upper Layer Upper Layer Encryption Security Header Encrypted Payload 2. The host microcontroller loads the 13-byte 6. Encrypt the frame by setting the TXNTRIG NONCE value into the UPNONCE12 through (TXNCON 0x1B<0>) bit and TXNSECEN UPNONCE0 (0x240 through 0x24C) registers. (TXNCON 0x1B<1>) to 1. 3. Program the 128-bit security key into the TX 7. A TXNIF (INTSTAT 0x31<0>) interrupt will be Normal FIFO Security Key FIFO memory issued. The TXNSTAT (TXSTAT 0x24<0>) bit = 0 address, 0x280 through 0x28F. indicates the encryption has completed. 4. Select the security suite and program the 8. The encrypted frame is available in the TXNCIPHER (SECCON0 0x2C<2:0>) bits. The TXNFIFO and can be read by the host security suite selection values are shown in microcontroller. Table 3-24. Application Hint: The encryption can be 5. Enable Upper Layer Security Encryption mode by checked by decrypting the frame data (refer setting the UPENC (SECCR2 0x37<6>) bit = 1. Section 3.17.4 “Upper Layer Decryption”) and comparing it to the original frame data. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 131

MRF24J40 3.17.4 UPPER LAYER DECRYPTION 3. Program the 128-bit security key into the TX Normal FIFO Security Key FIFO memory To decrypt an upper layer frame, perform the following address, 0x280 through 0x28F. steps: 4. Select the security suite and program the 1. The host microcontroller loads the TXNFIFO TXNCIPHER (SECCON0 0x2C<2:0>) bits. The with the upper layer frame for decryption into the security suite selection values are shown in TXNFIFO using the format shown in Table 3-24. Figure 3-23. The header length field indicates 5. Enable Upper Layer Security Decryption mode by the number of octets (bytes) that are not setting the UPDEC (SECCR2 0x37<7>) bit = 1. encrypted. 6. Start Decrypting the frame by setting the 2. The host microcontroller loads the 13-byte TXNTRIG (TXNCON 0x1B<0>) bit to 1. NONCE value into the UPNONCE12 through UPNONCE0 (0x240 through 0x24C) registers. 7. A TXNIF (INTSTAT 0x31<0>) interrupt will be issued. The TXNSTAT (TXSTAT 0x24<0>) bit = 0 Note: The header length field, as implemented in indicates that the decryption process has the MRF24J40, is 5-bits long. Therefore, completed. the header length maximum value is 8. Check if a MIC error occurred by reading the 31 octets (bytes). This conforms to the UPSECERR (0x30<6>) bit: IEEE 802.15.4-2003 Specification. How- ever, it does not conform to the UPSECERR = 0: No MIC error IEEE 802.15.4-2006 Standard. The work UPSECERR = 1: MIC error occurred; write ‘1’ around is to: to clear error - Use a header length no longer than 9. The decrypted frame is available in the TXNFIFO 31 octets (bytes) and can be read by the host microcontroller. - Implement a security algorithm in the upper layers TABLE 3-26: REGISTERS ASSOCIATED WITH SECURITY Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x1A TXBCON0 r r r r r r TXBSECEN TXBTRIG 0x1B TXNCON r r r FPSTAT INDIRECT TXNACKREQ TXNSECEN TXNTRIG 0x1C TXG1CON TXG1RETRY1 TXG1RETRY0 TXG1SLOT2 TXG1SLOT1 TXG1SLOT0 TXG1ACKREQ TXG1SECEN TXG1TRIG 0x1D TXG2CON TXG2RETRY1 TXG2RETRY0 TXG2SLOT2 TXG2SLOT1 TXG2SLOT0 TXG2ACKREQ TXG2SECEN TXG2TRIG 0x24 TXSTAT TXNRETRY1 TXNRETRY0 CCAFAIL TXG2FNT TXG1FNT TXG2STAT TXG1STAT TXNSTAT 0x2C SECCON0 SECIGNORE SECSTART RXCIPHER2 RXCIPHER1 RXCIPHER0 TXNCIPHER2 TXNCIPHER1 TXNCIPHER0 0x2D SECCON1 r TXBCIPHER2 TXBCIPHER1 TXBCIPHER0 r r DISDEC DISENC 0x30 RXSR r UPSECERR BATIND r r SECDECERR r r 0x31 INTSTAT SLPIF WAKEIF HSYMTMRIF SECIF RXIF TXG2IF TXG1IF TXNIF 0x32 INTCON SLPIE WAKEIE HSYMTMRIE SECIE RXIE TXG2IE TXG1IE TXNIE 0x37 SECCR2 UPDEC UPENC TXG2CIPHER2 TXG2CIPHER1 TXG2CIPHER0 TXG1CIPHER2 TXG1CIPHER1 TXG1CIPHER0 0x240 UPNONCE0 UPNONCE<7:0> 0x241 UPNONCE1 UPNONCE<15:8> 0x242 UPNONCE2 UPNONCE<23:16> 0x243 UPNONCE3 UPNONCE<31:24> 0x244 UPNONCE4 UPNONCE<39:32> 0x245 UPNONCE5 UPNONCE<47:40> 0x246 UPNONCE6 UPNONCE<55:48> 0x247 UPNONCE7 UPNONCE<63:56> 0x248 UPNONCE8 UPNONCE<71:64> 0x249 UPNONCE9 UPNONCE<79:72> 0x24A UPNONCE10 UPNONCE<87:80> 0x24B UPNONCE11 UPNONCE<95:88> 0x24C UPNONCE12 UPNONCE<103:96> Preliminary DS39776C-page 132 © 2010 Microchip Technology Inc.

MRF24J40 3.18 Turbo Mode 2. Set the baseband parameter, PREVALIDTH (BBREG3 0x3B<7:4>) bits = 0011. The MRF24J40 provides a Turbo mode to transmit and 3. Set baseband parameter, CSTH (BBREG4 receive at 625 kbps (2.5 times 250 kbps). This mode 0x3C<7:5>) bits = 010. enables higher data rates for proprietary protocols. 4. Perform a baseband circuitry Reset, RSTBB To configure the MRF24J40 for Turbo mode, perform (SOFTRST 0x2A<1>) = 1. the following steps: 1. Enable Turbo mode by setting the TURBO (BBREG0 0x38<0>) bit = 1. TABLE 3-27: REGISTERS ASSOCIATED WITH TURBO MODE Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x2A SOFTRST r r r r r RSTPWR RSTBB RSTMAC 0x38 BBREG0 r r r r r r r TURBO 0x3B BBREG3 PREVALIDTH3 PREVALIDTH2 PREVALIDTH1 PREVALIDTH0 PREDETTH2 PREDETTH1 PREDETTH0 r 0x3C BBREG4 CSTH2 CSTH1 CSTH0 PRECNT2 PRECNT1 PRECNT0 r r Preliminary © 2010 Microchip Technology Inc. DS39776C-page 133

MRF24J40 NOTES: Preliminary DS39776C-page 134 © 2010 Microchip Technology Inc.

MRF24J40 4.0 APPLICATIONS Figure 4-2 shows the measured impedance of the balun where the center of the band is very close to 50Ω. When using low tolerance components (i.e., ±5%) 4.1 Antenna/Balun along with an appropriate ground, the impedance will Figure 4-1 is an example of the circuit diagram of a remain close to the 50Ω measurement. balun to match to a 50Ω antenna. A balun is the imped- ance transformer from unbalanced input of the PCB antenna and the balanced input of the RF transceiver (pins RFP and RFN). FIGURE 4-1: EXAMPLE BALUN CIRCUIT DIAGRAM +V C12 0.01 μF L2 10 nH 50Ω ANT L4 C15 RFP 4.7 nH 0.5 pF C14 0.5 pF L1 10 nH C17 C16 RFN 0.3 pF 0.5 pF L3 C2 5.6 nH 0.5 pF FIGURE 4-2: BALUN CIRCUIT MEASURED IMPEDANCE Preliminary © 2010 Microchip Technology Inc. DS39776C-page 135

MRF24J40 4.2 External PA/LNA Control TABLE 4-1: GPIO EXTERNAL PA/LNA SIGNALING External PA, LNA and RF switches can be controlled by the MRF24J40 internal RF state machine. Figure 4-3 Maximum shows a typical application circuit with external PA, GPIO Receive Transmit Current LNA and RF switches. Setting TESTMODE Source (0x22F<2:0>) bits to ‘111’ will configure pins, GPIO0, GPIO0 Low High 4 ma GPIO1 and GPIO2, to operate according to Table 4-1. GPIO1 Low High 1 ma The external PA/LNA timing diagram is shown in Figure 4-4. GPIO2 High Low 1 ma FIGURE 4-3: EXTERNAL PA/LNA BLOCK DIAGRAM Antenna RF RF LNA Switch Switch Enable LNA RFP Balun RFN PA PA Enable MRF24J40 GPIO0 GPIO1 GPIO2 Preliminary DS39776C-page 136 © 2010 Microchip Technology Inc.

MRF24J40 FIGURE 4-4: EXTERNAL PA/LNA TIMING DIAGRAM Time Receive Transmit Beginning of Beginning of Transmit Packet GPIO0 GPIO1 GPIO2 t PAON 18 µs t TXON 98 µs t RFSTBL 144 µs RF Stabilization Time (t ) = RFSTBL * 16 µs RFSTBL 144 µs = 9 * 16 µs Transmit On Time (t ) = TXONTS * 16 µs + TXONT * 50 ns TXON 98 µs = 6 * 16 µs + 40 * 50 ns PA On Time (t ) = PAONTS * 16 µs + PAONT + 50 ns PAON 18.05 µs = 1 * 16 µs + 41 * 50 ns Rule: t > t > t rfstbl txon paon TABLE 4-2: REGISTERS ASSOCIATED WITH EXTERNAL PA/LNA Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x15 SYMTICKH TXONT6 TXONT5 TXONT4 TXONT3 TXONT2 TXONT1 TXONT0 TICKP8 0x16 PACON0 PAONT7 PAONT6 PAONT5 PAONT4 PAONT3 PAONT2 PAONT1 PAONT0 0x17 PACON1 r r r PAONTS3 PAONTS2 PAONTS1 PAONTS0 PAONT8 0x18 PACON2 FIFOEN r TXONTS3 TXONTS2 TXONTS1 TXONTS0 TXONT8 TXONT7 0x2E TXSTBL RFSTBL3 RFSTBL2 RFSTBL1 RFSTBL0 MSIFS3 MSIFS2 MSIFS1 MSIFS0 0x22F TESTMODE r r r RSSIWAIT1 RSSIWAIT0 TESTMODE2 TESTMODE1 TESTMODE0 Preliminary © 2010 Microchip Technology Inc. DS39776C-page 137

MRF24J40 4.3 PCB Layout Design The printed circuit board is comprised of four basic FR4 layers: signal layout, RF ground, power line routing and The following guidelines are intended to aid users in ground (see Figure 4-5). The guidelines will explain the high-frequency PCB layout design. requirements of these layers. FIGURE 4-5: FOUR BASIC COPPER FR4 LAYERS Signal Layout, Thickness = 1.8 mils Dielectric ε = 4.5, Thickness = 7 mils RF Ground, Thickness = 1.2 mils Dielectric ε = 4.5, Thickness = 19 mils Power Line Routing, Thickness = 1.2 mils Dielectric ε = 4.5, Thickness = 7 mils Ground, Thickness = 1.8 mils Note: Care should be taken with all ground lines to prevent breakage. • It is important to keep the original PCB thickness • A via filled ground patch underneath the IC since any change will affect antenna performance transceiver is mandatory. (see total thickness of dielectric) or microstrip • A power supply must be distributed to each pin in lines characteristic impedance. a star topology and low-ESR capacitors must be • The first layer width of a 50Ω characteristic placed at each pin for proper decoupling noise. impedance microstrip line is 12 mils. • Thorough decoupling on each power pin is • Avoid having microstrip lines longer than 2.5 cm, beneficial for reducing in-band transceiver noise, since that line might get very close to a quarter particularly when this noise degrades perfor- wave length of the working frequency of the board mance. Usually, low value caps (27-47 pF) which is 3.0 cm, and start behaving as an combined with large value caps (100 nF) will antenna. cover a large spectrum of frequency. • Except for the antenna layout, avoid sharp • Passive components (inductors) must be in the corners since they can act as an antenna. Round high-frequency category and the SRF corners will eliminate possible future EMI (Self-Resonant Frequency) should be at least two problems. times higher than the operating frequency. • Digital lines by definition are prone to be very noisy when handling periodic waveforms and fast clock/switching rates. Avoid laying out a RF signal close to any digital lines. Preliminary DS39776C-page 138 © 2010 Microchip Technology Inc.

© 4.4 MRF24J40 Schematic and Bill of Materials 2 0 1 0 4.4.1 SCHEMATIC M ic ro FIGURE 4-6: MRF24J40 SCHEMATIC c h ip T VIN e c h n o logy 47 CpF6 VIN 1C81 p9F In c . C7 VIN X1 20.00 MHz 0.01 μF VIN C18 1 CμF8 18 pF VIN 100 CpF9 C475 pF VIN P 50Ω Antenna C r C12 C13 N e 0.01 μF 47 pF 0987654321 C4 lim 4333333333 47 pF 0.01 μF PDCDDD12DD inary C17 4.7L 4nHC16 0C.51 p5F 0C.51 p4F L120 nH 1234 VRRVDDFFDDPN LCAVDNVDGNVDOSCOCSVDLLVPPDOOSSNNCCCC12 32220987 NNNNCCCC 0.3 pF 0.5 pF L1 5 VDD IC1 NC 26 NC 10 nH 6 GND MRF24J40/ML GND 25 L3 7 GPIO0 GND 24 5.6 nH 8 GPIO1 NC 23 NC VIN 9 GPIO5 GND 22 0.5 CpF2 10 GPIO4 GPIO2GPIO3RESETGNDWAKEINTSDOSDISCKCSVDD 21 C0.301 μF 1234567890 1111111112 CS M VIN VIN 5 R VCC IC2 DS397 47C p1F0 VIN SSDCIK 21 OAE Y4NC7SZ125PS5DXO F2 7 4 6C-pa 0.1C μ1F1 VIN NRP1 IWNATKE G3ND J g RESET 4 e Note: NP = Not Placed. 1 0 3 9

MRF24J40 4.4.2 BILL OF MATERIALS TABLE 4-3: MRF24J40 BILL OF MATERIALS Designator Description C2 Chip Capacitor 0402 COG 0.5P C3 Chip Capacitor 0402 X7R 10N C4 Chip Capacitor 0402 COG 47P C5 Chip Capacitor 0402 COG 47P C6 Chip Capacitor 0402 COG 47P C7 Chip Capacitor 0402 X7R 10N C8 Chip Capacitor 0402 X5R 1U C9 Chip Capacitor 0402 COG 100P C10 Chip Capacitor 0402 COG 47P C11 Chip Capacitor 0402 X5R 100N C12 Chip Capacitor 0402 X5R 100N C13 Chip Capacitor 0402 COG 47P C14 Chip Capacitor 0402 COG 0.5P C15 Chip Capacitor 0402 COG 0.5P C16 Chip Capacitor 0402 COG 0.5P C17 Chip Capacitor 0402 COG 0.3P C18 Chip Capacitor 0402 COG 18P C19 Chip Capacitor 0402 COG 18P IC1 MRF24J40-I/ML IC2 Buffer, SC70 Package, NC7SZ125P5X L1 Chip Inductor 0402 10N L2 Chip Inductor 0402 10N L3 Chip Inductor 0402 5.6N L4 Chip Inductor 0402 4.7N R1 Not Placed X1 20 MHz Crystal, Abracon P/N ABM8 - 156 - 20.000MHz - T Preliminary DS39776C-page 140 © 2010 Microchip Technology Inc.

MRF24J40 5.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................. -40°C to +85°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any combined digital and analog pin with respect to VSS (except VDD)........................-0.5V to (VDD + 0.5V) Voltage on VDD with respect to VSS............................................................................................................ -0.3V to 3.6V Maximum output current sunk by GPIO1-GPIO5 pins..............................................................................................1 mA Maximum output current sourced by GPIO1-GPIO5 pins.........................................................................................1 mA Maximum output current sunk by GPIO0 pin............................................................................................................4 mA Maximum output current sourced by GPIO0 pin.......................................................................................................4 mA † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 141

MRF24J40 TABLE 5-1: RECOMMENDED OPERATING CONDITIONS Parameters Min Typ Max Units Ambient Operating Temperature -40 — +85 °C Supply Voltage for RF, Analog and Digital 2.4 — 3.6 V Circuits Supply Voltage for Digital I/O 2.4 3.3 3.6 V Input High Voltage (VIH) 0.5 x VDD — VDD + 0.3 V Input Low Voltage (VIL) -0.3 — 0.2 x VDD V TABLE 5-2: CURRENT CONSUMPTION Typical Values: TA = 25°C, VDD = 3.3V Chip Mode Condition Min Typ Max Units Sleep Sleep Clock Disabled — 2 — μA TX At maximum output power — 23 — mA RX — — 19 — mA TABLE 5-3: RECEIVER AC CHARACTERISTICS Typical Values: TA = 25°C, VDD = 3.3V, LO Frequency = 2.445 GHz Parameters Condition Min Typ Max Units RF Input Frequency — 2.405 — 2.480 GHz RF Sensitivity At antenna input with O-QPSK signal — -95 — dBm and 3.5 dB front end loss is assumed Maximum RF Input LNA at high gain +5 — — dBm LO Leakage Measured at balun matching network — -60 — dBm input at frequency 2.405-2.48 GHz Noise Figure — 8 — dB (including matching) Adjacent Channel @ +/- 5 MHz 30 — — dB Rejection Alternate Channel @ +/- 10 MHz 40 — — dB Rejection RSSI Range — — 50 — dB RSSI Error — -5 — 5 dB Preliminary DS39776C-page 142 © 2010 Microchip Technology Inc.

MRF24J40 TABLE 5-4: TRANSMITTER AC CHARACTERISTICS Typical Values: TA = 25°C, VDD = 3.3V, LO Frequency = 2.445 GHz Parameters Condition Min Typ Max Units RF Carrier Frequency — 2.405 — 2.480 GHz Maximum RF Output Power — — 0 — dBm RF Output Power Control Range — — 36 — dB TX Gain Control Resolution Programmed by register — 1.25 — dB Carrier Suppression — — -30 — dBc TX Spectrum Mask for O-QPSK Offset frequency > 3.5 MHz, -33 — — dBm Signal at 0 dBm output power TX EVM — — 13 — % FIGURE 5-1: EXAMPLE SPI SLAVE MODE TIMING 82 CS 70 SCK 80 SDO MSb bit 6 - - - - - - 1 LSb SDI MSb In bit 6 - - - - 1 LSb In 74 TABLE 5-5: EXAMPLE SPI SLAVE MODE REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH CS ↓ to SCK ↑ Input 50 — ns — 71 TSCH SCK Input High Time Single Byte 50 — ns — 72 TSCL SCK Input Low Time Single Byte 50 — ns — 74 TSCH2DIL Hold Time of SDI Data Input to SCK Edge 25 — ns — 75 TDOR SDO Data Output Rise Time — 25 ns — 76 TDOF SDO Data Output Fall Time — 25 ns — 78 TSCR SCK Output Rise Time (Master mode) — 25 ns — 80 TSCH2DOV, SDO Data Output Valid after SCK Edge 50 — ns — TSCL2DOV 82 TSSL2DOV SDO Data Output Valid after CS ↓ Edge 50 — ns — 83 TSCL2SSH CS ↑ after SCK Edge 50 — ns — Preliminary © 2010 Microchip Technology Inc. DS39776C-page 143

MRF24J40 NOTES: Preliminary DS39776C-page 144 © 2010 Microchip Technology Inc.

MRF24J40 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 40-Lead QFN Example XXXXXXXXXX MRF24J40 XXXXXXXXXX -I/ML e3 XXXXXXXXXX 0810017 YYWWNNN Legend: XX...X Product-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 145

MRF24J40 6.2 Package Details The following sections give the technical details of the packages. 40-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6x0.9 mm Body [QFN] with 0.40 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSEDPAD e E E2 b 2 2 1 1 N N NOTE1 L K TOPVIEW BOTTOMVIEW A A3 A1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 40 Pitch e 0.50 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E 6.00 BSC Exposed Pad Width E2 4.50 4.65 4.80 Overall Length D 6.00 BSC Exposed Pad Length D2 4.50 4.65 4.80 Contact Width b 0.18 0.25 0.30 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 – – Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-118C Preliminary DS39776C-page 146 © 2010 Microchip Technology Inc.

MRF24J40 APPENDIX A: REVISION HISTORY Revision B (October 2008) Rewritten the entire data sheet. Revision C (August 2010) This document includes the updated technical information. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 147

MRF24J40 NOTES: Preliminary © 2010 Microchip Technology Inc. DS39776C-page 148

MRF24J40 INDEX External PA/LNA Associated Registers ...............................................131 A G Absolute Maximum Ratings .............................................135 Generation .......................................................................115 AC Characteristics GTSFIFO State Diagram ...................................................95 Receiver ...................................................................136 Transmitter ...............................................................137 H Acknowledgement ............................................................112 Hardware Description ..........................................................5 Associated Registers ...............................................113 Antenna/Balun .................................................................129 I Applications ......................................................................129 IEEE 802.15.4-2003 Standard .............................................4 External PA/LNA Control .........................................130 Impedance B Measured .................................................................129 Initialization ........................................................................86 Battery Monitor .................................................................114 Associated Registers .................................................86 Beacon-Enabled Network ..................................................93 Interframe Spacing (IFS) .................................................102 Bill of Materials .................................................................134 Associated Registers ...............................................102 Block Diagrams Internet Address ..............................................................146 20 MHz Main Oscillator Crystal Circuit ........................8 Interrupts ...........................................................................87 32 kHz External Oscillator Crystal Circuit ....................9 Beacon-Enabled Coordinator Sleep Time Line ........118 L Beacon-Enabled Device Sleep Time Line ...............119 Link Quality Indication (LQI) ..............................................93 Example Circuit ........................................................129 Long Address Control Register Summary .........................16 External PA/LNA ......................................................130 IEEE 802.15.4 PHY Packet and MAC M Frame Structure ...................................................4 MAC Timer .......................................................................122 Interrupt Logic ............................................................87 Associated Registers ...............................................122 MRF24J40 Architecture ...............................................6 Memory Map ......................................................................11 Nonbeacon-Enabled (Coordinator or Device) Memory Organization ........................................................11 Sleep Time Line ...............................................120 Long Address Register Interface ...............................13 Sleep Clock Generation ...........................................115 Short Address Register Interface ..............................12 Sleep Mode Counters ..............................................117 Microchip Internet Web Site .............................................146 Superframe Structure .................................................94 N Wireless Node ..............................................................3 Nonbeacon-Enabled Network ............................................93 C O CCA Associated Registers .................................................89 Oscillator Mode 1 .......................................................................89 100 kHz Internal ..........................................................9 Mode 2 .......................................................................89 20 MHz Main ...............................................................8 Mode 3 .......................................................................89 23 kHz External Crystal ...............................................8 Channel Selection ..............................................................88 P Associated Registers .................................................88 Clear Channel Assessment (CCA) ....................................89 Packaging ........................................................................139 Control Register Description ..............................................14 Details ......................................................................140 Control Registers Marking ....................................................................139 Mapping, Long Address .............................................14 PCB Mapping, Short Address ............................................14 Layout Design ..........................................................132 CSMA-CA ..........................................................................99 Phase-Locked Loop (PLL) ...................................................8 Associated Registers ...............................................101 Pin Descriptions ...................................................................7 Slotted Mode ............................................................100 CS (Serial Interface Enable) ........................................7 Unslotted Mode ..........................................................99 GND (Ground, Digital Circuit) ......................................7 Current Consumption .......................................................136 GND (Ground, PLL) .....................................................7 Customer Change Notification Service ............................146 GND (Guard Ring Ground) ..........................................7 Customer Notification Service ..........................................146 GPIO0 (External PA Enable) .......................................7 Customer Support ............................................................146 GPIO1 (External TX/RX Switch Control) .....................7 GPIO2 (External TX/RX Switch Control) .....................7 D GPIO3 (General Purpose Digital I/O) ..........................7 Device Overview ............................................................3, 85 GPIO4 (General Purpose Digital I/O) ..........................7 GPIO5 (General Purpose Digital I/O) ..........................7 E INT (Interrupt Pin) ........................................................7 Electrical Characteristics ..................................................135 LCAP (PLL Loop Filter External Capacitor) .................7 Energy Detection (ED) .......................................................90 LPOSC1 (32 kHz Crystal Input) ...................................7 Errata ...................................................................................2 LPOSC2 (32 kHz Crystal Input) ...................................7 Example SPI Slave Mode Requirements .........................137 NC (No Connection) ....................................................7 Preliminary © 2010 Microchip Technology Inc. DS39776C-page 149

MRF24J40 OSC1 (20 MHz Crystal Input) ......................................7 ASSOSADR1 (Associated Coordinator OSC2 (20 MHz Crystal Input) ......................................7 Short Address 1) ................................................76 RESET (Global Hardware Reset Active-Low) ..............7 BBREG0 (Baseband 0) ..............................................55 RFN (Differential RF Pin, Negative) .............................7 BBREG1 (Baseband 1) ..............................................55 RFP (Differential RF Pin, Positive) ...............................7 BBREG2 (Baseband 2) ..............................................56 SCK (Serial Interface Clock) ........................................7 BBREG3 (Baseband 3) ..............................................56 SDI (Serial Interface Data Input) ..................................7 BBREG4 (Baseband 4) ..............................................57 SDO (Serial Interface Data Output) .............................7 BBREG6 (Baseband 6) ..............................................57 VDD (Charge Pump Power Supply) ..............................7 CCAEDTH (Energy Detection VDD (Digital Circuit Power Supply) ...............................7 Threshold for CCA) ............................................58 VDD (Guard Ring Power Supply) ..................................7 EADR0 (Extended Address 0) ...................................21 VDD (PLL Power Supply) ..............................................7 EADR1 (Extended Address 1) ...................................21 VDD (Power Supply, Analog Circuit) .............................7 EADR2 (Extended Address 2) ...................................21 VDD (Power Supply, Band Gap EADR3 (Extended Address 3) ...................................22 Reference Circuit) ................................................7 EADR4 (Extended Address 4) ...................................22 VDD (RF Power Supply) ...............................................7 EADR5 (Extended Address 5) ...................................22 VDD (VCO Supply) .......................................................7 EADR6 (Extended Address 6) ...................................23 WAKE (External Wake-up Trigger) ..............................7 EADR7 (Extended Address 7) ...................................23 Pins ESLOTG1 (GTS1 and CAP End Slot) .......................28 General Purpose Input/Output (GPIO) .........................9 ESLOTG23 (End Slot of GTS3 and GTS2) ...............35 Interrupt (INT) ..............................................................9 ESLOTG45 (End Slot of GTS5 and GTS4) ...............35 Reset (RESET) ............................................................9 ESLOTG67 (End Slot of GTS6) .................................35 Serial Peripheral Interface (SPI) ................................10 FRMOFFSET (Superframe Counter Offset Wake (WAKE) ..............................................................9 to Align Beacon) ................................................38 Power and Ground Pins .......................................................8 GATECLK (Gated Clock Control) ..............................41 Power Management GPIO (GPIO Port) ......................................................51 Associated Registers ...............................................114 HSYMTMRH (Half Symbol Timer High Byte) ............43 Proprietary Protocols HSYMTMRL (Half Symbol Timer Low Byte) ..............43 MiWi .............................................................................1 INTCON (Interrupt Control) ........................................50 MiWi P2P .....................................................................1 INTSTAT (Interrupt Status) ........................................49 ZigBee ..........................................................................1 MAINCNT0 (Main Counter 0) ....................................69 Proprietary Wireless Networking Protocols ..........................1 MAINCNT1 (Main Counter 1) ....................................69 MAINCNT2 (Main Counter 2) ....................................70 R MAINCNT3 (Main Counter 3) ....................................70 Reader Response ............................................................147 ORDER (Beacon and Superframe Order) .................25 Received Signal Strength Indicator (RSSI) ........................90 PACON0 (Power Amplifier Control 0) ........................30 Reception .........................................................................103 PACON1 (Power Amplifier Control 1) ........................30 Acknowledgement Request .....................................104 PACON2 (Power Amplifier Control 2) ........................31 Associated Registers ...............................................105 PANIDH (PAN ID High Byte) .....................................19 Interrupt ....................................................................104 PANIDL (PAN ID Low Byte) .......................................19 Modes ......................................................................104 REMCNTH (Remain Counter High) ...........................68 Error .................................................................104 REMCNTL (Remain Counter Low) ............................68 Normal .............................................................104 RFCON0 (RF Control 0) ............................................59 Promiscuous ....................................................104 RFCON1 (RF Control 1) ............................................59 Recommended Operating Conditions ..............................136 RFCON2 (RF Control 2) ............................................60 Registers RFCON3 (RF Control 3) ............................................60 ACKTMOUT (MAC ACK Time-out Duration) .............27 RFCON5 (RF Control 5) ............................................61 ASSOEADR0 (Associated Coordinator RFCON6 (RF Control 6) ............................................61 Extended Address 0) .........................................72 RFCON7 (RF Control 7) ............................................62 ASSOEADR1 (Associated Coordinator RFCON8 (RF Control 8) ............................................62 Extended Address 1) .........................................72 RFCTL (RF Mode Control) ........................................53 ASSOEADR2 (Associated Coordinator RFSTATE (RF State) .................................................65 Extended Address 2) .........................................73 RSSI (Averaged RSSI Value) ....................................65 ASSOEADR3 (Associated Coordinator RXFLUSH (Receive FIFO Flush) ...............................24 Extended Address 3) .........................................73 RXMCR (Receive MAC Control) ................................18 ASSOEADR4 (Associated Coordinator RXSR (RX MAC Status) ............................................48 Extended Address 4) .........................................74 SADRH (Short Address High Byte) ...........................20 ASSOEADR5 (Associated Coordinator SADRL (Short Address Low Byte) .............................20 Extended Address 5) .........................................74 SECCON0 (Security Control 0) .................................45 ASSOEADR6 (Associated Coordinator SECCON1 (Security Control 1) .................................46 Extended Address 6) .........................................75 SECCR2 (Security Control 2) ....................................54 ASSOEADR7 (Associated Coordinator SLPACK (Sleep Acknowledgement and Extended Address 7) .........................................75 Wake-up Counter) .............................................52 ASSOSADR0 (Associated Coordinator SLPCAL0 (Sleep Calibration 0) .................................63 Short Address 0) ................................................76 SLPCAL1 (Sleep Calibration 1) .................................63 Preliminary DS39776C-page 150 © 2010 Microchip Technology Inc.

MRF24J40 SLPCAL2 (Sleep Calibration 2) .................................64 S SLPCON0 (Sleep Clock Control 0) ............................66 Schematic ........................................................................133 SLPCON1 (Sleep Clock Control 1) ............................66 Security ............................................................................123 SOFTRST (Software Reset) ......................................44 MAC Sublayer Receive Decryption .........................125 SYMTICKH (Symbol Period Tick High Byte) .............29 MAC Sublayer Transmit Encryption ........................123 SYMTICKL (Symbol Period Tick Low Byte) ...............29 Memory Map ............................................................123 TESTMODE (Test Mode) ...........................................71 Upper Layer Decryption ...........................................127 TRISGPIO (GPIO Pin Direction) ................................51 Upper Layer Encryption ...........................................126 TXBCON0 (Transmit Beacon FIFO Control 0) ...........32 Security TXBCON1 (Transmit Beacon Control 1) ....................40 Associated Registers ...............................................127 TXG1CON (GTS1 FIFO Control) ...............................34 Setting Up Beacon-Enabled/Nonbeacon-Enabled Networks TXG2CON (GTS2 FIFO Control) ...............................34 Associated Registers .................................................98 TXMCR (CSMA-CA Mode Control) ............................26 Short Address Control Register Summary .........................15 TXNCON (Transmit Normal FIFO Control) ................33 Sleep ...............................................................................115 TXPEND (TX Data Pending) ......................................36 Associated Registers ...............................................121 TXSTAT (TX MAC Status) .........................................39 Sleep Timer TXSTBL (TX Stabilization) .........................................47 Beacon-Enabled Coordinator Mode ........................118 TXTIME (TX Turnaround Time) .................................42 Beacon-Enabled Device Mode ................................119 UPNONCE0 (Upper Nonce Security 0) .....................77 Immediate Sleep and Wake-up Mode .....................121 UPNONCE1 (Upper Nonce Security 1) .....................77 Nonbeacon-Enabled (Coordinator or UPNONCE10 (Upper Nonce Security 10) .................82 Device) Mode ..................................................120 UPNONCE11 (Upper Nonce Security 11) .................82 Timed Sleep Mode ..................................................115 UPNONCE12 (Upper Nonce Security 12) .................83 UPNONCE2 (Upper Nonce Security 2) .....................78 T UPNONCE3 (Upper Nonce Security 3) .....................78 Timing Diagrams UPNONCE4 (Upper Nonce Security 4) .....................79 Example SPI Slave Mode ........................................137 UPNONCE5 (Upper Nonce Security 5) .....................79 External PA/LNA ......................................................131 UPNONCE6 (Upper Nonce Security 6) .....................80 Long Address Read ...................................................13 UPNONCE7 (Upper Nonce Security 7) .....................80 Long Address Write ...................................................13 UPNONCE8 (Upper Nonce Security 8) .....................81 Short Address Read ..................................................12 UPNONCE9 (Upper Nonce Security 9) .....................81 Short Address Write ..................................................12 WAKECON (Wake Control) .......................................37 SPI Port Read (Output) .............................................10 WAKETIMEH (Wake-up Time Match SPI Port Write (Input) ................................................10 Value High) ........................................................67 Transmission ...................................................................106 WAKETIMEL (Wake-up Time Match Associated Registers ...............................................111 Value Low) .........................................................67 Turbo Mode .....................................................................128 Reset ..................................................................................85 Associated Registers ...............................................128 Associated Registers .................................................85 TX Beacon FIFO ..............................................................109 Revision History ...............................................................141 TX FIFOs Frame Structure ..............................................108 RF Transceiver ................................................................129 TX GTSx FIFO .................................................................110 RSSI TX Normal FIFO ..............................................................108 Mode 1 .......................................................................90 Mode 2 .......................................................................90 W RSSI/ED WWW Address ................................................................146 Associated Registers .................................................90 WWW, On-Line Support ......................................................2 Preliminary © 2010 Microchip Technology Inc. DS39776C-page 151

MRF24J40 NOTES: Preliminary DS39776C-page 152 © 2010 Microchip Technology Inc.

MRF24J40 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design • Development Systems Information Line resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQs), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. Preliminary © 2010 Microchip Technology Inc. DS39776C-page 153

MRF24J40 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: MRF24J40 Literature Number: DS39776C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? Preliminary DS39776C-page 154 © 2010 Microchip Technology Inc.

MRF24J40 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Example: Device Temperature Package Pattern a) MRF24J40-I/ML: Industrial temperature, Range QFN package. b) MRF24J40T-I/ML: Industrial temperature, QFN package, tape and reel. Device MRF24J40: IEEE 802.15.4™ 2.4 GHz RF Transceiver Temperature Range I = -40°C to +85°C (Industrial) Package ML = QFN (Plastic Quad Flat, No Lead) T = Tape and Reel Preliminary © 2010 Microchip Technology Inc. DS39776C-page 155

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