Freescale Semiconductor MPC866EC Rev. 2, 2/2006 Technical Data MPC866/MPC859 Hardware Specifications This document contains detailed information on power Contents considerations, DC/AC electrical characteristics, and AC timing 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 specifications for the MPC866/859 family (refer to Table1 for a 3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 8 list of devices). The MPC866P is the superset device of the 4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9 MPC866/859 family.This document describes pertinent electrical 5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 and physical characteristics of the MPC8245. For functional 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 10 characteristics of the processor, refer to the MPC866 7. Thermal Calculation and Measurement . . . . . . . . . . 12 PowerQUICC Family Users Manual (MPC866UM/D). 8. Power Supply and Power Sequencing . . . . . . . . . . . 15 9. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1 Overview 11. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 46 12. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 48 13. UTOPIA AC Electrical Specifications . . . . . . . . . . . 72 The MPC866/859 is a derivative of Freescale’s MPC860 14. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 74 PowerQUICC™ family of devices. It is a versatile single-chip 15. Mechanical Data and Ordering Information . . . . . . . 78 integrated microprocessor and peripheral combination that can be 16. Document Revision History . . . . . . . . . . . . . . . . . . . 93 used in a variety of controller applications and communications and networking systems. The MPC866/859/859DSL provides enhanced ATM functionality over that of other ATM-enabled members of the MPC860 family. ©Freescale Semiconductor, Inc., 2006. All rights reserved.

Features Table1 shows the functionality supported by the members of the MPC866/859 family. 2 Features Table1. MPC866 Family Functionality Cache Ethernet Part SCC SMC Instruction Data 10T 10/100 MPC866P 16 Kbytes 8 Kbytes Up to 4 1 4 2 MPC866T 4 Kbytes 4 Kbytes Up to 4 1 4 2 MPC859P 16 Kbytes 8 Kbytes 1 1 1 2 MPC859T 4 Kbytes 4 Kbytes 1 1 1 2 MPC859DSL 4 Kbytes 4 Kbytes 1 1 1 1 1 2 MPC852T 3 4 KBytes 4 Kbytes 2 1 2 1 1 On the MPC859DSL, the SCC (SCC1) is for ethernet only. Also, the MPC859DSL does not support the Time Slot Assigner (TSA). 2 On the MPC859DSL, the SMC (SMC1) is for UART only. 3 For more details on the MPC852T, please refer to the MPC852T Hardware Specifications. The following list summarizes the key MPC866/859 features: (cid:129) Embedded single-issue, 32-bit PowerPC™ core (implementing the PowerPC architecture) with thirty-two32-bit general-purpose registers (GPRs) — The core performs branch prediction with conditional prefetch, without conditional execution — 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table1) – 16-Kbyte instruction cache (MPC866P and MPC859P) is four-way, set-associative with 256 sets; 4-Kbyte instruction cache (MPC866T, MPC859T, and MPC859DSL) is two-way, set-associative with 128 sets. – 8-Kbyte data cache (MPC866P and MPC859P) is two-way, set-associative with 256 sets; 4-Kbyte data cache(MPC866T, MPC859T, and MPC859DSL) is two-way, set-associative with 128 sets. – Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks – Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis. — MMUs with 32-entry TLB, fully associative instruction and data TLBs — MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups. — Advanced on-chip-emulation debug mode (cid:129) The MPC866/859 provides enhanced ATM functionality over that of the MPC860SAR. The MPC866/859 adds major new features available in 'enhanced SAR' (ESAR) mode, including the following: — Improved operation, administration, and maintenance (OAM) support — OAM performance monitoring (PM) support — Multiple APC priority levels available to support a range of traffic pace requirements MPC866/MPC859 Hardware Specifications, Rev. 2 2 Freescale Semiconductor

Features — ATM port-to-port switching capability without the need for RAM-based microcode — Simultaneous MII (10/100Base-T) and UTOPIA (half-duplex) capability — Optional statistical cell counters per PHY — UTOPIA level 2 compliant interface with added FIFO buffering to reduce the total cell transmission time. (The earlier UTOPIA level1 specification is also supported.) – Multi-PHY support on the MPC866, MPC859P, and MPC859T – Four PHY support on the MPC866/859 — Parameter RAM for both SPI and I2C can be relocated without RAM-based microcode — Supports full-duplex UTOPIA both master (ATM side) and slave (PHY side) operation using a 'split' bus — AAL2/VBR functionality is ROM-resident. (cid:129) Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) (cid:129) Thirty-two address lines (cid:129) Memory controller (eight banks) — Contains complete dynamic RAM (DRAM) controller — Each bank can be a chip select or RAS to support a DRAM bank — Up to 30 wait states programmable per memory bank — Glueless interface to page mode/EDO/SDRAM, SRAM, EPROMs, flash EPROMs, and other memory devices. — DRAM controller programmable to support most size and speed memory interfaces — Four CAS lines, four WE lines, and one OE line — Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) — Variable block sizes (32 Kbytes–256 Mbytes) — Selectable write protection — On-chip bus arbitration logic (cid:129) General-purpose timers — Four 16-bit timers cascadable to be two 32-bit timers — Gate mode can enable/disable counting — Interrupt can be masked on reference match and event capture (cid:129) Fast Ethernet controller (FEC) — Simultaneous MII (10/100Base-T) and UTOPIA operation when using the UTOPIA multiplexed bus (cid:129) System integration unit (SIU) — Bus monitor — Software watchdog — Periodic interrupt timer (PIT) — Low-power stop mode — Clock synthesizer — Decrementer and time base from the PowerPC architecture — Reset controller — IEEE 1149.1 test access port (JTAG) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 3

Features (cid:129) Interrupts — Seven external interrupt request (IRQ) lines — Twelve port pins with interrupt capability — The MPC866P and MPC866T have 23 internal interrupt sources; the MPC859P, MPC859T, and MPC859DSL have 20 internal interrupt sources. — Programmable priority between SCCs (MPC866P and MPC866T) — Programmable highest priority request (cid:129) Communications processor module (CPM) — RISC controller — Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and RESTART TRANSMIT) — Supports continuous mode transmission and reception on all serial channels — Up to 8-Kbytes of dual-port RAM — MPC866P and MPC866T have 16 serial DMA (SDMA) channels; MPC859P, MPC859T, and MPC859DSL have 10 serial DMA (SDMA) channels. — Three parallel I/O registers with open-drain capability (cid:129) Four baud rate generators — Independent (can be connected to any SCC or SMC) — Allow changes during operation — Autobaud support option (cid:129) MPC866P and MPC866T have four SCCs (serial communication controller); MPC859P, MPC859T, and MPC859DSL have one SCC; and SCC1 on MPC859DSL supports Ethernet only. — Serial ATM capability on all SCCs — Optional UTOPIA port on SCC4 — Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation — HDLC/SDLC — HDLC bus (implements an HDLC-based local area network (LAN)) — Asynchronous HDLC to support PPP (point-to-point protocol) — AppleTalk — Universal asynchronous receiver transmitter (UART) — Synchronous UART — Serial infrared (IrDA) — Binary synchronous communication (BISYNC) — Totally transparent (bit streams) — Totally transparent (frame based with optional cyclic redundancy check (CRC) (cid:129) Two SMCs (serial management channels) (MPC859DSL has one SMC (SMC1) for UART.) — UART — Transparent — General circuit interface (GCI) controller — Can be connected to the time-division multiplexed (TDM) channels MPC866/MPC859 Hardware Specifications, Rev. 2 4 Freescale Semiconductor

Features (cid:129) One serial peripheral interface (SPI) — Supports master and slave modes — Supports multiple-master operation on the same bus (cid:129) One inter-integrated circuit (I 2C) port — Supports master and slave modes — Multiple-master environment support (cid:129) Time slot assigner (TSA) (MPC859DSL does not have TSA.) — Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation — Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined — 1- or 8-bit resolution — Allows independent transmit and receive routing, frame synchronization, and clocking — Allows dynamic changes — On MPC866P and MPC866T, can be internally connected to six serial channels (four SCCs and two SMCs); on MPC859P and MPC859T, can be connected to three serial channels (one SCC and two SMCs). (cid:129) Parallel interface port (PIP) — Centronics interface support — Supports fast connection between compatible ports on MPC866/859 or MC68360 (cid:129) PCMCIA interface — Master (socket) interface, compliant with PCI Local Bus Specification (Rev 2.1) — Supports one or two PCMCIA sockets whether ESAR functionality is enabled — Eight memory or I/O windows supported (cid:129) Debug interface — Eight comparators: four operate on instruction address, two operate on data address, and two operate on data. — Supports conditions: = ≠ < > — Each watchpoint can generate a breakpoint internally (cid:129) Normal high and normal low power modes to conserve power (cid:129) 1.8 V core and 3.3 V I/O operation with 5-V TTL compatibility; refer to Table6 for a listing of the 5-V tolerant pins. (cid:129) 357-pin plastic ball grid array (PBGA) package (cid:129) Operation up to 133 MHz MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 5

Features The MPC866/859 is comprised of three modules that each use a 32-bit internal bus: MPC8xx core, system integration unit (SIU), and communication processor module (CPM). The MPC866P block diagram is shown in Figure1. The MPC859P/859T/859DSL block diagram is shown in Figure2. Instruction 16-Kbyte System Interface Unit (SIU) Bus Instruction Cache Unified Memory Controller Instruction MMU Bus Embedded 32-Entry ITLB Internal External MPC8xx Bus Interface Bus Interface Processor Core Load/Store 8-Kbyte Unit Unit Bus Data Cache System Functions Data MMU PCMCIA/ATA Interface 32-Entry DTLB Fast Ethernet Controller DMAs FIFOs 4 Interrupt 8-Kbyte 16 Virtual Parallel I/O Timers Controllers Dual-Port RAM Serial and 10/100 4 Baud Rate Base-T Generators 32-Bit RISC Controller 2 Media Access and Program Independent Control Parallel Interface Port ROM DMA Timers and UTOPIA Channels MII SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI I2C TiTmimee S Slloott AAssssigignenrer Serial Interface Figure1. MPC866P Block Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 6 Freescale Semiconductor

Features Instruction 4-Kbyte † System Interface Unit (SIU) Bus Instruction Cache Unified Memory Controller Instruction MMU Bus Embedded 32-Entry ITLB Internal External MPC8xx Bus Interface Bus Interface ProCcoersesor Load/Store 4-Kbyte † Unit Unit Bus Data Cache System Functions Data MMU PCMCIA/ATA Interface 32-Entry DTLB Fast Ethernet Controller DMAs FIFOs 4 Interrupt 8-Kbyte 10 Virtual Parallel I/O Timers Controllers Dual-Port RAM Serial and 10/100 4 Baud Rate Base-T Generators 32-Bit RISC Controller 2 Media Access and Program Independent Control Parallel Interface Port ROM DMA Timers and UTOPIA Channels MII SCC1 SMC1 SMC2* SPI I2C TimTime eS Slolott AAssssigignneerr* Serial Interface † The MPC859P has a 16-Kbyte instruction cache and a 8-Kbyte data cache. * The MPC859DSL does not contain SMC2 nor the time slot assigner, and provides eight SDMA controllers. Figure2. MPC859P/859T/MPC859DSL Block Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 7

Maximum Tolerated Ratings 3 Maximum Tolerated Ratings This section provides the maximum tolerated voltage and temperature ranges for the MPC866/859. Table2 shows the maximum tolerated ratings, and Table3 shows the operating temperatures. Table2. Maximum Tolerated Ratings Rating Symbol Value Unit Supply voltage 1 VDDH – 0.3 to 4.0 V VDDL – 0.3 to 2.0 V VDDSYN – 0.3 to 2.0 V Difference between VDDL to VDDSYN 100 mV Input voltage 2 V GND – 0.3 to VDDH V in Storage temperature range T –55 to +150 °C stg 1 The power supply of the device must start its ramp from 0.0 V. 2 Functional operating conditions are provided with the DC electrical specifications in Table6. Absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device. See page 15. Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than VDDH. This restriction applies to power-up and normal operation (that is, if the MPC866/859 is unpowered, a voltage greater than 2.5 V must not be applied to its inputs). Table3. Operating Temperatures Rating Symbol Value Unit Temperature 1 (standard) T 0 °C A(min) T 95 °C j(max) Temperature (extended) T –40 °C A(min) T 100 °C j(max) 1 Minimum temperatures are guaranteed as ambient temperature, T . Maximum temperatures are guaranteed as A junction temperature, T. j This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or V ). DD MPC866/MPC859 Hardware Specifications, Rev. 2 8 Freescale Semiconductor

Thermal Characteristics 4 Thermal Characteristics Table4 shows the thermal characteristics for the MPC866/859. Table4. MPC866/859 Thermal Resistance Data Rating Environment Symbol Value Unit Junction-to-ambient 1 Natural Convection Single-layer board (1s) RθJA 2 37 °C/W Four-layer board (2s2p) RθJMA 3 23 Airflow (200 ft/min) Single-layer board (1s) RθJMA3 30 Four-layer board (2s2p) RθJMA3 19 Junction-to-board 4 RθJB 13 Junction-to-case 5 RθJC 6 Junction-to-package top 6 Natural Convection Ψ 2 JT Airflow (200 ft/min) Ψ 2 JT 1 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 2 Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal. 3 Per JEDEC JESD51-6 with the board horizontal. 4 Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5 Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed pad packages where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated value from the junction to the exposed pad without contact resistance. 6 Thermal characterization parameter indicating the temperature difference between package top and junction temperature per JEDEC JESD51-2. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 9

Power Dissipation 5 Power Dissipation Table5 shows power dissipation information. The modes are 1:1, where CPU and bus speeds are equal, and 2:1 mode, where CPU frequency is twice the bus speed. Table5. Power Dissipation (P ) D CPU Die Revision Bus Mode Typical 1 Maximum 2 Unit Frequency 0 1:1 50 MHz 110 140 mW 66 MHz 150 180 mW 2:1 66 MHz 140 160 mW 80 MHz 170 200 mW 100 MHz 210 250 mW 133 MHz 260 320 mW 1 Typical power dissipation at VDDL and VDDSYN is at 1.8 V. and VDDH is at 3.3 V. 2 Maximum power dissipation at VDDL and VDDSYN is at 1.9 V, and VDDH is at 3.465 V. NOTE Values in Table5 represent VDDL based power dissipation and do not include I/O power dissipation over VDDH. I/O power dissipation varies widely by application due to buffer current, depending on external circuitry. The VDDSYN power dissipation is negligible. 6 DC Characteristics Table6 shows the DC electrical characteristics for the MPC866/859. Table6. DC Electrical Specifications Characteristic Symbol Min Max Unit Operating voltage VDDL (core) 1.7 1.9 V VDDH (I/O) 3.135 3.465 V VDDSYN 1 1.7 1.9 V Difference between — 100 mV VDDL to VDDSYN Input high voltage (all inputs except EXTAL and VIH 2.0 3.465 V EXTCLK) 2 MPC866/MPC859 Hardware Specifications, Rev. 2 10 Freescale Semiconductor

DC Characteristics Table6. DC Electrical Specifications (continued) Characteristic Symbol Min Max Unit Input low voltage VIL GND 0.8 V EXTAL, EXTCLK input high voltage VIHC 0.7*(VDDH) VDDH V Input leakage current, Vin = 5.5V (except TMS, TRST, I — 100 µA in DSCK and DSDI pins) for 5 Volts Tolerant Pins 2 Input leakage current, Vin = VDDH (except TMS, TRST, I — 10 µA In DSCK, and DSDI) Input leakage current, Vin = 0 V (except TMS, TRST, I — 10 µA In DSCK and DSDI pins) Input capacitance 3 C — 20 pF in Output high voltage, IOH = – 2.0 mA, VOH 2.4 — V except XTAL, and Open drain pins Output low voltage VOL — 0.5 V (cid:129) IOL = 2.0 mA (CLKOUT) (cid:129) IOL = 3.2 mA 4 (cid:129) IOL = 5.3 mA 5 (cid:129) IOL = 7.0 mA (TXD1/PA14, TXD2/PA12) (cid:129) IOL = 8.9 mA (TS, TA, TEA, BI, BB, HRESET, SRESET) 1 The difference between VDDL and VDDSYN can not be more than 100 m V. 2 The signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], TDI, TDO, TCK, TRST_B, TMS, MII_TXEN, MII_MDIO are 5 V tolerant. 3 Input capacitance is periodically sampled. 4 A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IP_B(0:1)/IWP(0:1)/VFLS(0:1), IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3, RXD1 /PA15, RXD2/PA13, L1TXDB/PA11, L1RXDB/PA10, L1TXDA/PA9, L1RXDA/PA8, TIN1/L1RCLKA/BRGO1/CLK1/PA7, BRGCLK1/TOUT1/CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5, TOUT2/CLK4/PA4, TIN3/BRGO3/CLK5/PA3, BRGCLK2/L1RCLKB/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/PA1, L1TCLKB/TOUT4/CLK8/PA0, REJCT1/SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/PB28, BRGO1/I2CSDA/PB27, BRGO2/I2CSCL/PB26, SMTXD1/PB25, SMRXD1/PB24, SMSYN1/SDACK1/PB23, SMSYN2/SDACK2/PB22, SMTXD2/L1CLKOB/PB21, SMRXD2/L1CLKOA/PB20, L1ST1/RTS1/PB19, L1ST2/RTS2/PB18, L1ST3/L1RQB/PB17, L1ST4/L1RQA/PB16, BRGO3/PB15, RSTRT1/PB14, L1ST1/RTS1/DREQ0/PC15, L1ST2/RTS2/DREQ1/PC14, L1ST3/L1RQB/PC13, L1ST4/L1RQA/PC12, CTS1/PC11, TGATE1/CD1/PC10, CTS2/PC9, TGATE2/CD2/PC8, CTS3/SDACK2/L1TSYNCB/PC7, CD3/L1RSYNCB/PC6, CTS4/SDACK1/L1TSYNCA/PC5, CD4/L1RSYNCA/PC4, PD15/L1TSYNCA, PD14/L1RSYNCA, PD13/L1TSYNCB, PD12/L1RSYNCB, PD11/RXD3, PD10/TXD3, PD9/RXD4, PD8/TXD4, PD5/REJECT2, PD6/RTS4, PD7/RTS3, PD4/REJECT3, PD3, MII_MDC, MII_TX_ER, MII_EN, MII_MDIO, MII_TXD[0:3]. 5 BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD, WE1/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A, ALE_B/DSCK/AT1, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, BADDR(28:30). MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 11

Thermal Calculation and Measurement 7 Thermal Calculation and Measurement For the following discussions, P = (VDDL x IDDL) + PI/O, where PI/O is the power dissipation of the I/O drivers. D The VDDSYN power dissipation is negligible. 7.1 Estimation with Junction-to-Ambient Thermal Resistance An estimation of the chip junction temperature, T , in °C can be obtained from the equation: J TJ = TA +(RθJA x PD) where: T = ambient temperature (ºC) A RθJA = package junction-to-ambient thermal resistance (ºC/W) P = power dissipation in package D The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity T -T ) are possible. J A 7.2 Estimation with Junction-to-Case Thermal Resistance Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RθJA = RθJC + RθCA where: RθJA = junction-to-ambient thermal resistance (ºC/W) RθJC = junction-to-case thermal resistance (ºC/W) RθCA = case-to-ambient thermal resistance (ºC/W) RθJC is device related and cannot be influenced by the user. The user adjusts the thermal environment to affect the case-to-ambient thermal resistance, RθCA. For instance, the user can change the airflow around the device, add a heat sink, change the mounting arrangement on the printed-circuit board, or change the thermal dissipation on the printed-circuit board surrounding the device. This thermal model is most useful for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most packages, a better model is required. 7.3 Estimation with Junction-to-Board Thermal Resistance A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed-circuit board. It has been observed that the thermal performance of most plastic packages and especially PBGA packages is strongly dependent on the board temperature; see Figure3. MPC866/MPC859 Hardware Specifications, Rev. 2 12 Freescale Semiconductor

Thermal Calculation and Measurement Figure3. Effect of Board Temperature Rise on Thermal Behavior If the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: TJ = TB +(RθJB x PD) where: RθJB = junction-to-board thermal resistance (ºC/W) T = board temperature ºC B P = power dissipation in package D If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. For this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground plane. 7.4 Estimation Using Simulation When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor model can be used with the thermal simulation of the application [2], or a more accurate and complex model of the package can be used in the thermal simulation. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 13

Thermal Calculation and Measurement 7.5 Experimental Determination To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (Ψ ) can be used to determine the junction temperature with a measurement of the JT temperature at the top center of the package case using the following equation: T = T +(Ψ x P ) J T JT D where: Ψ = thermal characterization parameter JT T = thermocouple temperature on top of package T P = power dissipation in package D The thermal characterization parameter is measured per JESD51-2 specification published by JEDEC using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 7.6 References Semiconductor Equipment and Materials International(415) 964-5111 805 East Middlefield Rd. Mountain View, CA 94043 MIL-SPEC and EIA/JESD (JEDEC) specifications800-854-7179 or (Available from Global Engineering Documents)303-397-7956 JEDEC Specifications http://www.jedec.org 1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. 2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220. MPC866/MPC859 Hardware Specifications, Rev. 2 14 Freescale Semiconductor

Power Supply and Power Sequencing 8 Power Supply and Power Sequencing This section provides design considerations for the MPC866/859 power supply. The MPC866/859 has a core voltage (VDDL) and PLL voltage (VDDSYN) that operates at a lower voltage than the I/O voltage VDDH. The I/O section of the MPC866/859 is supplied with 3.3 V across VDDH and V (GND). SS Signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], TDI, TDO, TCK, TRST_B, TMS, MII_TXEN, and MII_MDIO are 5-V tolerant. All inputs cannot be more than 2.5 V greater than VDDH. In addition, 5-V tolerant pins cannot exceed 5.5 V and the remaining input pins cannot exceed 3.465 V. This restriction applies to power up/down and normal operation. One consequence of multiple power supplies is that when power is initially applied the voltage rails ramp up at different rates. The rates depend on the nature of the power supply, the type of load on each power supply, and the manner in which different voltages are derived. The following restrictions apply: (cid:129) VDDL must not exceed VDDH during power up and power down. (cid:129) VDDL must not exceed 1.9 V and VDDH must not exceed 3.465 V. These cautions are necessary for the long term reliability of the part. If they are violated, the electrostatic discharge (ESD) protection diodes are forward-biased and excessive current can flow through these diodes. If the system power supply design does not control the voltage sequencing, the circuit shown in Figure4 can be added to meet these requirements. The MUR420 Schottky diodes control the maximum potential difference between the external bus and core power supplies on powerup and the 1N5820 diodes regulate the maximum potential difference on powerdown. VDDH VDDL MUR420 1N5820 Figure4. Example Voltage Sequencing Circuit 9 Layout Practices Each V pin on the MPC866/859 should be provided with a low-impedance path to the board’s supply. DD Furthermore, each GND pin should be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The V power supply should be bypassed to ground using at least four 0.1 µF DD bypass capacitors located as close as possible to the four sides of the package. Each board designed should be characterized and additional appropriate decoupling capacitors should be used if required. The capacitor leads and associated printed-circuit traces connecting to chip V and GND should be kept to less than 1/2” per capacitor lead. DD At a minimum, a four-layer board employing two inner layers as V and GND planes should be used. DD All output pins on the MPC866/859 have fast rise and fall times. Printed-circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 15

Bus Signal Timing This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of 6” are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the V and GND circuits. Pull up all unused DD inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. For more information, please refer to Section 14.4.3, Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1), in the MPC866 User’s Manual. 10 Bus Signal Timing The maximum bus speed supported by the MPC866/859 is 66 MHz. Higher-speed parts must be operated in half-speed bus mode (for example, an MPC866/859 used at 100 MHz must be configured for a 50-MHz bus). Table7 and Table8 show the frequency ranges for standard part frequencies. Table7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode) Part Freq 50 MHz 66 MHz Min Max Min Max Core 40 50 40 66.67 Bus 40 50 40 66.67 Table8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode) Part 50 MHz 66 MHz 100 MHz 133 MHz Freq Min Max Min Max Min Max Min Max Core 40 50 40 66.67 40 100 40 133.34 Bus 20 25 20 33.33 20 50 20 66.67 Table9 shows the timings for the MPC866/859 at 33, 40, 50, and 66 MHz bus operation. The timing for the MPC866/859 bus shown in this table assumes a 50-pF load for maximum delays and a 0-pF load for minimum delays. CLKOUT assumes a 100-pF load maximum delay. Table9. Bus Operation Timings 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B1 Bus Period (CLKOUT) See Table7 — — — — — — — — ns B1a EXTCLK to CLKOUT phase skew – 2 +2 – 2 +2 – 2 +2 – 2 +2 ns B1b CLKOUT frequency jitter peak-to-peak — 1 — 1 — 1 — 1 ns B1c Frequency jitter on EXTCLK — 0.50 — 0.50 — 0.50 — 0.50 % MPC866/MPC859 Hardware Specifications, Rev. 2 16 Freescale Semiconductor

Bus Signal Timing Table9. Bus Operation Timings (continued) 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B1d CLKOUT phase jitter peak-to-peak — 4 — 4 — 4 — 4 ns for OSCLK ≥ 15 MHz CLKOUT phase jitter peak-to-peak — 5 — 5 — 5 — 5 ns for OSCLK < 15 MHz B2 CLKOUT pulse width low (MIN = 0.4 x 12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns B1, MAX = 0.6 x B1) B3 CLKOUT pulse width high (MIN = 0.4 x 12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns B1, MAX = 0.6 x B1) B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 4.00 ns B5 CLKOUT fall time — 4.00 — 4.00 — 4.00 — 4.00 ns B7 CLKOUT to A(0:31), BADDR(28:30), 7.60 — 6.30 — 5.00 — 3.80 — ns RD/WR, BURST, D(0:31), DP(0:3) output hold (MIN = 0.25 x B1) B7a CLKOUT to TSIZ(0:1), REG, RSV, 7.60 — 6.30 — 5.00 — 3.80 — ns AT(0:3), BDIP, PTR output hold (MIN = 0.25 x B1) B7b CLKOUT to BR, BG, FRZ, VFLS(0:1), 7.60 — 6.30 — 5.00 — 3.80 — ns VF(0:2), IWP(0:2), LWP(0:1), STS output hold (MIN = 0.25 x B1) B8 CLKOUT to A(0:31), BADDR(28:30) — 13.80 — 12.50 — 11.30 — 10.00 ns RD/WR, BURST, D(0:31), DP(0:3), valid (MAX = 0.25 x B1 + 6.3) B8a CLKOUT to TSIZ(0:1), REG, RSV, — 13.80 — 12.50 — 11.30 — 10.00 ns AT(0:3), BDIP, PTR valid (MAX = 0.25 x B1 + 6.3) B8b CLKOUT to BR, BG, VFLS(0:1), — 13.80 — 12.50 — 11.30 — 10.00 ns VF(0:2), IWP(0:2), FRZ, LWP(0:1), STS valid 4 (MAX = 0.25 x B1 + 6.3) B9 CLKOUT to A(0:31), BADDR(28:30), 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns RD/WR, BURST, D(0:31), DP(0:3), TSIZ(0:1), REG, RSV, AT(0:3), PTR High-Z (MAX = 0.25 x B1 + 6.3) B11 CLKOUT to TS, BB assertion (MAX = 7.60 13.60 6.30 12.30 5.00 11.00 3.80 9.80 ns 0.25 x B1 + 6.0) B11a CLKOUT to TA, BI assertion (when 2.50 9.30 2.50 9.30 2.50 9.30 2.50 9.80 ns driven by the memory controller or PCMCIA interface) (MAX = 0.00 x B1 + 9.30 1) B12 CLKOUT to TS, BB negation (MAX = 7.60 12.30 6.30 11.00 5.00 9.80 3.80 8.50 ns 0.25 x B1 + 4.8) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 17

Bus Signal Timing Table9. Bus Operation Timings (continued) 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B12a CLKOUT to TA, BI negation (when 2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns driven by the memory controller or PCMCIA interface) (MAX = 0.00 x B1 + 9.00) B13 CLKOUT to TS, BB High-Z (MIN = 0.25 7.60 21.60 6.30 20.30 5.00 19.00 3.80 14.00 ns x B1) B13a CLKOUT to TA, BI High-Z (when driven 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns by the memory controller or PCMCIA interface) (MIN = 0.00 x B1 + 2.5) B14 CLKOUT to TEA assertion (MAX = 2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns 0.00 x B1 + 9.00) B15 CLKOUT to TEA High-Z (MIN = 0.00 x 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns B1 + 2.50) B16 TA, BI valid to CLKOUT (setup time) 6.00 — 6.00 — 6.00 — 6.00 — ns (MIN = 0.00 x B1 + 6.00) B16a TEA, KR, RETRY, CR valid to CLKOUT 4.50 — 4.50 — 4.50 — 4.50 — ns (setup time) (MIN = 0.00 x B1 + 4.5) B16b BB, BG, BR, valid to CLKOUT (setup 4.00 — 4.00 — 4.00 — 4.00 — ns time) 2 (4 MIN = 0.00 x B1 + 0.00 ) B17 CLKOUT to TA, TEA, BI, BB, BG, BR 1.00 — 1.00 — 1.00 — 2.00 — ns valid (hold time) (MIN = 0.00 x B1 + 1.00 3) B17a CLKOUT to KR, RETRY, CR valid (hold 2.00 — 2.00 — 2.00 — 2.00 — ns time) (MIN = 0.00 x B1 + 2.00) B18 D(0:31), DP(0:3) valid to CLKOUT 6.00 — 6.00 — 6.00 — 6.00 — ns rising edge (setup time) 4 (MIN = 0.00 x B1 + 6.00) B19 CLKOUT rising edge to D(0:31), 1.00 — 1.00 — 1.00 — 2.00 — ns DP(0:3) valid (hold time) 4 (MIN = 0.00 x B1 + 1.00 5) B20 D(0:31), DP(0:3) valid to CLKOUT 4.00 — 4.00 — 4.00 — 4.00 — ns falling edge (setup time) 6(MIN = 0.00 x B1 + 4.00) B21 CLKOUT falling edge to D(0:31), 2.00 — 2.00 — 2.00 — 2.00 — ns DP(0:3) valid (hold Time) 6 (MIN = 0.00 x B1 + 2.00) B22 CLKOUT rising edge to CS asserted 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns GPCM ACS = 00 (MAX = 0.25 x B1 + 6.3) B22a CLKOUT falling edge to CS asserted — 8.00 — 8.00 — 8.00 — 8.00 ns GPCM ACS = 10, TRLX = 0 (MAX = 0.00 x B1 + 8.00) MPC866/MPC859 Hardware Specifications, Rev. 2 18 Freescale Semiconductor

Bus Signal Timing Table9. Bus Operation Timings (continued) 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B22b CLKOUT falling edge to CS asserted 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns GPCM ACS = 11, TRLX = 0, EBDF = 0 (MAX = 0.25 x B1 + 6.3) B22c CLKOUT falling edge to CS asserted 10.90 18.00 10.90 16.00 7.00 14.10 5.20 12.30 ns GPCM ACS = 11, TRLX = 0, EBDF = 1 (MAX = 0.375 x B1 + 6.6) B23 CLKOUT rising edge to CS negated 2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns GPCM read access, GPCM write access ACS = 00, TRLX = 0 & CSNT = 0 (MAX = 0.00 x B1 + 8.00) B24 A(0:31) and BADDR(28:30) to CS 5.60 — 4.30 — 3.00 — 1.80 — ns asserted GPCM ACS = 10, TRLX = 0 (MIN = 0.25 x B1 - 2.00) B24a A(0:31) and BADDR(28:30) to CS 13.20 — 10.50 — 8.00 — 5.60 — ns asserted GPCM ACS = 11, TRLX = 0 (MIN = 0.50 x B1 - 2.00) B25 CLKOUT rising edge to OE, WE(0:3) — 9.00 — 9.00 — 9.00 — 9.00 ns asserted (MAX = 0.00 x B1 + 9.00) B26 CLKOUT rising edge to OE negated 2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns (MAX = 0.00 x B1 + 9.00) B27 A(0:31) and BADDR(28:30) to CS 35.90 — 29.30 — 23.00 — 16.90 — ns asserted GPCM ACS = 10, TRLX = 1 (MIN = 1.25 x B1 - 2.00) B27a A(0:31) and BADDR(28:30) to CS 43.50 — 35.50 — 28.00 — 20.70 — ns asserted GPCM ACS = 11, TRLX = 1 (MIN = 1.50 x B1 - 2.00) B28 CLKOUT rising edge to WE(0:3) — 9.00 — 9.00 — 9.00 — 9.00 ns negated GPCM write access CSNT = 0 (MAX = 0.00 x B1 + 9.00) B28a CLKOUT falling edge to WE(0:3) 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns negated GPCM write access TRLX = 0,1, CSNT = 1, EBDF = 0 (MAX = 0.25 x B1 + 6.80) B28b CLKOUT falling edge to CS negated — 14.30 — 13.00 — 11.80 — 10.50 ns GPCM write access TRLX = 0,1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 0 (MAX = 0.25 x B1 + 6.80) B28c CLKOUT falling edge to WE(0:3) 10.90 18.00 10.90 18.00 7.00 14.30 5.20 12.30 ns negated GPCM write access TRLX = 0, CSNT = 1 write access TRLX = 0,1, CSNT = 1, EBDF = 1 (MAX = 0.375 x B1 + 6.6) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 19

Bus Signal Timing Table9. Bus Operation Timings (continued) 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B28d CLKOUT falling edge to CS negated — 18.00 — 18.00 — 14.30 — 12.30 ns GPCM write access TRLX = 0,1, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 1 (MAX = 0.375 x B1 + 6.6) B29 WE(0:3) negated to D(0:31), DP(0:3) 5.60 — 4.30 — 3.00 — 1.80 — ns High-Z GPCM write access, CSNT = 0, EBDF = 0 (MIN = 0.25 x B1 - 2.00) B29a WE(0:3) negated to D(0:31), DP(0:3) 13.20 — 10.50 — 8.00 — 5.60 — ns High-Z GPCM write access, TRLX = 0, CSNT = 1, EBDF = 0 (MIN = 0.50 x B1 – 2.00) B29b CS negated to D(0:31), DP(0:3), High 5.60 — 4.30 — 3.00 — 1.80 — ns Z GPCM write access, ACS = 00, TRLX = 0,1 & CSNT = 0 (MIN = 0.25 x B1– 2.00) B29c CS negated to D(0:31), DP(0:3) High-Z 13.20 — 10.50 — 8.00 — 5.60 — ns GPCM write access, TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 0 (MIN = 0.50 x B1 – 2.00) B29d WE(0:3) negated to D(0:31), DP(0:3) 43.50 — 35.50 — 28.00 — 20.70 — ns High-Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 0 (MIN = 1.50 x B1 – 2.00) B29e CS negated to D(0:31), DP(0:3) High-Z 43.50 — 35.50 — 28.00 — 20.70 — ns GPCM write access, TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 0 (MIN = 1.50 x B1 – 2.00) B29f WE(0:3) negated to D(0:31), DP(0:3) 5.00 — 3.00 — 1.10 — 0.00 — ns High Z GPCM write access, TRLX = 0, CSNT = 1, EBDF = 1 (MIN = 0.375 x B1 – 6.30) B29g CS negated to D(0:31), DP(0:3) High-Z 5.00 — 3.00 — 1.10 — 0.00 — ns GPCM write access, TRLX = 0, CSNT = 1 ACS = 10 or ACS = 11, EBDF = 1 (MIN = 0.375 x B1 – 6.30) B29h WE(0:3) negated to D(0:31), DP(0:3) 38.40 — 31.10 — 24.20 — 17.50 — ns High Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 1 (MIN = 0.375 x B1 – 3.30) B29i CS negated to D(0:31), DP(0:3) High-Z 38.40 — 31.10 — 24.20 — 17.50 — ns GPCM write access, TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 (MIN = 0.375 x B1 – 3.30) MPC866/MPC859 Hardware Specifications, Rev. 2 20 Freescale Semiconductor

Bus Signal Timing Table9. Bus Operation Timings (continued) 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B30 CS, WE(0:3) negated to A(0:31), 5.60 — 4.30 — 3.00 — 1.80 — ns BADDR(28:30) invalid GPCM write access 7 (MIN = 0.25 x B1 – 2.00) B30a WE(0:3) negated to A(0:31), 13.20 — 10.50 — 8.00 — 5.60 — ns BADDR(28:30) invalid GPCM, write access, TRLX = 0, CSNT = 1, CS negated to A(0:31) invalid GPCM write access TRLX = 0, CSNT =1 ACS = 10, or ACS == 11, EBDF = 0 (MIN = 0.50 x B1 – 2.00) B30b WE(0:3) negated to A(0:31) invalid 43.50 — 35.50 — 28.00 — 20.70 — ns GPCM BADDR(28:30) invalid GPCM write access, TRLX = 1, CSNT = 1. CS negated to A(0:31) invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10, or ACS == 11 EBDF = 0 (MIN = 1.50 x B1 – 2.00) B30c WE(0:3) negated to A(0:31), 8.40 — 6.40 — 4.50 — 2.70 — ns BADDR(28:30) invalid GPCM write access, TRLX = 0, CSNT = 1. CS negated to A(0:31) invalid GPCM write access, TRLX = 0, CSNT = 1 ACS = 10, ACS == 11, EBDF = 1 (MIN = 0.375 x B1 – 3.00) B30d WE(0:3) negated to A(0:31), 38.67 — 31.38 — 24.50 — 17.83 — ns BADDR(28:30) invalid GPCM write access TRLX = 1, CSNT =1, CS negated to A(0:31) invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10 or 11, EBDF = 1 B31 CLKOUT falling edge to CS valid, as 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns requested by control bit CST4 in the corresponding word in the UPM (MAX = 0.00 X B1 + 6.00) B31a CLKOUT falling edge to CS valid, as 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns requested by control bit CST1 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80) B31b CLKOUT rising edge to CS valid, as 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns requested by control bit CST2 in the corresponding word in the UPM (MAX = 0.00 x B1 + 8.00) B31c CLKOUT rising edge to CS valid, as 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns requested by control bit CST3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.30) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 21

Bus Signal Timing Table9. Bus Operation Timings (continued) 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B31d CLKOUT falling edge to CS valid, as 13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns requested by control bit CST1 in the corresponding word in the UPM EBDF = 1 (MAX = 0.375 x B1 + 6.6) B32 CLKOUT falling edge to BS valid, as 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns requested by control bit BST4 in the corresponding word in the UPM (MAX = 0.00 x B1 + 6.00) B32a CLKOUT falling edge to BS valid, as 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns requested by control bit BST1 in the corresponding word in the UPM, EBDF = 0 (MAX = 0.25 x B1 + 6.80) B32b CLKOUT rising edge to BS valid, as 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns requested by control bit BST2 in the corresponding word in the UPM (MAX = 0.00 x B1 + 8.00) B32c CLKOUT rising edge to BS valid, as 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns requested by control bit BST3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80) B32d CLKOUT falling edge to BS valid- as 13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns requested by control bit BST1 in the corresponding word in the UPM, EBDF = 1 (MAX = 0.375 x B1 + 6.60) B33 CLKOUT falling edge to GPL valid, as 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns requested by control bit GxT4 in the corresponding word in the UPM (MAX = 0.00 x B1 + 6.00) B33a CLKOUT rising edge to GPL valid, as 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns requested by control bit GxT3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80) B34 A(0:31), BADDR(28:30), and D(0:31) 5.60 — 4.30 — 3.00 — 1.80 — ns to CS valid, as requested by control bit CST4 in the corresponding word in the UPM (MIN = 0.25 x B1 - 2.00) B34a A(0:31), BADDR(28:30), and D(0:31) 13.20 — 10.50 — 8.00 — 5.60 — ns to CS valid, as requested by control bit CST1 in the corresponding word in the UPM (MIN = 0.50 x B1 – 2.00) B34b A(0:31), BADDR(28:30), and D(0:31) 20.70 — 16.70 — 13.00 — 9.40 — ns to CS valid, as requested by CST2 in the corresponding word in UPM (MIN = 0.75 x B1 – 2.00) MPC866/MPC859 Hardware Specifications, Rev. 2 22 Freescale Semiconductor

Bus Signal Timing Table9. Bus Operation Timings (continued) 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B35 A(0:31), BADDR(28:30) to CS valid, as 5.60 — 4.30 — 3.00 — 1.80 — ns requested by control bit BST4 in the corresponding word in the UPM (MIN = 0.25 x B1 – 2.00) B35a A(0:31), BADDR(28:30), and D(0:31) 13.20 — 10.50 — 8.00 — 5.60 — ns to BS valid, as Requested by BST1 in the corresponding word in the UPM (MIN = 0.50 x B1 – 2.00) B35b A(0:31), BADDR(28:30), and D(0:31) 20.70 — 16.70 — 13.00 — 9.40 — ns to BS valid, as requested by control bit BST2 in the corresponding word in the UPM (MIN = 0.75 x B1 – 2.00) B36 A(0:31), BADDR(28:30), and D(0:31) 5.60 — 4.30 — 3.00 — 1.80 — ns to GPL valid as requested by control bit GxT4 in the corresponding word in the UPM (MIN = 0.25 x B1 – 2.00) B37 UPWAIT valid to CLKOUT falling 6.00 — 6.00 — 6.00 — 6.00 — ns edge 8 (MIN = 0.00 x B1 + 6.00) B38 CLKOUT falling edge to UPWAIT 1.00 — 1.00 — 1.00 — 1.00 — ns valid8 (MIN = 0.00 x B1 + 1.00) B39 AS valid to CLKOUT rising edge 9 (MIN 7.00 — 7.00 — 7.00 — 7.00 — ns = 0.00 x B1 + 7.00) B40 A(0:31), TSIZ(0:1), RD/WR, BURST, 7.00 — 7.00 — 7.00 — 7.00 — ns valid to CLKOUT rising edge (MIN = 0.00 x B1 + 7.00) B41 TS valid to CLKOUT rising edge (setup 7.00 — 7.00 — 7.00 — 7.00 — ns time) (MIN = 0.00 x B1 + 7.00) B42 CLKOUT rising edge to TS valid (hold 2.00 — 2.00 — 2.00 — 2.00 — ns time) (MIN = 0.00 x B1 + 2.00) B43 AS negation to memory controller — TBD — TBD — TBD — TBD ns signals negation (MAX = TBD) 1 For part speeds above 50 MHz, use 9.80 ns for B11a. 2 The timing required for BR input is relevant when the MPC866/859 is selected to work with the internal bus arbiter. The timing for BG input is relevant when the MPC866/859 is selected to work with the external bus arbiter. 3 For part speeds above 50 MHz, use 2 ns for B17. 4 The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of CLKOUT, in which the TA input signal is asserted. 5 For part speeds above 50 MHz, use 2 ns for B19. 6 The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats, where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) 7 The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 23

Bus Signal Timing 8 The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally. The timings specified in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure20. 9 The AS signal is considered asynchronous to CLKOUT. The timing B39 is specified in order to allow the behavior specified in Figure23. Figure5 shows the control timing diagram. 2.0 V 2.0 V CLKOUT 0.8 V 0.8 V A B 2.0 V 2.0 V Outputs 0.8 V 0.8 V A B 2.0 V 2.0 V Outputs 0.8 V 0.8 V D C 2.0 V 2.0 V Inputs 0.8 V 0.8 V D C 2.0 V 2.0 V Inputs 0.8 V 0.8 V A Maximum output delay specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification Figure5. Control Timing MPC866/MPC859 Hardware Specifications, Rev. 2 24 Freescale Semiconductor

Bus Signal Timing Figure6 shows the timing for the external clock. CLKOUT B1 B3 B1 B2 B4 B5 Figure6. External Clock Timing Figure7 shows the timing for the synchronous output signals. CLKOUT B8 B7 B9 Output Signals B8a B7a B9 Output Signals B8b B7b Output Signals Figure7. Synchronous Output Signals Timing MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 25

Bus Signal Timing Figure8 shows the timing for the synchronous active pull-up and open-drain output signals. CLKOUT B13 B11 B12 TS, BB B13a B11a B12a TA, BI B14 B15 TEA Figure8. Synchronous Active Pull-Up Resistor and Open-Drain Output Signals Timing Figure9 shows the timing for the synchronous input signals. CLKOUT B16 B17 TA, BI B16a B17a TEA, KR, RETRY, CR B16b B17 BB, BG, BR Figure9. Synchronous Input Signals Timing MPC866/MPC859 Hardware Specifications, Rev. 2 26 Freescale Semiconductor

Bus Signal Timing Figure10 shows normal case timing for input data. It also applies to normal read accesses under the control of the UPM in the memory controller. CLKOUT B16 B17 TA B18 B19 D[0:31], DP[0:3] Figure10. Input Data Timing in Normal Case Figure11 shows the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) CLKOUT TA B20 B21 D[0:31], DP[0:3] Figure11. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1 MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 27

Bus Signal Timing Figure12 through Figure15 show the timing for the external bus read controlled by various GPCM factors. CLKOUT B11 B12 TS B8 A[0:31] B22 B23 CSx B25 B26 OE B28 WE[0:3] B19 B18 D[0:31], DP[0:3] Figure12. External Bus Read Timing (GPCM Controlled—ACS = 00) MPC866/MPC859 Hardware Specifications, Rev. 2 28 Freescale Semiconductor

Bus Signal Timing CLKOUT B11 B12 TS B8 A[0:31] B22a B23 CSx B24 B25 B26 OE B18 B19 D[0:31], DP[0:3] Figure13. External Bus Read Timing (GPCM Controlled—TRLX = 0 or 1, ACS = 10) CLKOUT B11 B12 TS B8 B22b A[0:31] B22c B23 CSx B24a B25 B26 OE B18 B19 D[0:31], DP[0:3] Figure14. External Bus Read Timing (GPCM Controlled—TRLX = 0 or 1, ACS = 11) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 29

Bus Signal Timing CLKOUT B11 B12 TS B8 A[0:31] B22a B23 CSx B27 B26 OE B27a B22bB22c B18 B19 D[0:31], DP[0:3] Figure15. External Bus Read Timing (GPCM Controlled—TRLX=0 or 1, ACS=10, ACS=11) MPC866/MPC859 Hardware Specifications, Rev. 2 30 Freescale Semiconductor

Bus Signal Timing Figure16 through Figure18 show the timing for the external bus write controlled by various GPCM factors. CLKOUT B11 B12 TS B8 B30 A[0:31] B22 B23 CSx B25 B28 WE[0:3] B26 B29b OE B29 B8 B9 D[0:31], DP[0:3] Figure16. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 0) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 31

Bus Signal Timing CLKOUT B11 B12 TS B8 B30aB30c A[0:31] B22 B28b B28d B23 CSx B25 B29cB29g WE[0:3] B26 B29a B29f OE B28aB28c B8 B9 D[0:31], DP[0:3] Figure17. External Bus Write Timing (GPCM Controlled—TRLX =0,CSNT = 1) MPC866/MPC859 Hardware Specifications, Rev. 2 32 Freescale Semiconductor

Bus Signal Timing CLKOUT B11 B12 TS B8 B30bB30d A[0:31] B22 B28b B28d B23 CSx B25 B29e B29i WE[0:3] B26 B29d B29h OE B29b B8 B28a B28c B9 D[0:31], DP[0:3] Figure18. External Bus Write Timing (GPCM Controlled—TRLX =1,CSNT = 1) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 33

Bus Signal Timing Figure19 shows the timing for the external bus controlled by the UPM. CLKOUT B8 A[0:31] B31a B31d B31c B31 B31b CSx B34 B34a B34b B32a B32d B32c B32 B32b BS_A[0:3], BS_B[0:3] B35 B36 B35a B33a B35b B33 GPL_A[0:5], GPL_B[0:5] Figure19. External Bus Timing (UPM Controlled Signals) MPC866/MPC859 Hardware Specifications, Rev. 2 34 Freescale Semiconductor

Bus Signal Timing Figure20 shows the timing for the asynchronous asserted UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT B38 CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure20. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure21 shows the timing for the asynchronous negated UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT B38 CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure21. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 35

Bus Signal Timing Figure22 shows the timing for the synchronous external master access controlled by the GPCM. CLKOUT B41 B42 TS B40 A[0:31], TSIZ[0:1], R/W, BURST B22 CSx Figure22. Synchronous External Master Access Timing (GPCM Handled ACS = 00) MPC866/MPC859 Hardware Specifications, Rev. 2 36 Freescale Semiconductor

Bus Signal Timing Figure23 shows the timing for the asynchronous external master memory access controlled by the GPCM. CLKOUT B39 AS B40 A[0:31], TSIZ[0:1], R/W B22 CSx Figure23. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00) Figure24 shows the timing for the asynchronous external master control signals negation. AS B43 CSx, WE[0:3], OE, GPLx, BS[0:3] Figure24. Asynchronous External Master—Control Signals Negation Timing Table10 shows the interrupt timing for the MPC866/859. Table10. Interrupt Timing All Frequencies Num Characteristic 1 Unit Min Max I39 IRQx valid to CLKOUT rising edge (setup time) 6.00 — ns I40 IRQx hold time after CLKOUT 2.00 — ns I41 IRQx pulse width low 3.00 — ns I42 IRQx pulse width high 3.00 — ns I43 IRQx edge-to-edge time 4xT — — CLOCKOUT 1 The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT. The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has no direct relation with the total system interrupt latency that the MPC866/859 is able to support. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 37

Bus Signal Timing Figure25 shows the interrupt detection timing for the external level-sensitive lines. CLKOUT I39 I40 IRQx Figure25. Interrupt Detection Timing for External Level Sensitive Lines Figure26 shows the interrupt detection timing for the external edge-sensitive lines. CLKOUT I41 I42 IRQx I43 I43 Figure26. Interrupt Detection Timing for External Edge Sensitive Lines Table11 shows the PCMCIA timing for the MPC866/859. Table11. PCMCIA Timing 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max A(0:31), REG valid to PCMCIA 20.70 — 16.70 — 13.00 — 9.40 — ns P44 Strobe asserted 1 (MIN = 0.75 x B1 – 2.00) A(0:31), REG valid to ALE 28.30 — 23.00 — 18.00 — 13.20 — ns P45 negation1 (MIN = 1.00 x B1 – 2.00) CLKOUT to REG valid (MAX = 0.25 7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns P46 x B1 + 8.00) CLKOUT to REG invalid (MIN = 8.60 — 7.30 — 6.00 — 4.80 — ns P47 0.25 x B1 + 1.00) CLKOUT to CE1, CE2 asserted 7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns P48 (MAX = 0.25 x B1 + 8.00) CLKOUT to CE1, CE2 negated 7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns P49 (MAX = 0.25 x B1 + 8.00) MPC866/MPC859 Hardware Specifications, Rev. 2 38 Freescale Semiconductor

Bus Signal Timing Table11. PCMCIA Timing (continued) 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max CLKOUT to PCOE, IORD, PCWE, — 11.00 — 11.00 — 11.00 — 11.00 ns P50 IOWR assert time (MAX = 0.00 x B1 + 11.00) CLKOUT to PCOE, IORD, PCWE, 2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns P51 IOWR negate time (MAX = 0.00 x B1 + 11.00) CLKOUT to ALE assert time (MAX 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns P52 = 0.25 x B1 + 6.30) CLKOUT to ALE negate time (MAX — 15.60 — 14.30 — 13.00 — 11.80 ns P53 = 0.25 x B1 + 8.00) PCWE, IOWR negated to D(0:31) 5.60 — 4.30 — 3.00 — 1.80 — ns P54 invalid1 (MIN = 0.25 x B1 – 2.00) WAITA and WAITB valid to 8.00 — 8.00 — 8.00 — 8.00 — ns P55 CLKOUT rising edge1 (MIN = 0.00 x B1 + 8.00) CLKOUT rising edge to WAITA and 2.00 — 2.00 — 2.00 — 2.00 — ns P56 WAITB invalid1 (MIN = 0.00 x B1 + 2.00) 1 PSST = 1. Otherwise, add PSST times cycle time. PSHT = 0. Otherwise, add PSHT times cycle time. These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See PCMCIA Interface in the MPC866 PowerQUICC User’s Manual. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 39

Bus Signal Timing Figure27 shows the PCMCIA access cycle timing for the external bus read. CLKOUT TS P44 A[0:31] P46 P45 P47 REG P48 P49 CE1/CE2 P50 P51 PCOE, IORD P52 P53 P52 ALE B18 B19 D[0:31] Figure27. PCMCIA Access Cycles Timing External Bus Read MPC866/MPC859 Hardware Specifications, Rev. 2 40 Freescale Semiconductor

Bus Signal Timing Figure28 shows the PCMCIA access cycle timing for the external bus write. CLKOUT TS P44 A[0:31] P46 P45 P47 REG P48 P49 CE1/CE2 P50 P51 P54 PCWE, IOWR P52 P53 P52 ALE B8 B9 D[0:31] Figure28. PCMCIA Access Cycles Timing External Bus Write Figure29 shows the PCMCIA WAIT signals detection timing. CLKOUT P55 P56 WAITx Figure29. PCMCIA WAIT Signals Detection Timing MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 41

Bus Signal Timing Table12 shows the PCMCIA port timing for the MPC866/859. Table12. PCMCIA Port Timing 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max CLKOUT to OPx, valid (MAX = 0.00 x B1 — 19.00 — 19.00 — 19.00 — 19.00 ns P57 + 19.00) HRESET negated to OPx drive 1(MIN = 25.70 — 21.70 — 18.00 — 14.40 — ns P58 0.75 x B1 + 3.00) IP_Xx valid to CLKOUT rising edge (MIN 5.00 — 5.00 — 5.00 — 5.00 — ns P59 = 0.00 x B1 + 5.00) CLKOUT rising edge to IP_Xx invalid 1.00 — 1.00 — 1.00 — 1.00 — ns P60 (MIN = 0.00 x B1 + 1.00) 1 OP2 and OP3 only. Figure30 shows the PCMCIA output port timing for the MPC866/859. CLKOUT P57 Output Signals HRESET P58 OP2, OP3 Figure30. PCMCIA Output Port Timing Figure31 shows the PCMCIA output port timing for the MPC866/859. CLKOUT P59 P60 Input Signals Figure31. PCMCIA Input Port Timing MPC866/MPC859 Hardware Specifications, Rev. 2 42 Freescale Semiconductor

Bus Signal Timing Table13 shows the debug port timing for the MPC866/859. Table13. Debug Port Timing All Frequencies Num Characteristic Unit Min Max D61 DSCK cycle time 3xT — CLOCKOUT D62 DSCK clock pulse width 1.25xT — CLOCKOUT D63 DSCK rise and fall times 0.00 3.00 ns D64 DSDI input data setup time 8.00 — ns D65 DSDI data hold time 5.00 — ns D66 DSCK low to DSDO data valid 0.00 15.00 ns D67 DSCK low to DSDO invalid 0.00 2.00 ns Figure32 shows the input timing for the debug port clock. DSCK D61 D62 D61 D62 D63 D63 Figure32. Debug Port Clock Input Timing Figure33 shows the timing for the debug port. DSCK D64 D65 DSDI D66 D67 DSDO Figure33. Debug Port Timings MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 43

Bus Signal Timing Table14 shows the reset timing for the MPC866/859. Table14. Reset Timing 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max CLKOUT to HRESET high impedance — 20.00 — 20.00 — 20.00 — 20.00 ns R69 (MAX = 0.00 x B1 + 20.00) CLKOUT to SRESET high impedance — 20.00 — 20.00 — 20.00 — 20.00 ns R70 (MAX = 0.00 x B1 + 20.00) RSTCONF pulse width (MIN = 17.00 x 515.20 — 425.00 — 340.00 — 257.60 — ns R71 B1) R72 — — — — — — — — — — Configuration data to HRESET rising 504.50 — 425.00 — 350.00 — 277.30 — ns R73 edge setup time (MIN = 15.00 x B1 + 50.00) Configuration data to RSTCONF rising 350.00 — 350.00 — 350.00 — 350.00 — ns R74 edge setup time (MIN = 0.00 x B1 + 350.00) Configuration data hold time after 0.00 — 0.00 — 0.00 — 0.00 — ns R75 RSTCONF negation (MIN = 0.00 x B1 + 0.00) Configuration data hold time after 0.00 — 0.00 — 0.00 — 0.00 — ns R76 HRESET negation (MIN = 0.00 x B1 + 0.00) HRESET and RSTCONF asserted to — 25.00 — 25.00 — 25.00 — 25.00 ns R77 data out drive (MAX = 0.00 x B1 + 25.00) RSTCONF negated to data out high — 25.00 — 25.00 — 25.00 — 25.00 ns R78 impedance (MAX = 0.00 x B1 + 25.00) CLKOUT of last rising edge before chip — 25.00 — 25.00 — 25.00 — 25.00 ns R79 three-states HRESET to data out high impedance (MAX = 0.00 x B1 + 25.00) R80 DSDI, DSCK setup (MIN = 3.00 x B1) 90.90 — 75.00 — 60.00 — 45.50 — ns DSDI, DSCK hold time (MIN = 0.00 x B1 0.00 — 0.00 — 0.00 — 0.00 — ns R81 + 0.00) SRESET negated to CLKOUT rising 242.40 — 200.00 — 160.00 — 121.20 — ns R82 edge for DSDI and DSCK sample (MIN = 8.00 x B1) MPC866/MPC859 Hardware Specifications, Rev. 2 44 Freescale Semiconductor

Bus Signal Timing Figure34 shows the reset timing for the data bus configuration. HRESET R71 R76 RSTCONF R73 R74 R75 D[0:31] (IN) Figure34. Reset Timing—Configuration from Data Bus Figure35 shows the reset timing for the data bus weak drive during configuration. CLKOUT R69 HRESET R79 RSTCONF R77 R78 D[0:31] (OUT) (Weak) Figure35. Reset Timing—Data Bus Weak Drive During Configuration MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 45

IEEE 1149.1 Electrical Specifications Figure36 shows the reset timing for the debug port configuration. CLKOUT R70 R82 SRESET R80 R80 R81 R81 DSCK, DSDI Figure36. Reset Timing—Debug Port Configuration 11 IEEE 1149.1 Electrical Specifications Table15 shows the JTAG timings for the MPC866/859 shown in Figure37 through Figure40. Table15. JTAG Timing All Frequencies Num Characteristic Unit Min Max J82 TCK cycle time 100.00 — ns J83 TCK clock pulse width measured at 1.5 V 40.00 — ns J84 TCK rise and fall times 0.00 10.00 ns J85 TMS, TDI data setup time 5.00 — ns J86 TMS, TDI data hold time 25.00 — ns J87 TCK low to TDO data valid — 27.00 ns J88 TCK low to TDO data invalid 0.00 — ns J89 TCK low to TDO high impedance — 20.00 ns J90 TRST assert time 100.00 — ns J91 TRST setup time to TCK low 40.00 — ns J92 TCK falling edge to output valid — 50.00 ns J93 TCK falling edge to output valid out of high impedance — 50.00 ns J94 TCK falling edge to output high impedance — 50.00 ns J95 Boundary scan input valid to TCK rising edge 50.00 — ns J96 TCK rising edge to boundary scan input invalid 50.00 — ns MPC866/MPC859 Hardware Specifications, Rev. 2 46 Freescale Semiconductor

IEEE 1149.1 Electrical Specifications TCK J82 J83 J82 J83 J84 J84 Figure37. JTAG Test Clock Input Timing TCK J85 J86 TMS, TDI J87 J88 J89 TDO Figure38. JTAG Test Access Port Timing Diagram TCK J91 J90 TRST Figure39. JTAG TRST Timing Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 47

CPM Electrical Characteristics TCK J92 J94 Output Signals J93 Output Signals J95 J96 Output Signals Figure40. Boundary Scan (JTAG) Timing Diagram 12 CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module (CPM) of the MPC866/859. 12.1 PIP/PIO AC Electrical Specifications Table16 shows the PIP/PIO AC timings as shown in Figure41 through Figure45. Table16. PIP/PIO Timing All Frequencies Num Characteristic Unit Min Max 21 Data-in setup time to STBI low 0 — ns 22 Data-In hold time to STBI high 2.5 – t3 1 — clk 23 STBI pulse width 1.5 — clk 24 STBO pulse width 1 clk – 5ns — ns 25 Data-out setup time to STBO low 2 — clk 26 Data-out hold time from STBO high 5 — clk 27 STBI low to STBO low (Rx interlock) — 2 clk 28 STBI low to STBO high (Tx interlock) 2 — clk 29 Data-in setup time to clock high 15 — ns 30 Data-in hold time from clock high 7.5 — ns 31 Clock low to data-out valid (CPU writes data, control, or direction) — 25 ns 1 t3 = Specification 23 MPC866/MPC859 Hardware Specifications, Rev. 2 48 Freescale Semiconductor

CPM Electrical Characteristics DATA-IN 21 22 23 STBI 27 24 STBO Figure41. PIP Rx (Interlock Mode) Timing Diagram DATA-OUT 25 26 24 STBO (Output) 28 23 STBI (Input) Figure42. PIP Tx (Interlock Mode) Timing Diagram DATA-IN 21 22 23 STBI (Input) 24 STBO (Output) Figure43. PIP Rx (Pulse Mode) Timing Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 49

CPM Electrical Characteristics DATA-OUT 25 26 24 STBO (Output) 23 STBI (Input) Figure44. PIP TX (Pulse Mode) Timing Diagram CLKO 29 30 DATA-IN 31 DATA-OUT Figure45. Parallel I/O Data-In/Data-Out Timing Diagram 12.2 Port C Interrupt AC Electrical Specifications Table17 shows timings for port C interrupts. Table17. Port C Interrupt Timing 33.34 MHz Num Characteristic Unit Min Max 35 Port C interrupt pulse width low (edge-triggered mode) 55 — ns 36 Port C interrupt minimum time between active edges 55 — ns Figure46 shows the port C interrupt detection timing. MPC866/MPC859 Hardware Specifications, Rev. 2 50 Freescale Semiconductor

CPM Electrical Characteristics 36 Port C (Input) 35 Figure46. Port C Interrupt Detection Timing 12.3 IDMA Controller AC Electrical Specifications Table18 shows the IDMA controller timings as shown in Figure47 through Figure50. Table18. IDMA Controller Timing All Frequencies Num Characteristic Unit Min Max 40 DREQ setup time to clock high 7 — ns 41 DREQ hold time from clock high 3 — ns 42 SDACK assertion delay from clock high — 12 ns 43 SDACK negation delay from clock low — 12 ns 44 SDACK negation delay from TA low — 20 ns 45 SDACK negation delay from clock high — 15 ns 46 TA assertion to falling edge of the clock setup time (applies to external TA) 7 — ns CLKO (Output) 41 40 DREQ (Input) Figure47. IDMA External Requests Timing Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 51

CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) 42 43 DATA 46 TA (Input) SDACK Figure48. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) 42 44 DATA TA (Output) SDACK Figure49. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA MPC866/MPC859 Hardware Specifications, Rev. 2 52 Freescale Semiconductor

CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) 42 45 DATA TA (Output) SDACK Figure50. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA 12.4 Baud Rate Generator AC Electrical Specifications Table19 shows the baud rate generator timings as shown in Figure51. Table19. Baud Rate Generator Timing All Frequencies Num Characteristic Unit Min Max 50 BRGO rise and fall time — 10 ns 51 BRGO duty cycle 40 60 % 52 BRGO cycle 40 — ns 50 50 BRGOX 51 51 52 Figure51. Baud Rate Generator Timing Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 53

CPM Electrical Characteristics 12.5 Timer AC Electrical Specifications Table20 shows the general-purpose timer timings as shown in Figure52. Table20. Timer Timing All Frequencies Num Characteristic Unit Min Max 61 TIN/TGATE rise and fall time 10 — ns 62 TIN/TGATE low time 1 — clk 63 TIN/TGATE high time 2 — clk 64 TIN/TGATE cycle time 3 — clk 65 CLKO low to TOUT valid 3 25 ns CLKO 60 61 63 62 TIN/TGATE (Input) 61 64 65 TOUT (Output) Figure52. CPM General-Purpose Timers Timing Diagram 12.6 Serial Interface AC Electrical Specifications Table21 shows the serial interface timings as shown in Figure53 through Figure57. Table21. SI Timing All Frequencies Num Characteristic Unit Min Max 70 L1RCLK, L1TCLK frequency (DSC = 0) 1, 2 — SYNCCLK/2.5 MHz 71 L1RCLK, L1TCLK width low (DSC = 0) 2 P + 10 — ns 71a L1RCLK, L1TCLK width high (DSC = 0) 3 P + 10 — ns 72 L1TXD, L1ST(1–4), L1RQ, L1CLKO rise/fall time — 15.00 ns 73 L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC 20.00 — ns setup time) MPC866/MPC859 Hardware Specifications, Rev. 2 54 Freescale Semiconductor

CPM Electrical Characteristics Table21. SI Timing (continued) All Frequencies Num Characteristic Unit Min Max 74 L1CLK edge to L1RSYNC, L1TSYNC, invalid 35.00 — ns (SYNC hold time) 75 L1RSYNC, L1TSYNC rise/fall time — 15.00 ns 76 L1RXD valid to L1CLK edge (L1RXD setup time) 17.00 — ns 77 L1CLK edge to L1RXD invalid (L1RXD hold time) 13.00 — ns 78 L1CLK edge to L1ST(1–4) valid 4 10.00 45.00 ns 78A L1SYNC valid to L1ST(1–4) valid 10.00 45.00 ns 79 L1CLK edge to L1ST(1–4) invalid 10.00 45.00 ns 80 L1CLK edge to L1TXD valid 10.00 55.00 ns 80A L1TSYNC valid to L1TXD valid 4 10.00 55.00 ns 81 L1CLK edge to L1TXD high impedance 0.00 42.00 ns 82 L1RCLK, L1TCLK frequency (DSC =1) — 16.00 or SYNCCLK/2 MHz 83 L1RCLK, L1TCLK width low (DSC =1) P + 10 — ns 83a L1RCLK, L1TCLK width high (DSC = 1)3 P + 10 — ns 84 L1CLK edge to L1CLKO valid (DSC = 1) — 30.00 ns 85 L1RQ valid before falling edge of L1TSYNC4 1.00 — L1TCLK 86 L1GR setup time2 42.00 — ns 87 L1GR hold time 42.00 — ns 88 L1CLK edge to L1SYNC valid (FSD=00) CNT = — 0.00 ns 0000, BYT = 0, DSC = 0) 1 The ratio SyncCLK/L1RCLK must be greater than 2.5/1. 2 These specs are valid for IDL mode only. 3 Where P = 1/CLKOUT. Thus, for a 25-MHz CLKO1 rate, P = 40 ns. 4 These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 55

CPM Electrical Characteristics L1RCLK (FE=0, CE=0) (Input) 71 70 71a 72 L1RCLK (FE=1, CE=1) (Input) RFSD=1 75 L1RSYNC (Input) 73 74 77 L1RXD BIT0 (Input) 76 78 79 L1ST(4-1) (Output) Figure53. SI Receive Timing Diagram with Normal Clocking (DSC = 0) MPC866/MPC859 Hardware Specifications, Rev. 2 56 Freescale Semiconductor

CPM Electrical Characteristics L1RCLK (FE=1, CE=1) (Input) 72 83a 82 L1RCLK (FE=0, CE=0) (Input) RFSD=1 75 L1RSYNC (Input) 73 74 77 L1RXD BIT0 (Input) 76 78 79 L1ST(4-1) (Output) 84 L1CLKO (Output) Figure54. SI Receive Timing with Double-Speed Clocking (DSC = 1) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 57

CPM Electrical Characteristics L1TCLK (FE=0, CE=0) (Input) 71 70 72 L1TCLK (FE=1, CE=1) (Input) 73 TFSD=0 75 L1TSYNC (Input) 74 80a 81 L1TXD BIT0 (Output) 80 78 79 L1ST(4-1) (Output) Figure55. SI Transmit Timing Diagram (DSC = 0) MPC866/MPC859 Hardware Specifications, Rev. 2 58 Freescale Semiconductor

CPM Electrical Characteristics L1RCLK (FE=0, CE=0) (Input) 72 83a 82 L1RCLK (FE=1, CE=1) (Input) TFSD=0 75 L1RSYNC (Input) 73 74 81 L1TXD BIT0 (Output) 80 78a 79 L1ST(4-1) (Output) 78 84 L1CLKO (Output) Figure56. SI Transmit Timing with Double Speed Clocking (DSC = 1) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 59

CPM Electrical Characteristics M M 0 2 2 2 D D 9 1 0 0 2 2 B B 8 1 1 1 2 2 B B 7 1 2 2 2 2 B B 6 1 3 3 2 2 B B 5 1 4 4 2 2 B B 4 1 5 5 2 2 B B 3 1 26 26 B B 2 1 1 7 8 7 2 2 B B 1 1 A A 0 1 1 1 D D 9 0 0 1 1 B B 8 1 1 1 1 8 B B 7 7 2 2 1 1 B B 6 7 3 3 8 1 1 B B 5 4 4 1 1 B B 2 4 7 1 5 5 71 7 B1 B1 3 6 6 1 1 B B 6 2 4 7 5 6 7 7 7 8 8 1 1 3 B B 7 1 7 7 0 8 1RCLK(Input) RSYNC(Input) L1TXDOutput) L1RXD(Input) ST(4-1)Output) L1RQOutput) L1GR(Input) L 1 ( 1( ( L L Figure57. IDL Timing MPC866/MPC859 Hardware Specifications, Rev. 2 60 Freescale Semiconductor

CPM Electrical Characteristics 12.7 SCC in NMSI Mode Electrical Specifications Table22 shows the NMSI external clock timings. Table22. NMSI External Clock Timings All Frequencies Num Characteristic Unit Min Max 100 RCLK1 and TCLK1 width high 1 1/SYNCCLK — ns 101 RCLK1 and TCLK1 width low 1/SYNCCLK +5 — ns 102 RCLK1 and TCLK1 rise/fall time — 15.00 ns 103 TXD1 active delay (from TCLK1 falling edge) 0.00 50.00 ns 104 RTS1 active/inactive delay (from TCLK1 falling edge) 0.00 50.00 ns 105 CTS1 setup time to TCLK1 rising edge 5.00 — ns 106 RXD1 setup time to RCLK1 rising edge 5.00 — ns 107 RXD1 hold time from RCLK1 rising edge 2 5.00 — ns 108 CD1 setup time to RCLK1 rising edge 5.00 — ns 1 The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2.25/1. 2 Also applies to CD and CTS hold time when they are used as an external sync signal. Table23 shows the NMSI internal clock timings. Table23. NMSI Internal Clock Timings All Frequencies Num Characteristic Unit Min Max 100 RCLK1 and TCLK1 frequency 1 0.00 SYNCCLK/3 MHz 102 RCLK1 and TCLK1 rise/fall time — — ns 103 TXD1 active delay (from TCLK1 falling edge) 0.00 30.00 ns 104 RTS1 active/inactive delay (from TCLK1 falling edge) 0.00 30.00 ns 105 CTS1 setup time to TCLK1 rising edge 40.00 — ns 106 RXD1 setup time to RCLK1 rising edge 40.00 — ns 107 RXD1 hold time from RCLK1 rising edge 2 0.00 — ns 108 CD1 setup time to RCLK1 rising edge 40.00 — ns 1 The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1. 2 Also applies to CD and CTS hold time when they are used as an external sync signals. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 61

CPM Electrical Characteristics Figure58 through Figure60 show the NMSI timings. RCLK1 102 102 101 106 100 RxD1 (Input) 107 108 CD1 (Input) 107 CD1 (SYNC Input) Figure58. SCC NMSI Receive Timing Diagram TCLK1 102 102 101 100 TxD1 (Output) 103 105 RTS1 (Output) 104 104 CTS1 (Input) 107 CTS1 (SYNC Input) Figure59. SCC NMSI Transmit Timing Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 62 Freescale Semiconductor

CPM Electrical Characteristics TCLK1 102 102 101 100 TxD1 (Output) 103 RTS1 (Output) 104 107 104 105 CTS1 (Echo Input) Figure60. HDLC Bus Timing Diagram 12.8 Ethernet Electrical Specifications Table24 shows the Ethernet timings as shown in Figure61 through Figure65. Table24. Ethernet Timing All Frequencies Num Characteristic Unit Min Max 120 CLSN width high 40 — ns 121 RCLK1 rise/fall time — 15 ns 122 RCLK1 width low 40 — ns 123 RCLK1 clock period 1 80 120 ns 124 RXD1 setup time 20 — ns 125 RXD1 hold time 5 — ns 126 RENA active delay (from RCLK1 rising edge of the last data bit) 10 — ns 127 RENA width low 100 — ns 128 TCLK1 rise/fall time — 15 ns 129 TCLK1 width low 40 — ns 130 TCLK1 clock period 1 99 101 ns 131 TXD1 active delay (from TCLK1 rising edge) — 50 ns 132 TXD1 inactive delay (from TCLK1 rising edge) 6.5 50 ns 133 TENA active delay (from TCLK1 rising edge) 10 50 ns MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 63

CPM Electrical Characteristics Table24. Ethernet Timing (continued) All Frequencies Num Characteristic Unit Min Max 134 TENA inactive delay (from TCLK1 rising edge) 10 50 ns 135 RSTRT active delay (from TCLK1 falling edge) 10 50 ns 136 RSTRT inactive delay (from TCLK1 falling edge) 10 50 ns 137 REJECT width low 1 — CLK 138 CLKO1 low to SDACK asserted 2 — 20 ns 139 CLKO1 low to SDACK negated 2 — 20 ns 1 The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2/1. 2 SDACK is asserted whenever the SDMA writes the incoming frame DA into memory. CLSN(CTS1) (Input) 120 Figure61. Ethernet Collision Timing Diagram RCLK1 121 121 124 123 RxD1 Last Bit (Input) 125 126 127 RENA(CD1) (Input) Figure62. Ethernet Receive Timing Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 64 Freescale Semiconductor

CPM Electrical Characteristics TCLK1 128 128 129 131 121 TxD1 (Output) 132 133 134 TENA(RTS1) (Input) RENA(CD1) (Input) Notes: 1. Transmit clock invert (TCI) bit in GSMR is set. 2. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the CSL bit is set in the buffer descriptor at the end of the frame transmission. Figure63. Ethernet Transmit Timing Diagram RCLK1 RxD1 0 1 1 BIT1 BIT2 (Input) Start Frame Delimiter 136 125 RSTRT (Output) Figure64. CAM Interface Receive Start Timing Diagram REJECT 137 Figure65. CAM Interface REJECT Timing Diagram 12.9 SMC Transparent AC Electrical Specifications Table25 shows the SMC transparent timings as shown in Figure66. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 65

CPM Electrical Characteristics Table25. SMC Transparent Timing All Frequencies Num Characteristic Unit Min Max 150 SMCLK clock period 1 100 — ns 151 SMCLK width low 50 — ns 151A SMCLK width high 50 — ns 152 SMCLK rise/fall time — 15 ns 153 SMTXD active delay (from SMCLK falling edge) 10 50 ns 154 SMRXD/SMSYNC setup time 20 — ns 155 RXD1/SMSYNC hold time 5 — ns 1 Sync CLK must be at least twice as fast as SMCLK. SMCLK 152 152 151 151A 150 SMTXD (Output) NOTE 1 154 153 155 SMSYNC 154 155 SMRXD (Input) NOTE: 1. This delay is equal to an integer number of character-length clocks. Figure66. SMC Transparent Timing Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 66 Freescale Semiconductor

CPM Electrical Characteristics 12.10SPI Master AC Electrical Specifications Table26 shows the SPI master timings as shown in Figure67 and Figure68. Table26. SPI Master Timing All Frequencies Num Characteristic Unit Min Max 160 MASTER cycle time 4 1024 t cyc 161 MASTER clock (SCK) high or low time 2 512 t cyc 162 MASTER data setup time (inputs) 15 — ns 163 Master data hold time (inputs) 0 — ns 164 Master data valid (after SCK edge) — 10 ns 165 Master data hold time (outputs) 0 — ns 166 Rise time output — 15 ns 167 Fall time output — 15 ns SPICLK (CI=0) (Output) 161 167 166 161 160 SPICLK (CI=1) (Output) 163 167 162 166 SPIMISO msb Data lsb msb (Input) 165 164 167 166 SPIMOSI msb Data lsb msb (Output) Figure67. SPI Master (CP = 0) Timing Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 67

CPM Electrical Characteristics SPICLK (CI=0) (Output) 161 167 166 161 160 SPICLK (CI=1) (Output) 163 167 162 166 SPIMISO msb Data lsb msb (Input) 165 164 167 166 SPIMOSI msb Data lsb msb (Output) Figure68. SPI Master (CP = 1) Timing Diagram 12.11SPI Slave AC Electrical Specifications Table27 shows the SPI slave timings as shown in Figure69 and Figure70. Table27. SPI Slave Timing All Frequencies Num Characteristic Unit Min Max 170 Slave cycle time 2 — t cyc 171 Slave enable lead time 15 — ns 172 Slave enable lag time 15 — ns 173 Slave clock (SPICLK) high or low time 1 — t cyc 174 Slave sequential transfer delay (does not require deselect) 1 — t cyc 175 Slave data setup time (inputs) 20 — ns 176 Slave data hold time (inputs) 20 — ns 177 Slave access time — 50 ns MPC866/MPC859 Hardware Specifications, Rev. 2 68 Freescale Semiconductor

CPM Electrical Characteristics SPISEL (Input) 172 171 174 SPICLK (CI=0) (Input) 173 182 181 173 170 SPICLK (CI=1) (Input) 177 181 182 180 178 SPIMISO msb Data lsb Undef msb (Output) 175 179 176 181 182 SPIMOSI msb Data lsb msb (Input) Figure69. SPI Slave (CP = 0) Timing Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 69

CPM Electrical Characteristics SPISEL (Input) 172 171 170 174 SPICLK (CI=0) (Input) 173 182 181 173 181 SPICLK (CI=1) (Input) 177 182 180 178 SPIMISO msb Undef msb Data lsb (Output) 175 179 176 181 182 SPIMOSI msb msb Data lsb (Input) Figure70. SPI Slave (CP = 1) Timing Diagram 12.12I2C AC Electrical Specifications MPC866/MPC859 Hardware Specifications, Rev. 2 70 Freescale Semiconductor

CPM Electrical Characteristics Table28 shows the I2C (SCL < 100 kHz) timings. Table28. I2C Timing (SCL < 100 kHz) All Frequencies Num Characteristic Unit Min Max 200 SCL clock frequency (slave) 0 100 kHz 200 SCL clock frequency (master) 1 1.5 100 kHz 202 Bus free time between transmissions 4.7 — μs 203 Low period of SCL 4.7 — μs 204 High period of SCL 4.0 — μs 205 Start condition setup time 4.7 — μs 206 Start condition hold time 4.0 — μs 207 Data hold time 0 — μs 208 Data setup time 250 — ns 209 SDL/SCL rise time — 1 μs 210 SDL/SCL fall time — 300 ns 211 Stop condition setup time 4.7 — μs 1 SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2). The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1. Table29 shows the I2C (SCL > 100 kHz) timings. Table29. I2C Timing (SCL > 100 kHz) All Frequencies Num Characteristic Expression Unit Min Max 200 SCL clock frequency (slave) fSCL 0 BRGCLK/48 Hz 200 SCL clock frequency (master) 1 fSCL BRGCLK/16512 BRGCLK/48 Hz 202 Bus free time between transmissions — 1/(2.2 * fSCL) — s 203 Low period of SCL — 1/(2.2 * fSCL) — s 204 High period of SCL — 1/(2.2 * fSCL) — s 205 Start condition setup time — 1/(2.2 * fSCL) — s 206 Start condition hold time — 1/(2.2 * fSCL) — s 207 Data hold time — 0 — s 208 Data setup time — 1/(40 * fSCL) — s 209 SDL/SCL rise time — — 1/(10 * fSCL) s 210 SDL/SCL fall time — — 1/(33 * fSCL) s 211 Stop condition setup time — 1/2(2.2 * fSCL) — s 1 SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2). The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 71

UTOPIA AC Electrical Specifications Figure71 shows the I2C bus timing. SDA 202 203 204 205 207 208 SCL 206 209 210 211 Figure71. I2C Bus Timing Diagram 13 UTOPIA AC Electrical Specifications Table30 through Table32 show the AC electrical specifications for the UTOPIA interface. Table30. UTOPIA Master (Muxed Mode) Electrical Specifications Num Signal Characteristic Direction Min Max Unit U1 UtpClk rise/fall time (Internal clock option) Output — 4 ns Duty cycle 50 50 % Frequency — 33 MHz U2 UTPB, SOC, RxEnb, TxEnb, RxAddr, and TxAddr-active Output 2 16 ns delay (and PHREQ and PHSEL active delay in MPHY mode) U3 UTPB, SOC, Rxclav and Txclav setup time Input 4 — ns U4 UTPB, SOC, Rxclav and Txclav hold time Input 1 — ns Table31. UTOPIA Master (Split Bus Mode) Electrical Specifications Num Signal Characteristic Direction Min Max Unit U1 UtpClk rise/fall time (Internal clock option) Output — 4 ns Duty cycle 50 50 % Frequency — 33 MHz U2 UTPB, SOC, RxEnb, TxEnb, RxAddr and TxAddr active Output 2 16 ns delay (PHREQ and PHSEL active delay in MPHY mode) U3 UTPB_Aux, SOC_Aux, Rxclav, and Txclav setup time Input 4 — ns U4 UTPB_Aux, SOC_Aux, Rxclav, and Txclav hold time Input 1 — ns MPC866/MPC859 Hardware Specifications, Rev. 2 72 Freescale Semiconductor

UTOPIA AC Electrical Specifications Table32. UTOPIA Slave (Split Bus Mode) Electrical Specifications Num Signal Characteristic Direction Min Max Unit U1 UtpClk rise/fall time (external clock option) Input — 4 ns Duty cycle 40 60 % Frequency — 33 MHz U2 UTPB, SOC, Rxclav and Txclav active delay Output 2 16 ns U3 UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr Input 4 — ns setup time U4 UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr Input 1 — ns hold time Figure72 shows signal timings during UTOPIA receive operations. U1 U1 UtpClk U2 PHREQn U33 U44 RxClav HighZ at MPHY HighZ at MPHY U22 RxEnb UTPB U33 U44 SOC Figure72. UTOPIA Receive Timing MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 73

FEC Electrical Characteristics Figure73 shows signal timings during UTOPIA transmit operations. U11 U1 UtpClk U52 PHSELn U33 U44 TxClav HighZ at MPHY High-Z at MPHY U22 TxEnb UTPB U52 SOC Figure73. UTOPIA Transmit Timing 14 FEC Electrical Characteristics This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 or 3.3 V. 14.1 MII Receive Signal Timing (MII_RXD [3:0], MII_RX_DV, MII_RX_ER, MII_RX_CLK) The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency – 1%. Table33 shows the timings for MII receive signal. Table33. MII Receive Signal Timing Num Characteristic Min Max Unit M1 MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup 5 — ns M2 MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold 5 — ns M3 MII_RX_CLK pulse width high 35% 65% MII_RX_CLK period M4 MII_RX_CLK pulse width low 35% 65% MII_RX_CLK period Figure74 shows the timings for MII receive signal. MPC866/MPC859 Hardware Specifications, Rev. 2 74 Freescale Semiconductor

FEC Electrical Characteristics M3 MII_RX_CLK (input) M4 MII_RXD[3:0] (inputs) MII_RX_DV MII_RX_ER M1 M2 Figure74. MII Receive Signal Timing Diagram 14.2 MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN, MII_TX_ER, MII_TX_CLK) The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25MHz+1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK frequency - 1%. Table34 shows information on the MII transmit signal timing. Table34. MII Transmit Signal Timing Num Characteristic Min Max Unit M5 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER 5 — ns invalid M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER — 25 — valid M7 MII_TX_CLK pulse width high 35% 65% MII_TX_CLK period M8 MII_TX_CLK pulse width low 35% 65% MII_TX_CLK period MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 75

FEC Electrical Characteristics Figure75 shows the MII transmit signal timing diagram. M7 MII_TX_CLK (input) M5 M8 MII_TXD[3:0] (outputs) MII_TX_EN MII_TX_ER M6 Figure75. MII Transmit Signal Timing Diagram 14.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL) Table35 shows the timing for on the MII async inputs signal. Table35. MII Async Inputs Signal Timing Num Characteristic Min Max Unit M9 MII_CRS, MII_COL minimum pulse width 1.5 — MII_TX_CLK period Figure76 shows the MII asynchronous inputs signal timing diagram. MII_CRS, MII_COL M9 Figure76. MII Async Inputs Timing Diagram 14.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC) Table36 shows the timing for the MII serial management channel signal. The FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation. Table36. MII Serial Management Channel Timing Num Characteristic Min Max Unit M10 MII_MDC falling edge to MII_MDIO output invalid (minimum 0 — ns propagation delay) M11 MII_MDC falling edge to MII_MDIO output valid (maximum — 25 ns propagation delay) M12 MII_MDIO (input) to MII_MDC rising edge setup 10 — ns MPC866/MPC859 Hardware Specifications, Rev. 2 76 Freescale Semiconductor

FEC Electrical Characteristics Table36. MII Serial Management Channel Timing Num Characteristic Min Max Unit M13 MII_MDIO (input) to MII_MDC rising edge hold 0 — ns M14 MII_MDC pulse width high 40% 60% MII_MDC period M15 MII_MDC pulse width low 40% 60% MII_MDC period Figure77 shows the MII serial management channel timing diagram. M14 MM15 MII_MDC (output) M10 MII_MDIO (output) M11 MII_MDIO (input) M12 M13 Figure77. MII Serial Management Channel Timing Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 77

Mechanical Data and Ordering Information 15 Mechanical Data and Ordering Information Table37 shows information on the MPC866/859 derivative devices. Table37. MPC866/859 Derivatives Number Cache Size Ethernet Multi-Channel Device of ATM Support Support HDLC Support SCCs 1 Instruction Data MPC866T 4 10/100 Mbps Yes Yes 4 Kbyte 4 Kbytes MPC866P 4 10/100 Mbps Yes Yes 16 Kbyte 8 Kbytes MPC859T 1 (SCC1) 10/100 Mbps Yes Yes 4 Kbyte 4 Kbytes MPC859DSL 1 (SCC1) 10/100 Mbps No Up to 4 addresses 4 Kbyte 4 Kbytes 1 Serial communications controller (SCC). Table38 identifies the packages and operating frequencies orderable for the MPC866/859 derivative devices. Table38. MPC866/859 Package/Frequency Orderable Package Type Temperature (Tj) Frequency (MHz) Order Number Plastic ball grid array 0° to 95°C 50 MPC859DSLZP50A (ZP suffix) 66 MPC859DSLZP66A Non lead free 100 MPC859PZP100A MPC859TZP100A MPC866PZP100A MPC866TZP100A 133 MPC859PZP133A MPC859TZP133A MPC866PZP133A MPC866TZP133A Plastic ball grid array –40° to 100°C 50 MPC859DSLCZP50A (CZP suffix) 66 MPC859DSLCZP66A Non lead free 100 MPC859PCZP100A MPC859TCZP100A MPC866PCZP100A MPC866TCZP100A MPC866/MPC859 Hardware Specifications, Rev. 2 78 Freescale Semiconductor

Mechanical Data and Ordering Information Table38. MPC866/859 Package/Frequency Orderable (continued) Plastic ball grid array 0° to 95°C 50 MPC859DSLVR50A (VR suffix) 66 MPC859DSLVR66A Lead free 100 MPC859PVR100A MPC859TVR100A MPC866PVR100A MPC866TVR100A 133 MPC859PVR133A MPC859TVR133A MPC866PVR133A MPC866TVR133A Plastic ball grid array –40° to 100°C 50 MPC859DSLCVR50A (CVR suffix) 66 MPC859DSLCVR66A Lead free 100 MPC859PCVR100A MPC859TCVR100A MPC866PCVR100A MPC866TCVR100A MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 79

Mechanical Data and Ordering Information 15.1 Pin Assignments Figure78 shows the top view pinout of the PBGA package. For additional information, see the MPC866 PowerQUICC Family User’s Manual. NOTE: This is the top view of the device. W PD10 PD8 PD3 IRQ7 D0 D4 D1 D2 D3 D5 VDDL D6 D7 D29 DP2 CLKOUT IPA3 V PD14 PD13 PD9 PD6 M_Tx_ENIRQ0 D13 D27 D10 D14 D18 D20 D24 D28 DP1 DP3 DP0 N/CVSSSYN1 U PA0 PB14 PD15 PD4 PD5 IRQ1 D8 D23 D11 D16 D19 D21 D26 D30 IPA5 IPA4 IPA2 N/C VSSSYN T PA1 PC5 PC4 PD11 PD7 VDDHD12 D17 D9 D15 D22 D25 D31 IPA6 IPA0 IPA1 IPA7 N/C VDDSYN R PC6 PA2 PB15 PD12 VDDH VDDH WAIT_B WAIT_A PORESET VDDL P PA4 PB17 PA3 VDDL GND GND VDDLRSTCONF SRESETXTAL N PB19 PA5 PB18 PB16 HRESETTEXPEXTCLK EXTAL M PA7 PC8 PA6 PC7 MODCK2BADDR28 BADDR29 VDDL L PB22 PC9 PA8 PB20 OP0 AS OP1MODCK1 K PC10 PA9 PB23 PB21 GND BADDR30IPB6 ALEA IRQ4 J PC11 PB24 PA10 PB25 IPB5 IPB1 IPB2 ALEB H VDDL M_MDIO TDI TCK M_COL IRQ2 IPB0 IPB7 G TRST TMS TDO PA11 BR IRQ6 IPB4 IPB3 GND GND F PB26 PC12 PA12 VDDL VDDL TS IRQ3 BURST VDDH VDDH E PB27 PC13 PA13 PB29 CS3 BI BG BB D PB28 PC14 PA14 PC15 A8 N/C N/C A15 A19 A25 A18 BSA0 GPLA0 N/C CS6 CS2 GPLA5 BDIP TEA C PB30 PA15 PB31 A3 A9 A12 A16 A20 A24 A26 TSIZ1 BSA1 WE0 GPLA1GPLA3 CS7 CS0 TA GPLA4 B A0 A1 A4 A6 A10 A13 A17 A21 A23 A22 TSIZ0 BSA3 M_CRS WE2 GPLA2 CS5 CE1A WR GPLB4 A A2 A5 A7 A11 A14 A27 A29 A30 A28 A31 VDDL BSA2 WE1 WE3 CS4 CE2A CS1 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure78. Pinout of the PBGA Package MPC866/MPC859 Hardware Specifications, Rev. 2 80 Freescale Semiconductor

Mechanical Data and Ordering Information Table39 contains a list of the MPC866 input and output signals and shows multiplexing and pin assignments. Table39. Pin Assignments Name Pin Number Type A[0:31] B19, B18, A18, C16, B17, A17, B16, A16, D15, C15, B15, A15, Bidirectional C14, B14, A14, D12, C13, B13, D9, D11, C12, B12, B10, B11, C11, Three-state D10, C10, A13, A10, A12, A11, A9 TSIZ0 B9 Bidirectional REG Three-state TSIZ1 C9 Bidirectional Three-state RD/WR B2 Bidirectional Three-state BURST F1 Bidirectional Three-state BDIP D2 Output GPL_B5 TS F3 Bidirectional Active Pull-up TA C2 Bidirectional Active Pull-up TEA D1 Open-drain BI E3 Bidirectional Active Pull-up IRQ2 H3 Bidirectional RSV Three-state IRQ4 K1 Bidirectional KR Three-state RETRY SPKROUT CR F2 Input IRQ3 D[0:31] W14, W12, W11, W10, W13, W9, W7, W6, U13, T11, V11, U11, Bidirectional T13, V13, V10, T10, U10, T12, V9, U9, V8, U8, T9, U12, V7, T8, Three-state U7, V12, V6, W5, U6, T7 DP0 V3 Bidirectional IRQ3 Three-state DP1 V5 Bidirectional IRQ4 Three-state DP2 W4 Bidirectional IRQ5 Three-state DP3 V4 Bidirectional IRQ6 Three-state MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 81

Mechanical Data and Ordering Information Table39. Pin Assignments (continued) Name Pin Number Type BR G4 Bidirectional BG E2 Bidirectional BB E1 Bidirectional Active Pull-up FRZ G3 Bidirectional IRQ6 IRQ0 V14 Input IRQ1 U14 Input M_TX_CLK W15 Input IRQ7 CS[0:5] C3, A2, D4, E4, A4, B4 Output CS6 D5 Output CE1_B CS7 C4 Output CE2_B WE0 C7 Output BS_B0 IORD WE1 A6 Output BS_B1 IOWR WE2 B6 Output BS_B2 PCOE WE3 A5 Output BS_B3 PCWE BS_A[0:3] D8, C8, A7, B8 Output GPL_A0 D7 Output GPL_B0 OE C6 Output GPL_A1 GPL_B1 GPL_A[2:3] B5, C5 Output GPL_B[2:3] CS[2–3] UPWAITA C1 Bidirectional GPL_A4 MPC866/MPC859 Hardware Specifications, Rev. 2 82 Freescale Semiconductor

Mechanical Data and Ordering Information Table39. Pin Assignments (continued) Name Pin Number Type UPWAITB B1 Bidirectional GPL_B4 GPL_A5 D3 Output PORESET R2 Input RSTCONF P3 Input HRESET N4 Open-drain SRESET P2 Open-drain XTAL P1 Analog Output EXTAL N1 Analog Input (3.3V only) CLKOUT W3 Output EXTCLK N2 Input (3.3V only) TEXP N3 Output ALE_A K2 Output MII-TXD1 CE1_A B3 Output MII-TXD2 CE2_A A3 Output MII-TXD3 WAIT_A R3 Input SOC_Split2 WAIT_B R4 Input IP_A0 T5 Input UTPB_Split02 MII-RXD3 IP_A1 T4 Input UTPB_Split12 MII-RXD2 IP_A2 U3 Input IOIS16_A UTPB_Split22 MII-RXD1 IP_A3 W2 Input UTPB_Split32 MII-RXD0 IP_A4 U4 Input UTPB_Split42 MII-RXCLK MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 83

Mechanical Data and Ordering Information Table39. Pin Assignments (continued) Name Pin Number Type IP_A5 U5 Input UTPB_Split52 MII-RXERR IP_A6 T6 Input UTPB_Split62 MII-TXERR IP_A7 T3 Input UTPB_Split72 MII-RXDV ALE_B J1 Bidirectional DSCK/AT1 Three-state IP_B[0:1] H2, J3 Bidirectional IWP[0:1] VFLS[0:1] IP_B2 J2 Bidirectional IOIS16_B Three-state AT2 IP_B3 G1 Bidirectional IWP2 VF2 IP_B4 G2 Bidirectional LWP0 VF0 IP_B5 J4 Bidirectional LWP1 VF1 IP_B6 K3 Bidirectional DSDI Three-state AT0 IP_B7 H1 Bidirectional PTR Three-state AT3 OP0 L4 Bidirectional MII-TXD0 UtpClk_Split2 OP1 L2 Output OP2 L1 Bidirectional MODCK1 STS MPC866/MPC859 Hardware Specifications, Rev. 2 84 Freescale Semiconductor

Mechanical Data and Ordering Information Table39. Pin Assignments (continued) Name Pin Number Type OP3 M4 Bidirectional MODCK2 DSDO BADDR30 K4 Output REG BADDR[28:29] M3, M2 Output AS L3 Input PA15 C18 Bidirectional RXD1 RXD4 PA14 D17 Bidirectional TXD1 (Optional: Open-drain) TXD4 PA13 E17 Bidirectional RXD2 PA12 F17 Bidirectional TXD2 (Optional: Open-drain) PA11 G16 Bidirectional L1TXDB (Optional: Open-drain) RXD3 PA10 J17 Bidirectional L1RXDB (Optional: Open-drain) TXD3 PA9 K18 Bidirectional L1TXDA (Optional: Open-drain) RXD4 PA8 L17 Bidirectional L1RXDA (Optional: Open-drain) TXD4 PA7 M19 Bidirectional CLK1 L1RCLKA BRGO1 TIN1 PA6 M17 Bidirectional CLK2 TOUT1 MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 85

Mechanical Data and Ordering Information Table39. Pin Assignments (continued) Name Pin Number Type PA5 N18 Bidirectional CLK3 L1TCLKA BRGO2 TIN2 PA4 P19 Bidirectional CLK4 TOUT2 PA3 P17 Bidirectional CLK5 BRGO3 TIN3 PA2 R18 Bidirectional CLK6 TOUT3 L1RCLKB PA1 T19 Bidirectional CLK7 BRGO4 TIN4 PA0 U19 Bidirectional CLK8 TOUT4 L1TCLKB PB31 C17 Bidirectional SPISEL (Optional: Open-drain) REJECT1 PB30 C19 Bidirectional SPICLK (Optional: Open-drain) RSTRT2 PB29 E16 Bidirectional SPIMOSI (Optional: Open-drain) PB28 D19 Bidirectional SPIMISO (Optional: Open-drain) BRGO4 PB27 E19 Bidirectional I2CSDA (Optional: Open-drain) BRGO1 PB26 F19 Bidirectional I2CSCL (Optional: Open-drain) BRGO2 MPC866/MPC859 Hardware Specifications, Rev. 2 86 Freescale Semiconductor

Mechanical Data and Ordering Information Table39. Pin Assignments (continued) Name Pin Number Type PB25 J16 Bidirectional RXADDR32 (Optional: Open-drain) SMTXD1 PB24 J18 Bidirectional TXADDR32 (Optional: Open-drain) SMRXD1 PB23 K17 Bidirectional TXADDR22 (Optional: Open-drain) SDACK1 SMSYN1 PB22 L19 Bidirectional TXADDR42 (Optional: Open-drain) SDACK2 SMSYN2 PB21 K16 Bidirectional SMTXD2 (Optional: Open-drain) L1CLKOB PHSEL1 1 TXADDR1 2 PB20 L16 Bidirectional SMRXD2 (Optional: Open-drain) L1CLKOA PHSEL01 TXADDR02 PB19 N19 Bidirectional RTS1 (Optional: Open-drain) L1ST1 PB18 N17 Bidirectional RXADDR42 (Optional: Open-drain) RTS2 L1ST2 PB17 P18 Bidirectional L1RQb (Optional: Open-drain) L1ST3 RTS3 PHREQ11 RXADDR12 MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 87

Mechanical Data and Ordering Information Table39. Pin Assignments (continued) Name Pin Number Type PB16 N16 Bidirectional L1RQa (Optional: Open-drain) L1ST4 RTS4 PHREQ01 RXADDR02 PB15 R17 Bidirectional BRGO3 TxClav RxClav PB14 U18 Bidirectional RXADDR22 RSTRT1 PC15 D16 Bidirectional DREQ0 RTS1 L1ST1 RxClav TxClav PC14 D18 Bidirectional DREQ1 RTS2 L1ST2 PC13 E18 Bidirectional L1RQb L1ST3 RTS3 PC12 F18 Bidirectional L1RQa L1ST4 RTS4 PC11 J19 Bidirectional CTS1 PC10 K19 Bidirectional CD1 TGATE1 PC9 L18 Bidirectional CTS2 PC8 M18 Bidirectional CD2 TGATE2 MPC866/MPC859 Hardware Specifications, Rev. 2 88 Freescale Semiconductor

Mechanical Data and Ordering Information Table39. Pin Assignments (continued) Name Pin Number Type PC7 M16 Bidirectional CTS3 L1TSYNCB SDACK2 PC6 R19 Bidirectional CD3 L1RSYNCB PC5 T18 Bidirectional CTS4 L1TSYNCA SDACK1 PC4 T17 Bidirectional CD4 L1RSYNCA PD15 U17 Bidirectional L1TSYNCA MII-RXD3 UTPB0 PD14 V19 Bidirectional L1RSYNCA MII-RXD2 UTPB1 PD13 V18 Bidirectional L1TSYNCB MII-RXD1 UTPB2 PD12 R16 Bidirectional L1RSYNCB MII-MDC UTPB3 PD11 T16 Bidirectional RXD3 MII-TXERR RXENB PD10 W18 Bidirectional TXD3 MII-RXD0 TXENB MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 89

Mechanical Data and Ordering Information Table39. Pin Assignments (continued) Name Pin Number Type PD9 V17 Bidirectional RXD4 MII-TXD0 UTPCLK PD8 W17 Bidirectional TXD4 MII-MDC MII-RXCLK PD7 T15 Bidirectional RTS3 MII-RXERR UTPB4 PD6 V16 Bidirectional RTS4 MII-RXDV UTPB5 PD5 U15 Bidirectional REJECT2 MII-TXD3 UTPB6 PD4 U16 Bidirectional REJECT3 MII-TXD2 UTPB7 PD3 W16 Bidirectional REJECT4 MII-TXD1 SOC TMS G18 Input TDI H17 Input DSDI TCK H16 Input DSCK TRST G19 Input TDO G17 Output DSDO MII_CRS B7 Input MII_MDIO H18 Bidirectional MII_TXEN V15 Output MPC866/MPC859 Hardware Specifications, Rev. 2 90 Freescale Semiconductor

Mechanical Data and Ordering Information Table39. Pin Assignments (continued) Name Pin Number Type MII_COL H4 Input VSSSYN1 V1 PLL analog VDD and GND VSSSYN U1 Power VDDSYN T1 Power GND F6, F7, F8, F9, F10, F11, F12, F13, F14, G6, G7, G8, G9, G10, Power G11, G12, G13, G14, H6, H7, H8, H9, H10, H11, H12, H13, H14, J6, J7, J8, J9, J10, J11, J12, J13, J14, K6, K7, K8, K9, K10, K11, K12, K13, K14, L6, L7, L8, L9, L10, L11, L12, L13, L14, M6, M7, M8, M9, M10, M11, M12, M13, M14, N6, N7, N8, N9, N10, N11, N12, N13, N14, P6, P7, P8, P9, P10, P11, P12, P13, P14 VDDL A8, M1, W8, H19, F4, F16, P4, P16, R1 Power VDDH E5, E6, E7, E8, E9, E10, E11, E12, E13, E14, E15, F5, F15, G5, Power G15, H5, H15, J5, J15, K5, K15, L5, L15, M5, M15, N5, N15, P5, P15, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, T14 N/C D6, D13, D14, U2, V2, T2 No-connect 1 Classic SAR mode only 2 ESAR mode only MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 91

Mechanical Data and Ordering Information 15.2 Mechanical Dimensions of the PBGA Package For more information on the printed-circuit board layout of the PBGA package, including thermal via design and suggested pad layout, please refer to Plastic Ball Grid Array Application Note (order number: AN1231/D) available from your local Freescale sales office. Figure79 shows the mechanical dimensions of the PBGA package. Note: Solder sphere composition for MPC866XZP, MPC859PZP, MPC859DSLZP, and MPC859TZP is 62%Sn 36%Pb 2%Ag Figure79. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC866/MPC859 Hardware Specifications, Rev. 2 92 Freescale Semiconductor

Document Revision History 16 Document Revision History Table40 lists significant changes between revisions of this document. Table40. Document Revision History Revision Date Substantive Changes Number 0 5/2002 Initial revision 1 11/2002 Added the 5-V tolerant pins, new package dimensions, and other changes. 1.1 4/2003 Added the Spec. B1d and changed spec. B1a. Added the Note Solder sphere composition for MPC866XZP, MPC859DSLZP, and MPC859TZP is 62%Sn 36%Pb 2%Ag to Figure 15-79. 1.2 4/2003 Added the MPC859P. 1.3 5/2003 Changed the SPI Master Timing Specs. 162 and 164. 1.4 7-8/2003 (cid:129) Added TxClav and RxClav to PB15 and PC15. Changed B28a through B28d and B29b to show that TRLX can be 0 or 1. (cid:129) Added nontechnical reformatting. 1.5 3/14/2005 (cid:129) Updated document template. 2 2/10/2006 (cid:129) Updated orderable parts table. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 93

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