Freescale Semiconductor, Inc. Product Brief MPC565PB/D Rev. 3, 2/2003 MPC565/MPC566 Product Brief This document provides an overview of the MPC565/MPC566 microcontrollers, including a . block diagram showing the major modular components, sections that list the major features, . . and differences between the MPC565/MPC566 and the MPC555. The MPC565 and MPC566 c devices are members of the Motorola MPC500 RISC Microcontroller family. The parts herein n will be referred to only as MPC565 unless specific parts need to be referenced. I , Table1. MPC565/MPC566 Features r o Device Flash Code Compression t c MPC565 1 Mbyte Code compression not supported u MPC566 1 Mbyte Code compression supported d n o 1 Introduction c mi The MPC565 device offers the following features: e • PowerPC™ core with a floating point unit (FPU) and a burst buffer controller (BBC) S (cid:127) Unified system integration unit (USIU), a flexible memory controller, and improved e interrupt controller l (cid:127) 1 Mbyte of Flash memory (UC3F) a c — Typical endurance of 100,000 write/erase cycles @ 25ºC s — Typical data retention of 100 years @ 25ºC e (cid:127) 36 Kbytes of static RAM (two CALRAM modules) e r — 8 Kbytes of normal access or overlay access (sixteen 512-byte regions) F — 4 Kbytes in CALRAM A, 4 Kbytes in CALRAM B (cid:127) Three time processor units (TPU3) — TPU3 A and TPU3 B are connected to DPTRAM AB (6 Kbytes) — TPU3 C is connected to DPTRAM C (4 Kbytes) (cid:127) A 22-timer channel modular I/O system (MIOS14) — Same as MIOS1 plus a real-time clock sub-module (MRTCSM), 4 counter sub-modules (MCSM), and 4 PWM sub-modules (MPWMSM) (cid:127) Three TouCAN modules (TouCAN_A, TouCAN_B, and TouCAN_C) (cid:127) Two enhanced queued analog to digital converters (QADC64E A, QADC64E B) with analog multiplexers (AMUX) for 40 total analog channels. These modules are configured so each module can access all 40 of the analog inputs to the part. For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc. Block Diagram (cid:127) Two queued serial multi-channel modules (QSMCM A, QSMCM B), each of which contains a queued serial peripheral interface (QSPI) and two serial controller interfaces (SCI/UART) (cid:127) -40 °C – 125°C ambient temperature, -40°C – 85°C for suffix C devices, -55°C– 125°C for suffixA devices (cid:127) Debug features: — A J1850 (DLCMD2) communications module — A Nexus debug port (class 3) – IEEE-ISTO 5001-1999 — JTAG and background debug mode (BDM) (cid:127) Packaging and Electrical 1.1 Block Diagram . . Figure1 is a block diagram of the MPC565. . c n I JTAG 512 Kbytes 512 Kbytes Flash Flash , r Burst o Buffer t Controller 2 c U-Bus u DECRAM E-Bus d (4Kbytes) USIU n PowerPC READI o Core 4 Kbyte CALRAM B c + 4 Kbyte Overlay i FP m e S L2U e L-Bus l 32 Kbyte CALRAM A a c 28 Kbytes SRAM s No Overlay e 4 Kbyte Overlay e r F QADC64E QADC64E UIMB QSMCM QSMCM DLCMD2 w/AMUX w/AMUX I/F IMB3 6 Kbytes 4 Kbytes Tou Tou Tou TPU3 TPU3 TPU3 MIOS14 DPTRAM DPTRAM CAN CAN CAN Figure1. MPC565 Block Diagram 2 MPC565/MPC566 Product Brief MOTOROLA For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc. Detailed Feature List 1.2 Detailed Feature List The MPC565 key features are explained in the following sections. 1.2.1 High Performance CPU System (cid:127) Fully static design (cid:127) Four major power saving modes — On, doze, sleep, deep-sleep and power-down 1.2.2 RISC MCU Central Processing Unit (RCPU) (cid:127) High-performance core — PowerPC single issue integer core . . — Precise exception model . c — Floating point n I — Code compression (MPC566 only) , – Compression reduces usage of internal or external Flash memory r o – Compression optimized for automotive (non-cached) applications t c – New compression scheme decreases code size to 40% –50% of source u d 1.2.3 MPC500 System Interface (USIU) n o (cid:127) MPC500 system interface (USIU, BBC, L2U) c (cid:127) Periodic interrupt timer, bus monitor, clocks, decrementer and time base i m (cid:127) Clock synthesizer, power management, reset controller e (cid:127) External bus tolerates 5-V inputs, provides 2.6-V outputs S (cid:127) Enhanced interrupt controller supports a separate interrupt vector for up to eight external and 40 e internal interrupts al (cid:127) IEEE 1149.1 JTAG test access port c (cid:127) Bus supports multiple master designs s e (cid:127) USIU supports dual-mapping of Flash to move part of internal Flash memory to external bus for e development r (cid:127) External bus, supporting non-wraparound burst for instruction fetches, with up to 8 instructions F per memory cycle 1.2.4 Burst Buffer Controller (BBC) Module (cid:127) Exception vector table relocation features allow exception table to be relocated to following locations: — 0x0000 0000 - 0x0000 1FFF (normal MPC500 exception table location) — 0x0001 0000 - 0x0001 1FFF (0 + 64 Kbytes; second page of internal Flash) — Second internal Flash module — Internal SRAM — 0x0FFF_0100 (external memory space; normal MPC500 exception table location) MOTOROLA MPC565/MPC566 Product Brief 3 For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc. Detailed Feature List 1.2.5 Flexible Memory Protection Unit (cid:127) Flexible memory protection units in BBC (IMPU) and L2U (DMPU) (cid:127) Default attributes available in one global entry (cid:127) Attribute support for speculative accesses 1.2.6 Memory Controller (cid:127) Flexible chip selects via memory controller (cid:127) 24-bit address and 32-bit data buses (cid:127) 4- to 16-Mbyte (data) or 4-Gbyte (instruction) region size support (cid:127) Four-beat transfer bursts, two-clock minimum bus transactions (cid:127) Use with SRAM, EPROM, Flash and other peripherals . . (cid:127) Byte selects or write enables . c (cid:127) 32-bit address decodes with bit masks n (cid:127) Four instruction regions I , (cid:127) Four data regions r o 1.2.7 1 Mbyte of CDR3 Flash EEPROM Memory (UC3F) t c u (cid:127) 1 Mbyte Flash d — Two UC3F modules, 512 Kbytes each n (cid:127) Page mode read o c (cid:127) Block (64-Kbyte) erasable mi (cid:127) External 4.75- to 5.25-V VPP program and erase power supply e (cid:127) Typical endurance of 100,000 write/erase cycles @ 25ºC S (cid:127) Typical data retention of 100 years @ 25ºC e l 1.2.8 36-Kbyte Static RAM (CALRAM) a c (cid:127) 36-Kbyte static calibration RAM s — Composed of 4-Kbyte and 32-Kbyte CALRAM modules e e (cid:127) Fast access: one clock r (cid:127) Keep-alive power F (cid:127) Soft defect detection (SDD) (cid:127) 4 Kbyte calibration (overlay) RAM per module (8 Kbytes total) (cid:127) Eight 512-byte overlay regions per module (16 regions total) 1.2.9 General Purpose I/O Support (GPIO) (cid:127) General-purpose I/O support (cid:127) Address (24) and data (32) pins can be used as GPIO in single-chip mode (cid:127) 16 GPIO in MIOS14 (cid:127) Many peripheral pins can be used as GPIO when not used as primary functions (cid:127) 5-V outputs with slew rate control 4 MPC565/MPC566 Product Brief MOTOROLA For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc. Detailed Feature List 1.2.10 Debug Features (cid:127) Extensive system debug support (cid:127) On-chip watchpoints and breakpoints (cid:127) Program flow tracking (cid:127) Background debug mode (BDM) 1.2.10.1 Nexus Debug Port (Class 3) (cid:127) Nexus/IEEE – ISTO 5001-1999 debug port (Class 3) (cid:127) Nine- or 16-pin interface 1.2.10.2 Message Data Link Controller (DLCMD2) Module . (cid:127) Two pins muxed with QSMCMB pins. Muxing controlled by QSMCMB PCS3 pin assignment . . register c n (cid:127) SAE J1850 Class B data communications network interface compatible and ISO compatible for I low-speed (<125 Kbps) serial data communications in automotive applications , r (cid:127) 10.4 Kbps variable pulse width (VPW) bit format o t (cid:127) Digital noise filter, collision detection c (cid:127) Hardware cyclical redundancy check (CRC) generation and checking u d (cid:127) Block mode receive and transmit supported n (cid:127) 4x receive mode supported (41.6 Kbps) o c (cid:127) Digital loopback mode i (cid:127) In-frame response (IFR) types 0, 1, 2, and 3 supported m e (cid:127) Dedicated register for symbol timing adjustments S (cid:127) Inter-module bus 3 (IMB3) slave interface e (cid:127) Power-saving IMB3 stop mode with automatic wakeup on network activity al (cid:127) Power-saving IMB3 CLOCKDIS mode c (cid:127) Debug mode available through IMB3 FREEZE signal or user controllable SOFT_FRZ bit s e (cid:127) Polling and IMB3 interrupt generation with vector lookup available e r 1.2.11 Integrated I/O System F (cid:127) True 5-V I/O 1.2.11.1 Time Processor Units (TPU3) (cid:127) Three time processing units (TPU3) — 16 channels each (cid:127) Each TPU3 is a microcoded timer subsystem (cid:127) One 6-Kbyte and one 4-Kbyte dual-port TPU RAM (DPTRAM), one (6-Kbyte) shared by two TPU3 modules for TPU microcode and the 4-Kbyte dedicated to the third TPU3 for microcode. MOTOROLA MPC565/MPC566 Product Brief 5 For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc. Detailed Feature List 1.2.11.2 22-Channel Modular I/O System (MIOS14) (cid:127) 22-channel MIOS timer (MIOS14) (cid:127) Six modulus counter submodules (MCSM) — Four additional MCSM submodules compared to MIOS1 (cid:127) 10 double action submodules (DASM). (cid:127) 12 dedicated PWM submodules (PWMSM) — Four additional PWM submodules compared to MIOS1 (shared with MIOS GPIO pins) (cid:127) MIOS real-time clock submodule (MRTCSM) provides low power clock/counter — Requires external 32-KHz crystal — Uses four pins: two for 32-KHz crystal, two for power/ground. 1.2.12 Two Enhanced Queued Analog-to-Digital Converter . . . Modules (QADC64E) c n (cid:127) Two enhanced queued analog to digital converters (QADC64E A, QADC64E B) with AMUXes I for 40 total analog channels. , r (cid:127) 10 bit A/D converter with internal sample/hold o t — Typical conversion time is 4 µs (250-Kbyte samples/sec) c — Two conversion command queues of variable length u d (cid:127) Automated queue modes initiated by: n — External edge trigger/level gate o — Software command c i — Periodic/interval timer, assignable to both queue 1 and 2 m (cid:127) 64 result registers in each QADC64E module e — Output data is right or left justified, signed or unsigned S (cid:127) Synchronized clock mode allows both QADC64Es to see the same conversion clock. This allows e the two modules to look like one large QADC with four queues. l a (cid:127) Conversions alternate reference (ALTREF) pin. This pin can be connected to a different reference c voltage s e e 1.2.13 Three CAN 2.0B Controller (TouCAN) Modules r F (cid:127) Three TouCAN modules (TouCAN_A, TouCAN_B, and TouCAN_C) (cid:127) 16 message buffers each, programmable I/O modes (cid:127) Maskable interrupts (cid:127) Programmable loopback for self-test operation (cid:127) Independent of the transmission medium (external transceiver is assumed) (cid:127) Open network architecture, multimaster concept (cid:127) High immunity to EMI (cid:127) Short latency time for high-priority messages (cid:127) Low power sleep mode, with programmable wake up on bus activity (cid:127) TouCAN_C pins shared with MIOS14 GPIO pins 6 MPC565/MPC566 Product Brief MOTOROLA For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc. Detailed Feature List 1.2.14 Queued Serial Multi-Channel Modules (QSMCM) (cid:127) Two queued serial modules with one queued-SPI and two SCI each (QSMCM_A, QSMCM_B) — QSMCM_A matches full MPC555 QSMCM functionality — QSMCM_B has pins muxed with DLCMD2 module – Two pins are muxed with DLCMD2 (J1850) transmit and receive pins (B_PCS3_J1850_TX and B_RXD2_J1850_RX) – QSMCM B vs J1850 mux control provided by QPAPCS3 bit in QSMCM pin assignment register (PQSPAR) (cid:127) Queued-SPI — Provides full-duplex communication port for peripheral expansion or interprocessor communication — Up to 32 preprogrammed transfers, reducing overhead . . — Synchronous serial interface with baud rate of up to system clock / 4 . c — Four programmable peripheral-select pins support up to 16 devices n I — Special wrap-around mode allows continuous sampling of a serial peripheral for efficient , interfacing to serial analog-to-digital (A/D) converters r o (cid:127) SCI t — UART mode provides NRZ format and half- or full-duplex interface c u — 16 register receive buffer and 16 register transmit buffer on one SCI d — Advanced error detection, and optional parity generation and detection n — Word length programmable as 8 or 9 bits o c — Separate transmitter and receiver enable bits, and double buffering of data mi — Wake-up functions allow the CPU to run uninterrupted until either a true idle line is detected, or a new address byte is received e S 1.2.15 Electrical Specifications and Packaging e l (cid:127) 40 MHz operation (56 MHz operation is optional for the MPC566) a c (cid:127) -40 °C – 125°C ambient temperature, -40°C – 85°C for suffix C device, -55°C– 125°C for suffix A s devices e (cid:127) 2.6 V ± 0.1 V external bus e r — External bus is compatible with external memory devices operating from 2.5 V to 3.4 V. F — Extended voltage range (2.7 – 3.4 V) degrades data drive timing by 1.1 ns on date writes. (cid:127) 2.6 ± 0.1 V internal logic (cid:127) 5-V I/O (5.0 ± 0.25 V) (cid:127) Available in package or bumped die (cid:127) Plastic ball grid array (PBGA) packaging – 388 ball PBGA – 27 mm x 27 mm body size (cid:127) 1.0 mm ball pitch MOTOROLA MPC565/MPC566 Product Brief 7 For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc. MPC565 Optional Features 1.3 MPC565 Optional Features The following features of the MPC565 are optional features and may not appear in certain configurations: (cid:127) 56-MHz operation (40-MHz is default) (cid:127) MPC566 supports code compression 2 Differences between the MPC565 and the MPC555 The MPC565 is an enhanced version of the MPC555. Most functional features of the MPC555 are unchanged on the MPC565. Table2 shows the high level differences. Table2. Differences Between Modules of the MPC555 and the MPC565 Module MPC555 MPC565 . . . CPU Core No Change c BBC BBC BBC with improved code compression 1 n I L2U No Change , r SRAM 26-Kbytes 36-Kbyte CALRAM with overlay features o Flash 448-Kbyte CMF 1-Mbyte UC3F t c (new programming, etc.) u USIU USIU USIU with enhanced interrupt controller d n JTAG No Change o READI None New Module c UIMB No Change i m QADC64 2 QADC64 (16 channels on each QADC 2 QADC64E w/AMUXes e for 32 total channels) ( 40 channels accessible from either S QADC64E) e QSMCM (1) No Change (2) l DLCMD2 (J1850) None 1 a c MIOS MIOS1 MIOS14: MIOS1 with real-time clock s (MRTCSM), 4 more PWMSMs and 4 more e MCSMs e TouCAN (2) No Change (3) r F TPU3 (2) No Change (3) DPTRAM (6-Kbytes) No Change (6-Kbytes, 4-Kbytes) Power Supplies — 40 MHz with two power supplies: 56 MHz with two power supplies: nominal 3.3-V to 5.0-V power supplies 5.0-V I/O, 2.6-V internal logic 1 Available on some options. 8 MPC565/MPC566 Product Brief MOTOROLA For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc. Additional MPC565 Differences 2.1 Additional MPC565 Differences The following are additional differences between the MPC555 and the MPC565. (cid:127) SPI (MISO, MOSI, and SCK) pin drive. — MPC565 provides 21-ns rise/fall with 200-pf load using CMOS (20%/70%) levels (cid:127) GPIO on MODCK1 pin outputs only 2.6 V — MODCK1 pin is in keep-alive power section with no 5-V rail available — 5.0-V compatibility modes – Input is 5-V friendly – 2.6-V output has less slew rate control – 2.6-V: VOH = 2.3 V (cid:127) Power supplies for external bus pins . . — QVDDL is quiet supply to hold non-switching outputs quiet even when noisy supply . c (NVDDL) sags n — QVDDL supplies pre-drive and other pad logic I — NVDDL only supplies final PMOS driver stage , r o — QVDDL and NVDDL shorted on customer board after filtering t (cid:127) Pull-up and pull-down changes during PORESET and HRESET c u — All 2.6-V/5-V pads (external bus: address/data/control) pull down at reset d — All 5-V pads pull up at reset n — Additional control granularity in the PDMCR register o c (cid:127) No pull-ups on QSMCM SCI receive pads i (cid:127) A_RXD1_QGPI1, A_RXD2_QGPI2, B_RXD1_QGPI1 pins do not have weak pull-up during m reset or any other time e (cid:127) CLKOUT has 3 drive strength options S — Better matches drive to requirements to reduce EMI e l — 25, 50, 100 pf instead of 45 and 90 pf a c (cid:127) Change reset value of ENGCLK to maximum divide (crystal/128) s — For a 4-MHz crystal, this is 31.25 KHz e – ENGCLK is selectable between 2.6 V and 5 V e (cid:127) A daisy chain between UC3F modules allows either module to provide the reset configuration r F word (RCW) (cid:127) Censorship operation — A RCW bit controls whether or not the entire UC3F can be erased while censorship is violated (cid:127) BBC SPRs (PPC regs) access in two clocks instead of one clock (cid:127) CALRAM internal protection block size is 8 Kbytes — Instead of 4 Kbytes on MPC555 LRAM (cid:127) CALRAM causes machine check exception instead of data storage interrupt (DSI) exception in certain cases — For non-overlay CPU core accesses, a DSI exception is taken — For overlay accesses and any non-core access (slave mode), a machine check exception is taken MOTOROLA MPC565/MPC566 Product Brief 9 For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc. Additional MPC565 Differences (cid:127) CALRAM causes DSI exception only if the data relocation (DR) bit in the core machine state register, MSR[DR], is set. — L2U on MPC555 already followed this protocol, but the LRAM did not. Now all L-bus peripherals follow this protocol. — The MSR[DR] bit is described in the reference manual for more information. (cid:127) Four additional PRDS control bits were added to the USIU to allow more granularity of PRDS control on a part (cid:127) BBC includes a 4-Kbyte DECRAM that can be used if compression is not used or is not available. 3 SRAM Keep-Alive Power Behavior The SRAM has three keep-alive power pins (VDDSRAM1, VDDSRAM2, and VDDSRAM3). These pins provide keep-alive power to the SRAM arrays in the CALRAM modules and the DPTRAM modules. . . . c The VDDSRAM1 pin powers the 32-Kbyte CALRAM A during keep-alive while power is off to the n MPC565 (except for the keep-alive power supplies). CALRAM A keeps all of its 32 Kbytes powered during I power down. , r The VDDSRAM2 pin powers the 4-Kbyte CALRAM B module. The VDDSRAM3 pin powers the o DPTRAM modules during keep-alive as well as during normal operation. The CALRAM modules only t c power their arrays from the VDDSRAM pins during keep-alive. During normal operation, they are powered u by the normal internal VDD of the part. d The DPTRAM modules (6 Kbytes and 4 Kbytes) and the 4-Kbyte DECRAM in the BBC module power their n arrays via the VDDSRAM3 pin during keep-alive and are supplied by VDD during normal operation. o c i 4 MPC565 Memory Map m e The internal memory map is organized as a single 4-Mbyte block. This is shown in Figure3. This block can S be moved to one of eight different locations. The internal memory space is divided into the following e sections: al (cid:127) Flash memory (1 Mbyte) — U-bus memory c (cid:127) Static RAM memory (36 Kbytes CALRAM) — L-bus memory s e (cid:127) Control registers and IMB3 modules (64 Kbytes), partitioned as e — USIU and flash control registers r F — UIMB interface and IMB3 modules — CALRAM and READI control registers (L-bus control register space) The internal memory block can reside in one of eight possible 4-Mbyte memory spaces. These eight locations are the first eight 4-Mbyte memory blocks starting with address 0x0000 0000, as shown in Figure2. There is a user programmable register in the USIU to configure the internal memory map to one of the eight possible locations. Programmability of internal memory map location allows multiple chip system. The IMB3 address space block in Figure3 shows memory allocation for IMB3 modules. It does not show the actual memory space required for individual modules. All modules are mapped to the low address, numerically, of the memory allocated for that module in the IMB3 address space. 10 MPC565/MPC566 Product Brief MOTOROLA For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc. Additional MPC565 Differences Internal 4-Mbyte Memory Block 0x0000 0000 (Resides in one of eight locations) 0x003F FFFF 0x0040 0000 0x007F FFFF 0x0080 0000 0x00BF FFFF 0x00C0 0000 0x00FF FFFF 0x0100 0000 . . . 0x013F FFFF c 0x0140 0000 n I 0x017F FFFF , 0x0180 0000 r o t 0x01BF FFFF c 0x01C0 0000 u d 0x01FF FFFF n o c i m e S e l a c 0xFFFF FFFF s e Figure2. Memory Map e r F MOTOROLA MPC565/MPC566 Product Brief 11 For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc. Additional MPC565 Differences 0x00 0000 UC3F_A Flash USIU Control Registers 0x2F C000 512 Kbytes 0x07 FFFF UC3F_A Control 0x2F C800 0x08 0000 UC3F_B Flash (64 bytes) 0x0F FFFF 512 Kbytes UC3F_B Control 0x2F C840 (64 bytes) 0x2F C87F 0x10 0000 Reserved for Flash 0x2F 7FFF (2,016 Kbytes) DPTRAM_AB 0x30 0000 Ox2F 8000 DECRAM Registers (64 bytes) 0x2F 8FFF 4 Kbytes DPTRAM_C 0x30 0040 Registers (64 bytes) 0x2F 9000 Reserved 0x2F 9FFF DLCMD2 (16 bytes) 0x30 0080 0x2F A000 BBC Control Registers Reserved (3952 bytes) 0x30 0090 . 0x2F BFFF 8 Kbytes . c. 0x2F C000 USIU & Flash Control DPTRAM_C (4 Kbytes) 0x30 1000 0x2F FFFF 16 Kbytes n 0x30 0000 DPTRAM_AB (6 Kbytes) 0x30 2000 I , UIMB I/F & IMB Reserved (2 Kbytes) 0x30 3800 r Modules o 32 Kbytes TPU3_A (1 Kbytes) 0x30 4000 t c 0x30 7FFF TPU3_B (1 Kbytes) 0x30 4400 u 0x30 8000 Reserved for IMB d QADC64_A (1 Kbytes) 0x30 4800 0x37 FFFF 480 Kbytes n o 0x38 0000 CALRAM/ QADC64_B (1 Kbytes) 0x30 4C00 c Readi Control QSMCM_A (1 Kbytes) 0x30 5000 mi 0x38 00FF 256 bytes 0x38 0100 Reserved (L-bus Control) QSMCM_B (1 Kbytes) 0x30 5400 e 0x38 3FFF ~32 Kbytes S 0x38 4000 Reserved (1 Kbytes) 0x30 5800 e l Reserved (L-bus Mem) TPU3_C (1 Kbytes) 0x30 5C00 a 444 Kbytes 0x30 6000 c MIOS14 (4 Kbytes) s 0x3F 6FFF e 0x3F 7000 All 4-Kbytes can be TOUCAN_A (1 Kbytes) 0x30 7000 Overlay Section e 0x3F 7FFF CALRAM_B (4 Kbyte) TOUCAN_B (1 Kbytes) 0x30 7400 r F 0x3F 8000 TOUCAN_C (1 Kbytes) 0x30 7800 Reserved (896 bytes) 0x30 7900 CALRAM_A (32 Kbyte) 0x30 7F80 UIMB Control Registers (128 bytes) 0x30 7FFF 0x3F FFFF 4-Kbyte Overlay Section Figure3. Internal Memory Block 12 MPC565/MPC566 Product Brief MOTOROLA For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc. Additional MPC565 Differences 5 MPC565 Pinout Diagram Figure4 shows the pinout for the MPC565. A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 23242526 VSSB_TPUCH10B_TPUCH12B_TPUCH14 VSSVDDB_TPUCH7B_TPUCH13 VSSVDDB_TPUCH8B_TPUCH15 VSSVDDB_TPUCH2B_TPUCH0 VDDB_T2CLKMPWM17B_TPUCH1 MPWM5_MPWM18MDA11MDA13MPIO32B6 MDA12MDA27MDA28MDA29 MDA30MDA31MPWM0MPWM1 MPWM20_MPWM3MPWM2MPWM16MPIO32B11 MPWM21_C_CNTX0_MDA15MDA14MPIO32B12MPIO32B13 C_CNRX0_MPIO32B15MPWM19VF0_MPIO32B14MPIO32B0 MPWM4_VFLS0_VF1_VF2_MPIO32B5MPIO32B3MPIO32B2MPIO32B1 B_PCS1_VFLS1_B_PCS0_SSVDDHQGPIO1MPIO32B4__BQGPIO0 B_MISO_B_PCS3_B_MOSI_B_ECKJ1850_TXQGPIO5QGPIO4 B_PCS2_B_SCK_B_TXD1_B_TXD2_QGPIO2QGPO2QGPO1QGPIO6 A_SCK_A_MISO_B_RXD2_A_TXD1_QGPIO6QGPIO4J1850_RXQGPO1(C3F_CLK) A_RXD1_A_PCS3_A_PCS2_A_MOSI_QPI1QGPIO3QGPIO2QGPIO5(C3F_IOUT)(C3F_SUP1) A_PCS0_A_RXD2_SS_B_A_TXD2_B_RXD1_QPI2QGPO2QGPI1QGPIO0 (C3F_SUP2) A_PCS1_NVDDLVFLASHPULLSELQGPIO1 VDDFEXTCLKA_CNTXOKAPWR A_CNRXOVSSFXTALPORESET_B_TRST_B IRQ6_B_RSTCONF_HRESET_BEXTALMODCK2B_TEXP IRQ7_B_QVDDLSRESET_BVSSSYNMODCK3 IRQ5_B_XFCVSSQVDDLSGPIOC5_MODCK1 VDDVSSQVDDLVDDSYN NCVDDVSSQVDDL 23242526 2122 A_TPUCH1B_TPUCH5 B_TPUCH3B_TPUCH6 B_TPUCH4B_TPUCH11 NVDDLB_TPUCH9 VDDVSS CLKOUTVDD BDIP_BNC EPEEENGCLK_BUCLK 2122 .. 20 A_TPUCH14 A_T2CLK A_TPUCH15 A_TPUCH0 VDDH B0EPEE TS_B TA_B 20 nc. 19 A_TPUCH10 A_TPUCH11 A_TPUCH12 A_TPUCH13 BI_B_STS_B TSIZ0 BURST_B TSIZ1 19 escale Semiconductor, I 6789101112131415161718 AN53_A_AN72_B_AN80AN48_A_VDDAVSSAAN76_B_AN67_B_AN65_B_QVDDLA_TPUCH2A_TPUCH4A_TPUCH6MA1_PQA1MA0_PQA0PQB3PQB1PQB4PQA4 AN52_A_AN73_B_AN81AN49_A_AN56_A_AN58_A_AN77_B_AN69_B_AN66_B_QVDDLETRIG2A_TPUCH5A_TPUCH8MA0_PQA0MA1_PQA1PQB5PQB2PQB5PQA4PQA6PQA5 AN54_A_AN46_ANY_AN83AN50_A_AN57_A_AN79_B_AN75_B_AN71_B_AN70_B_QVDDLETRIG1B_CNRX0A_TPUCH9MA2_PQA2A_PQB2PQA7PQA3PQB7PQB6PQB6PQA5 AN74_B_AN47_ANZ_AN86AN82AN51_A_AN55_A_AN59_A_AN78_B_AN68_B_QVDDLVDDHA_TPUCH3A_TPUCH7MA2_PQA2A_PQB3PQA7PQA6PQB4PQA3PQB7 NOTE: This is a top down view of the balls. VSSVSSVSSVSSVSSVSS VSSVSSVSSVSSVSSVSS VSSVSSVSSVSSVSSVSS VSSVSSVSSVSSVSSVSS VSSVSSVSSVSSVSSVSS VSSVSSVSSVSSVSSVSS DATA_DATA_DATA_DATA_DATA_SGPIOC7_VDDHNVDDLWE_B_AT1NVDDLCS3_BNVDDLNVDDLSGPIOD29SGPIOD27SGPIOD24SGPIOD22SGPIOD20IRQOUT_B_LWP0 DATA_DATA_DATA_DATA_DATA_DATA_DATA_DATA_IRQ2_B_CR_B_SIRQ4_B_AT2TEA_BCS1_BWE_B_AT2GPIOC2 SGPIOD31SGPIOD30SGPIOD28SGPIOD26SGPIOD25SGPIOD23SGPIOD21SGPIOD19_SGPIOC4 IRQ3_B_KR_BDATA_SGPIOD1DATA_DATA_DATA_DATA_DATA_DATA_SGPIOD9_RETRY_B_BB_B_OE_BCS0_BRD_WR_BWE_B_AT01SGPIOD13SGPIOD15SGPIOD17SGPIOC3VF2_IWP3SGPIOD7SGPIOD5 DATA_SGPIOD1DATA_SGPIOD1DATA_DATA_SGPIOD1DATA_IRQ1_B_RSV_B_BG_B_VF0IRQ0_B_DATA_DATA_BR_B_VF1CS2_BWE_B_AT302SGPIOD146SGPIOD18SGPIOC1_LWP1SGPIOC0SGPIOD8SGPIOD6_IWP2 6789101112131415161718 re 5 AN84 AN85 AN87 VDDH VDD NC DATA_SGPIOD3 DATA_SGPIOD4 5 F 4 VRL ALTREF AN45_ANX_A_PQB1 VDD VSS NVDDL VDDSRAM3 C_T2CLK C_TPUCH13 C_TPUCH4 MCKI MSEI_B MDO_5_MPIO32B9 MDO_0 IWP1_VFLS1 SGPIOC6_FRZ_PTR_B NVDDL ADDR_SGPIOA10 ADDR_SGPIOA12 ADDR_SGPIOA14 ADDR_SGPIOA30 QVDDL VSS VDD DATA_SGPIOD1 DATA_SGPIOD2 4 123 VDDAN64_B_VRHPQB0 AN44_ANW_VSSVDDA_PQB0 VDDRTCVSSVDD EXTAL32VSSVDDSRAM2 XTAL32B_CNTX0VDDSRAM1 VSSRTCC_TPUCH14C_TPUCH15 C_TPUCH10C_TPUCH11C_TPUCH12 C_TPUCH9C_TPUCH7C_TPUCH8 C_TPUCH6C_TPUCH5C_TPUCH3 C_TPUCH2C_TPUCH1C_TPUCH0 MDI_0TCK_DSCKMDI_1 TDI_DSDIEVTI_BRSTI_B MDO_4_MDO_6_TMSMPIO32B10MPIO32B8 MDO_7_JCOMPMCKOMPIO32B7 MDO_1TDO_DSDOMDO_2 MDO_3MSEO_BIWP0_VFLS0 ADDR_ADDR_ADDR_SGPIOA16SGPIOA17SGPIOA8 ADDR_ADDR_ADDR_SGPIOA18SGPIOA19SGPIOA9 ADDR_ADDR_ADDR_SGPIOA20SGPIOA21SGPIOA11 ADDR_ADDR_ADDR_SGPIOA22SGPIOA23SGPIOA13 ADDR_ADDR_ADDR_SGPIOA24SGPIOA25SGPIOA15 ADDR_ADDR_ADDR_SGPIOA26SGPIOA27SGPIOA31 ADDR_NCQVDDLSGPIOA28 ADDR_QVDDLVSSSGPIOA29 QVDDLVSSVDD VSSVDDDATA_SGPIOD0 123 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Figure4. MPC565 Pinout Diagram MOTOROLA MPC565/MPC566 Product Brief 13 For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc. Additional MPC565 Differences THIS PAGE INTENTIONALLY LEFT BLANK . . . c n I , r o t c u d n o c i m e S e l a c s e e r F 14 MPC565/MPC566 Product Brief MOTOROLA For More Information On This Product, Go to: www.freescale.com

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