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M M 7 4 February 2008 H C 7 4 A MM74HC74A — Dual D-Type Flip-Flop with Preset and Clear D u a l D Features General Description - T y ■ Typical propagation delay: 20ns The MM74HC74A utilizes advanced silicon-gate CMOS p ■ Wide power supply range: 2V–6V technology to achieve operating speeds similar to the e equivalent LS-TTL part. It possesses the high noise F ■ Low quiescent current: 40µA maximum (74HC Series) l immunity and low power consumption of standard ip ■ Low input current: 1µA maximum CMOS integrated circuits, along with the ability to drive -F ■ Fanout of 10 LS-TTL loads 10 LS-TTL loads. lo p This flip-flop has independent data, preset, clear, and w clock inputs and Q and Q outputs. The logic level i t present at the data input is transferred to the output dur- h ing the positive-going transition of the clock pulse. Pre- P r set and clear are independent of the clock and e s accomplished by a low level at the appropriate input. e t The 74HC logic family is functionally and pinout compat- a n ible with the standard 74LS logic family. All inputs are d protected from damage due to static discharge by inter- C nal diode clamps to V and ground. l CC e a r Ordering Information Package Order Number Number Package Description MM74HC74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC74ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC74AMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com MM74HC74A Rev. 1.3.0

M M Connection Diagram Truth Table 7 4 Pin Assignments for DIP, SOIC, SOP and TSSOP Inputs Outputs H C PR CLR CLK D Q Q 7 4 A L H X X H L — H L X X L H D L L X X H(1) H(1) u a H H ↑ H H L l D H H ↑ L L H - T H H L X Q0 Q0 y p e Note: F Q0 = the level of Q before the indicated input conditions lip were established. -F l 1. This configuration is nonstable; that is, it will not persist o p when preset and clear inputs return to their inactive w (HIGH) level. i t Top View h P r Logic Diagram e s e t a n d C l e a r ©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com MM74HC74A Rev. 1.3.0 2

M M Absolute Maximum Ratings(2) 7 4 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be H operable above the recommended operating conditions and stressing the parts to these levels is not recommended. C 7 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. 4 The absolute maximum ratings are stress ratings only. A — Symbol Parameter Rating D V Supply Voltage –0.5 to +7.0V u CC a VIN DC Input Voltage –1.5 to VCC+1.5V l D V DC Output Voltage –0.5 to V +0.5V - OUT CC T y IIK, IOK Clamp Diode Current ±20mA p e I DC Output Current, per pin ±25mA OUT F l ICC DC VCC or GND Current, per pin ±50mA ip - T Storage Temperature Range –65°C to +150°C F STG l o PD Power Dissipation p Note 3 600mW w i S.O. Package only 500mW th T Lead Temperature (Soldering 10 seconds) 260°C P L r e Notes: s e 2. Unless otherwise specified all voltages are referenced to ground. t a 3. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C. n d C l e a Recommended Operating Conditions r The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Units V Supply Voltage 2 6 V CC V , V DC Input or Output Voltage 0 V V IN OUT CC T Operating Temperature Range –40 +85 °C A t , t Input Rise or Fall Times r f VCC = 2.0V 1000 ns V = 4.5V 500 ns CC V = 6.0V 400 ns CC ©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com MM74HC74A Rev. 1.3.0 3

M DC Electrical Characteristics(4) M 7 4 T = –40°C T = –55°C H A A C TA = 25°C to 85°C to 125°C 7 4 Symbol Parameter V (V) Conditions Typ. Guaranteed Limits Units A CC — V Minimum HIGH 2.0 1.5 1.5 1.5 V IH Level Input D 4.5 3.15 3.15 3.15 Voltage u 6.0 4.2 4.2 4.2 a l D V Maximum LOW 2.0 0.5 0.5 0.5 V IL - Level Input T 4.5 1.35 1.35 1.35 y Voltage p 6.0 1.8 1.8 1.8 e F VOH Minimum HIGH 2.0 VIN = VIH or VIL, 2.0 1.9 1.9 1.9 V li Level Output |I | ≤ 20µA p 4.5 OUT 4.5 4.4 4.4 4.4 - Voltage F l 6.0 6.0 5.9 5.9 5.9 o p 4.5 V = V or V , 4.3 3.98 3.84 3.7 IN IH IL w |I | ≤ 4.0mA i OUT t h 6.0 V = V or V , 5.2 5.48 5.34 5.2 IN IH IL P |I | ≤ 5.2mA r OUT e VOL Maximum LOW 2.0 VIN = VIH or VIL, 0 0.1 0.1 0.1 V se Level Output 4.5 |IOUT| ≤ 20µA 0 0.1 0.1 0.1 t a Voltage n 6.0 0 0.1 0.1 0.1 d 4.5 V = V or V , 0.2 0.26 0.33 0.4 C IN IH IL l |IOUT| ≤ 4.0mA ea r 6.0 |V = V or V , 0.2 0.26 0.33 0.4 IN IH IL I | ≤ 5.2mA OUT I Maximum Input 6.0 V = V or GND ±0.1 ±1.0 ±1.0 µA IN IN CC Current I Maximum 6.0 V =V or GND, 4.0 40 80 µA CC I N CC Quiescent I = 0µA OUT Supply Current Note: 4. For a power supply of 5V ±10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V OH OL values should be used when designing with this supply. Worst case V and V occur at V = 5.5V and 4.5V IH IL CC respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and I ) occur for CMOS at IH IN CC OZ the higher voltage and so the 6.0V values should be used. ©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com MM74HC74A Rev. 1.3.0 4

M M AC Electrical Characteristics 7 V = 5V, T = 25°C, C = 15pF, t = t = 6ns 4 CC A L r f H C Guaranteed 7 Symbol Parameter Conditions Typ. Limit Units 4 A f Maximum Operating Frequency 72 30 MHz — MAX t , t Maximum Propagation, 10 30 ns D PHL PLH Delay Clock to Q or Q u a l tPHL, tPLH Maximum Propagation, 17 40 ns D Delay Preset or Clear to Q or Q - T y tREM Minimum Removal Time, 6 5 ns p Preset or Clear to Clock e F ts Minimum Setup Time, Data to Clock 10 20 ns lip tH Minimum Hold Time, Clock to Data 0 0 ns -F l t Minimum Pulse Width Clock, Preset or Clear 8 16 ns o W p w i t h P r e s e t a n d C l e a r ©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com MM74HC74A Rev. 1.3.0 5

M M AC Electrical Characteristics 7 C = 50 pF, t = t = 6ns (unless otherwise specified) 4 L r f H C TA = –40°C TA = –55°C 7 T = 25°C to 85°C to 125°C 4 A A Symbol Parameter Conditions V (V) Typ. Guaranteed Limits Units — CC f Maximum Operating 2.0 22 6 5 4 MHz D MAX u Frequency 4.5 72 30 24 20 a l 6.0 94 35 28 24 D - T t , t Maximum Propagation 2.0 34 110 140 165 ns PHL PLH y Delay Clock to Q or Q 4.5 12 22 28 33 pe 6.0 10 19 24 28 F l i p t , t Maximum Propagation 2.0 66 150 190 225 ns PHL PLH - F Delay Preset or Clear 4.5 20 30 38 45 l o to Q or Q p 6.0 16 26 33 38 w t Minimum Removal 2.0 20 50 65 75 ns i REM t h Time, Preset or Clear 4.5 6 10 13 15 P to Clock r 6.0 5 9 11 13 e s t Minimum Setup Time 2.0 35 80 100 120 ns e s t Data to Clock 4.5 10 16 20 24 a n 6.0 8 14 17 20 d C tH Minimum Hold Time 2.0 0 0 0 ns le Clock to Data 4.5 0 0 0 a r 6.0 0 0 0 t Minimum, Pulse Width 2.0 30 80 101 119 ns W Clock, Preset or Clear 4.5 9 16 20 24 6.0 8 14 17 20 t , t Maximum Output 2.0 25 75 95 110 ns TLH THL Rise and Fall Time 4.5V 7 15 19 22 6.0V 6 13 16 19 t, t Maximum Input Rise 2.0 1000 1000 1000 ns r f and Fall Time 4.5 500 500 500 6.0 400 400 400 C Power Dissipation (per flip-flop) 80 pF PD Capacitance(5) C Maximum Input 5 10 10 10 pF IN Capacitance Note: 5. C determines the no load dynamic power consumption, P = C V 2 f + I V , and the no load dynamic PD D PD CC CC CC current consumption, I = C V f + I . S PD CC CC ©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com MM74HC74A Rev. 1.3.0 6

0.65 (cid:24)(cid:17)(cid:19)(cid:19)(cid:147)(cid:19)(cid:17)(cid:20)(cid:19) A 0.43TYP 14 8 B 6.4 (cid:23)(cid:17)(cid:23)(cid:19)(cid:147)(cid:19)(cid:17)(cid:20)(cid:19) 6.10 3.2 1.65 1 7 0.2 C B A PIN1IDENT TOPVIEW ALLLEADTIPS 0.45 RECOMMENDEDLANDPATTERN 1.2MAX SEEDETAILA +0.15 0.90 -0.10 0.20 (cid:19)(cid:17)(cid:20)(cid:19)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) 0.09 ALLLEADTIPS 0.30 0.19 C 0.1 C 0.65 0.13 A B C (cid:20)(cid:21)(cid:17)(cid:19)(cid:19)(cid:131)(cid:3)(cid:55)(cid:50)(cid:51)(cid:3)(cid:9)(cid:3)(cid:37)(cid:50)(cid:55)(cid:55)(cid:50)(cid:48) FRONTVIEW 0.09MIN NOTES: GAGEPLANE A.CONFORMSTOJEDECREGISTRATIONMO-153, VARIATIONAB,REFNOTE6 B.DIMENSIONSAREINMILLIMETERS. 0.25 0.09MIN C.DIMENSIONSAREEXCLUSIVEOFBURRS, (cid:19)(cid:131)(cid:16)(cid:3)(cid:27)(cid:131) (cid:19)(cid:17)(cid:25)(cid:147)(cid:19)(cid:17)(cid:20) MOLDFLASH,ANDTIEBAREXTRUSIONS SEATINGPLANE 1.00 D.DIMENSIONINGANDTOLERANCESPERANSI DETAILA Y14.5M,2009. E.LANDPATTERNSTANDARD:SOP65P640X110-14M. F.DRAWINGFILENAME:MKT-MTC14rev7.

None

8.75 A 8.50 7.62 14 0.65 8 14 8 B 4.00 6.00 5.60 3.80 1.70 1 7 PIN #1 1.27 0.51 1 7 IDENT. 1.27 0.35 (0.33) 0.25 M C B A LAND PATTERN RECOMMENDATION TOP VIEW 1.75 MAX A C 0.25 0.19 1.50 0.10 C 0.25 1.25 0.10 SIDE VIEW FRONT VIEW NOTES: A. CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C B. ALL DIMENSIONS ARE IN MILLIMETERS 0.50 0.25 x 45 C. DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS R0.10 GAGE D. LAND PATTERN STANDARD: PLANE SOIC127P600X145-14M R0.10 E. CONFORMS TO ASME Y14.5M, 2009 0.36 D. DRAWING FILENAME: MKT-M14Arev14 8° 0° 0.90 0.50 SEATING PLANE (1.04) DETAIL A SCALE 16 : 1

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: MM74HC74AMTCX MM74HC74ASJX MM74HC74AM MM74HC74AN MM74HC74AMTC MM74HC74ASJ MM74HC74AMX