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M M 7 4 February 2008 H C 1 6 4 MM74HC164 — 8 8-Bit Serial-in/Parallel-out Shift Register - B i t S Features General Description e r i ■ Typical operating frequency: 50MHz The MM74HC164 utilizes advanced silicon-gate CMOS a l ■ Typical propagation delay: 19ns (clock to Q) technology. It has the high noise immunity and low con- -in ■ Wide operating supply voltage range: 2V to 6V sumption of standard CMOS integrated circuits. It also /P offers speeds comparable to low power Schottky a ■ Low input current: 1µA maximum r devices. a ■ Low quiescent supply current: 80µA maximum l l (74HC Series) This 8-bit shift register has gated serial inputs and el ■ Fanout of 10 LS-TTL loads CLEAR. Each register bit is a D-type master/slave flip- -o flop. Inputs A & B permit complete control over the u t incoming data. A LOW at either or both inputs inhibits S entry of new data and resets the first flip-flop to the low h i level at the next clock pulse. A high level on one input ft enables the other input which will then determine the R e state of the first flip-flop. Data at the serial inputs may be g changed while the clock is HIGH or LOW, but only infor- is mation meeting the setup and hold time requirements te will be entered. Data is serially shifted in and out of the r 8-bit register during the positive going transition of the clock pulse. Clear is independent of the clock and accomplished by a low level at the CLEAR input. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to V and ground. CC Ordering Information Package Order Number Number Package Description MM74HC164M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC164MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC164N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com MM74HC164 Rev. 1.5.0

M M Connection Diagram Truth Table 7 4 Inputs Outputs H C Clear Clock A B Q Q ... Q 1 A B H 6 4 L X X X L L ... L — H L X X Q Q ... Q AO BO HO 8 H ↑ H H H QAn ... QGn -B H ↑ L X L Q ... Q it A Gn S H ↑ X L L Q ... Q e An Gn r i H = HIGH Level (steady state) a l - L = LOW Level (steady state) in / P X = Irrelevant (any input, including transitions) a r ↑ = Transition from LOW-to-HIGH level. al l e Q , Q , Q = the level of Q , Q , or Q , l AO BO HO A B H - o respectively, before the indicated steady state input u conditions were established. t S Q , Q = The level of Q or Q before the most h An Gn A G Top View recent ↑ transition of the clock; indicated a one-bit shift. ift R e g Logic Diagram is t e r ©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com MM74HC164 Rev. 1.5.0 2

M M Absolute Maximum Ratings(1) 7 4 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be H operable above the recommended operating conditions and stressing the parts to these levels is not recommended. C 1 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. 6 The absolute maximum ratings are stress ratings only. 4 — Symbol Parameter Rating 8 - V Supply Voltage –0.5 to +7.0V B CC i t VIN DC Input Voltage –1.5 to VCC+1.5V S V DC Output Voltage –0.5 to V +0.5V e OUT CC r i a I , I Clamp Diode Current ±20mA IK OK l - i I DC Output Current, per pin ±25mA n OUT / P ICC DC VCC or GND Current, per pin ±50mA a r T Storage Temperature Range –65°C to +150°C a STG l l P Power Dissipation e D l - Note 2 600mW o u S.O. Package only 500mW t S T Lead Temperature (Soldering 10 seconds) 260°C h L i f t Notes: R 1. Unless otherwise specified all voltages are referenced to ground. e g 2. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C. i s t e r Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Units V Supply Voltage 2 6 V CC V , V DC Input or Output Voltage 0 V V IN OUT CC T Operating Temperature Range –40 +85 °C A t , t Input Rise or Fall Times r f VCC = 2.0V 1000 ns V = 4.5V 500 ns CC V = 6.0V 400 ns CC ©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com MM74HC164 Rev. 1.5.0 3

M DC Electrical Characteristics(3) M 7 4 T = –40°C T = –55°C H A A C TA = 25°C to 85°C to 125°C 1 6 Symbol Parameter V (V) Conditions Typ. Guaranteed Limits Units 4 CC — V Minimum HIGH Level 2.0 1.5 1.5 1.5 V IH Input Voltage 8 4.5 3.15 3.15 3.15 - B 6.0 4.2 4.2 4.2 it S VIL Maximum LOW Level 2.0 0.5 0.5 0.5 V e Input Voltage 4.5 1.35 1.35 1.35 ria l 6.0 1.8 1.8 1.8 -i n V Minimum HIGH Level 2.0 V = V or V , 2.0 1.9 1.9 1.9 V /P OH IN IH IL Output Voltage |I | ≤ 20µA a 4.5 OUT 4.5 4.4 4.4 4.4 r a l 6.0 6.0 5.9 5.9 5.9 le l 4.5 VIN = VIH or VIL, 4.2 3.98 3.84 3.7 -o |I | ≤ 4.0mA u OUT t 6.0 V = V or V , 5.7 5.48 5.34 5.2 S IN IH IL h |IOUT| ≤ 5.2mA if t VOL Maximum LOW Level 2.0 VIN = VIH or VIL, 0 0.1 0.1 0.1 V R Output Voltage |I | ≤ 20µA e 4.5 OUT 0 0.1 0.1 0.1 g i 6.0 0 0.1 0.1 0.1 s t e 4.5 V = V or V , 0.2 0.26 0.33 0.4 r IN IH IL |I | ≤ 4.0mA OUT 6.0 V = V or V , 0.2 0.26 0.33 0.4 IN IH IL |I | ≤ 5.2mA OUT I Maximum Input 6.0 V = V or GND ±0.1 ±1.0 ±1.0 µA IN IN CC Current I Maximum Quiescent 6.0 V = V or GND, 8.0 80 160 µA CC IN CC Supply Current I = 0µA OUT Note: 3. For a power supply of 5V ±10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V OH OL values should be used when designing with this supply. Worst case V and V occur at V = 5.5V and 4.5V IH IL CC respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and I ) occur for CMOS at IH IN CC OZ the higher voltage and so the 6.0V values should be used. AC Electrical Characteristics V = 5V, T = 25°C, C = 15pF, t = t = 6ns CC A L r f Guaranteed Symbol Parameter Conditions Typ. Limit Units f Maximum Operating Frequency 30 MHz MAX t , t Maximum Propagation Delay, Clock to 19 30 ns PHL PLH Output t Maximum Propagation Delay, Clear to 23 35 ns PHL Output t Minimum Removal Time, Clear to Clock –2 0 ns REM t Minimum Setup Time, Data to Clock 12 20 ns S t Minimum Hold Time, Clock to Data 1 5 ns H t Minimum Pulse Width, Clear or Clock 10 16 ns W ©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com MM74HC164 Rev. 1.5.0 4

M M AC Electrical Characteristics 7 C = 50pF, t = t = 6ns (unless otherwise specified) 4 L r f H C TA = –40°C TA = –55°C 1 T = 25°C to 85°C to 125°C 6 A 4 Symbol Parameter V (V) Conditions Typ. Guaranteed Limits Units — CC f Maximum Operating 2.0 5 4 3 MHz 8 MAX - Frequency B 4.5 27 21 18 i t 6.0 31 24 20 S e tPHL, tPLH Maximum Propagation 2.0 115 175 218 254 ns ria Delay, Clock to Output l 4.5 13 35 44 51 - i n 6.0 20 30 38 44 / P a tPHL Maximum Propagation 2.0 140 205 256 297 ns r a Delay, Clear to Output 4.5 28 41 51 59 ll e 6.0 24 35 44 51 l- o u t Minimum Removal 2.0 –7 0 0 0 ns REM t Time, Clear to Clock S 4.5 –3 0 0 0 h i 6.0 –2 0 0 0 f t R t Minimum Setup Time, 2.0 25 100 125 150 ns S e Data to Clock 4.5 14 20 25 30 g i s 6.0 12 17 21 25 t e r t Minimum Hold Time, 2.0 –2 5 5 5 ns H Clock to Data 4.5 0 5 5 5 6.0 1 5 5 5 t Minimum Pulse Width 2.0 22 80 100 120 ns W Clear or Clock 4.5 11 16 20 24 6.0 10 14 18 20 t , t Maximum Output 2.0 75 95 110 ns THL TLH Rise and Fall Time 4.5 15 19 22 6.0 13 16 19 t, t Maximum Input 2.0 1000 1000 1000 ns r f Rise and Fall Time 4.5 500 500 500 6.0 400 400 400 C Power Dissipation 5.0 (per package) 150 pF PD Capacitance(4) C Maximum Input 5 10 10 10 pF IN Capacitance Note: 4. C determines the no load dynamic power consumption, P = C V 2 f + I V , and the no load dynamic PD D PD CC CC CC current consumption, I = C V f + I . S PD CC CC ©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com MM74HC164 Rev. 1.5.0 5

0.65 (cid:24)(cid:17)(cid:19)(cid:19)(cid:147)(cid:19)(cid:17)(cid:20)(cid:19) A 0.43TYP 14 8 B 6.4 (cid:23)(cid:17)(cid:23)(cid:19)(cid:147)(cid:19)(cid:17)(cid:20)(cid:19) 6.10 3.2 1.65 1 7 0.2 C B A PIN1IDENT TOPVIEW ALLLEADTIPS 0.45 RECOMMENDEDLANDPATTERN 1.2MAX SEEDETAILA +0.15 0.90 -0.10 0.20 (cid:19)(cid:17)(cid:20)(cid:19)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) 0.09 ALLLEADTIPS 0.30 0.19 C 0.1 C 0.65 0.13 A B C (cid:20)(cid:21)(cid:17)(cid:19)(cid:19)(cid:131)(cid:3)(cid:55)(cid:50)(cid:51)(cid:3)(cid:9)(cid:3)(cid:37)(cid:50)(cid:55)(cid:55)(cid:50)(cid:48) FRONTVIEW 0.09MIN NOTES: GAGEPLANE A.CONFORMSTOJEDECREGISTRATIONMO-153, VARIATIONAB,REFNOTE6 B.DIMENSIONSAREINMILLIMETERS. 0.25 0.09MIN C.DIMENSIONSAREEXCLUSIVEOFBURRS, (cid:19)(cid:131)(cid:16)(cid:3)(cid:27)(cid:131) (cid:19)(cid:17)(cid:25)(cid:147)(cid:19)(cid:17)(cid:20) MOLDFLASH,ANDTIEBAREXTRUSIONS SEATINGPLANE 1.00 D.DIMENSIONINGANDTOLERANCESPERANSI DETAILA Y14.5M,2009. E.LANDPATTERNSTANDARD:SOP65P640X110-14M. F.DRAWINGFILENAME:MKT-MTC14rev7.

8.75 A 8.50 7.62 14 0.65 8 14 8 B 4.00 6.00 5.60 3.80 1.70 1 7 PIN #1 1.27 0.51 1 7 IDENT. 1.27 0.35 (0.33) 0.25 M C B A LAND PATTERN RECOMMENDATION TOP VIEW 1.75 MAX A C 0.25 0.19 1.50 0.10 C 0.25 1.25 0.10 SIDE VIEW FRONT VIEW NOTES: A. CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C B. ALL DIMENSIONS ARE IN MILLIMETERS 0.50 0.25 x 45 C. DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS R0.10 GAGE D. LAND PATTERN STANDARD: PLANE SOIC127P600X145-14M R0.10 E. CONFORMS TO ASME Y14.5M, 2009 0.36 D. DRAWING FILENAME: MKT-M14Arev14 8° 0° 0.90 0.50 SEATING PLANE (1.04) DETAIL A SCALE 16 : 1

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