Freescale Semiconductor, Inc. Document Number: KL26P64M48SF5 Data Sheet: Technical Data Rev 5 08/2014 Kinetis KL26 Sub-Family MKL26ZxxxVFM4 48 MHz Cortex-M0+ Based Microcontroller MKL26ZxxxVFT4 MKL26ZxxxVLH4 Designed with efficiency in mind. Compatible with all other Kinetis L families as well as Kinetis K2x family. General purpose MCU with USB 2.0, featuring market leading ultra low-power to provide developers an appropriate entry-level 32-bit solution. 32-pin QFN (FM) 48-pin QFN (FT) 5 x 5 x 1 Pitch 0.5 mm 7 x 7 x 1 Pitch 0.5 mm This product offers: • Run power consumption down to 40 μA/MHz in very low power run mode • Static power consumption down to 2 μA with full state retention and 4.5 μs wakeup • Ultra-efficient Cortex-M0+ processor running up to 48 MHz 64-pin LQFP (LH) with industry leading throughput 10 x 10 x 1.4 Pitch 0.5 mm • Memory option is up to 128 KB flash and 16 KB RAM • Energy-saving architecture is optimized for low power with 90nm TFS technology, clock and power gating techniques, and zero wait state flash memory controller Performance Human-machine interface • 48 MHz ARM® Cortex®-M0+ core • Low-power hardware touch sensor interface (TSI) • Up to 50 general-purpose input/output (GPIO) Memories and memory interfaces • Up to 128 KB program flash memory Communication interfaces • Up to 16 KB SRAM • USB full-/low-speed On-the-Go controller with on- chip transceiver and 5 V to 3.3 V regulator System peripherals • Two 16-bit SPI modules • Nine low-power modes to provide power optimization • I2S (SAI) module based on application requirements • One low power UART module • COP Software watchdog • Two UART modules • 4-channel DMA controller, supporting up to 63 request • Two I2C module sources • Low-leakage wakeup unit Analog Modules • SWD debug interface and Micro Trace Buffer • 16-bit SAR ADC • Bit Manipulation Engine • 12-bit DAC • Analog comparator (CMP) containing a 6-bit DAC Clocks and programmable reference input • 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator • Multi-purpose clock source Timers • Six channel Timer/PWM (TPM) Operating Characteristics • Two 2-channel Timer/PWM modules • Voltage range: 1.71 to 3.6 V • Periodic interrupt timers • Flash write voltage range: 1.71 to 3.6 V • 16-bit low-power timer (LPTMR) • Temperature range (ambient): -40 to 105°C • Real time clock Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2013–2014 Freescale Semiconductor, Inc. All rights reserved.

Security and integrity modules • 80-bit unique identification number per chip Ordering Information Part Number Memory Maximum number of I\O's Flash (KB) SRAM (KB) MKL26Z32VFM4 32 4 23 MKL26Z64VFM4 64 8 23 MKL26Z128VFM4 128 16 23 MKL26Z32VFT4 32 4 36 MKL26Z64VFT4 64 8 36 MKL26Z128VFT4 128 16 36 MKL26Z32VLH4 32 4 50 MKL26Z64VLH4 64 8 50 MKL26Z128VLH4 128 16 50 Related Resources Type Description Resource Selector Guide The Freescale Solution Advisor is a web-based tool that features Solution Advisor interactive application wizards and a dynamic product selector. Reference The Reference Manual contains a comprehensive description of the KL26P64M48SF5RM1 Manual structure and function (operation) of a device. Data Sheet The Data Sheet includes electrical characteristics and signal KL26P64M48SF51 connections. Chip Errata The chip mask set Errata provides additional or corrective KINETIS_L_xN15J 2 information for a particular device mask set. Package Package dimensions are provided in package drawings. QFN 32-pin: 98ASA00473D1 drawing QFN 48-pin: 98ASA00466D1 LQFP 64-pin: 98ASS23234W1 1. To find the associated resource, go to http://www.freescale.com and perform a search using this term. 2. To find the associated resource, go to http://www.freescale.com and perform a search using this term with the “x” replaced by the revision of the device you are using. 2 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Table of Contents 1 Ratings..................................................................................4 3.6.3 12-bit DAC electrical characteristics..................33 1.1 Thermal handling ratings...............................................4 3.7 Timers............................................................................36 1.2 Moisture handling ratings...............................................4 3.8 Communication interfaces.............................................36 1.3 ESD handling ratings.....................................................4 3.8.1 USB electrical specifications..............................36 1.4 Voltage and current operating ratings............................4 3.8.2 USB VREG electrical specifications...................37 2 General.................................................................................5 3.8.3 SPI switching specifications...............................37 2.1 AC electrical characteristics...........................................5 3.8.4 Inter-Integrated Circuit Interface (I2C) timing.....42 2.2 Nonswitching electrical specifications............................6 3.8.5 UART.................................................................43 2.2.1 Voltage and current operating requirements......6 3.8.6 I2S/SAI switching specifications........................43 2.2.2 LVD and POR operating requirements..............6 3.9 Human-machine interfaces (HMI)..................................47 2.2.3 Voltage and current operating behaviors...........7 3.9.1 TSI electrical specifications................................47 2.2.4 Power mode transition operating behaviors.......8 4 Dimensions...........................................................................48 2.2.5 Power consumption operating behaviors...........9 4.1 Obtaining package dimensions......................................48 2.2.6 EMC radiated emissions operating behaviors...15 5 Pinout....................................................................................48 2.2.7 Designing with radiated emissions in mind........16 5.1 KL26 Signal Multiplexing and Pin Assignments.............48 2.2.8 Capacitance attributes.......................................16 5.2 KL26 pinouts..................................................................51 2.3 Switching specifications.................................................16 6 Ordering parts.......................................................................54 2.3.1 Device clock specifications................................16 6.1 Determining valid orderable parts..................................54 2.3.2 General switching specifications........................17 7 Part identification...................................................................54 2.4 Thermal specifications...................................................17 7.1 Description.....................................................................55 2.4.1 Thermal operating requirements........................17 7.2 Format...........................................................................55 2.4.2 Thermal attributes..............................................18 7.3 Fields.............................................................................55 3 Peripheral operating requirements and behaviors................18 7.4 Example.........................................................................55 3.1 Core modules................................................................18 8 Terminology and guidelines..................................................56 3.1.1 SWD electricals .................................................18 8.1 Definition: Operating requirement..................................56 3.2 System modules............................................................20 8.2 Definition: Operating behavior.......................................56 3.3 Clock modules...............................................................20 8.3 Definition: Attribute........................................................56 3.3.1 MCG specifications............................................20 8.4 Definition: Rating...........................................................57 3.3.2 Oscillator electrical specifications......................22 8.5 Result of exceeding a rating..........................................57 3.4 Memories and memory interfaces.................................24 8.6 Relationship between ratings and operating 3.4.1 Flash electrical specifications............................24 requirements..................................................................57 3.5 Security and integrity modules.......................................26 8.7 Guidelines for ratings and operating requirements........58 3.6 Analog............................................................................26 8.8 Definition: Typical value.................................................58 3.6.1 ADC electrical specifications..............................26 8.9 Typical value conditions.................................................59 3.6.2 CMP and 6-bit DAC electrical specifications......31 9 Revision history.....................................................................60 Kinetis KL26 Sub-Family, Rev5 08/2014. 3 Freescale Semiconductor, Inc.

Ratings 1 Ratings 1.1 Thermal handling ratings Table 1. Thermal handling ratings Symbol Description Min. Max. Unit Notes T Storage temperature –55 150 °C 1 STG T Solder temperature, lead-free — 260 °C 2 SDR 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Table 2. Moisture handling ratings Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD handling ratings Table 3. ESD handling ratings Symbol Description Min. Max. Unit Notes V Electrostatic discharge voltage, human body model –2000 +2000 V 1 HBM V Electrostatic discharge voltage, charged-device –500 +500 V 2 CDM model I Latch-up current at ambient temperature of 105 °C –100 +100 mA 3 LAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 4 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

General 1.4 Voltage and current operating ratings Table 4. Voltage and current operating ratings Symbol Description Min. Max. Unit V Digital supply voltage –0.3 3.8 V DD I Digital supply current — 120 mA DD V IO pin input voltage –0.3 V + 0.3 V IO DD I Instantaneous maximum current single pin limit (applies to –25 25 mA D all port pins) V Analog supply voltage V – 0.3 V + 0.3 V DDA DD DD V USB_DP input voltage –0.3 3.63 V USB_DP V USB_DM input voltage –0.3 3.63 V USB_DM V USB regulator input –0.3 6.0 V REGIN 2 General 2.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Low High V IH 80% Input Signal Midpoint1 50% 20% V IL Fall Time Rise Time The midpoint is V + (V - V ) / 2 IL IH IL Figure 1. Input signal measurement reference All digital I/O switching characteristics, unless otherwise specified, assume the output pins have the following characteristics. • C =30 pF loads L • Slew rate disabled • Normal drive strength Kinetis KL26 Sub-Family, Rev5 08/2014. 5 Freescale Semiconductor, Inc.

General 2.2 Nonswitching electrical specifications 2.2.1 Voltage and current operating requirements Table 5. Voltage and current operating requirements Symbol Description Min. Max. Unit Notes V Supply voltage 1.71 3.6 V DD V Analog supply voltage 1.71 3.6 V DDA V – V V -to-V differential voltage –0.1 0.1 V DD DDA DD DDA V – V V -to-V differential voltage –0.1 0.1 V SS SSA SS SSA V Input high voltage IH • 2.7 V ≤ V ≤ 3.6 V 0.7 × V — V DD DD • 1.7 V ≤ V ≤ 2.7 V 0.75 × V — V DD DD V Input low voltage IL • 2.7 V ≤ V ≤ 3.6 V — 0.35 × V V DD DD • 1.7 V ≤ V ≤ 2.7 V — 0.3 × V V DD DD V Input hysteresis 0.06 × V — V HYS DD I IO pin negative DC injection current — single pin 1 ICIO -3 — mA • V < V -0.3V IN SS I Contiguous pin DC injection current —regional limit, ICcont includes sum of negative injection currents of 16 contiguous pins -25 — mA • Negative current injection V Open drain pullup voltage level V V V 2 ODPU DD DD V V voltage required to retain RAM 1.2 — V RAM DD 1. All I/O pins are internally clamped to V through a ESD protection diode. There is no diode connection to V . If V SS DD IN greater than V (= V -0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If IO_MIN SS this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (V - V )/|I |. IO_MIN IN ICIO 2. Open drain outputs must be pulled to V . DD 2.2.2 LVD and POR operating requirements Table 6. V supply LVD and POR operating requirements DD Symbol Description Min. Typ. Max. Unit Notes V Falling V POR detect voltage 0.8 1.1 1.5 V — POR DD Table continues on the next page... 6 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

General Table 6. V supply LVD and POR operating requirements (continued) DD Symbol Description Min. Typ. Max. Unit Notes V Falling low-voltage detect threshold — high 2.48 2.56 2.64 V — LVDH range (LVDV = 01) Low-voltage warning thresholds — high range 1 V • Level 1 falling (LVWV = 00) LVW1H 2.62 2.70 2.78 V V • Level 2 falling (LVWV = 01) LVW2H 2.72 2.80 2.88 V V • Level 3 falling (LVWV = 10) LVW3H 2.82 2.90 2.98 V V • Level 4 falling (LVWV = 11) LVW4H 2.92 3.00 3.08 V V Low-voltage inhibit reset/recover hysteresis — — ±60 — mV — HYSH high range V Falling low-voltage detect threshold — low 1.54 1.60 1.66 V — LVDL range (LVDV=00) Low-voltage warning thresholds — low range 1 V • Level 1 falling (LVWV = 00) LVW1L 1.74 1.80 1.86 V V • Level 2 falling (LVWV = 01) LVW2L 1.84 1.90 1.96 V V • Level 3 falling (LVWV = 10) LVW3L 1.94 2.00 2.06 V V • Level 4 falling (LVWV = 11) LVW4L 2.04 2.10 2.16 V V Low-voltage inhibit reset/recover hysteresis — — ±40 — mV — HYSL low range V Bandgap voltage reference 0.97 1.00 1.03 V — BG t Internal low power oscillator period — factory 900 1000 1100 μs — LPO trimmed 1. Rising thresholds are falling threshold + hysteresis voltage 2.2.3 Voltage and current operating behaviors Table 7. Voltage and current operating behaviors Symbol Description Min. Max. Unit Notes V Output high voltage — Normal drive pad (except 1, 2 OH RESET_b) V – 0.5 — V DD • 2.7 V ≤ V ≤ 3.6 V, I = -5 mA DD OH V – 0.5 — V DD • 1.71 V ≤ V ≤ 2.7 V, I = -2.5 mA DD OH V Output high voltage — High drive pad (except 1, 2 OH RESET_b) V – 0.5 — V DD • 2.7 V ≤ V ≤ 3.6 V, I = -20 mA DD OH V – 0.5 — V DD • 1.71 V ≤ V ≤ 2.7 V, I = -10 mA DD OH I Output high current total for all ports — 100 mA OHT Table continues on the next page... Kinetis KL26 Sub-Family, Rev5 08/2014. 7 Freescale Semiconductor, Inc.

General Table 7. Voltage and current operating behaviors (continued) Symbol Description Min. Max. Unit Notes V Output low voltage — Normal drive pad 1 OL • 2.7 V ≤ V ≤ 3.6 V, I = 5 mA — 0.5 V DD OL • 1.71 V ≤ V ≤ 2.7 V, I = 2.5 mA — 0.5 V DD OL V Output low voltage — High drive pad 1 OL • 2.7 V ≤ V ≤ 3.6 V, I = 20 mA — 0.5 V DD OL • 1.71 V ≤ V ≤ 2.7 V, I = 10 mA — 0.5 V DD OL I Output low current total for all ports — 100 mA OLT I Input leakage current (per pin) for full temperature — 1 μA 3 IN range I Input leakage current (per pin) at 25 °C — 0.025 μA 3 IN I Input leakage current (total all pins) for full — 65 μA 3 IN temperature range I Hi-Z (off-state) leakage current (per pin) — 1 μA OZ R Internal pullup resistors 20 50 kΩ 4 PU 1. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When configured as a GPIO output, it acts as a pseudo open drain output. 3. Measured at V = 3.6 V DD 4. Measured at V supply voltage = V min and Vinput = V DD DD SS 2.2.4 Power mode transition operating behaviors All specifications except t and VLLSx→RUN recovery times in the following table POR assume this clock configuration: • CPU and system clocks = 48 MHz • Bus and flash clock = 24 MHz • FEI clock mode POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz. Table 8. Power mode transition operating behaviors Symbol Description Min. Typ. Max. Unit Notes t After a POR event, amount of time from the — — 300 μs 1 POR point V reaches 1.8 V to execution of the first DD instruction across the operating temperature range of the chip. Table continues on the next page... 8 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

General Table 8. Power mode transition operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes • VLLS0 → RUN — 106 120 μs • VLLS1 → RUN — 105 117 μs • VLLS3 → RUN — 47 54 μs • LLS → RUN — 4.5 5.0 μs • VLPS → RUN — 4.5 5.0 μs • STOP → RUN — 4.5 5.0 μs 1. Normal boot (FTFA_FOPT[LPBOOT]=11). 2.2.5 Power consumption operating behaviors The maximum values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). Table 9. Power consumption operating behaviors Symbol Description Temp. Typ. Max Unit Note I Analog supply current — — See note mA 1 DDA I Run mode current in compute — 6.1 — mA 2 DD_RUNCO_ CM operation - 48 MHz core / 24 MHz flash/ bus disabled, LPTMR running using 4 MHz internal reference clock, CoreMark® benchmark code executing from flash, at 3.0 V I Run mode current in compute — 3.8 4.4 mA 3 DD_RUNCO operation - 48 MHz core / 24 MHz flash / bus clock disabled, code of while(1) loop executing from flash, at 3.0 V I Run mode current - 48 MHz core / 24 — 4.6 5.2 mA 3 DD_RUN MHz bus and flash, all peripheral clocks disabled, code executing from flash, at 3.0 V Table continues on the next page... Kinetis KL26 Sub-Family, Rev5 08/2014. 9 Freescale Semiconductor, Inc.

General Table 9. Power consumption operating behaviors (continued) Symbol Description Temp. Typ. Max Unit Note I Run mode current - 48 MHz core / 24 at 25 °C 6.0 6.2 mA 3, 4 DD_RUN MHz bus and flash, all peripheral at 70 °C 6.2 6.4 mA clocks enabled, code executing from flash, at 3.0 V at 125 °C 6.2 6.5 mA I Wait mode current - core disabled / 48 — 2.7 3.2 mA 3 DD_WAIT MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled, at 3.0 V I Wait mode current - core disabled / 24 — 2.1 2.6 mA 3 DD_WAIT MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled, at 3.0 V I Stop mode current with partial stop 2 — 1.5 2.0 mA 3 DD_PSTOP2 clocking option - core and system disabled / 10.5 MHz bus, at 3.0 V I Very-low-power run mode current in — 732 — µA 5 DD_VLPRCO _CM compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, LPTMR running with 4 MHz internal reference clock, CoreMark benchmark code executing from flash, at 3.0 V I Very low power run mode current in — 161 329 µA 6 DD_VLPRCO compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, code executing from flash, at 3.0 V I Very low power run mode current - 4 — 185 352 µA 6 DD_VLPR MHz core / 0.8 MHz bus and flash, all peripheral clocks disabled, code executing from flash, at 3.0 V I Very low power run mode current - 4 — 255 421 µA 4, 6 DD_VLPR MHz core / 0.8 MHz bus and flash, all peripheral clocks enabled, code executing from flash, at 3.0 V I Very low power wait mode current - — 110 281 µA 6 DD_VLPW core disabled / 4 MHz system / 0.8 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled, at 3.0 V I Stop mode current at 3.0 V at 25 °C 305 326 µA — DD_STOP at 50 °C 317 344 µA at 70 °C 337 380 µA at 85 °C 364 428 µA at 105 °C 429 553 µA I Very-low-power stop mode current at at 25 °C 2.69 4.14 µA — DD_VLPS 3.0 V at 50 °C 5.54 9.80 µA at 70 °C 11.80 21.94 µA Table continues on the next page... 10 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

General Table 9. Power consumption operating behaviors (continued) Symbol Description Temp. Typ. Max Unit Note at 85 °C 21.13 39.13 µA at 105 °C 45.85 85.45 µA I Low leakage stop mode current at 3.0 at 25 °C 1.98 2.65 µA — DD_LLS V at 50 °C 3.13 4.35 µA at 70 °C 5.65 8.34 µA at 85 °C 9.58 14.29 µA at 105 °C 20.52 31.74 µA I Very low-leakage stop mode 3 current at 25 °C 1.46 2.06 µA — DD_VLLS3 at 3.0 V at 50 °C 2.29 3.22 µA at 70 °C 4.10 5.90 µA at 85 °C 6.93 10.02 µA at 105 °C 14.80 22.12 µA I Very low-leakage stop mode 1 current at 25 °C 0.71 1.20 µA — DD_VLLS1 at 3.0V at 50 °C 1.10 1.71 µA at 70 °C 2.09 3.03 µA at 85 °C 3.80 5.42 µA at 105 °C 8.84 12.98 µA I Very low-leakage stop mode 0 current at 25 °C 0.40 0.88 µA — DD_VLLS0 (SMC_STOPCTRL[PORPO] = 0) at at 50 °C 0.80 1.40 µA 3.0 V at 70 °C 1.79 2.72 µA at 85 °C 3.50 5.10 µA at 105 °C 8.54 12.63 µA I Very low-leakage stop mode 0 current at 25 °C 0.23 0.69 µA 7 DD_VLLS0 (SMC_STOPCTRL[PORPO] = 1) at at 50 °C 0.61 1.19 µA 3.0 V at 70 °C 1.59 2.50 µA at 85 °C 3.30 4.89 µA at 105 °C 8.36 12.41 µA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. MCG configured for PEE mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized for balanced. 3. MCG configured for FEI mode. 4. Incremental current consumption from peripheral activity is not included. 5. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized for balanced. 6. MCG configured for BLPI mode. 7. No brownout. Kinetis KL26 Sub-Family, Rev5 08/2014. 11 Freescale Semiconductor, Inc.

General Table 10. Low power mode peripheral adders — typical value Symbol Description Temperature (°C) Unit -40 25 50 70 85 105 I 4 MHz internal reference clock (IRC) adder. 56 56 56 56 56 56 µA IREFSTEN4MHz Measured by entering STOP or VLPS mode with 4 MHz IRC enabled. I 32 kHz internal reference clock (IRC) adder. 52 52 52 52 52 52 µA IREFSTEN32KHz Measured by entering STOP mode with the 32 kHz IRC enabled. I External 4 MHz crystal clock adder. 206 228 237 245 251 258 µA EREFSTEN4MHz Measured by entering STOP or VLPS mode with the crystal enabled. I External 32 kHz crystal clock VLLS1 440 490 540 560 570 580 nA EREFSTEN32KHz adder by means of the VLLS3 440 490 540 560 570 580 OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured LLS 490 490 540 560 570 680 by entering all modes with the VLPS 510 560 560 560 610 680 crystal enabled. STOP 510 560 560 560 610 680 I CMP peripheral adder measured by placing 22 22 22 22 22 22 µA CMP the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. I RTC peripheral adder measured by placing 432 357 388 475 532 810 nA RTC the device in VLLS1 mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC ALARM set for 1 minute. Includes ERCLK32K (32 kHz external crystal) power consumption. I UART peripheral adder MCGIRCLK 66 66 66 66 66 66 µA UART measured by placing the (4 MHz device in STOP or VLPS internal mode with selected clock reference source waiting for RX data at clock) 115200 baud rate. Includes OSCERCLK 214 237 246 254 260 268 selected clock source power (4 MHz consumption. external crystal) I TPM peripheral adder MCGIRCLK 86 86 86 86 86 86 µA TPM measured by placing the (4 MHz device in STOP or VLPS internal mode with selected clock reference source configured for output clock) compare generating 100 Hz OSCERCLK 235 256 265 274 280 287 clock signal. No load is (4 MHz placed on the I/O generating external the clock signal. Includes crystal) selected clock source and I/O switching currents. Table continues on the next page... 12 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

General Table 10. Low power mode peripheral adders — typical value (continued) Symbol Description Temperature (°C) Unit -40 25 50 70 85 105 I Bandgap adder when BGEN bit is set and 45 45 45 45 45 45 µA BG device is placed in VLPx, LLS, or VLLSx mode. I ADC peripheral adder combining the 366 366 366 366 366 366 µA ADC measured values at V and V by placing DD DDA the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 2.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: • MCG in FBE for run mode, and BLPE for VLPR mode • USB regulator disabled • No GPIOs toggled • Code execution from flash with cache enabled • For the ALLOFF curve, all peripheral clocks are disabled except FTFA Kinetis KL26 Sub-Family, Rev5 08/2014. 13 Freescale Semiconductor, Inc.

General Run Mode Current VS Core Frequency Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE 7.00E-03 6.00E-03 5.00E-03 )A ( D D V n 4.00E-03 o n All Peripheral CLK Gates o itp All Off m us 3.00E-03 All On n o C tn e rru 2.00E-03 C 1.00E-03 000.00E+00 CLK Ratio '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2 Flash-Core 1 2 3 4 6 12 24 48 Core Freq (MHz) Figure 2. Run mode supply current vs. core frequency 14 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

General VLPR Mode Current Vs Core Frequency Temperature = 25, V D D = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE 400.00E-06 350.00E-06 A) 300.00E-06 (D D V n n o 250.00E-06 o mpti All Peripheral CLK Gates u s 200.00E-06 n o All Off C nt All On e urr 150.00E-06 C 100.00E-06 50.00E-06 000.00E+00 CLK Ratio '1-1 '1-2 '1-2 '1-4 Flash-Core 1 2 4 Core Freq (MHz) Figure 3. VLPR mode current vs. core frequency 2.2.6 EMC radiated emissions operating behaviors Table 11. EMC radiated emissions operating behaviors Symbol Description Frequency Typ. Unit Notes band (MHz) V Radiated emissions voltage, band 1 0.15–50 16 dBμV 1, 2 RE1 V Radiated emissions voltage, band 2 50–150 18 dBμV RE2 V Radiated emissions voltage, band 3 150–500 11 dBμV RE3 V Radiated emissions voltage, band 4 500–1000 13 dBμV RE4 V IEC level 0.15–1000 M — 2, 3 RE_IEC 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic Kinetis KL26 Sub-Family, Rev5 08/2014. 15 Freescale Semiconductor, Inc.

General application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. V = 3.3 V, T = 25 °C, f = 8 MHz (crystal), f = 48 MHz, f = 24 MHz DD A OSC SYS BUS 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 2.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for “EMC design.” 2.2.8 Capacitance attributes Table 12. Capacitance attributes Symbol Description Min. Max. Unit C Input capacitance — 7 pF IN 2.3 Switching specifications 2.3.1 Device clock specifications Table 13. Device clock specifications Symbol Description Min. Max. Unit Normal run mode f System and core clock — 48 MHz SYS f Bus clock — 24 MHz BUS f Flash clock — 24 MHz FLASH f System and core clock when Full Speed USB in operation 20 — MHz SYS_USB f LPTMR clock — 24 MHz LPTMR VLPR and VLPS modes1 f System and core clock — 4 MHz SYS f Bus clock — 1 MHz BUS f Flash clock — 1 MHz FLASH f LPTMR clock2 — 24 MHz LPTMR Table continues on the next page... 16 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

General Table 13. Device clock specifications (continued) Symbol Description Min. Max. Unit f External reference clock — 16 MHz ERCLK f LPTMR external reference clock — 16 MHz LPTMR_ERCLK f Oscillator crystal or resonator frequency — high frequency — 16 MHz osc_hi_2 mode (high range) (MCG_C2[RANGE]=1x) f TPM asynchronous clock — 8 MHz TPM f UART0 asynchronous clock — 8 MHz UART0 1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN or from VLPR. 2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin. 2.3.2 General switching specifications These general-purpose specifications apply to all signals configured for GPIO and UART signals. Table 14. General switching specifications Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) 1.5 — Bus clock 1 — Synchronous path cycles External RESET and NMI pin interrupt pulse width — 100 — ns 2 Asynchronous path GPIO pin interrupt pulse width — Asynchronous path 16 — ns 2 Port rise and fall time — 36 ns 3 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 75 pF load 2.4 Thermal specifications 2.4.1 Thermal operating requirements Table 15. Thermal operating requirements Symbol Description Min. Max. Unit T Die junction temperature –40 125 °C J T Ambient temperature –40 105 °C A Kinetis KL26 Sub-Family, Rev5 08/2014. 17 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 2.4.2 Thermal attributes Table 16. Thermal attributes Board type Symbol Description 64 LQFP 48 QFN 32 QFN Unit Notes Single-layer (1S) R Thermal resistance, junction to 71 83 98 °C/W 1 θJA ambient (natural convection) Four-layer (2s2p) R Thermal resistance, junction to 53 30 34 °C/W θJA ambient (natural convection) Single-layer (1S) R Thermal resistance, junction to 59 68 82 °C/W θJMA ambient (200 ft./min. air speed) Four-layer (2s2p) R Thermal resistance, junction to 46 24 28 °C/W θJMA ambient (200 ft./min. air speed) — R Thermal resistance, junction to 35 12 13 °C/W 2 θJB board — R Thermal resistance, junction to 21 2.3 2.3 °C/W 3 θJC case — Ψ Thermal characterization 6 5 8 °C/W 4 JT parameter, junction to package top outside center (natural convection) 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). 3 Peripheral operating requirements and behaviors 3.1 Core modules 18 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 3.1.1 SWD electricals Table 17. SWD full voltage range electricals Symbol Description Min. Max. Unit Operating voltage 1.71 3.6 V J1 SWD_CLK frequency of operation • Serial wire debug 0 25 MHz J2 SWD_CLK cycle period 1/J1 — ns J3 SWD_CLK clock pulse width • Serial wire debug 20 — ns J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J2 J3 J3 SWD_CLK (input) J4 J4 Figure 4. Serial wire clock input timing Kinetis KL26 Sub-Family, Rev5 08/2014. 19 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors SWD_CLK J9 J10 SWD_DIO Input data valid J11 SWD_DIO Output data valid J12 SWD_DIO J11 SWD_DIO Output data valid Figure 5. Serial wire data timing 3.2 System modules There are no specifications necessary for the device's system modules. 3.3 Clock modules 3.3.1 MCG specifications Table 18. MCG specifications Symbol Description Min. Typ. Max. Unit Notes f Internal reference frequency (slow clock) — — 32.768 — kHz ints_ft factory trimmed at nominal V and 25 °C DD f Internal reference frequency (slow clock) — 31.25 — 39.0625 kHz ints_t user trimmed Δ Resolution of trimmed average DCO output — ± 0.3 ± 0.6 %f 1 fdco_res_t dco frequency at fixed voltage and temperature — using C3[SCTRIM] and C4[SCFTRIM] Table continues on the next page... 20 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 18. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes Δf Total deviation of trimmed average DCO output — +0.5/-0.7 ± 3 %f 1, 2 dco_t dco frequency over voltage and temperature Δf Total deviation of trimmed average DCO output — ± 0.4 ± 1.5 %f 1, 2 dco_t dco frequency over fixed voltage and temperature range of 0–70 °C f Internal reference frequency (fast clock) — — 4 — MHz intf_ft factory trimmed at nominal V and 25 °C DD Δf Frequency deviation of internal reference clock — +1/-2 ± 3 %f 2 intf_ft intf_ft (fast clock) over temperature and voltage — factory trimmed at nominal V and 25 °C DD f Internal reference frequency (fast clock) — user 3 — 5 MHz intf_t trimmed at nominal V and 25 °C DD f Loss of external clock minimum frequency — (3/5) x — — kHz loc_low RANGE = 00 f ints_t f Loss of external clock minimum frequency — (16/5) x — — kHz loc_high RANGE = 01, 10, or 11 f ints_t FLL f FLL reference frequency range 31.25 — 39.0625 kHz fll_ref f DCO output Low range (DRS = 00) 20 20.97 25 MHz 3, 4 dco frequency range 640 × f fll_ref Mid range (DRS = 01) 40 41.94 48 MHz 1280 × f fll_ref f DCO output Low range (DRS = 00) — 23.99 — MHz 5, 6 dco_t_DMX3 frequency 2 732 × f fll_ref Mid range (DRS = 01) — 47.97 — MHz 1464 × f fll_ref J FLL period jitter — 180 — ps 7 cyc_fll • f = 48 MHz VCO t FLL target frequency acquisition time — — 1 ms 8 fll_acquire PLL f VCO operating frequency 48.0 — 100 MHz vco I PLL operating current 9 pll — 1060 — µA • PLL at 96 MHz (f = 8 MHz, f = osc_hi_1 pll_ref 2 MHz, VDIV multiplier = 48) I PLL operating current 9 pll — 600 — µA • PLL at 48 MHz (f = 8 MHz, f = osc_hi_1 pll_ref 2 MHz, VDIV multiplier = 24) f PLL reference frequency range 2.0 — 4.0 MHz pll_ref J PLL period jitter (RMS) 10 cyc_pll • f = 48 MHz — 120 — ps vco • f = 100 MHz — 50 — ps vco Table continues on the next page... Kinetis KL26 Sub-Family, Rev5 08/2014. 21 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 18. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes J PLL accumulated jitter over 1µs (RMS) 10 acc_pll • f = 48 MHz — 1350 — ps vco • f = 100 MHz — 600 — ps vco D Lock entry frequency tolerance ± 1.49 — ± 2.98 % lock D Lock exit frequency tolerance ± 4.47 — ± 5.97 % unl t Lock detector detection time — — 150 × 10-6 s 11 pll_lock + 1075(1/ f ) pll_ref 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. The deviation is relative to the factory trimmed frequency at nominal V and 25 °C, f . DD ints_ft 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. 4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation (Δf ) over voltage and temperature must be considered. dco_t 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. Excludes any oscillator currents that are also consuming power while PLL is in operation. 10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3.3.2 Oscillator electrical specifications 3.3.2.1 Oscillator DC electrical specifications Table 19. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit Notes V Supply voltage 1.71 — 3.6 V DD I Supply current — low-power mode (HGO=0) 1 DDOSC • 32 kHz — 500 — nA • 4 MHz — 200 — μA • 8 MHz (RANGE=01) — 300 — μA • 16 MHz — 950 — μA — 1.2 — mA Table continues on the next page... 22 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 19. Oscillator DC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit Notes • 24 MHz — 1.5 — mA • 32 MHz I Supply current — high gain mode (HGO=1) 1 DDOSC • 32 kHz — 25 — μA • 4 MHz — 400 — μA • 8 MHz (RANGE=01) — 500 — μA • 16 MHz — 2.5 — mA • 24 MHz — 3 — mA • 32 MHz — 4 — mA C EXTAL load capacitance — — — 2, 3 x C XTAL load capacitance — — — 2, 3 y R Feedback resistor — low-frequency, low-power — — — MΩ 2, 4 F mode (HGO=0) Feedback resistor — low-frequency, high-gain — 10 — MΩ mode (HGO=1) Feedback resistor — high-frequency, low-power — — — MΩ mode (HGO=0) Feedback resistor — high-frequency, high-gain — 1 — MΩ mode (HGO=1) R Series resistor — low-frequency, low-power — — — kΩ S mode (HGO=0) Series resistor — low-frequency, high-gain — 200 — kΩ mode (HGO=1) Series resistor — high-frequency, low-power — — — kΩ mode (HGO=0) Series resistor — high-frequency, high-gain mode (HGO=1) — 0 — kΩ V 5 Peak-to-peak amplitude of oscillation (oscillator — 0.6 — V pp mode) — low-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator — V — V DD mode) — low-frequency, high-gain mode (HGO=1) Peak-to-peak amplitude of oscillation (oscillator — 0.6 — V mode) — high-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator — V — V DD mode) — high-frequency, high-gain mode (HGO=1) 1. V =3.3 V, Temperature =25 °C DD 2. See crystal or resonator manufacturer's recommendation Kinetis KL26 Sub-Family, Rev5 08/2014. 23 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 3. C ,C can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For x y all other cases external capacitors must be used. 4. When low power mode is selected, R is integrated and must not be attached externally. F 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.2.2 Oscillator frequency specifications Table 20. Oscillator frequency specifications Symbol Description Min. Typ. Max. Unit Notes f Oscillator crystal or resonator frequency — low- 32 — 40 kHz osc_lo frequency mode (MCG_C2[RANGE]=00) f Oscillator crystal or resonator frequency — high- 3 — 8 MHz osc_hi_1 frequency mode (low range) (MCG_C2[RANGE]=01) f Oscillator crystal or resonator frequency — high 8 — 32 MHz osc_hi_2 frequency mode (high range) (MCG_C2[RANGE]=1x) f Input clock frequency (external clock mode) — — 48 MHz 1, 2 ec_extal t Input clock duty cycle (external clock mode) 40 50 60 % dc_extal t Crystal startup time — 32 kHz low-frequency, — 750 — ms 3, 4 cst low-power mode (HGO=0) Crystal startup time — 32 kHz low-frequency, — 250 — ms high-gain mode (HGO=1) Crystal startup time — 8 MHz high-frequency — 0.6 — ms (MCG_C2[RANGE]=01), low-power mode (HGO=0) Crystal startup time — 8 MHz high-frequency — 1 — ms (MCG_C2[RANGE]=01), high-gain mode (HGO=1) 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 3.4 Memories and memory interfaces 3.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 24 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 3.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 21. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit Notes t Longword Program high-voltage time — 7.5 18 μs — hvpgm4 t Sector Erase high-voltage time — 13 113 ms 1 hversscr t Erase All high-voltage time — 52 452 ms 1 hversall 1. Maximum time based on expectations at cycling end-of-life. 3.4.1.2 Flash timing specifications — commands Table 22. Flash command timing specifications Symbol Description Min. Typ. Max. Unit Notes t Read 1s Section execution time (flash sector) — — 60 μs 1 rd1sec1k t Program Check execution time — — 45 μs 1 pgmchk t Read Resource execution time — — 30 μs 1 rdrsrc t Program Longword execution time — 65 145 μs — pgm4 t Erase Flash Sector execution time — 14 114 ms 2 ersscr t Read 1s All Blocks execution time — — 1.8 ms — rd1all t Read Once execution time — — 25 μs 1 rdonce t Program Once execution time — 65 — μs — pgmonce t Erase All Blocks execution time — 88 650 ms 2 ersall t Verify Backdoor Access Key execution time — — 30 μs 1 vfykey 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 Flash high voltage current behaviors Table 23. Flash high voltage current behaviors Symbol Description Min. Typ. Max. Unit I Average current adder during high voltage — 2.5 6.0 mA DD_PGM flash programming operation I Average current adder during high voltage — 1.5 4.0 mA DD_ERS flash erase operation Kinetis KL26 Sub-Family, Rev5 08/2014. 25 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 3.4.1.4 Reliability specifications Table 24. NVM reliability specifications Symbol Description Min. Typ.1 Max. Unit Notes Program Flash t Data retention after up to 10 K cycles 5 50 — years — nvmretp10k t Data retention after up to 1 K cycles 20 100 — years — nvmretp1k n Cycling endurance 10 K 50 K — cycles 2 nvmcycp 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ T ≤ 125 °C. j 3.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 3.6 Analog 3.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 25 and Table 26 are achievable on the differential pins ADCx_DP0, ADCx_DM0. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 3.6.1.1 16-bit ADC operating conditions Table 25. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes V Supply voltage Absolute 1.71 — 3.6 V — DDA ΔV Supply voltage Delta to V (V – V ) -100 0 +100 mV 2 DDA DD DD DDA ΔV Ground voltage Delta to V (V – V ) -100 0 +100 mV 2 SSA SS SS SSA V ADC reference 1.13 V V V 3 REFH DDA DDA voltage high V ADC reference V V V V 3 REFL SSA SSA SSA voltage low Table continues on the next page... 26 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 25. 16-bit ADC operating conditions (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes V Input voltage • 16-bit differential mode VREFL — 31/32 * V — ADIN VREFH • All other modes VREFL — VREFH C Input • 16-bit mode — 8 10 pF — ADIN capacitance • 8-bit / 10-bit / 12-bit — 4 5 modes R Input series — 2 5 kΩ — ADIN resistance R Analog source 13-bit / 12-bit modes 4 AS resistance f < 4 MHz — — 5 kΩ (external) ADCK f ADC conversion ≤ 13-bit mode 1.0 — 18.0 MHz 5 ADCK clock frequency f ADC conversion 16-bit mode 2.0 — 12.0 MHz 5 ADCK clock frequency C ADC conversion ≤ 13-bit modes 6 rate rate No ADC hardware averaging 20.000 — 818.330 Ksps Continuous conversions enabled, subsequent conversion time C ADC conversion 16-bit mode 6 rate rate No ADC hardware averaging 37.037 — 461.467 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume V = 3.0 V, Temp = 25 °C, f = 1.0 MHz, unless otherwise stated. Typical values are for DDA ADCK reference only, and are not tested in production. 2. DC potential difference. 3. For packages without dedicated VREFH and VREFL pins, V is internally tied to V , and V is internally tied REFH DDA REFL to V . SSA 4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The R /C time constant should be kept to < 1 ns. AS AS 5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. Kinetis KL26 Sub-Family, Rev5 08/2014. 27 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED Pad ZAS leakage CHANNEL SELECT due to CIRCUIT ADC SAR RAS input RADIN ENGINE protection VADIN VAS CAS RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure 6. ADC input impedance equivalency diagram 3.6.1.2 16-bit ADC electrical characteristics Table 26. 16-bit ADC characteristics (V = V , V = V ) REFH DDA REFL SSA Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes I Supply current 0.215 — 1.7 mA 3 DDA_ADC ADC • ADLPC = 1, ADHSC = 1.2 2.4 3.9 MHz t = ADACK asynchronous 0 1/f 2.4 4.0 6.1 MHz ADACK clock source • ADLPC = 1, ADHSC = 3.0 5.2 7.3 MHz 1 f 4.4 6.2 9.5 MHz ADACK • ADLPC = 0, ADHSC = 0 • ADLPC = 0, ADHSC = 1 Sample Time See Reference Manual chapter for sample times TUE Total unadjusted • 12-bit modes — ±4 ±6.8 LSB4 5 error • <12-bit modes — ±1.4 ±2.1 DNL Differential non- • 12-bit modes — ±0.7 –1.1 to LSB4 5 linearity +1.9 • <12-bit modes — ±0.2 –0.3 to 0.5 Table continues on the next page... 28 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 26. 16-bit ADC characteristics (V = V , V = V ) (continued) REFH DDA REFL SSA Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes INL Integral non- • 12-bit modes — ±1.0 –2.7 to LSB4 5 linearity +1.9 • <12-bit modes — ±0.5 –0.7 to +0.5 E Full-scale error • 12-bit modes — –4 –5.4 LSB4 V = FS ADIN V 5 • <12-bit modes — –1.4 –1.8 DDA E Quantization • 16-bit modes — –1 to 0 — LSB4 Q error • ≤13-bit modes — — ±0.5 ENOB Effective number 16-bit differential mode 6 12.8 14.5 — bits of bits • Avg = 32 11.9 13.8 — bits • Avg = 4 12.2 13.9 — bits 16-bit single-ended mode 11.4 13.1 — bits • Avg = 32 • Avg = 4 Signal-to-noise See ENOB SINAD 6.02 × ENOB + 1.76 dB plus distortion THD Total harmonic 16-bit differential mode 7 — -94 — dB distortion • Avg = 32 — -85 — dB 16-bit single-ended mode • Avg = 32 SFDR Spurious free 16-bit differential mode 7 82 95 — dB dynamic range • Avg = 32 78 90 — dB 16-bit single-ended mode • Avg = 32 E Input leakage I × R mV I = IL In AS In error leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor Across the full temperature 1.55 1.62 1.69 mV/°C 8 slope range of the device V Temp sensor 25 °C 706 716 726 mV 8 TEMP25 voltage Kinetis KL26 Sub-Family, Rev5 08/2014. 29 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 1. All accuracy numbers assume the ADC is calibrated with V = V REFH DDA 2. Typical values assume V = 3.0 V, Temp = 25 °C, f = 2.0 MHz unless otherwise stated. Typical values are for DDA ADCK reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (V - V )/2N REFH REFL 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. 8. ADC conversion clock < 3 MHz Typical ADC 16-bit Differential ENOB vs ADC Clock 100Hz, 90% FS Sine Input 15.00 14.70 14.40 14.10 13.80 B O 13.50 N E 13.20 12.90 12.60 Hardware Averaging Disabled 12.30 Averaging of 4 samples Averaging of 8 samples Averaging of 32 samples 12.00 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 7. Typical ENOB vs. ADC_CLK for 16-bit differential mode Typical ADC 16-bit Single-Ended ENOB vs ADC Clock 100Hz, 90% FS Sine Input 14.00 13.75 13.50 13.25 13.00 12.75 B O 12.50 N E 12.25 12.00 11.75 11.50 11.25 Averaging of 4 samples Averaging of 32 samples 11.00 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 8. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 30 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 3.6.2 CMP and 6-bit DAC electrical specifications Table 27. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit V Supply voltage 1.71 — 3.6 V DD I Supply current, High-speed mode (EN=1, — — 200 μA DDHS PMODE=1) I Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA DDLS V Analog input voltage V – 0.3 — V V AIN SS DD V Analog input offset voltage — — 20 mV AIO V Analog comparator hysteresis1 H • CR0[HYSTCTR] = 00 — 5 — mV • CR0[HYSTCTR] = 01 — 10 — mV • CR0[HYSTCTR] = 10 — 20 — mV • CR0[HYSTCTR] = 11 — 30 — mV V Output high V – 0.5 — — V CMPOh DD V Output low — — 0.5 V CMPOl t Propagation delay, high-speed mode (EN=1, 20 50 200 ns DHS PMODE=1) t Propagation delay, low-speed mode (EN=1, 80 250 600 ns DLS PMODE=0) Analog comparator initialization delay2 — — 40 μs I 6-bit DAC current adder (enabled) — 7 — μA DAC6b INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to V –0.6 V. DD 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = V /64 reference Kinetis KL26 Sub-Family, Rev5 08/2014. 31 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 0.08 0.07 0.06 ) 0.05 HYSTCT R V Setting ( s eri 00 r 0.04 e 01 st y 1100 H P 0.03 11 M C 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) 32 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 0.18 0.16 0.14 0.12 HYSTC TR ) V Setting ( s esi 0.1 00 r e 01 st y 0.08 1100 H P 11 M C 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin le vel (V) Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 3.6.3 12-bit DAC electrical characteristics 3.6.3.1 12-bit DAC operating requirements Table 28. 12-bit DAC operating requirements Symbol Desciption Min. Max. Unit Notes V Supply voltage 1.71 3.6 V DDA V Reference voltage 1.13 3.6 V 1 DACR C Output load capacitance — 100 pF 2 L I Output load current — 1 mA L 1. The DAC reference can be selected to be V or VREFH. DDA 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC Kinetis KL26 Sub-Family, Rev5 08/2014. 33 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 3.6.3.2 12-bit DAC operating behaviors Table 29. 12-bit DAC operating behaviors Symbol Description Min. Typ. Max. Unit Notes I Supply current — low-power mode — — 250 μA DDA_DACL P I Supply current — high-speed mode — — 900 μA DDA_DACH P t Full-scale settling time (0x080 to 0xF7F) — — 100 200 μs 1 DACLP low-power mode t Full-scale settling time (0x080 to 0xF7F) — — 15 30 μs 1 DACHP high-power mode t Code-to-code settling time (0xBF8 to — 0.7 1 μs 1 CCDACLP 0xC08) — low-power mode and high-speed mode V DAC output voltage range low — high- — — 100 mV dacoutl speed mode, no load, DAC set to 0x000 V DAC output voltage range high — high- V — V mV dacouth DACR DACR speed mode, no load, DAC set to 0xFFF −100 INL Integral non-linearity error — high speed — — ±8 LSB 2 mode DNL Differential non-linearity error — V > 2 — — ±1 LSB 3 DACR V DNL Differential non-linearity error — V = — — ±1 LSB 4 DACR VREF_OUT V Offset error — ±0.4 ±0.8 %FSR 5 OFFSET E Gain error — ±0.1 ±0.6 %FSR 5 G PSRR Power supply rejection ratio, V ≥ 2.4 V 60 — 90 dB DDA T Temperature coefficient offset voltage — 3.7 — μV/C 6 CO T Temperature coefficient gain error — 0.000421 — %FSR/C GE Rop Output resistance (load = 3 kΩ) — — 250 Ω SR Slew rate -80h→ F7Fh→ 80h V/μs • High power (SP ) 1.2 1.7 — HP • Low power (SP ) 0.05 0.12 — LP BW 3dB bandwidth kHz • High power (SP ) 550 — — HP • Low power (SP ) 40 — — LP 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to V −100 mV DACR 3. The DNL is measured for 0 + 100 mV to V −100 mV DACR 4. The DNL is measured for 0 + 100 mV to V −100 mV with V > 2.4 V DACR DDA 5. Calculated by a best fit curve from V + 100 mV to V − 100 mV SS DACR 6. V = 3.0 V, reference select set for V (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set DDA DDA to 0x800, temperature range is across the full range of the device 34 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 8 6 4 2 B) S L L ( N 0 2 I 1 C A D -2 -4 -6 -8 0 500 1000 1500 2000 2500 3000 3500 4000 Digital Code Figure 11. Typical INL error vs. digital code Kinetis KL26 Sub-Family, Rev5 08/2014. 35 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 1.499 1.4985 ge 1.498 a olt V e d o C vel 1.4975 e L d Mi 2 1 C A D 1.497 1.4965 1.496 -40 25 55 85 105 125 Temperature °C Figure 12. Offset at half scale vs. temperature 3.7 Timers See General switching specifications. 3.8 Communication interfaces 3.8.1 USB electrical specifications The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit usb.org. 36 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors NOTE The MCGPLLCLK meets the USB jitter specifications for certification with the use of an external clock/crystal for both Device and Host modes. The MCGFLLCLK does not meet the USB jitter specifications for certification. 3.8.2 USB VREG electrical specifications Table 30. USB VREG electrical specifications Symbol Description Min. Typ.1 Max. Unit Notes VREGIN Input supply voltage 2.7 — 5.5 V I Quiescent current — Run mode, load current — 125 186 μA DDon equal zero, input supply (VREGIN) > 3.6 V I Quiescent current — Standby mode, load — 1.1 10 μA DDstby current equal zero I Quiescent current — Shutdown mode DDoff — 650 — nA • VREGIN = 5.0 V and temperature=25 °C — — 4 μA • Across operating voltage and temperature I Maximum load current — Run mode — — 120 mA LOADrun I Maximum load current — Standby mode — — 1 mA LOADstby V Regulator output voltage — Input supply Reg33out (VREGIN) > 3.6 V • Run mode 3 3.3 3.6 V • Standby mode 2.1 2.8 3.6 V V Regulator output voltage — Input supply 2.1 — 3.6 V 2 Reg33out (VREGIN) < 3.6 V, pass-through mode C External output capacitor 1.76 2.2 8.16 μF OUT ESR External output capacitor equivalent series 1 — 100 mΩ resistance I Short circuit current — 290 — mA LIM 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I . Load Kinetis KL26 Sub-Family, Rev5 08/2014. 37 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 3.8.3 SPI switching specifications The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. See the SPI chapter of the chip's Reference Manual for information about the modified transfer formats used for communicating with slower peripheral devices. All timing is shown with respect to 20% V and 80% V thresholds, unless noted, as DD DD well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins. Table 31. SPI master mode timing on slew rate disabled pads Num. Symbol Description Min. Max. Unit Note 1 f Frequency of operation f /2048 f /2 Hz 1 op periph periph 2 t SPSCK period 2 x t 2048 x ns 2 SPSCK periph t periph 3 t Enable lead time 1/2 — t — Lead SPSCK 4 t Enable lag time 1/2 — t — Lag SPSCK 5 t Clock (SPSCK) high or low time t - 30 1024 x ns — WSPSCK periph t periph 6 t Data setup time (inputs) 18 — ns — SU 7 t Data hold time (inputs) 0 — ns — HI 8 t Data valid (after SPSCK edge) — 15 ns — v 9 t Data hold time (outputs) 0 — ns — HO 10 t Rise time input — t - 25 ns — RI periph t Fall time input FI 11 t Rise time output — 25 ns — RO t Fall time output FO 1. For SPI0 f is the bus clock (f ). For SPI1 f is the system clock (f ). periph BUS periph SYS 2. t = 1/f periph periph Table 32. SPI master mode timing on slew rate enabled pads Num. Symbol Description Min. Max. Unit Note 1 f Frequency of operation f /2048 f /2 Hz 1 op periph periph 2 t SPSCK period 2 x t 2048 x ns 2 SPSCK periph t periph 3 t Enable lead time 1/2 — t — Lead SPSCK 4 t Enable lag time 1/2 — t — Lag SPSCK 5 t Clock (SPSCK) high or low time t - 30 1024 x ns — WSPSCK periph t periph 6 t Data setup time (inputs) 96 — ns — SU 7 t Data hold time (inputs) 0 — ns — HI Table continues on the next page... 38 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 32. SPI master mode timing on slew rate enabled pads (continued) Num. Symbol Description Min. Max. Unit Note 8 t Data valid (after SPSCK edge) — 52 ns — v 9 t Data hold time (outputs) 0 — ns — HO 10 t Rise time input — t - 25 ns — RI periph t Fall time input FI 11 t Rise time output — 36 ns — RO t Fall time output FO 1. For SPI0 f is the bus clock (f ). For SPI1 f is the system clock (f ). periph BUS periph SYS 2. t = 1/f periph periph SS1 (OUTPUT) 3 2 10 11 4 SPSCK 5 (CPOL=0) (OUTPUT) 5 10 11 SPSCK (CPOL=1) (OUTPUT) 6 7 MISO MSB IN2 BIT 6 . . . 1 LSB IN (INPUT) 8 9 MOSI (OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 13. SPI master mode timing (CPHA = 0) Kinetis KL26 Sub-Family, Rev5 08/2014. 39 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors SS1 (OUTPUT) 2 3 10 11 4 SPSCK (CPOL=0) (OUTPUT) 5 5 10 11 SPSCK (CPOL=1) (OUTPUT) 6 7 MISO (INPUT) MSB IN2 BIT 6 . . . 1 LSB IN 8 9 MOSI (OUTPUT) PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 14. SPI master mode timing (CPHA = 1) Table 33. SPI slave mode timing on slew rate disabled pads Num. Symbol Description Min. Max. Unit Note 1 f Frequency of operation 0 f /4 Hz 1 op periph 2 t SPSCK period 4 x t — ns 2 SPSCK periph 3 t Enable lead time 1 — t — Lead periph 4 t Enable lag time 1 — t — Lag periph 5 t Clock (SPSCK) high or low time t - 30 — ns — WSPSCK periph 6 t Data setup time (inputs) 2.5 — ns — SU 7 t Data hold time (inputs) 3.5 — ns — HI 8 t Slave access time — t ns 3 a periph 9 t Slave MISO disable time — t ns 4 dis periph 10 t Data valid (after SPSCK edge) — 31 ns — v 11 t Data hold time (outputs) 0 — ns — HO 12 t Rise time input — t - 25 ns — RI periph t Fall time input FI 13 t Rise time output — 25 ns — RO t Fall time output FO 1. For SPI0 f is the bus clock (f ). For SPI1 f is the system clock (f ). periph BUS periph SYS 2. t = 1/f periph periph 3. Time to data active from high-impedance state 4. Hold time to high-impedance state 38 <<CLASSIFICATION>> 40 Kinetis KL26 Sub-Family, Rev5 08/2014. <<NDA MESSAGE>> Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 34. SPI slave mode timing on slew rate enabled pads Num. Symbol Description Min. Max. Unit Note 1 f Frequency of operation 0 f /4 Hz 1 op periph 2 t SPSCK period 4 x t — ns 2 SPSCK periph 3 t Enable lead time 1 — t — Lead periph 4 t Enable lag time 1 — t — Lag periph 5 t Clock (SPSCK) high or low time t - 30 — ns — WSPSCK periph 6 t Data setup time (inputs) 2 — ns — SU 7 t Data hold time (inputs) 7 — ns — HI 8 t Slave access time — t ns 3 a periph 9 t Slave MISO disable time — t ns 4 dis periph 10 t Data valid (after SPSCK edge) — 122 ns — v 11 t Data hold time (outputs) 0 — ns — HO 12 t Rise time input — t - 25 ns — RI periph t Fall time input FI 13 t Rise time output — 36 ns — RO t Fall time output FO 1. For SPI0 f is the bus clock (f ). For SPI1 f is the system clock (f ). periph BUS periph SYS 2. t = 1/f periph periph 3. Time to data active from high-impedance state 4. Hold time to high-impedance state SS (INPUT) 2 12 13 4 SPSCK (CPOL=0) (INPUT) 3 5 5 SPSCK 12 13 (CPOL=1) (INPUT) 9 8 10 11 11 MISO see SEE (OUTPUT) note SLAVE MSB BIT 6 . . . 1 SLAVE LSB OUT NOTE 6 7 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: Not defined Figure 15. SPI slave mode timing (CPHA = 0) Kinetis KL26 Sub-Family, Rev5 08/2014. 41 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors SS (INPUT) 2 4 3 12 13 SPSCK (CPOL=0) (INPUT) 5 5 12 13 SPSCK (CPOL=1) (INPUT) 10 11 9 MISO see SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT (OUTPUT) note 8 6 7 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: Not defined Figure 16. SPI slave mode timing (CPHA = 1) 3.8.4 Inter-Integrated Circuit Interface (I2C) timing Table 35. I2C timing Characteristic Symbol Standard Mode Fast Mode Unit Minimum Maximum Minimum Maximum SCL Clock Frequency f 0 100 0 4001 kHz SCL Hold time (repeated) START condition. t ; STA 4 — 0.6 — µs HD After this period, the first clock pulse is generated. LOW period of the SCL clock t 4.7 — 1.3 — µs LOW HIGH period of the SCL clock t 4 — 0.6 — µs HIGH Set-up time for a repeated START t ; STA 4.7 — 0.6 — µs SU condition Data hold time for I2C bus devices t ; DAT 02 3.453 04 0.92 µs HD Data set-up time t ; DAT 2505 — 1003, 6 — ns SU Rise time of SDA and SCL signals t — 1000 20 +0.1C 7 300 ns r b Fall time of SDA and SCL signals t — 300 20 +0.1C 6 300 ns f b Set-up time for STOP condition t ; STO 4 — 0.6 — µs SU Bus free time between STOP and t 4.7 — 1.3 — µs BUF START condition Pulse width of spikes that must be t N/A N/A 0 50 ns SP suppressed by the input filter 1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only achieved when using the High drive pins (see Voltage and current operating behaviors) or when using the Normal drive pins and VDD ≥ 2.7 V 42 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

  Peripheral operating requirements and behaviors 2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 4. Input signal Slew = 10 ns and Output Load = 50 pF 5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement t ≥ 250 ns SU; DAT must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t rmax + t = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is SU; DAT released. 7. C = total capacitance of the one bus line in pF. b SDA tSU; DAT tf tf tLOW tr tHD; STA tSP tr tBUF SCL HD; STA tSU; STA tSU; STO S t t SR P S HD; DAT HIGH Figure 17. Timing definition for fast and standard mode devices on the I2C bus 3.8.5 UART See General switching specifications. 3.8.6 I2S/SAI switching specifications This section provides the AC timing for the I2S/SAI module in master mode (clocks are driven) and slave mode (clocks are input). All timing is given for noninverted serial clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the frame sync (FS) signal shown in the following figures. Kinetis KL26 Sub-Family, Rev5 08/2014. 43 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 3.8.6.1 Normal Run, Wait and Stop mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes. Table 36. I2S/SAI master mode timing Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 40 — ns S2 I2S_MCLK (as an input) pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 — ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ — 15.5 ns I2S_RX_FS output valid S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ 0 — ns I2S_RX_FS output invalid S7 I2S_TX_BCLK to I2S_TXD valid — 19 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns S9 I2S_RXD/I2S_RX_FS input setup before 26 — ns I2S_RX_BCLK S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ S4 I2S_RX_BCLK (output) S4 S5 S6 I2S_TX_FS/ I2S_RX_FS (output) S9 S10 I2S_TX_FS/ I2S_RX_FS (input) S7 S7 S8 S8 I2S_TXD S9 S10 I2S_RXD Figure 18. I2S/SAI timing — master modes 44 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 37. I2S/SAI slave mode timing Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 — ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% MCLK period (input) S13 I2S_TX_FS/I2S_RX_FS input setup before 10 — ns I2S_TX_BCLK/I2S_RX_BCLK S14 I2S_TX_FS/I2S_RX_FS input hold after 2 — ns I2S_TX_BCLK/I2S_RX_BCLK S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 33 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output 0 — ns invalid S17 I2S_RXD setup before I2S_RX_BCLK 10 — ns S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 — 28 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear S11 S12 I2S_TX_BCLK/ S12 I2S_RX_BCLK (input) S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 S14 I2S_TX_FS/ I2S_RX_FS (input) S15 S19 S15 S16 S16 I2S_TXD S17 S18 I2S_RXD Figure 19. I2S/SAI timing — slave modes 3.8.6.2 VLPR, VLPW, and VLPS mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes. Kinetis KL26 Sub-Family, Rev5 08/2014. 45 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 38. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 62.5 — ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 — ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ — 45 ns I2S_RX_FS output valid S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ — ns I2S_RX_FS output invalid S7 I2S_TX_BCLK to I2S_TXD valid — 45 ns S8 I2S_TX_BCLK to I2S_TXD invalid — ns S9 I2S_RXD/I2S_RX_FS input setup before — ns I2S_RX_BCLK S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ S4 I2S_RX_BCLK (output) S4 S5 S6 I2S_TX_FS/ I2S_RX_FS (output) S9 S10 I2S_TX_FS/ I2S_RX_FS (input) S7 S7 S8 S8 I2S_TXD S9 S10 I2S_RXD Figure 20. I2S/SAI timing — master modes Table 39. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 — ns Table continues on the next page... 46 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 39. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) (continued) Num. Characteristic Min. Max. Unit S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% MCLK period (input) S13 I2S_TX_FS/I2S_RX_FS input setup before 30 — ns I2S_TX_BCLK/I2S_RX_BCLK S14 I2S_TX_FS/I2S_RX_FS input hold after — ns I2S_TX_BCLK/I2S_RX_BCLK S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_RX_BCLK 30 — ns S18 I2S_RXD hold after I2S_RX_BCLK — ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 — 72 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear S11 S12 I2S_TX_BCLK/ S12 I2S_RX_BCLK (input) S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 S14 I2S_TX_FS/ I2S_RX_FS (input) S15 S19 S15 S16 S16 I2S_TXD S17 S18 I2S_RXD Figure 21. I2S/SAI timing — slave modes 3.9 Human-machine interfaces (HMI) 3.9.1 TSI electrical specifications Table 40. TSI electrical specifications Symbol Description Min. Typ. Max. Unit TSI_RUNF Fixed power consumption in run mode — 100 — µA Table continues on the next page... Kinetis KL26 Sub-Family, Rev5 08/2014. 47 Freescale Semiconductor, Inc.

Dimensions Table 40. TSI electrical specifications (continued) Symbol Description Min. Typ. Max. Unit TSI_RUNV Variable power consumption in run mode 1.0 — 128 µA (depends on oscillator's current selection) TSI_EN Power consumption in enable mode — 100 — µA TSI_DIS Power consumption in disable mode — 1.2 — µA TSI_TEN TSI analog enable time — 66 — µs TSI_CREF TSI reference capacitor — 1.0 — pF TSI_DVOLT Voltage variation of VP & VM around nominal 0.19 — 1.03 V values 4 Dimensions 4.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 32-pin QFN 98ASA00473D 48-pin QFN 98ASA00466D 64-pin LQFP 98ASS23234W 5 Pinout 5.1 KL26 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 48 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Pinout 64 48 32 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 LQFP QFN QFN 1 — 1 PTE0 DISABLED PTE0 SPI1_MISO UART1_TX RTC_ CMP0_OUT I2C1_SDA CLKOUT 2 — — PTE1 DISABLED PTE1 SPI1_MOSI UART1_RX SPI1_MISO I2C1_SCL 3 1 — VDD VDD VDD 4 2 2 VSS VSS VSS 5 3 3 USB0_DP USB0_DP USB0_DP 6 4 4 USB0_DM USB0_DM USB0_DM 7 5 5 VOUT33 VOUT33 VOUT33 8 6 6 VREGIN VREGIN VREGIN 9 7 — PTE20 ADC0_DP0/ ADC0_DP0/ PTE20 TPM1_CH0 UART0_TX ADC0_SE0 ADC0_SE0 10 8 — PTE21 ADC0_DM0/ ADC0_DM0/ PTE21 TPM1_CH1 UART0_RX ADC0_SE4a ADC0_SE4a 11 — — PTE22 ADC0_DP3/ ADC0_DP3/ PTE22 TPM2_CH0 UART2_TX ADC0_SE3 ADC0_SE3 12 — — PTE23 ADC0_DM3/ ADC0_DM3/ PTE23 TPM2_CH1 UART2_RX ADC0_SE7a ADC0_SE7a 13 9 7 VDDA VDDA VDDA 14 10 — VREFH VREFH VREFH 15 11 — VREFL VREFL VREFL 16 12 8 VSSA VSSA VSSA 17 13 — PTE29 CMP0_IN5/ CMP0_IN5/ PTE29 TPM0_CH2 TPM_CLKIN0 ADC0_SE4b ADC0_SE4b 18 14 9 PTE30 DAC0_OUT/ DAC0_OUT/ PTE30 TPM0_CH3 TPM_CLKIN1 ADC0_SE23/ ADC0_SE23/ CMP0_IN4 CMP0_IN4 19 — — PTE31 DISABLED PTE31 TPM0_CH4 20 15 — PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL 21 16 — PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA 22 17 10 PTA0 SWD_CLK TSI0_CH1 PTA0 TPM0_CH5 SWD_CLK 23 18 11 PTA1 DISABLED TSI0_CH2 PTA1 UART0_RX TPM2_CH0 24 19 12 PTA2 DISABLED TSI0_CH3 PTA2 UART0_TX TPM2_CH1 25 20 13 PTA3 SWD_DIO TSI0_CH4 PTA3 I2C1_SCL TPM0_CH0 SWD_DIO 26 21 14 PTA4 NMI_b TSI0_CH5 PTA4 I2C1_SDA TPM0_CH1 NMI_b 27 — — PTA5 DISABLED PTA5 USB_CLKIN TPM0_CH2 I2S0_TX_ BCLK 28 — — PTA12 DISABLED PTA12 TPM1_CH0 I2S0_TXD0 29 — — PTA13 DISABLED PTA13 TPM1_CH1 I2S0_TX_FS 30 22 15 VDD VDD VDD 31 23 16 VSS VSS VSS 32 24 17 PTA18 EXTAL0 EXTAL0 PTA18 UART1_RX TPM_CLKIN0 33 25 18 PTA19 XTAL0 XTAL0 PTA19 UART1_TX TPM_CLKIN1 LPTMR0_ ALT1 Kinetis KL26 Sub-Family, Rev5 08/2014. 49 Freescale Semiconductor, Inc.

Pinout 64 48 32 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 LQFP QFN QFN 34 26 19 PTA20 RESET_b PTA20 RESET_b 35 27 20 PTB0/ ADC0_SE8/ ADC0_SE8/ PTB0/ I2C0_SCL TPM1_CH0 LLWU_P5 TSI0_CH0 TSI0_CH0 LLWU_P5 36 28 21 PTB1 ADC0_SE9/ ADC0_SE9/ PTB1 I2C0_SDA TPM1_CH1 TSI0_CH6 TSI0_CH6 37 29 — PTB2 ADC0_SE12/ ADC0_SE12/ PTB2 I2C0_SCL TPM2_CH0 TSI0_CH7 TSI0_CH7 38 30 — PTB3 ADC0_SE13/ ADC0_SE13/ PTB3 I2C0_SDA TPM2_CH1 TSI0_CH8 TSI0_CH8 39 31 — PTB16 TSI0_CH9 TSI0_CH9 PTB16 SPI1_MOSI UART0_RX TPM_CLKIN0 SPI1_MISO 40 32 — PTB17 TSI0_CH10 TSI0_CH10 PTB17 SPI1_MISO UART0_TX TPM_CLKIN1 SPI1_MOSI 41 — — PTB18 TSI0_CH11 TSI0_CH11 PTB18 TPM2_CH0 I2S0_TX_ BCLK 42 — — PTB19 TSI0_CH12 TSI0_CH12 PTB19 TPM2_CH1 I2S0_TX_FS 43 33 — PTC0 ADC0_SE14/ ADC0_SE14/ PTC0 EXTRG_IN audioUSB_ CMP0_OUT I2S0_TXD0 TSI0_CH13 TSI0_CH13 SOF_OUT 44 34 22 PTC1/ ADC0_SE15/ ADC0_SE15/ PTC1/ I2C1_SCL TPM0_CH0 I2S0_TXD0 LLWU_P6/ TSI0_CH14 TSI0_CH14 LLWU_P6/ RTC_CLKIN RTC_CLKIN 45 35 23 PTC2 ADC0_SE11/ ADC0_SE11/ PTC2 I2C1_SDA TPM0_CH1 I2S0_TX_FS TSI0_CH15 TSI0_CH15 46 36 24 PTC3/ DISABLED PTC3/ UART1_RX TPM0_CH2 CLKOUT I2S0_TX_ LLWU_P7 LLWU_P7 BCLK 47 — — VSS VSS VSS 48 — — VDD VDD VDD 49 37 25 PTC4/ DISABLED PTC4/ SPI0_PCS0 UART1_TX TPM0_CH3 I2S0_MCLK LLWU_P8 LLWU_P8 50 38 26 PTC5/ DISABLED PTC5/ SPI0_SCK LPTMR0_ I2S0_RXD0 CMP0_OUT LLWU_P9 LLWU_P9 ALT2 51 39 27 PTC6/ CMP0_IN0 CMP0_IN0 PTC6/ SPI0_MOSI EXTRG_IN I2S0_RX_ SPI0_MISO I2S0_MCLK LLWU_P10 LLWU_P10 BCLK 52 40 28 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_MISO audioUSB_ I2S0_RX_FS SPI0_MOSI SOF_OUT 53 — — PTC8 CMP0_IN2 CMP0_IN2 PTC8 I2C0_SCL TPM0_CH4 I2S0_MCLK 54 — — PTC9 CMP0_IN3 CMP0_IN3 PTC9 I2C0_SDA TPM0_CH5 I2S0_RX_ BCLK 55 — — PTC10 DISABLED PTC10 I2C1_SCL I2S0_RX_FS 56 — — PTC11 DISABLED PTC11 I2C1_SDA I2S0_RXD0 57 41 — PTD0 DISABLED PTD0 SPI0_PCS0 TPM0_CH0 58 42 — PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK TPM0_CH1 59 43 — PTD2 DISABLED PTD2 SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO 60 44 — PTD3 DISABLED PTD3 SPI0_MISO UART2_TX TPM0_CH3 SPI0_MOSI 61 45 29 PTD4/ DISABLED PTD4/ SPI1_PCS0 UART2_RX TPM0_CH4 LLWU_P14 LLWU_P14 50 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Pinout 64 48 32 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 LQFP QFN QFN 62 46 30 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI1_SCK UART2_TX TPM0_CH5 63 47 31 PTD6/ ADC0_SE7b ADC0_SE7b PTD6/ SPI1_MOSI UART0_RX SPI1_MISO LLWU_P15 LLWU_P15 64 48 32 PTD7 DISABLED PTD7 SPI1_MISO UART0_TX SPI1_MOSI 5.2 KL26 pinouts The following figures show the pinout diagrams for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see KL26 Signal Multiplexing and Pin Assignments. Kinetis KL26 Sub-Family, Rev5 08/2014. 51 Freescale Semiconductor, Inc.

Pinout 5 4 0 1 1 1 9 8 P P P P P U_ U_ U_ U_ U_ W W W W W L L L L L 7 6/L 5 4/L 3 2 1 0 11 10 9 8 7 6/L 5/L 4/L D D D D D D D D C C C C C C C C T T T T T T T T T T T T T T T T P P P P P P P P P P P P P P P P 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PTE0 1 48 VDD PTE1 2 47 VSS VDD 3 46 PTC3/LLWU_P7 VSS 4 45 PTC2 USB0_DP 5 44 PTC1/LLWU_P6/RTC_CLKIN USB0_DM 6 43 PTC0 VOUT33 7 42 PTB19 VREGIN 8 41 PTB18 PTE20 9 40 PTB17 PTE21 10 39 PTB16 PTE22 11 38 PTB3 PTE23 12 37 PTB2 VDDA 13 36 PTB1 VREFH 14 35 PTB0/LLWU_P5 VREFL 15 34 PTA20 VSSA 16 33 PTA19 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PTE29 PTE30 PTE31 PTE24 PTE25 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 PTA12 PTA13 VDD VSS PTA18 Figure 22. KL26 64-pin LQFP pinout diagram 52 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Pinout 5 4 0 1 1 1 9 8 P P P P P _ _ _ _ _ U U U U U W W W W W L L L L L L L L L L 7 6/ 5 4/ 3 2 1 0 7 6/ 5/ 4/ D D D D D D D D C C C C T T T T T T T T T T T T P P P P P P P P P P P P 48 47 46 45 44 43 42 41 40 39 38 37 VDD 1 36 PTC3/LLWU_P7 VSS 2 35 PTC2 USB0_DP 3 34 PTC1/LLWU_P6/RTC_CLKIN USB0_DM 4 33 PTC0 VOUT33 5 32 PTB17 VREGIN 6 31 PTB16 PTE20 7 30 PTB3 PTE21 8 29 PTB2 VDDA 9 28 PTB1 VREFH 10 27 PTB0/LLWU_P5 VREFL 11 26 PTA20 VSSA 12 25 PTA19 13 14 15 16 17 18 19 20 21 22 23 24 TE29 TE30 TE24 TE25 PTA0 PTA1 PTA2 PTA3 PTA4 VDD VSS TA18 P P P P P Figure 23. KL26 48-pin QFN pinout diagram Kinetis KL26 Sub-Family, Rev5 08/2014. 53 Freescale Semiconductor, Inc.

Ordering parts 5 4 0 1 1 1 9 8 P P P P P _ _ _ _ _ U U U U U W W W W W L L L L L L L L L L 7 6/ 5 4/ 7 6/ 5/ 4/ D D D D C C C C T T T T T T T T P P P P P P P P 32 31 30 29 28 27 26 25 PTE0 1 24 PTC3/LLWU_P7 VSS 2 23 PTC2 USB0_DP 3 22 PTC1/LLWU_P6/RTC_CLKIN USB0_DM 4 21 PTB1 VOUT33 5 20 PTB0/LLWU_P5 VREGIN 6 19 PTA20 VDDA 7 18 PTA19 VSSA 8 17 PTA18 9 10 11 12 13 14 15 16 0 0 1 2 3 4 D S TE3 PTA PTA PTA PTA PTA VD VS P Figure 24. KL26 32-pin QFN pinout diagram 6 Ordering parts 6.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: PKL26 and MKL26 7 Part identification 54 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Part identification 7.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 7.2 Format Part numbers for this device have the following format: Q KL## A FFF R T PP CC N 7.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow • P = Prequalification KL## Kinetis family • KL26 A Key attribute • Z = Cortex-M0+ FFF Program flash memory size • 32 = 32 KB • 64 = 64 KB • 128 = 128 KB R Silicon revision • (Blank) = Main • A = Revision after main T Temperature range (°C) • V = –40 to 105 PP Package identifier • FM = 32 QFN (5 mm x 5 mm) • FT = 48 QFN (7 mm x 7 mm) • LH = 64 LQFP (10 mm x 10 mm) CC Maximum CPU frequency (MHz) • 4 = 48 MHz N Packaging type • R = Tape and reel 7.4 Example This is an example part number: MKL26Z128VFM4 Kinetis KL26 Sub-Family, Rev5 08/2014. 55 Freescale Semiconductor, Inc.

Terminology and guidelines 8 Terminology and guidelines 8.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 8.1.1 Example This is an example of an operating requirement: Symbol Description Min. Max. Unit V 1.0 V core supply 0.9 1.1 V DD voltage 8.2 Definition: Operating behavior Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 8.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 8.3.1 Example This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: — 7 pF digital pins 56 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Terminology and guidelines 8.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. 8.4.1 Example This is an example of an operating rating: Symbol Description Min. Max. Unit V 1.0 V core supply –0.3 1.2 V DD voltage 8.5 Result of exceeding a rating 40 m) 30 p p e ( m s in ti 20 Tsohoen l ikaesl iah ocohda roafc pteerrimstiacn beengt icnhsi pto f aeixlucreee idn corneea soef sit sra oppidelrya atins g ratings. e ur Fail 10 0 Operating rating Measured characteristic Kinetis KL26 Sub-Family, Rev5 08/2014. 57 Freescale Semiconductor, Inc.

Terminology and guidelines 8.6 Relationship between ratings and operating requirements O perating rating (min.) O perating require m ent (min.) O perating require m ent (m ax.) O perating rating (m ax.) Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - No permanent failure - No permanent failure Expected permanent failure - Possible decreased life - Correct operation - Possible decreased life - Possible incorrect operation - Possible incorrect operation –∞ ∞ Operating (power on) H andling rating (min.) H andling rating (m ax.) Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure –∞ ∞ Handling (power off) 8.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 8.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. 58 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Terminology and guidelines 8.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit I Digital I/O weak 10 70 130 µA WP pullup/pulldown current 8.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 T 3500 J 150 °C A) 3000 μ ( 105 °C P O 2500 T D_S 25 °C ID 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 V (V) DD 8.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Kinetis KL26 Sub-Family, Rev5 08/2014. 59 Freescale Semiconductor, Inc.

Revision history Table 41. Typical value conditions Symbol Description Value Unit T Ambient temperature 25 °C A V 3.3 V supply voltage 3.3 V DD 9 Revision history The following table provides a revision history for this document. Table 42. Revision history Rev. No. Date Substantial Changes 3 3/2014 • Updated the front page and restructured the chapters 4 5/2014 • Updated Power consumption operating behaviors • Updated USB electrical specifications • Updated Definition: Operating behavior 5 08/2014 • Updated related source in the front page • Updated Power consumption operating behaviors • Updated the note in USB electrical specifications 60 Kinetis KL26 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express Home Page: or implied copyright licenses granted hereunder to design or fabricate freescale.com any integrated circuits based on the information in this document. Web Support: Freescale reserves the right to make changes without further notice to freescale.com/support any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale, Freescale logo, Energy Efficient Solutions logo, and Kinetis are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. © 2012-2014 Freescale Semiconductor, Inc. Document Number KL26P64M48SF5 Revision 5 08/2014

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: N XP: MKL26Z128VLL4 MKL26Z128VMC4 MKL26Z256VLL4 MKL26Z256VMC4 MKL26Z256VLH4 MKL26Z128VLH4 MKL26Z32VLH4 MKL26Z64VLH4 MKL24Z64VFT4 MKL25Z64VFM4 MKL26Z64VFT4 MKL26Z128VFM4 MKL26Z128VFT4 MKL26Z32VFM4 MKL26Z32VFT4 MKL26Z64VFM4 MKL26Z128VLH4R MKL26Z64VFT4R MKL26Z128VFT4R