NXP Semiconductors Document Number: KL02P32M48SF0 Data Sheet: Technical Data Rev. 5 08/2017 Kinetis KL02 32 KB Flash MKL02ZxxVFG4 48 MHz Cortex-M0+ Based Microcontroller MKL02ZxxVFK4 MKL02ZxxVFM4 Designed with efficiency in mind. Features a size efficient, ultra- small package, energy efficient ARM Cortex-M0+ 32-bit performance. Shares the comprehensive enablement and scalability of the Kinetis family. This product offers: 16-pin QFN (FG) 24-pin QFN (FK) 3 x 3 x 0.65 Pitch 0.5 4 x 4 x 1 Pitch 0.5 mm • Run power consumption down to 36 μA/MHz in very low mm power run mode • Static power consumption down to 2 μA with full state retention and 4 μs wakeup • Ultra-efficient Cortex-M0+ processor running up to 48 MHz with industry leading throughput 32-pin QFN (FM) • Memory option is up to 32 KB flash and 4 KB RAM 5 x 5 x 1 Pitch 0.5 mm • Energy-saving architecture is optimized for low power with 90nm TFS technology, clock and power gating techniques, and zero wait state flash memory controller Performance Human-machine interface • 48 MHz ARM® Cortex®-M0+ core • Up to 28 general-purpose input/output (GPIO) Memories and memory interfaces Communication interfaces • Up to 32 KB program flash memory • One 8-bit SPI module • Up to 4 KB SRAM • One low power UART module • Two I2C module System peripherals • Nine low-power modes to provide power optimization Analog Modules based on application requirements • 12-bit SAR ADC • COP Software watchdog • Analog comparator (CMP) containing a 6-bit DAC • SWD debug interface and Micro Trace Buffer and programmable reference input • Bit Manipulation Engine Timers Clocks • Two 2-channel Timer/PWM modules • 32 kHz to 40 kHz crystal oscillator • 16-bit low-power timer (LPTMR) • Multi-purpose clock source • 1 kHz LPO clock Security and integrity modules • 80-bit unique identification number per chip Operating Characteristics • Voltage range: 1.71 to 3.6 V • Flash write voltage range: 1.71 to 3.6 V • Temperature range (ambient): -40 to 105°C NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

Ordering Information 1 Part Number Memory Maximum number of I\O's Flash (KB) SRAM (KB) MKL02Z8VFG4 8 1 14 MKL02Z16VFG4 16 2 14 MKL02Z32VFG4 32 4 14 MKL02Z16VFK4 16 2 22 MKL02Z32VFK4 32 4 22 MKL02Z16VFM4 16 2 28 MKL02Z32VFM4 32 4 28 1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search. Related Resources Type Description Resource Selector Guide The NXP Solution Advisor is a web-based tool that features Solution Advisor interactive application wizards and a dynamic product selector. Product Brief The Product Brief contains concise overview/summary information to KL0XPB1 enable quick evaluation of a device for design suitability. Reference The Reference Manual contains a comprehensive description of the KL02P32M48SF0RM1 Manual structure and function (operation) of a device. Data Sheet The Data Sheet includes electrical characteristics and signal KL02P32M48SF01 connections. Chip Errata The chip mask set Errata provides additional or corrective KINETIS_L_xN33H2 information for a particular device mask set. Package Package dimensions are provided in package drawings. QFN 16-pin: 98ASA00525D1 drawing QFN 24-pin: 98ASA00474D1 QFN 32-pin: 98ASA00473D1 1. To find the associated resource, go to http://www.nxp.com and perform a search using this term. 2. To find the associated resource, go to http://www.nxp.com and perform a search using this term with the “x” replaced by the revision of the device you are using. Figure 1 shows the functional modules in the chip. 2 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

Kinetis KL02 Family ARM Cortex-M0+ System Memories and Clocks Core Memory Interfaces Internal Frequency- Debug watchdog Program locked loop interfaces flash Low BME frequency Interrupt oscillator controller RAM Internal reference clocks MTB Security Analog Timers Communication Human-Machine and Integrity Interfaces Interface (HMI) Internal 12-bit ADC Timers watchdog x1 2x2ch GPIOs II22CC with xx22 interrupt Analog Low Power comparator x1 Timer Low power UART x1 6-bit DAC SPI x1 Figure 1. Functional block diagram Kinetis KL02 32 KB Flash, Rev. 5 08/2017 3 NXP Semiconductors

Table of Contents 1 Ratings..................................................................................5 3.6 Analog............................................................................24 1.1 Thermal handling ratings...............................................5 3.6.1 ADC electrical specifications.............................24 1.2 Moisture handling ratings...............................................5 3.6.2 CMP and 6-bit DAC electrical specifications.....27 1.3 ESD handling ratings.....................................................5 3.7 Timers............................................................................29 1.4 Voltage and current operating ratings............................5 3.8 Communication interfaces.............................................29 2 General.................................................................................6 3.8.1 SPI switching specifications..............................29 2.1 AC electrical characteristics...........................................6 3.8.2 Inter-Integrated Circuit Interface (I2C) timing....33 2.2 Nonswitching electrical specifications............................6 3.8.3 UART.................................................................35 2.2.1 Voltage and current operating requirements.....7 4 Dimensions...........................................................................35 2.2.2 LVD and POR operating requirements..............7 4.1 Obtaining package dimensions......................................35 2.2.3 Voltage and current operating behaviors...........8 5 Pinout....................................................................................36 2.2.4 Power mode transition operating behaviors......9 5.1 KL02 signal multiplexing and pin assignments..............36 2.2.5 Power consumption operating behaviors..........10 5.2 KL02 pinouts..................................................................37 2.2.6 EMC radiated emissions operating behaviors...15 6 Ordering parts.......................................................................40 2.2.7 EMC Radiated Emissions Web Search 6.1 Determining valid orderable parts..................................40 Procedure boilerplate........................................16 7 Part identification...................................................................40 2.2.8 Capacitance attributes.......................................16 7.1 Description.....................................................................40 2.3 Switching specifications.................................................16 7.2 Format...........................................................................41 2.3.1 Device clock specifications................................16 7.3 Fields.............................................................................41 2.3.2 General switching specifications.......................17 7.4 Example.........................................................................41 2.4 Thermal specifications...................................................17 8 Small package marking.........................................................42 2.4.1 Thermal operating requirements.......................17 9 Terminology and guidelines..................................................42 2.4.2 Thermal attributes..............................................17 9.1 Definition: Operating requirement..................................42 3 Peripheral operating requirements and behaviors................18 9.2 Definition: Operating behavior.......................................43 3.1 Core modules................................................................18 9.3 Definition: Attribute........................................................43 3.1.1 SWD electricals ................................................18 9.4 Definition: Rating...........................................................43 3.2 System modules............................................................20 9.5 Result of exceeding a rating..........................................44 3.3 Clock modules...............................................................20 9.6 Relationship between ratings and operating 3.3.1 MCG specifications............................................20 requirements..................................................................44 3.3.2 Oscillator electrical specifications......................21 9.7 Guidelines for ratings and operating requirements........45 3.4 Memories and memory interfaces.................................22 9.8 Definition: Typical value.................................................45 3.4.1 Flash electrical specifications............................22 9.9 Typical value conditions.................................................46 3.5 Security and integrity modules.......................................24 10 Revision history.....................................................................47 4 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

Ratings 1 Ratings 1.1 Thermal handling ratings Table 1. Thermal handling ratings Symbol Description Min. Max. Unit Notes T Storage temperature –55 150 °C 1 STG T Solder temperature, lead-free — 260 °C 2 SDR 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Table 2. Moisture handling ratings Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD handling ratings Table 3. ESD handling ratings Symbol Description Min. Max. Unit Notes V Electrostatic discharge voltage, human body model –2000 +2000 V 1 HBM V Electrostatic discharge voltage, charged-device –500 +500 V 2 CDM model I Latch-up current at ambient temperature of 105 °C –100 +100 mA 3 LAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. Kinetis KL02 32 KB Flash, Rev. 5 08/2017 5 NXP Semiconductors

General 1.4 Voltage and current operating ratings Table 4. Voltage and current operating ratings Symbol Description Min. Max. Unit V Digital supply voltage –0.3 3.8 V DD I Digital supply current — 120 mA DD V IO pin input voltage –0.3 V + 0.3 V IO DD I Instantaneous maximum current single pin limit (applies to –25 25 mA D all port pins) V Analog supply voltage V – 0.3 V + 0.3 V DDA DD DD 2 General 2.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Low High V IH 80% Input Signal Midpoint1 50% 20% V IL Fall Time Rise Time The midpoint is V + (V - V ) / 2 IL IH IL Figure 2. Input signal measurement reference All digital I/O switching characteristics, unless otherwise specified, assume the output pins have the following characteristics. • C =30 pF loads L • Slew rate disabled • Normal drive strength 2.2 Nonswitching electrical specifications 6 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

General 2.2.1 Voltage and current operating requirements Table 5. Voltage and current operating requirements Symbol Description Min. Max. Unit Notes V Supply voltage 1.71 3.6 V DD V Analog supply voltage 1.71 3.6 V — DDA V – V V -to-V differential voltage –0.1 0.1 V — DD DDA DD DDA V – V V -to-V differential voltage –0.1 0.1 V — SS SSA SS SSA V Input high voltage — IH • 2.7 V ≤ V ≤ 3.6 V 0.7 × V — V DD DD • 1.7 V ≤ V ≤ 2.7 V 0.75 × V — V DD DD V Input low voltage — IL • 2.7 V ≤ V ≤ 3.6 V — 0.35 × V V DD DD • 1.7 V ≤ V ≤ 2.7 V — 0.3 × V V DD DD V Input hysteresis 0.06 × V — V — HYS DD I IO pin negative DC injection current—single pin 1 ICIO –3 — mA • V < V –0.3V IN SS I Contiguous pin DC injection current —regional limit, — ICcont includes sum of negative injection currents of 16 contiguous pins –25 — mA • Negative current injection V Open drain pullup voltage level V V V 2 ODPU DD DD V V voltage required to retain RAM 1.2 — V — RAM DD 1. All I/O pins are internally clamped to V through a ESD protection diode. There is no diode connection to V . If V SS DD IN greater than V (= V -0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If IO_MIN SS this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (V - V )/|I |. IO_MIN IN ICIO 2. Open drain outputs must be pulled to V . DD 2.2.2 LVD and POR operating requirements Table 6. V supply LVD and POR operating requirements DD Symbol Description Min. Typ. Max. Unit Notes V Falling V POR detect voltage 0.8 1.1 1.5 V — POR DD V Falling low-voltage detect threshold — high 2.48 2.56 2.64 V — LVDH range (LVDV = 01) Low-voltage warning thresholds — high range 1 Table continues on the next page... Kinetis KL02 32 KB Flash, Rev. 5 08/2017 7 NXP Semiconductors

General Table 6. V supply LVD and POR operating requirements (continued) DD Symbol Description Min. Typ. Max. Unit Notes V • Level 1 falling (LVWV = 00) 2.62 2.70 2.78 V LVW1H V • Level 2 falling (LVWV = 01) 2.72 2.80 2.88 V LVW2H V • Level 3 falling (LVWV = 10) 2.82 2.90 2.98 V LVW3H V • Level 4 falling (LVWV = 11) 2.92 3.00 3.08 V LVW4H V Low-voltage inhibit reset/recover hysteresis — — ±60 — mV — HYSH high range V Falling low-voltage detect threshold — low 1.54 1.60 1.66 V — LVDL range (LVDV=00) Low-voltage warning thresholds — low range 1 V • Level 1 falling (LVWV = 00) LVW1L 1.74 1.80 1.86 V V • Level 2 falling (LVWV = 01) LVW2L 1.84 1.90 1.96 V V • Level 3 falling (LVWV = 10) LVW3L 1.94 2.00 2.06 V V • Level 4 falling (LVWV = 11) LVW4L 2.04 2.10 2.16 V V Low-voltage inhibit reset/recover hysteresis — — ±40 — mV — HYSL low range V Bandgap voltage reference 0.97 1.00 1.03 V — BG t Internal low power oscillator period — factory 900 1000 1100 μs — LPO trimmed 1. Rising thresholds are falling threshold + hysteresis voltage 2.2.3 Voltage and current operating behaviors Table 7. Voltage and current operating behaviors Symbol Description Min. Max. Unit Notes V Output high voltage — Normal drive pad (except 1, 2 OH RESET) V – 0.5 — V • 2.7 V ≤ V ≤ 3.6 V, I = –5 mA DD DD OH V – 0.5 — V • 1.71 V ≤ V ≤ 2.7 V, I = –2.5 mA DD DD OH V Output high voltage — High drive pad (except 1, 2 OH RESET) V – 0.5 — V • 2.7 V ≤ V ≤ 3.6 V, I = –20 mA DD DD OH V – 0.5 — V • 1.71 V ≤ V ≤ 2.7 V, I = –10 mA DD DD OH I Output high current total for all ports — 100 mA — OHT V Output low voltage — Normal drive pad 1 OL • 2.7 V ≤ V ≤ 3.6 V, I = 5 mA DD OL — 0.5 V • 1.71 V ≤ V ≤ 2.7 V, I = 2.5 mA DD OL — 0.5 V Table continues on the next page... 8 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

General Table 7. Voltage and current operating behaviors (continued) Symbol Description Min. Max. Unit Notes V Output low voltage — High drive pad 1 OL • 2.7 V ≤ V ≤ 3.6 V, I = 20 mA DD OL — 0.5 V • 1.71 V ≤ V ≤ 2.7 V, I = 10 mA DD OL — 0.5 V I Output low current total for all ports — 100 mA — OLT I Input leakage current (per pin) for full temperature — 1 μA 3 IN range I Input leakage current (per pin) at 25 °C — 0.025 μA 3 IN I Input leakage current (total all pins) for full — 41 μA 3 IN temperature range I Hi-Z (off-state) leakage current (per pin) — 1 μA — OZ R Internal pullup resistors 20 50 kΩ 4 PU 1. PTA12, PTA13, PTB0 and PTB1 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When configured as a GPIO output, it acts as a pseudo open drain output. 3. Measured at V = 3.6 V DD 4. Measured at V supply voltage = V min and Vinput = V DD DD SS 2.2.4 Power mode transition operating behaviors All specifications except t and VLLSx→RUN recovery times in the following POR table assume this clock configuration: • CPU and system clocks = 48 MHz • Bus and flash clock = 24 MHz • FEI clock mode POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz. Table 8. Power mode transition operating behaviors Symbol Description Min. Typ. Max. Unit t After a POR event, amount of time from the — — 300 μs 1 POR point V reaches 1.8 V to execution of the first DD instruction across the operating temperature range of the chip. • VLLS0 → RUN — 95 115 μs Table continues on the next page... Kinetis KL02 32 KB Flash, Rev. 5 08/2017 9 NXP Semiconductors

General Table 8. Power mode transition operating behaviors (continued) Symbol Description Min. Typ. Max. Unit • VLLS1 → RUN — 93 115 μs • VLLS3 → RUN — 42 53 μs • VLPS → RUN — 4 4.4 μs • STOP → RUN — 4 4.4 μs 1. Normal boot (FTFA_FOPT[LPBOOT]=11). 2.2.5 Power consumption operating behaviors The maximum values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). Table 9. Power consumption operating behaviors Symbol Description Temp. Typ. Max Unit Note I Analog supply current — — See note mA 1 DDA I Run mode current in compute operation - — 3.6 4 mA 2 DD_RUNCO 48 MHz core / 24 MHz flash / bus clock disabled, code of while(1) loop executing from flash, at 3.0 V I Run mode current - 48 MHz core / 24 MHz — 4.3 4.6 mA 2 DD_RUN bus and flash, all peripheral clocks disabled, code executing from flash, at 3.0 V I Run mode current - 48 MHz core / 24 MHz at 25 °C 4.8 5 mA 2, 3 DD_RUN bus and flash, all peripheral clocks at 125 °C 5 5.2 mA enabled, code executing from flash, at 3.0 V I Wait mode current - core disabled / 48 MHz — 2.3 2.6 mA 2 DD_WAIT system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled, at 3.0 V I Wait mode current - core disabled / 24 MHz — 1.8 2.1 mA 2 DD_WAIT system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled, at 3.0 V I Stop mode current with partial stop 2 — 1.3 1.5 mA 2 DD_PSTOP2 clocking option - core and system disabled / 10.5 MHz bus, at 3.0 V Table continues on the next page... 10 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

General Table 9. Power consumption operating behaviors (continued) Symbol Description Temp. Typ. Max Unit Note I Very low power run mode current in — 145 198 µA 4 DD_VLPRCO compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, code executing from flash, at 3.0 V I Very low power run mode current - 4 MHz — 165 217 µA 4 DD_VLPR core / 0.8 MHz bus and flash, all peripheral clocks disabled, code executing from flash, at 3.0 V I Very low power run mode current - 4 MHz — 185 237 µA 3, 4 DD_VLPR core / 0.8 MHz bus and flash, all peripheral clocks enabled, code executing from flash, at 3.0 V I Very low power wait mode current - core — 86 141 µA 4 DD_VLPW disabled / 4 MHz system / 0.8 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled, at 3.0 V I Stop mode current at 3.0 V at 25 °C 230 268 µA — DD_STOP at 50 °C 238 301 µA at 70 °C 259 307 µA at 85 °C 290 352 µA at 105 °C 341 437 µA I Very-low-power stop mode current at 3.0 V at 25 °C 2.3 4.28 µA — DD_VLPS at 50 °C 4.75 8.29 µA at 70 °C 10.1 17.63 µA at 85 °C 20.23 33.55 µA at 105 °C 40.54 64.75 µA I Very low-leakage stop mode 3 current at at 25 °C 1.12 1.33 µA — DD_VLLS3 3.0 V at 50 °C 1.59 2.12 µA at 70 °C 2.81 3.57 µA at 85 °C 5.26 6.45 µA at 105 °C 10.82 13.59 µA I Very low-leakage stop mode 1 current at at 25 °C 0.58 0.69 µA — DD_VLLS1 3.0 V at 50 °C 0.9 1.04 µA at 70 °C 1.68 2.02 µA at 85 °C 3.51 4.05 µA at 105 °C 7.89 9.42 µA I Very low-leakage stop mode 0 current at 25 °C 0.3 0.4 µA — DD_VLLS0 (SMC_STOPCTRL[PORPO] = 0) at 3.0 V at 50 °C 0.62 0.75 µA at 70 °C 1.38 1.71 µA at 85 °C 3.16 3.71 µA at 105 °C 7.44 8.98 µA Table continues on the next page... Kinetis KL02 32 KB Flash, Rev. 5 08/2017 11 NXP Semiconductors

General Table 9. Power consumption operating behaviors (continued) Symbol Description Temp. Typ. Max Unit Note I Very low-leakage stop mode 0 current at 25 °C 0.12 0.23 µA 5 DD_VLLS0 (SMC_STOPCTRL[PORPO] = 1) at 3.0 V at 50 °C 0.44 0.58 µA at 70 °C 1.21 1.55 µA at 85 °C 3.01 3.57 µA at 105 °C 7.34 8.89 µA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. MCG configured for FEI mode. 3. Incremental current consumption from peripheral activity is not included. 4. MCG configured for BLPI mode. 5. No brownout. Table 10. Low power mode peripheral adders — typical value Symbol Description Temperature (°C) Unit -40 25 50 70 85 105 I 4 MHz internal reference clock (IRC) adder. 56 56 56 56 56 56 µA IREFSTEN4MHz Measured by entering STOP or VLPS mode with 4 MHz IRC enabled. I 32 kHz internal reference clock (IRC) adder. 52 52 52 52 52 52 µA IREFSTEN32KHz Measured by entering STOP mode with the 32 kHz IRC enabled. I External 32 kHz crystal clock VLLS1 440 490 540 560 570 580 nA EREFSTEN32KHz adder by means of the VLLS3 440 490 540 560 570 580 OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured VLPS 510 560 560 560 610 680 by entering all modes with the STOP 510 560 560 560 610 680 crystal enabled. I CMP peripheral adder measured by placing 22 22 22 22 22 22 µA CMP the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. I UART peripheral adder MCGIRCLK 66 66 66 66 66 66 µA UART measured by placing the (4 MHz device in STOP or VLPS internal mode with selected clock reference source waiting for RX data at clock) 115200 baud rate. Includes selected clock source power consumption. I TPM peripheral adder MCGIRCLK 86 86 86 86 86 86 µA TPM measured by placing the (4 MHz device in STOP or VLPS internal mode with selected clock reference source configured for output clock) compare generating 100 Hz Table continues on the next page... 12 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

General Table 10. Low power mode peripheral adders — typical value (continued) Symbol Description Temperature (°C) Unit -40 25 50 70 85 105 clock signal. No load is OSCERCLK 235 256 265 274 280 287 placed on the I/O generating (4 MHz the clock signal. Includes external selected clock source and I/O crystal) switching currents. I Bandgap adder when BGEN bit is set and 45 45 45 45 45 45 µA BG device is placed in VLPx, or VLLSx mode. I ADC peripheral adder combining the 366 366 366 366 366 366 µA ADC measured values at V and V by placing DD DDA the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 2.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: • MCG in FBE for run mode, and BLPE for VLPR mode • No GPIOs toggled • Code execution from flash with cache enabled • For the ALLOFF curve, all peripheral clocks are disabled except FTFA Kinetis KL02 32 KB Flash, Rev. 5 08/2017 13 NXP Semiconductors

General Run Mode Current VS Core Frequency Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE 7.00E-03 6.00E-03 5.00E-03 )A ( D D V n 4.00E-03 o n All Peripheral CLK Gates o itp All Off m us 3.00E-03 All On n o C tn e rru 2.00E-03 C 1.00E-03 000.00E+00 CLK Ratio '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2 Flash-Core 1 2 3 4 6 12 24 48 Core Freq (MHz) Figure 3. Run mode supply current vs. core frequency 14 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

General VLPR Mode Current VS Core Frequency Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE 350.00E-06 300.00E-06 250.00E-06 )A ( D D 200.00E-06 V All Peripheral CLK Gates n o n o All Off itpm 150.00E-06 All On u s n o C tn 100.00E-06 e rru C 50.00E-06 000.00E+00 CLK Ratio '1-1 '1-2 '1-2 '1-4 Flash-Core 1 2 4 Core Freq (MHz) Figure 4. VLPR mode current vs. core frequency 2.2.6 EMC radiated emissions operating behaviors Table 11. EMC radiated emissions operating behaviors for 32-pin QFN package Symbol Description Frequency Typ. Unit Notes band (MHz) V Radiated emissions voltage, band 1 0.15–50 7 dBμV 1, 2 RE1 V Radiated emissions voltage, band 2 50–150 6 dBμV RE2 V Radiated emissions voltage, band 3 150–500 4 dBμV RE3 V Radiated emissions voltage, band 4 500–1000 4 dBμV RE4 V IEC level 0.15–1000 N — 2, 3 RE_IEC 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. Kinetis KL02 32 KB Flash, Rev. 5 08/2017 15 NXP Semiconductors

General 2. V = 3.3 V, T = 25 °C, f = 32.768 kHz (crystal), f = 48 MHz, f = 24 MHz DD A OSC SYS BUS 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 2.2.7 EMC Radiated Emissions Web Search Procedure boilerplate To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.nxp.com. 2. Perform a keyword search for "EMC design" 2.2.8 Capacitance attributes Table 12. Capacitance attributes Symbol Description Min. Max. Unit C Input capacitance — 7 pF IN 2.3 Switching specifications 2.3.1 Device clock specifications Table 13. Device clock specifications Symbol Description Min. Max. Unit Normal run mode f System and core clock — 48 MHz SYS f Bus clock — 24 MHz BUS f Flash clock — 24 MHz FLASH f LPTMR clock — 24 MHz LPTMR VLPR and VLPS modes1 f System and core clock — 4 MHz SYS f Bus clock — 1 MHz BUS f Flash clock — 1 MHz FLASH f LPTMR clock2 — 24 MHz LPTMR f External reference clock — 32.768 kHz ERCLK f LPTMR external reference clock — 16 MHz LPTMR_ERCLK f TPM asynchronous clock — 8 MHz TPM Table continues on the next page... 16 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

General Table 13. Device clock specifications (continued) Symbol Description Min. Max. Unit f UART0 asynchronous clock — 8 MHz UART0 1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN or from VLPR. 2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin. 2.3.2 General switching specifications These general-purpose specifications apply to all signals configured for GPIO and UART signals. Table 14. General switching specifications Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) 1.5 — Bus clock 1 — Synchronous path cycles External RESET and NMI pin interrupt pulse width — 100 — ns 2 Asynchronous path GPIO pin interrupt pulse width — Asynchronous path 16 — ns 2 Port rise and fall time — 36 ns 3 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 75 pF load 2.4 Thermal specifications 2.4.1 Thermal operating requirements Table 15. Thermal operating requirements Symbol Description Min. Max. Unit Notes T Die junction temperature –40 125 °C J T Ambient temperature –40 105 °C 1 A 1. Maximum T can be exceeded only if the user ensures that T does not exceed the maximum. The simplest method to A J determine T is: T = T + θ × chip power dissipation. J J A JA Kinetis KL02 32 KB Flash, Rev. 5 08/2017 17 NXP Semiconductors

Peripheral operating requirements and behaviors 2.4.2 Thermal attributes Table 16. Thermal attributes Board type Symbol Description 16 QFN 24 QFN 32 QFN Unit Notes Single-layer (1S) R Thermal resistance, junction to 141 114 101 °C/W 1 θJA ambient (natural convection) Four-layer (2s2p) R Thermal resistance, junction to 55 42 35 °C/W θJA ambient (natural convection) Single-layer (1S) R Thermal resistance, junction to 120 96 84 °C/W θJMA ambient (200 ft./min. air speed) Four-layer (2s2p) R Thermal resistance, junction to 49 36 30 °C/W θJMA ambient (200 ft./min. air speed) — R Thermal resistance, junction to 27 19 15 °C/W 2 θJB board — R Thermal resistance, junction to 20 3.4 3.4 °C/W 3 θJC case — Ψ Thermal characterization 23 15 11 °C/W 4 JT parameter, junction to package top outside center (natural convection) 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). 3 Peripheral operating requirements and behaviors 3.1 Core modules 3.1.1 SWD electricals Table 17. SWD full voltage range electricals Symbol Description Min. Max. Unit Operating voltage 1.71 3.6 V J1 SWD_CLK frequency of operation Table continues on the next page... 18 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

Peripheral operating requirements and behaviors Table 17. SWD full voltage range electricals (continued) Symbol Description Min. Max. Unit • Serial wire debug 0 25 MHz J2 SWD_CLK cycle period 1/J1 — ns J3 SWD_CLK clock pulse width • Serial wire debug 20 — ns J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J2 J3 J3 SWD_CLK (input) J4 J4 Figure 5. Serial wire clock input timing SWD_CLK J9 J10 SWD_DIO Input data valid J11 SWD_DIO Output data valid J12 SWD_DIO J11 SWD_DIO Output data valid Figure 6. Serial wire data timing Kinetis KL02 32 KB Flash, Rev. 5 08/2017 19 NXP Semiconductors

Peripheral operating requirements and behaviors 3.2 System modules There are no specifications necessary for the device's system modules. 3.3 Clock modules 3.3.1 MCG specifications Table 18. MCG specifications Symbol Description Min. Typ. Max. Unit Notes f Internal reference frequency (slow clock) — — 32.768 — kHz ints_ft factory trimmed at nominal V and 25 °C DD f Internal reference frequency (slow clock) — 31.25 — 39.0625 kHz ints_t user trimmed Δ Resolution of trimmed average DCO output — ± 0.3 ± 0.6 %f 1 fdco_res_t dco frequency at fixed voltage and temperature — using C3[SCTRIM] and C4[SCFTRIM] Δf Total deviation of trimmed average DCO output — +0.5/-0.7 ± 3 %f 1, 2 dco_t dco frequency over voltage and temperature Δf Total deviation of trimmed average DCO output — ± 0.4 ± 1.5 %f 1, 2 dco_t dco frequency over fixed voltage and temperature range of 0–70 °C f Internal reference frequency (fast clock) — — 4 — MHz intf_ft factory trimmed at nominal V and 25 °C DD Δf Frequency deviation of internal reference clock — +1/-2 ± 3 %f 2 intf_ft intf_ft (fast clock) over temperature and voltage — factory trimmed at nominal V and 25 °C DD f Internal reference frequency (fast clock) — user 3 — 5 MHz intf_t trimmed at nominal V and 25 °C DD f Loss of external clock minimum frequency — (3/5) x — — kHz loc_low RANGE = 00 f ints_t f Loss of external clock minimum frequency — (16/5) x — — kHz loc_high RANGE = 01, 10, or 11 f ints_t FLL f FLL reference frequency range 31.25 — 39.0625 kHz fll_ref f DCO output Low range (DRS = 00) 20 20.97 25 MHz 3, 4 dco frequency range 640 × f fll_ref Mid range (DRS = 01) 40 41.94 48 MHz 1280 × f fll_ref f DCO output Low range (DRS = 00) — 23.99 — MHz 5, 6 dco_t_DMX3 frequency 2 Table continues on the next page... 20 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

Peripheral operating requirements and behaviors Table 18. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes 732 × f fll_ref Mid range (DRS = 01) — 47.97 — MHz 1464 × f fll_ref J FLL period jitter — 180 — ps 7 cyc_fll • f = 48 MHz VCO t FLL target frequency acquisition time — — 1 ms 8 fll_acquire 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. The deviation is relative to the factory trimmed frequency at nominal V and 25 °C, f . DD ints_ft 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. 4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation (Δf ) over voltage and temperature must be considered. dco_t 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3.3.2 Oscillator electrical specifications 3.3.2.1 Oscillator DC electrical specifications Table 19. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit Notes V Supply voltage 1.71 — 3.6 V DD I Supply current — low-power mode (HGO=0) 1 DDOSC • 32 kHz — 500 — nA I Supply current — high gain mode (HGO=1) 1 DDOSC • 32 kHz — 25 — μA C EXTAL load capacitance — — — 2, 3 x C XTAL load capacitance — — — 2, 3 y R Feedback resistor — low-frequency, low-power — — — MΩ 2, 4 F mode (HGO=0) Feedback resistor — low-frequency, high-gain — 10 — MΩ mode (HGO=1) R Series resistor — low-frequency, low-power — — — kΩ S mode (HGO=0) Table continues on the next page... Kinetis KL02 32 KB Flash, Rev. 5 08/2017 21 NXP Semiconductors

Peripheral operating requirements and behaviors Table 19. Oscillator DC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit Notes Series resistor — low-frequency, high-gain — 200 — kΩ mode (HGO=1) V 5 Peak-to-peak amplitude of oscillation (oscillator — 0.6 — V pp mode) — low-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator — V — V DD mode) — low-frequency, high-gain mode (HGO=1) 1. V =3.3 V, Temperature =25 °C DD 2. See crystal or resonator manufacturer's recommendation 3. C ,C can be provided by using either the integrated capacitors or by using external components. x y 4. When low power mode is selected, R is integrated and must not be attached externally. F 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.2.2 Oscillator frequency specifications Table 20. Oscillator frequency specifications Symbol Description Min. Typ. Max. Unit Notes f Oscillator crystal or resonator frequency — low 32 — 40 kHz osc_lo frequency mode (MCG_C2[RANGE]=00) t Input clock duty cycle (external clock mode) 40 50 60 % dc_extal t Crystal startup time — 32 kHz low-frequency, — — ms 1, 2 cst low-power mode (HGO=0) Crystal startup time — 32 kHz low-frequency, — — ms high-gain mode (HGO=1) 1. Proper PC board layout procedures must be followed to achieve specifications. 2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 3.4 Memories and memory interfaces 3.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 22 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

Peripheral operating requirements and behaviors 3.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 21. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit Notes t Longword Program high-voltage time — 7.5 18 μs — hvpgm4 t Sector Erase high-voltage time — 13 113 ms 1 hversscr t Erase All high-voltage time — 52 452 ms 1 hversall 1. Maximum time based on expectations at cycling end-of-life. 3.4.1.2 Flash timing specifications — commands Table 22. Flash command timing specifications Symbol Description Min. Typ. Max. Unit Notes t Read 1s Section execution time (flash sector) — — 60 μs 1 rd1sec1k t Program Check execution time — — 45 μs 1 pgmchk t Read Resource execution time — — 30 μs 1 rdrsrc t Program Longword execution time — 65 145 μs — pgm4 t Erase Flash Sector execution time — 14 114 ms 2 ersscr t Read 1s All Blocks execution time — — 0.5 ms — rd1all t Read Once execution time — — 25 μs 1 rdonce t Program Once execution time — 65 — μs — pgmonce t Erase All Blocks execution time — 61 500 ms 2 ersall t Verify Backdoor Access Key execution time — — 30 μs 1 vfykey 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 Flash high voltage current behaviors Table 23. Flash high voltage current behaviors Symbol Description Min. Typ. Max. Unit I Average current adder during high voltage — 2.5 6.0 mA DD_PGM flash programming operation I Average current adder during high voltage — 1.5 4.0 mA DD_ERS flash erase operation Kinetis KL02 32 KB Flash, Rev. 5 08/2017 23 NXP Semiconductors

Peripheral operating requirements and behaviors 3.4.1.4 Reliability specifications Table 24. NVM reliability specifications Symbol Description Min. Typ.1 Max. Unit Notes Program Flash t Data retention after up to 10 K cycles 5 50 — years — nvmretp10k t Data retention after up to 1 K cycles 20 100 — years — nvmretp1k n Cycling endurance 10 K 50 K — cycles 2 nvmcycp 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ T ≤ 125 °C. j 3.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 3.6 Analog 3.6.1 ADC electrical specifications All ADC channels meet the 12-bit single-ended accuracy specifications. 3.6.1.1 12-bit ADC operating conditions Table 25. 12-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes V Supply voltage Absolute 1.71 — 3.6 V — DDA ΔV Supply voltage Delta to V (V – V ) -100 0 +100 mV 2 DDA DD DD DDA ΔV Ground voltage Delta to V (V – V ) -100 0 +100 mV 2 SSA SS SS SSA V ADC reference 1.13 V V V 3 REFH DDA DDA voltage high V ADC reference V V V V 3 REFL SSA SSA SSA voltage low V Input voltage V — V V — ADIN REFL REFH C Input • 8-bit / 10-bit / 12-bit — 4 5 pF — ADIN capacitance modes R Input series — 2 5 kΩ — ADIN resistance Table continues on the next page... 24 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

Peripheral operating requirements and behaviors Table 25. 12-bit ADC operating conditions (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes R Analog source 12-bit modes 4 AS resistance f < 4 MHz — — 5 kΩ (external) ADCK f ADC conversion ≤ 12-bit mode 1.0 — 18.0 MHz 5 ADCK clock frequency C ADC conversion ≤ 12-bit modes 6 rate rate No ADC hardware averaging 20.000 — 818.330 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume V = 3.0 V, Temp = 25 °C, f = 1.0 MHz, unless otherwise stated. Typical values are for DDA ADCK reference only, and are not tested in production. 2. DC potential difference. 3. For packages without dedicated VREFH and VREFL pins, V is internally tied to V , and V is internally tied REFH DDA REFL to V . SSA 4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The R /C time constant should be kept to < 1 ns. AS AS 5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED Pad ZAS leakage CHANNEL SELECT due to CIRCUIT ADC SAR RAS input RADIN ENGINE protection VADIN VAS CAS RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure 7. ADC input impedance equivalency diagram Kinetis KL02 32 KB Flash, Rev. 5 08/2017 25 NXP Semiconductors

Peripheral operating requirements and behaviors 3.6.1.2 12-bit ADC electrical characteristics Table 26. 12-bit ADC characteristics (V = V , V = V ) REFH DDA REFL SSA Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes I Supply current 0.215 — 1.7 mA 3 DDA_ADC ADC • ADLPC = 1, ADHSC = 1.2 2.4 3.9 MHz t = ADACK asynchronous 0 1/f 2.4 4.0 6.1 MHz ADACK clock source • ADLPC = 1, ADHSC = 3.0 5.2 7.3 MHz 1 f 4.4 6.2 9.5 MHz ADACK • ADLPC = 0, ADHSC = 0 • ADLPC = 0, ADHSC = 1 Sample Time See Reference Manual chapter for sample times TUE Total unadjusted • 12-bit modes — ±4 ±6.8 LSB4 5 error • <12-bit modes — ±1.4 ±2.1 DNL Differential non- • 12-bit modes — ±0.7 –1.1 to LSB4 5 linearity +1.9 • <12-bit modes — ±0.2 –0.3 to 0.5 INL Integral non- • 12-bit modes — ±1.0 –2.7 to LSB4 5 linearity +1.9 • <12-bit modes — ±0.5 –0.7 to +0.5 E Full-scale error • 12-bit modes — –4 –5.4 LSB4 V = FS ADIN V 5 • <12-bit modes — –1.4 –1.8 DDA E Quantization • 12-bit modes — — ±0.5 LSB4 Q error E Input leakage I × R mV I = IL In AS In error leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor Across the full temperature 1.55 1.62 1.69 mV/°C 6 slope range of the device V Temp sensor 25 °C 706 716 726 mV 6 TEMP25 voltage 1. All accuracy numbers assume the ADC is calibrated with V = V REFH DDA 2. Typical values assume V = 3.0 V, Temp = 25 °C, f = 2.0 MHz unless otherwise stated. Typical values are for DDA ADCK reference only and are not tested in production. 26 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

Peripheral operating requirements and behaviors 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (V - V )/2N REFH REFL 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. ADC conversion clock < 3 MHz Typical ADC 12-bit Single Ended ENOB vs ADC Clock 100Hz, 90% FS Sine Input 11.9 11.8 11.7 11.6 11.5 11.4 11.3 11.2 11.1 B 11 O N 10.9 E 10.8 10.7 10.6 10.5 10.4 10.3 10.2 Hardware Averaging Disabled 10.1 Averaging of 8 samples Averaging of 32 samples 10 0 2 4 6 8 10 12 14 16 18 20 22 ADC Clock Frequency (MHz) Figure 8. Typical ENOB vs. ADC_CLK for 12-bit single-ended mode 3.6.2 CMP and 6-bit DAC electrical specifications Table 27. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit V Supply voltage 1.71 — 3.6 V DD I Supply current, High-speed mode (EN=1, — — 200 μA DDHS PMODE=1) I Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA DDLS V Analog input voltage V – 0.3 — V V AIN SS DD V Analog input offset voltage — — 20 mV AIO V Analog comparator hysteresis1 H • CR0[HYSTCTR] = 00 — 5 — mV • CR0[HYSTCTR] = 01 — 10 — mV • CR0[HYSTCTR] = 10 — 20 — mV • CR0[HYSTCTR] = 11 — 30 — mV V Output high V – 0.5 — — V CMPOh DD V Output low — — 0.5 V CMPOl Table continues on the next page... Kinetis KL02 32 KB Flash, Rev. 5 08/2017 27 NXP Semiconductors

Peripheral operating requirements and behaviors Table 27. Comparator and 6-bit DAC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit t Propagation delay, high-speed mode (EN=1, 20 50 200 ns DHS PMODE=1) t Propagation delay, low-speed mode (EN=1, 80 250 600 ns DLS PMODE=0) Analog comparator initialization delay2 — — 40 μs I 6-bit DAC current adder (enabled) — 7 — μA DAC6b INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to V –0.6 V. DD 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = V /64 reference 0.08 0.07 0.06 ) 0.05 HYSTCT R V Setting ( s eri 00 r 0.04 e 01 st y 1100 H P 0.03 11 M C 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) 28 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

Peripheral operating requirements and behaviors 0.18 0.16 0.14 0.12 HYSTC TR ) V Setting ( s esi 0.1 00 r e 01 st y 0.08 1100 H P 11 M C 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin le vel (V) Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 3.7 Timers See General switching specifications. 3.8 Communication interfaces 3.8.1 SPI switching specifications The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. See the SPI chapter of the chip's Reference Manual for information about the modified transfer formats used for communicating with slower peripheral devices. All timing is shown with respect to 20% V and 80% V thresholds, unless noted, DD DD as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins. Kinetis KL02 32 KB Flash, Rev. 5 08/2017 29 NXP Semiconductors

Peripheral operating requirements and behaviors Table 28. SPI master mode timing on slew rate disabled pads Num. Symbol Description Min. Max. Unit Note 1 f Frequency of operation f /2048 f /2 Hz 1 op periph periph 2 t SPSCK period 2 x t 2048 x ns 2 SPSCK periph t periph 3 t Enable lead time 1/2 — t — Lead SPSCK 4 t Enable lag time 1/2 — t — Lag SPSCK 5 t Clock (SPSCK) high or low time t – 30 1024 x ns — WSPSCK periph t periph 6 t Data setup time (inputs) 20 — ns — SU 7 t Data hold time (inputs) 0 — ns — HI 8 t Data valid (after SPSCK edge) — 12 ns — v 9 t Data hold time (outputs) 0 — ns — HO 10 t Rise time input — t – 25 ns — RI periph t Fall time input FI 11 t Rise time output — 25 ns — RO t Fall time output FO 1. For SPI0, f is the bus clock (f ). periph BUS 2. t = 1/f periph periph Table 29. SPI master mode timing on slew rate enabled pads Num. Symbol Description Min. Max. Unit Note 1 f Frequency of operation f /2048 f /2 Hz 1 op periph periph 2 t SPSCK period 2 x t 2048 x ns 2 SPSCK periph t periph 3 t Enable lead time 1/2 — t — Lead SPSCK 4 t Enable lag time 1/2 — t — Lag SPSCK 5 t Clock (SPSCK) high or low time t – 30 1024 x ns — WSPSCK periph t periph 6 t Data setup time (inputs) 96 — ns — SU 7 t Data hold time (inputs) 0 — ns — HI 8 t Data valid (after SPSCK edge) — 52 ns — v 9 t Data hold time (outputs) 0 — ns — HO 10 t Rise time input — t – 25 ns — RI periph t Fall time input FI 11 t Rise time output — 36 ns — RO t Fall time output FO 1. For SPI0, f is the bus clock (f ). periph BUS 2. t = 1/f periph periph 30 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

Peripheral operating requirements and behaviors SS1 (OUTPUT) 3 2 10 11 4 SPSCK 5 (CPOL=0) (OUTPUT) 5 10 11 SPSCK (CPOL=1) (OUTPUT) 6 7 MISO MSB IN2 BIT 6 . . . 1 LSB IN (INPUT) 8 9 MOSI (OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 11. SPI master mode timing (CPHA = 0) SS1 (OUTPUT) 2 3 10 11 4 SPSCK (CPOL=0) (OUTPUT) 5 5 10 11 SPSCK (CPOL=1) (OUTPUT) 6 7 MISO (INPUT) MSB IN2 BIT 6 . . . 1 LSB IN 8 9 MOSI (OUTPUT) PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 12. SPI master mode timing (CPHA = 1) Table 30. SPI slave mode timing on slew rate disabled pads Num. Symbol Description Min. Max. Unit Note 1 f Frequency of operation 0 f /4 Hz 1 op periph 2 t SPSCK period 4 x t — ns 2 SPSCK periph 3 t Enable lead time 1 — t — Lead periph Table continues on the next page... Kinetis KL02 32 KB Flash, Rev. 5 08/2017 31 NXP Semiconductors 38 <<CLASSIFICATION>> <<NDA MESSAGE>>

Peripheral operating requirements and behaviors Table 30. SPI slave mode timing on slew rate disabled pads (continued) Num. Symbol Description Min. Max. Unit Note 4 t Enable lag time 1 — t — Lag periph 5 t Clock (SPSCK) high or low time t – 30 — ns — WSPSCK periph 6 t Data setup time (inputs) 3 — ns — SU 7 t Data hold time (inputs) 7 — ns — HI 8 t Slave access time 23 t ns 3 a periph 9 t Slave MISO disable time 23 t ns 4 dis periph 10 t Data valid (after SPSCK edge) — 25.7 ns — v 11 t Data hold time (outputs) 0 — ns — HO 12 t Rise time input — t – 25 ns — RI periph t Fall time input FI 13 t Rise time output — 25 ns — RO t Fall time output FO 1. For SPI0, f is the bus clock (f ). periph BUS 2. t = 1/f periph periph 3. Time to data active from high-impedance state 4. Hold time to high-impedance state Table 31. SPI slave mode timing on slew rate enabled pads Num. Symbol Description Min. Max. Unit Note 1 f Frequency of operation 0 f /4 Hz 1 op periph 2 t SPSCK period 4 x t — ns 2 SPSCK periph 3 t Enable lead time 1 — t — Lead periph 4 t Enable lag time 1 — t — Lag periph 5 t Clock (SPSCK) high or low time t – 30 — ns — WSPSCK periph 6 t Data setup time (inputs) 2 — ns — SU 7 t Data hold time (inputs) 7 — ns — HI 8 t Slave access time — t ns 3 a periph 9 t Slave MISO disable time — t ns 4 dis periph 10 t Data valid (after SPSCK edge) — 122 ns — v 11 t Data hold time (outputs) 0 — ns — HO 12 t Rise time input — t – 25 ns — RI periph t Fall time input FI 13 t Rise time output — 36 ns — RO t Fall time output FO 1. For SPI0, f is the bus clock (f ). periph BUS 2. t = 1/f periph periph 3. Time to data active from high-impedance state 4. Hold time to high-impedance state 32 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

Peripheral operating requirements and behaviors SS (INPUT) 2 12 13 4 SPSCK (CPOL=0) (INPUT) 3 5 5 SPSCK 12 13 (CPOL=1) (INPUT) 9 8 10 11 11 MISO see SEE (OUTPUT) note SLAVE MSB BIT 6 . . . 1 SLAVE LSB OUT NOTE 6 7 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: Not defined Figure 13. SPI slave mode timing (CPHA = 0) SS (INPUT) 2 4 3 12 13 SPSCK (CPOL=0) (INPUT) 5 5 12 13 SPSCK (CPOL=1) (INPUT) 10 11 9 MISO see SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT (OUTPUT) note 8 6 7 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: Not defined Figure 14. SPI slave mode timing (CPHA = 1) Kinetis KL02 32 KB Flash, Rev. 5 08/2017 33 NXP Semiconductors

Peripheral operating requirements and behaviors 3.8.2 Inter-Integrated Circuit Interface (I2C) timing Table 32. I2C timing Characteristic Symbol Standard Mode Fast Mode Unit Minimum Maximum Minimum Maximum SCL Clock Frequency f 0 1001 0 4002 kHz SCL Hold time (repeated) START condition. t ; STA 4 — 0.6 — µs HD After this period, the first clock pulse is generated. LOW period of the SCL clock t 4.7 — 1.25 — µs LOW HIGH period of the SCL clock t 4 — 0.6 — µs HIGH Set-up time for a repeated START t ; STA 4.7 — 0.6 — µs SU condition Data hold time for I2C bus devices t ; DAT 03 3.454 05 0.93 µs HD Data set-up time t ; DAT 2506 — 1004, 7 — ns SU Rise time of SDA and SCL signals t — 1000 20 +0.1C 8 300 ns r b Fall time of SDA and SCL signals t — 300 20 +0.1C 7 300 ns f b Set-up time for STOP condition t ; STO 4 — 0.6 — µs SU Bus free time between STOP and t 4.7 — 1.3 — µs BUF START condition Pulse width of spikes that must be t N/A N/A 0 50 ns SP suppressed by the input filter 1. The PTB3 and PTB4 pins can support only the Standard mode. 2. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the normal drive pins and VDD ≥ 2.7 V. 3. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 4. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 5. Input signal Slew = 10 ns and Output Load = 50 pF 6. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 7. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement t ≥ 250 ns SU; DAT must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t + t rmax SU; = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. DAT 8. C = total capacitance of the one bus line in pF. b Table 33. I 2C 1Mbit/s timing Characteristic Symbol Minimum Maximum Unit SCL Clock Frequency f 0 11 MHz SCL Hold time (repeated) START condition. After this t ; STA 0.26 — µs HD period, the first clock pulse is generated. LOW period of the SCL clock t 0.5 — µs LOW HIGH period of the SCL clock t 0.26 — µs HIGH Set-up time for a repeated START condition t ; STA 0.26 — µs SU Data hold time for I C bus devices t ; DAT 0 — µs 2 HD Table continues on the next page... 34 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

 Dimensions Table 33. I 2C 1Mbit/s timing (continued) Characteristic Symbol Minimum Maximum Unit Data set-up time t ; DAT 50 — ns SU Rise time of SDA and SCL signals t 20 +0.1C 120 ns r b Fall time of SDA and SCL signals t 20 +0.1C 2 120 ns f b Set-up time for STOP condition t ; STO 0.26 — µs SU Bus free time between STOP and START condition t 0.5 — µs BUF Pulse width of spikes that must be suppressed by t 0 50 ns SP the input filter 1. The maximum SCL clock frequency of 1 Mbit/s can support 200 pF bus loading when using the normal drive pins and VDD ≥ 2.7 V. 2. C = total capacitance of the one bus line in pF. b SDA tSU; DAT tf tf tLOW tr tHD; STA tSP tr tBUF SCL HD; STA tSU; STA tSU; STO S t t SR P S HD; DAT HIGH Figure 15. Timing definition for devices on the I2C bus 3.8.3 UART See General switching specifications. 4 Dimensions 4.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to nxp.com and perform a keyword search for the drawing’s document number: Kinetis KL02 32 KB Flash, Rev. 5 08/2017 35 NXP Semiconductors

Pinout If you want the drawing for this package Then use this document number 16-pin QFN 98ASA00525D 24-pin QFN 98ASA00474D 32-pin QFN 98ASA00473D 5 Pinout 5.1 KL02 signal multiplexing and pin assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE PTB3 and PTB4 are true open drain pins. To use these pins as outputs, you must use an external pullup resistor to make them output correct values when using I2C, GPIO, and UART0. 32 24 16 Pin Name Default ALT0 ALT1 ALT2 ALT3 QFN QFN QFN 1 1 — PTB6/ DISABLED PTB6/ TPM1_CH1 TPM_CLKIN1 IRQ_2/ IRQ_2/ LPTMR0_ALT3 LPTMR0_ALT3 2 2 — PTB7/ DISABLED PTB7/ TPM1_CH0 IRQ_3 IRQ_3 3 3 1 VDD VDD VDD 4 3 1 VREFH VREFH VREFH 5 4 2 VREFL VREFL VREFL 6 4 2 VSS VSS VSS 7 5 3 PTA3 EXTAL0 EXTAL0 PTA3 I2C0_SCL I2C1_SDA 8 6 4 PTA4 XTAL0 XTAL0 PTA4 I2C0_SDA I2C1_SCL 9 7 5 PTA5 DISABLED PTA5 TPM0_CH1 SPI0_SS_b 10 8 6 PTA6 DISABLED PTA6 TPM0_CH0 SPI0_MISO 11 — — PTB8 ADC0_SE11 ADC0_SE11 PTB8 12 — — PTB9 ADC0_SE10 ADC0_SE10 PTB9 13 9 — PTB10 ADC0_SE9 ADC0_SE9 PTB10 TPM0_CH1 14 10 — PTB11 ADC0_SE8 ADC0_SE8 PTB11 TPM0_CH0 15 11 7 PTA7/ ADC0_SE7 ADC0_SE7 PTA7/ SPI0_MISO SPI0_MOSI IRQ_4 IRQ_4 36 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

Pinout 32 24 16 Pin Name Default ALT0 ALT1 ALT2 ALT3 QFN QFN QFN 16 12 8 PTB0/ ADC0_SE6 ADC0_SE6 PTB0/ EXTRG_IN SPI0_SCK IRQ_5 IRQ_5 17 13 9 PTB1/ ADC0_SE5/ ADC0_SE5/ PTB1/ UART0_TX UART0_RX IRQ_6 CMP0_IN3 CMP0_IN3 IRQ_6 18 14 10 PTB2/ ADC0_SE4 ADC0_SE4 PTB2/ UART0_RX UART0_TX IRQ_7 IRQ_7 19 15 — PTA8 ADC0_SE3 ADC0_SE3 PTA8 I2C1_SCL 20 16 — PTA9 ADC0_SE2 ADC0_SE2 PTA9 I2C1_SDA 21 — — PTA10/ DISABLED PTA10/ IRQ_8 IRQ_8 22 — — PTA11/ DISABLED PTA11/ IRQ_9 IRQ_9 23 17 11 PTB3/ DISABLED PTB3/ I2C0_SCL UART0_TX IRQ_10 IRQ_10 24 18 12 PTB4/ DISABLED PTB4/ I2C0_SDA UART0_RX IRQ_11 IRQ_11 25 19 13 PTB5/ NMI_b ADC0_SE1/ PTB5/ TPM1_CH1 NMI_b IRQ_12 CMP0_IN1 IRQ_12 26 20 — PTA12/ ADC0_SE0/ ADC0_SE0/ PTA12/ TPM1_CH0 TPM_CLKIN0 IRQ_13/ CMP0_IN0 CMP0_IN0 IRQ_13/ LPTMR0_ALT2 LPTMR0_ALT2 27 — — PTA13 DISABLED PTA13 28 — — PTB12 DISABLED PTB12 29 21 — PTB13 ADC0_SE13 ADC0_SE13 PTB13 TPM1_CH1 30 22 14 PTA0/ SWD_CLK ADC0_SE12/ PTA0/ TPM1_CH0 SWD_CLK IRQ_0 CMP0_IN2 IRQ_0 31 23 15 PTA1/ RESET_b PTA1/ TPM_CLKIN0 RESET_b IRQ_1/ IRQ_1/ LPTMR0_ALT1 LPTMR0_ALT1 32 24 16 PTA2 SWD_DIO PTA2 CMP0_OUT SWD_DIO 5.2 KL02 pinouts The following figures show the pinout diagrams for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see KL02 signal multiplexing and pin assignments. Kinetis KL02 32 KB Flash, Rev. 5 08/2017 37 NXP Semiconductors

Pinout 2 T 1 L T A AL 0_ _ R R0 M M T P 2 1/IRQ_1/LPT 0/IRQ_0 13 12 13 12/IRQ_13/L 5/IRQ_12 A A A B B A A B T T T T T T T T P P P P P P P P 32 31 30 29 28 27 26 25 PTB6/IRQ_2/LPTMR0_ALT3 1 24 PTB4/IRQ_11 PTB7/IRQ_3 2 23 PTB3/IRQ_10 VDD 3 22 PTA11/IRQ_9 VREFH 4 21 PTA10/IRQ_8 VREFL 5 20 PTA9 VSS 6 19 PTA8 PTA3 7 18 PTB2/IRQ_7 PTA4 8 17 PTB1/IRQ_6 9 10 11 12 13 14 15 16 5 6 8 9 0 1 4 5 A A B B 1 1 _ _ T T T T B B Q Q P P P P PT PT 7/IR 0/IR A B T T P P Figure 16. KL02 32-pin QFN pinout diagram 38 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

Pinout 2 T 1 L T A AL 0_ _ R R0 M M PT 2 1/IRQ_1/LPT 0/IRQ_0 13 12/IRQ_13/L 5/IRQ_12 A A A B A B T T T T T T P P P P P P 24 23 22 21 20 19 PTB6/IRQ_2/LPTMR0_ALT3 1 18 PTB4/IRQ_11 PTB7/IRQ_3 2 17 PTB3/IRQ_10 VDD VREFH 3 16 PTA9 VREFL VSS 4 15 PTA8 PTA3 5 14 PTB2/IRQ_7 PTA4 6 13 PTB1/IRQ_6 7 8 9 10 11 12 5 6 0 1 4 5 A A 1 1 _ _ T T B B Q Q P P PT PT 7/IR 0/IR A B PT PT Figure 17. KL02 24-pin QFN pinout diagram Kinetis KL02 32 KB Flash, Rev. 5 08/2017 39 NXP Semiconductors

Ordering parts 1 T L A _ 0 R M T P Q_1/L Q_0 Q_12 R R R A2 A1/I A0/I B5/I T T T T P P P P 16 15 14 13 VDD VREFH 1 12 PTB4/IRQ_11 VREFL VSS 2 11 PTB3/IRQ_10 PTA3 3 10 PTB2/IRQ_7 PTA4 4 9 PTB1/IRQ_6 5 6 7 8 5 6 4 5 A A _ _ T T Q Q P P R R 7/I 0/I A B T T P P Figure 18. KL02 16-pin QFN pinout diagram 6 Ordering parts 6.1 Determining valid orderable parts Valid orderable part numbers are provided on the Web. To determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: PKL02 and MKL02 7 Part identification 7.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 40 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

Part identification 7.2 Format Part numbers for this device have the following format: Q KL## A FFF R T PP CC N 7.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Table 34. Part number fields descriptions Field Description Values Q Qualification status • M = Fully qualified, general market flow • P = Prequalification KL## Kinetis family • KL02 A Key attribute • Z = Cortex-M0+ FFF Program flash memory size • 8 = 8 KB • 16 = 16 KB • 32 = 32 KB R Silicon revision • (Blank) = Main • A = Revision after main T Temperature range (°C) • V = –40 to 105 PP Package identifier • FG = 16 QFN (3 mm x 3 mm) • FK = 24 QFN (4 mm x 4 mm) • FM = 32 QFN (5 mm x 5 mm) CC Maximum CPU frequency (MHz) • 4 = 48 MHz N Packaging type • R = Tape and reel • (Blank) = Trays 7.4 Example This is an example part number: MKL02Z8VFG4 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 41 NXP Semiconductors

Small package marking 8 Small package marking In order to save space, small package devices use special marking on the chip. Q FS FF (TP) Table 35. Small package marking Field Description Values Q Qualification status • M = M • P = P FS Kinetis family and CPU frequency • (0)2T = KL02, 48 MHz of CPU FF Program flash memory size • 3 = 8 KB • 4 = 16 KB • 5 = 32 KB TP Temperature range (°C) and package • V = –40 to 105, 24 or 32 QFN • blank = –40 to 105, 16 QFN For example: M2T4 = MKL02Z16VFG4 M02T4V = MKL02Z16VFK4 9 Terminology and guidelines 9.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 9.1.1 Example This is an example of an operating requirement: Symbol Description Min. Max. Unit V 1.0 V core supply 0.9 1.1 V DD voltage 42 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

Terminology and guidelines 9.2 Definition: Operating behavior Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 9.2.1 Example This is an example of an operating behavior: Symbol Description Min. Max. Unit I Digital I/O weak pullup/ 10 130 µA WP pulldown current 9.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 9.3.1 Example This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: — 7 pF digital pins 9.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. Kinetis KL02 32 KB Flash, Rev. 5 08/2017 43 NXP Semiconductors

Terminology and guidelines 9.4.1 Example This is an example of an operating rating: Symbol Description Min. Max. Unit V 1.0 V core supply –0.3 1.2 V DD voltage 9.5 Result of exceeding a rating 40 m) 30 p p e ( m s in ti 20 Tsohoen l ikaesl iah ocohda roafc pteerrimstiacn beengt icnhsi pto f aeixlucreee idn corneea soef sit sra oppidelrya atins g ratings. e ur Fail 10 0 Operating rating Measured characteristic 44 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

Terminology and guidelines 9.6 Relationship between ratings and operating requirements Operating rating (min.) Operating requirement (min.) Operating requirement (max.) Operating rating (max.) Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - No permanent failure - No permanent failure Expected permanent failure - Possible decreased life - Correct operation - Possible decreased life - Possible incorrect operation - Possible incorrect operation –∞ ∞ Operating (power on) Handling rating (min.) Handling rating (max.) Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure –∞ ∞ Handling (power off) 9.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 9.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. Kinetis KL02 32 KB Flash, Rev. 5 08/2017 45 NXP Semiconductors

Terminology and guidelines 9.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit I Digital I/O weak 10 70 130 µA WP pullup/pulldown current 9.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 T 3500 J 150 °C A) 3000 μ ( 105 °C P O 2500 T D_S 25 °C ID 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 V (V) DD 9.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): 46 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 NXP Semiconductors

Revision history Table 36. Typical value conditions Symbol Description Value Unit T Ambient temperature 25 °C A V 3.3 V supply voltage 3.3 V DD 10 Revision history The following table provides a revision history for this document. Table 37. Revision history Rev. No. Date Substantial Changes 2 05/2013 Public release. 2.1 07/2013 Removed the specification on OSCERCLK (4 MHz external crystal) because KL02 does not support it. 3 3/2014 • Updated the front page and restructured the chapters • Added a note to the I in the ESD handling ratings LAT • Updated table title in the Voltage and current operating ratings • Updated Voltage and current operating requirements • Updated footnote to the V in the Voltage and current operating OH behaviors • Updated Power mode transition operating behaviors • Updated Capacitance attributes • Updated the Device clock specifications • Added Inter-Integrated Circuit Interface (I2C) timing 4 08/2014 • Updated related source and added block diagram in the front page • Updated Power consumption operating behaviors • Updated t and t in Table 28, t , t , t in Table 30 SU v SU dis v • Updated the note in KL02 signal multiplexing and pin assignments 5 08/2017 • Added a note in the Thermal operating requirements • Added I2C 1 Mbit/s timing table and a footnote to the f of the SCL I2C timing table in the Inter-Integrated Circuit Interface (I2C) timing. Kinetis KL02 32 KB Flash, Rev. 5 08/2017 47 NXP Semiconductors

How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright Home Page: licenses granted hereunder to design or fabricate any integrated circuits based nxp.com on the information in this document. NXP reserves the right to make changes Web Support: without further notice to any products herein. nxp.com/support NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customerʼs technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/SalesTermsandConditions. . NXP, the NXP logo, Freescale, Freescale logo, Energy Efficient Solutions logo, and Kinetis are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. © 2012-2017 NXP B.V. Document Number KL02P32M48SF0 Revision 5 08/2017

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: N XP: MKL02Z16VFM4 MKL02Z32VFG4R MKL02Z32VFK4 MKL02Z32VFM4 MKL02Z16VFK4 MKL02Z8VFG4R MKL02Z16VFG4 MKL02Z8VFG4 MKL02Z32VFG4 MKL02Z32VFK4R MKL02Z32VFM4R