Freescale Semiconductor Document Number: K60P121M100SF2 Data Sheet: Technical Data Rev. 7, 02/2013 K60P121M100SF2 K60 Sub-Family Data Sheet Supports the following: MK60DN256ZVMC10, MK60DX256ZVMC10, MK60DN512ZVMC10 Features • Security and integrity modules • Operating Characteristics – Hardware CRC module to support fast cyclic – Voltage range: 1.71 to 3.6 V redundancy checks – Flash write voltage range: 1.71 to 3.6 V – Hardware random-number generator – Temperature range (ambient): -40 to 105°C – Hardware encryption supporting DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms • Performance – 128-bit unique identification (ID) number per chip – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per • Human-machine interface MHz – Low-power hardware touch sensor interface (TSI) – General-purpose input/output • Memories and memory interfaces – Up to 512 KB program flash memory on non- • Analog modules FlexMemory devices – Two 16-bit SAR ADCs – Up to 256 KB program flash memory on – Programmable gain amplifier (PGA) (up to x64) FlexMemory devices integrated into each ADC – Up to 256 KB FlexNVM on FlexMemory devices – Two 12-bit DACs – 4 KB FlexRAM on FlexMemory devices – Three analog comparators (CMP) containing a 6-bit – Up to 128 KB RAM DAC and programmable reference input – Serial programming interface (EzPort) – Voltage reference – FlexBus external bus interface • Timers • Clocks – Programmable delay block – 3 to 32 MHz crystal oscillator – Eight-channel motor control/general purpose/PWM – 32 kHz crystal oscillator timer – Multi-purpose clock generator – Two 2-channel quadrature decoder/general purpose timers • System peripherals – IEEE 1588 timers – Multiple low-power modes to provide power – Periodic interrupt timers optimization based on application requirements – 16-bit low-power timer – Memory protection unit with multi-master – Carrier modulator transmitter protection – Real-time clock – 16-channel DMA controller, supporting up to 63 request sources – External watchdog monitor – Software watchdog – Low-leakage wakeup unit Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2011–2013 Freescale Semiconductor, Inc.

• Communication interfaces – Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability – USB full-/low-speed On-the-Go controller with on-chip transceiver – Two Controller Area Network (CAN) modules – Three SPI modules – Two I2C modules – Six UART modules – Secure Digital host controller (SDHC) – I2S module K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 2 Freescale Semiconductor, Inc.

Table of Contents 1 Ordering parts...........................................................................5 5.4.2 Thermal attributes...............................................23 1.1 Determining valid orderable parts......................................5 6 Peripheral operating requirements and behaviors....................24 2 Part identification......................................................................5 6.1 Core modules....................................................................24 2.1 Description.........................................................................5 6.1.1 Debug trace timing specifications.......................24 2.2 Format...............................................................................5 6.1.2 JTAG electricals..................................................24 2.3 Fields.................................................................................5 6.2 System modules................................................................27 2.4 Example............................................................................6 6.3 Clock modules...................................................................27 3 Terminology and guidelines......................................................6 6.3.1 MCG specifications.............................................27 3.1 Definition: Operating requirement......................................6 6.3.2 Oscillator electrical specifications.......................29 3.2 Definition: Operating behavior...........................................7 6.3.3 32 kHz Oscillator Electrical Characteristics........32 3.3 Definition: Attribute............................................................7 6.4 Memories and memory interfaces.....................................32 3.4 Definition: Rating...............................................................8 6.4.1 Flash electrical specifications.............................32 3.5 Result of exceeding a rating..............................................8 6.4.2 EzPort Switching Specifications.........................37 3.6 Relationship between ratings and operating 6.4.3 Flexbus Switching Specifications........................38 requirements......................................................................8 6.5 Security and integrity modules..........................................41 3.7 Guidelines for ratings and operating requirements............9 6.6 Analog...............................................................................41 3.8 Definition: Typical value.....................................................9 6.6.1 ADC electrical specifications..............................41 3.9 Typical value conditions....................................................10 6.6.2 CMP and 6-bit DAC electrical specifications......49 4 Ratings......................................................................................11 6.6.3 12-bit DAC electrical characteristics...................51 4.1 Thermal handling ratings...................................................11 6.6.4 Voltage reference electrical specifications..........54 4.2 Moisture handling ratings..................................................11 6.7 Timers................................................................................55 4.3 ESD handling ratings.........................................................11 6.8 Communication interfaces.................................................55 4.4 Voltage and current operating ratings...............................11 6.8.1 Ethernet switching specifications........................55 5 General.....................................................................................12 6.8.2 USB electrical specifications...............................57 5.1 AC electrical characteristics..............................................12 6.8.3 USB DCD electrical specifications......................57 5.2 Nonswitching electrical specifications...............................12 6.8.4 USB VREG electrical specifications...................58 5.2.1 Voltage and current operating requirements......13 6.8.5 CAN switching specifications..............................58 5.2.2 LVD and POR operating requirements...............14 6.8.6 DSPI switching specifications (limited voltage 5.2.3 Voltage and current operating behaviors............14 range).................................................................59 5.2.4 Power mode transition operating behaviors.......16 6.8.7 DSPI switching specifications (full voltage 5.2.5 Power consumption operating behaviors............17 range).................................................................60 5.2.6 EMC radiated emissions operating behaviors....20 6.8.8 Inter-Integrated Circuit Interface (I2C) timing.....62 5.2.7 Designing with radiated emissions in mind.........21 6.8.9 UART switching specifications............................63 5.2.8 Capacitance attributes........................................21 6.8.10 SDHC specifications...........................................63 5.3 Switching specifications.....................................................21 6.8.11 I2S switching specifications................................64 5.3.1 Device clock specifications.................................21 6.9 Human-machine interfaces (HMI)......................................67 5.3.2 General switching specifications.........................21 6.9.1 TSI electrical specifications................................67 5.4 Thermal specifications.......................................................22 7 Dimensions...............................................................................68 5.4.1 Thermal operating requirements.........................22 7.1 Obtaining package dimensions.........................................68 K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 3

8 Pinout........................................................................................68 8.2 K60 Pinouts.......................................................................72 8.1 K60 Signal Multiplexing and Pin Assignments..................68 9 Revision History........................................................................73 K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 4 Freescale Semiconductor, Inc.

Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: PK60 and MK60. 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.2 Format Part numbers for this device have the following format: Q K## A M FFF R T PP CC N 2.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow • P = Prequalification K## Kinetis family • K60 A Key attribute • D = Cortex-M4 w/ DSP • F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only • X = Program flash and FlexMemory Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 5

Terminology and guidelines Field Description Values FFF Program flash memory size • 32 = 32 KB • 64 = 64 KB • 128 = 128 KB • 256 = 256 KB • 512 = 512 KB • 1M0 = 1 MB • 2M0 = 2 MB R Silicon revision • Z = Initial • (Blank) = Main • A = Revision after main T Temperature range (°C) • V = –40 to 105 • C = –40 to 85 PP Package identifier • FM = 32 QFN (5 mm x 5 mm) • FT = 48 QFN (7 mm x 7 mm) • LF = 48 LQFP (7 mm x 7 mm) • LH = 64 LQFP (10 mm x 10 mm) • MP = 64 MAPBGA (5 mm x 5 mm) • LK = 80 LQFP (12 mm x 12 mm) • LL = 100 LQFP (14 mm x 14 mm) • MC = 121 MAPBGA (8 mm x 8 mm) • LQ = 144 LQFP (20 mm x 20 mm) • MD = 144 MAPBGA (13 mm x 13 mm) • MJ = 256 MAPBGA (17 mm x 17 mm) CC Maximum CPU frequency (MHz) • 5 = 50 MHz • 7 = 72 MHz • 10 = 100 MHz • 12 = 120 MHz • 15 = 150 MHz N Packaging type • R = Tape and reel • (Blank) = Trays 2.4 Example This is an example part number: MK60DN512ZVMD10 3 Terminology and guidelines 3.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 6 Freescale Semiconductor, Inc.

Terminology and guidelines 3.1.1 Example This is an example of an operating requirement: Symbol Description Min. Max. Unit V 1.0 V core supply 0.9 1.1 V DD voltage 3.2 Definition: Operating behavior An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 Example This is an example of an operating behavior: Symbol Description Min. Max. Unit I Digital I/O weak pullup/ 10 130 µA WP pulldown current 3.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 Example This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: — 7 pF digital pins K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 7

Terminology and guidelines 3.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. 3.4.1 Example This is an example of an operating rating: Symbol Description Min. Max. Unit V 1.0 V core supply –0.3 1.2 V DD voltage 3.5 Result of exceeding a rating 40 m) 30 p p e ( s in tim 20 Tsohoen l ikaesl iah ocohda roafc pteerrimstiacn beengt icnhsi pto f aeixlucreee idn corneea soef sit sra oppidelrya atins g ratings. e ur Fail 10 0 Operating rating Measured characteristic K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 8 Freescale Semiconductor, Inc.

Terminology and guidelines 3.6 Relationship between ratings and operating requirements O perating rating (min.) O perating require m ent (min.) O perating require m ent (m ax.) O perating rating (m ax.) Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - No permanent failure - No permanent failure Expected permanent failure - Possible decreased life - Correct operation - Possible decreased life - Possible incorrect operation - Possible incorrect operation –∞ ∞ Operating (power on) H andling rating (min.) H andling rating (m ax.) Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure –∞ ∞ Handling (power off) 3.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 9

Terminology and guidelines 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit I Digital I/O weak 10 70 130 µA WP pullup/pulldown current 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 T 3500 J 150 °C A) 3000 μ ( 105 °C P O 2500 T S 25 °C _ D ID 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 V (V) DD 3.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit T Ambient temperature 25 °C A V 3.3 V supply voltage 3.3 V DD K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 10 Freescale Semiconductor, Inc.

Ratings 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes T Storage temperature –55 150 °C 1 STG T Solder temperature, lead-free — 260 °C 2 SDR Solder temperature, leaded — 245 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.2 Moisture handling ratings Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.3 ESD handling ratings Symbol Description Min. Max. Unit Notes V Electrostatic discharge voltage, human body model -2000 +2000 V 1 HBM V Electrostatic discharge voltage, charged-device model -500 +500 V 2 CDM I Latch-up current at ambient temperature of 105°C -100 +100 mA 3 LAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 4.4 Voltage and current operating ratings K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 11

General Symbol Description Min. Max. Unit V Digital supply voltage –0.3 3.8 V DD I Digital supply current — 185 mA DD V Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 5.5 V DIO V Analog1, RESET, EXTAL, and XTAL input voltage –0.3 V + 0.3 V AIO DD I Maximum current single pin limit (applies to all digital pins) –25 25 mA D V Analog supply voltage V – 0.3 V + 0.3 V DDA DD DD V USB_DP input voltage –0.3 3.63 V USB_DP V USB_DM input voltage –0.3 3.63 V USB_DM VREGIN USB regulator input –0.3 6.0 V V RTC battery supply voltage –0.3 3.8 V BAT 1. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 5 General 5.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Figure 1. Input signal measurement reference All digital I/O switching characteristics assume: 1. output pins • have C =30pF loads, L • are configured for fast slew rate (PORTx_PCRn[SRE]=0), and • are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins • have their passive filter disabled (PORTx_PCRn[PFE]=0) K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 12 Freescale Semiconductor, Inc.

General 5.2 Nonswitching electrical specifications 5.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit Notes V Supply voltage 1.71 3.6 V DD V Analog supply voltage 1.71 3.6 V DDA V – V V -to-V differential voltage –0.1 0.1 V DD DDA DD DDA V – V V -to-V differential voltage –0.1 0.1 V SS SSA SS SSA V RTC battery supply voltage 1.71 3.6 V BAT V Input high voltage IH • 2.7 V ≤ V ≤ 3.6 V 0.7 × V — V DD DD • 1.7 V ≤ V ≤ 2.7 V 0.75 × V — V DD DD V Input low voltage IL • 2.7 V ≤ V ≤ 3.6 V — 0.35 × V V DD DD • 1.7 V ≤ V ≤ 2.7 V — 0.3 × V V DD DD V Input hysteresis 0.06 × V — V HYS DD I Digital pin negative DC injection current — single pin 1 ICDIO -5 — mA • V < V -0.3V IN SS I Analog2, EXTAL, and XTAL pin DC injection current — 3 ICAIO single pin mA • V < V -0.3V (Negative current injection) -5 — IN SS • V > V +0.3V (Positive current injection) — +5 IN DD I Contiguous pin DC injection current —regional limit, ICcont includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins -25 — mA • Negative current injection — +25 • Positive current injection V Open drain pullup voltage level V V V 4 ODPU DD DD V V voltage required to retain RAM 1.2 — V RAM DD V V voltage required to retain the VBAT register file V — V RFVBAT BAT POR_VBAT 1. All 5 V tolerant digital I/O pins are internally clamped to V through an ESD protection diode. There is no diode SS connection to V . If V is less than V , a current limiting resistor is required. The negative DC injection current DD IN DIO_MIN limiting resistor is calculated as R=(V -V )/|I |. DIO_MIN IN ICDIO 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and XTAL are analog pins. 3. All analog pins are internally clamped to V and V through ESD protection diodes. If V is less than V or greater SS DD IN AIO_MIN than V , a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as AIO_MAX R=(V -V )/|I |. The positive injection current limiting resistor is calculated as R=(V -V )/|I |. Select the AIO_MIN IN ICAIO IN AIO_MAX ICAIO larger of these two calculated resistances if the pin is exposed to positive and negative injection currents. 4. Open drain outputs must be pulled to VDD. K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 13

General 5.2.2 LVD and POR operating requirements Table 2. V supply LVD and POR operating requirements DD Symbol Description Min. Typ. Max. Unit Notes V Falling VDD POR detect voltage 0.8 1.1 1.5 V POR V Falling low-voltage detect threshold — high 2.48 2.56 2.64 V LVDH range (LVDV=01) Low-voltage warning thresholds — high range 1 V • Level 1 falling (LVWV=00) 2.62 2.70 2.78 V LVW1H V • Level 2 falling (LVWV=01) 2.72 2.80 2.88 V LVW2H V • Level 3 falling (LVWV=10) 2.82 2.90 2.98 V LVW3H V • Level 4 falling (LVWV=11) 2.92 3.00 3.08 V LVW4H V Low-voltage inhibit reset/recover hysteresis — — ±80 — mV HYSH high range V Falling low-voltage detect threshold — low range 1.54 1.60 1.66 V LVDL (LVDV=00) Low-voltage warning thresholds — low range 1 V • Level 1 falling (LVWV=00) 1.74 1.80 1.86 V LVW1L V • Level 2 falling (LVWV=01) 1.84 1.90 1.96 V LVW2L V • Level 3 falling (LVWV=10) 1.94 2.00 2.06 V LVW3L V • Level 4 falling (LVWV=11) 2.04 2.10 2.16 V LVW4L V Low-voltage inhibit reset/recover hysteresis — — ±60 — mV HYSL low range V Bandgap voltage reference 0.97 1.00 1.03 V BG t Internal low power oscillator period — factory 900 1000 1100 μs LPO trimmed 1. Rising thresholds are falling threshold + hysteresis voltage Table 3. VBAT power operating requirements Symbol Description Min. Typ. Max. Unit Notes V Falling VBAT supply POR detect voltage 0.8 1.1 1.5 V POR_VBAT K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 14 Freescale Semiconductor, Inc.

General 5.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol Description Min. Typ.1 Max. Unit Notes V Output high voltage — high drive strength OH • 2.7 V ≤ V ≤ 3.6 V, I = -9mA V – 0.5 — — V DD OH DD • 1.71 V ≤ V ≤ 2.7 V, I = -3mA V – 0.5 — — V DD OH DD Output high voltage — low drive strength • 2.7 V ≤ V ≤ 3.6 V, I = -2mA V – 0.5 — — V DD OH DD • 1.71 V ≤ V ≤ 2.7 V, I = -0.6mA V – 0.5 — — V DD OH DD I Output high current total for all ports — — 100 mA OHT V Output low voltage — high drive strength 2 OL • 2.7 V ≤ V ≤ 3.6 V, I = 9mA — — 0.5 V DD OL • 1.71 V ≤ V ≤ 2.7 V, I = 3mA — — 0.5 V DD OL Output low voltage — low drive strength • 2.7 V ≤ V ≤ 3.6 V, I = 2mA — — 0.5 V DD OL • 1.71 V ≤ V ≤ 2.7 V, I = 0.6mA — — 0.5 V DD OL I Output low current total for all ports — — 100 mA OLT I Input leakage current, analog pins and digital 3, 4 INA pins configured as analog inputs • V ≤ V ≤ V SS IN DD • All pins except EXTAL32, XTAL32, — 0.002 0.5 μA EXTAL, XTAL — 0.004 1.5 μA • EXTAL (PTA18) and XTAL (PTA19) — 0.075 10 μA • EXTAL32, XTAL32 I Input leakage current, digital pins 4, 5 IND • V ≤ V ≤ V SS IN IL • All digital pins — 0.002 0.5 μA • V = V IN DD — 0.002 0.5 μA • All digital pins except PTD7 — 0.004 1 μA • PTD7 I Input leakage current, digital pins 4, 5, 6 IND • V < V < V IL IN DD • V = 3.6 V — 18 26 μA DD • V = 3.0 V — 12 49 μA DD • V = 2.5 V — 8 13 μA DD • V = 1.7 V — 3 6 μA DD Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 15

General Table 4. Voltage and current operating behaviors (continued) Symbol Description Min. Typ.1 Max. Unit Notes I Input leakage current, digital pins 4, 5 IND • V < V < 5.5 V — 1 50 μA DD IN Z Input impedance examples, digital pins 4, 7 IND • V = 3.6 V — — 48 kΩ DD • V = 3.0 V — — 55 kΩ DD • V = 2.5 V — — 57 kΩ DD • V = 1.7 V — — 85 kΩ DD R Internal pullup resistors 20 35 50 kΩ 8 PU R Internal pulldown resistors 20 35 50 kΩ 9 PD 1. Typical values characterized at 25°C and VDD = 3.6 V unless otherwise noted. 2. Open drain outputs must be pulled to V . DD 3. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 4. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL. 5. Internal pull-up/pull-down resistors disabled. 6. Characterized, not tested in production. 7. Examples calculated using V relation, V , and max I : Z =V /I . This is the impedance needed to pull a high IL DD IND IND IL IND signal to a level below V due to leakage when V < V < V . These examples assume signal source low = 0 V. IL IL IN DD 8. Measured at V supply voltage = V min and Vinput = V DD DD SS 9. Measured at V supply voltage = V min and Vinput = V DD DD DD I IND Digital input Z IND + – Source 5.2.4 Power mode transition operating behaviors All specifications except t , and VLLSx→RUN recovery times in the following table POR assume this clock configuration: • CPU and system clocks = 100 MHz • Bus clock = 50 MHz • FlexBus clock = 50 MHz • Flash clock = 25 MHz • MCG mode: FEI K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 16 Freescale Semiconductor, Inc.

General Table 5. Power mode transition operating behaviors Symbol Description Min. Max. Unit Notes t After a POR event, amount of time from the point V μs 1 POR DD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. — 300 • V slew rate ≥ 5.7 kV/s DD — 1.7 V / (V • V slew rate < 5.7 kV/s DD DD slew rate) — 134 μs • VLLS1 → RUN — 96 μs • VLLS2 → RUN — 96 μs • VLLS3 → RUN — 6.2 μs • LLS → RUN — 5.9 μs • VLPS → RUN — 5.9 μs • STOP → RUN 1. Normal boot (FTFL_OPT[LPBOOT]=1) 5.2.5 Power consumption operating behaviors Table 6. Power consumption operating behaviors Symbol Description Min. Typ. Max. Unit Notes I Analog supply current — — See note mA 1 DDA I Run mode current — all peripheral clocks 2 DD_RUN disabled, code executing from flash • @ 1.8V — 45 70 mA • @ 3.0V — 47 72 mA I Run mode current — all peripheral clocks 3, 4 DD_RUN enabled, code executing from flash • @ 1.8V — 61 85 mA • @ 3.0V • @ 25°C — 63 71 mA • @ 125°C — 72 87 mA I Wait mode high frequency current at 3.0 V — all — 35 — mA 2 DD_WAIT peripheral clocks disabled I Wait mode reduced frequency current at 3.0 V — — 15 — mA 5 DD_WAIT all peripheral clocks disabled I Very-low-power run mode current at 3.0 V — all — N/A — mA 6 DD_VLPR peripheral clocks disabled Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 17

General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes I Very-low-power run mode current at 3.0 V — all — N/A — mA 7 DD_VLPR peripheral clocks enabled I Very-low-power wait mode current at 3.0 V — all — N/A — mA 8 DD_VLPW peripheral clocks disabled I Stop mode current at 3.0 V DD_STOP • @ –40 to 25°C — 0.59 1.4 mA • @ 70°C — 2.26 7.9 mA • @ 105°C — 5.94 19.2 mA I Very-low-power stop mode current at 3.0 V DD_VLPS • @ –40 to 25°C — 93 435 μA • @ 70°C — 520 2000 μA • @ 105°C — 1350 4000 μA I Low leakage stop mode current at 3.0 V 9 DD_LLS • @ –40 to 25°C — 4.8 20 μA • @ 70°C — 28 68 μA • @ 105°C — 126 270 μA I Very low-leakage stop mode 3 current at 3.0 V 9 DD_VLLS3 • @ –40 to 25°C — 3.1 8.9 μA • @ 70°C — 17 35 μA • @ 105°C — 82 148 μA I Very low-leakage stop mode 2 current at 3.0 V DD_VLLS2 • @ –40 to 25°C — 2.2 5.4 μA • @ 70°C — 7.1 12.5 μA • @ 105°C — 41 125 μA I Very low-leakage stop mode 1 current at 3.0 V DD_VLLS1 • @ –40 to 25°C — 2.1 7.6 μA • @ 70°C — 6.2 13.5 μA • @ 105°C — 30 46 μA I Average current with RTC and 32kHz disabled at DD_VBAT 3.0 V • @ –40 to 25°C — 0.33 0.39 μA • @ 70°C — 0.60 0.78 μA • @ 105°C — 1.97 2.9 μA Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 18 Freescale Semiconductor, Inc.

General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes I Average current when CPU is not accessing RTC 10 DD_VBAT registers • @ 1.8V • @ –40 to 25°C — 0.71 0.81 μA • @ 70°C — 1.01 1.3 μA • @ 105°C — 2.82 4.3 μA • @ 3.0V • @ –40 to 25°C — 0.84 0.94 μA • @ 70°C — 1.17 1.5 μA • @ 105°C — 3.16 4.6 μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral clocks disabled. 3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled. 4. Max values are measured with CPU executing DSP instructions. 5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode. 6. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 7. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 9. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA. 10. Includes 32kHz oscillator current and RTC operation. 5.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: • MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater than 50 MHz frequencies. • USB regulator disabled • No GPIOs toggled • Code execution from flash with cache enabled • For the ALLOFF curve, all peripheral clocks are disabled except FTFL K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 19

General Figure 2. Run mode supply current vs. core frequency 5.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors as measured on 144LQFP and 144MAPBGA packages Symbol Description Frequency 144LQFP 144MAPBGA Unit Notes band (MHz) V Radiated emissions voltage, band 1 0.15–50 23 12 dBμV 1 , 2 RE1 V Radiated emissions voltage, band 2 50–150 27 24 dBμV RE2 V Radiated emissions voltage, band 3 150–500 28 27 dBμV RE3 V Radiated emissions voltage, band 4 500–1000 14 11 dBμV RE4 V IEC level 0.15–1000 K K — 2, 3 RE_IEC 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 20 Freescale Semiconductor, Inc.

General 2. V = 3.3 V, T = 25 °C, f = 12 MHz (crystal), f = 96 MHz, f = 48MHz DD A OSC SYS BUS 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 5.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for “EMC design.” 5.2.8 Capacitance attributes Table 8. Capacitance attributes Symbol Description Min. Max. Unit C Input capacitance: analog pins — 7 pF IN_A C Input capacitance: digital pins — 7 pF IN_D 5.3 Switching specifications 5.3.1 Device clock specifications Table 9. Device clock specifications Symbol Description Min. Max. Unit Notes Normal run mode f System and core clock — 100 MHz SYS f System and core clock when Full Speed USB in 20 — MHz SYS_USB operation f System and core clock when ethernet in operation MHz ENET • 10 Mbps 5 — • 100 Mbps 50 — f Bus clock — 50 MHz BUS FB_CLK FlexBus clock — 50 MHz f Flash clock — 25 MHz FLASH f LPTMR clock — 25 MHz LPTMR K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 21

General 5.3.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, UART, CAN, CMT, IEEE 1588 timer, and I2C signals. Table 10. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter 1.5 — Bus clock 1, 2 disabled) — Synchronous path cycles GPIO pin interrupt pulse width (digital glitch filter 100 — ns 3 disabled, analog filter enabled) — Asynchronous path GPIO pin interrupt pulse width (digital glitch filter 16 — ns 3 disabled, analog filter disabled) — Asynchronous path External reset pulse width (digital glitch filter disabled) 100 — ns 3 Mode select (EZP_CS) hold time after reset 2 — Bus clock deassertion cycles Port rise and fall time (high drive strength) 4 • Slew disabled • 1.71 ≤ V ≤ 2.7V — 12 ns DD • 2.7 ≤ V ≤ 3.6V — 6 ns DD • Slew enabled • 1.71 ≤ V ≤ 2.7V — 36 ns DD • 2.7 ≤ V ≤ 3.6V — 24 ns DD Port rise and fall time (low drive strength) 5 • Slew disabled • 1.71 ≤ V ≤ 2.7V — 12 ns DD • 2.7 ≤ V ≤ 3.6V — 6 ns DD • Slew enabled • 1.71 ≤ V ≤ 2.7V — 36 ns DD • 2.7 ≤ V ≤ 3.6V — 24 ns DD 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75 pF load 5. 15 pF load 5.4 Thermal specifications K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 22 Freescale Semiconductor, Inc.

General 5.4.1 Thermal operating requirements Table 11. Thermal operating requirements Symbol Description Min. Max. Unit T Die junction temperature –40 125 °C J T Ambient temperature –40 °C A 5.4.2 Thermal attributes Board type Symbol Description 121 MAPBGA Unit Notes Single-layer (1s) R Thermal 65 °C/W 1 θJA resistance, junction to ambient (natural convection) Four-layer (2s2p) R Thermal 36 °C/W 1 θJA resistance, junction to ambient (natural convection) Single-layer (1s) R Thermal 52 °C/W 1 θJMA resistance, junction to ambient (200 ft./ min. air speed) Four-layer (2s2p) R Thermal 31 °C/W 1 θJMA resistance, junction to ambient (200 ft./ min. air speed) — R Thermal 17 °C/W 2 θJB resistance, junction to board — R Thermal 13 °C/W 3 θJC resistance, junction to case — Ψ Thermal 3 °C/W 4 JT characterization parameter, junction to package top outside center (natural convection) 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 23

Peripheral operating requirements and behaviors 6 Peripheral operating requirements and behaviors 6.1 Core modules 6.1.1 Debug trace timing specifications Table 12. Debug trace operating behaviors Symbol Description Min. Max. Unit T Clock period Frequency dependent MHz cyc T Low pulse width 2 — ns wl T High pulse width 2 — ns wh T Clock and data rise time — 3 ns r T Clock and data fall time — 3 ns f T Data setup 3 — ns s T Data hold 2 — ns h Figure 3. TRACE_CLKOUT specifications TRACE_CLKOUT Ts Th Ts Th TRACE_D[3:0] Figure 4. Trace data specifications K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 24 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 6.1.2 JTAG electricals Table 13. JTAG limited voltage range electricals Symbol Description Min. Max. Unit Operating voltage 2.7 3.6 V J1 TCLK frequency of operation MHz • Boundary Scan 0 10 • JTAG and CJTAG 0 25 • Serial Wire Debug 0 50 J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width • Boundary Scan 50 — ns • JTAG and CJTAG 20 — ns • Serial Wire Debug 10 — ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 17 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns Table 14. JTAG full voltage range electricals Symbol Description Min. Max. Unit Operating voltage 1.71 3.6 V J1 TCLK frequency of operation MHz • Boundary Scan 0 10 • JTAG and CJTAG 0 20 • Serial Wire Debug 0 40 J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width • Boundary Scan 50 — ns • JTAG and CJTAG 25 — ns • Serial Wire Debug 12.5 — ns J4 TCLK rise and fall times — 3 ns Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 25

Peripheral operating requirements and behaviors Table 14. JTAG full voltage range electricals (continued) Symbol Description Min. Max. Unit J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns J11 TCLK low to TDO data valid — 22.1 ns J12 TCLK low to TDO high-Z — 22.1 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns J2 J3 J3 TCLK (input) J4 J4 Figure 5. Test clock input timing TCLK J5 J6 Data inputs Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 6. Boundary scan (JTAG) timing K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 26 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors TCLK J9 J10 TDI/TMS Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 7. Test Access Port timing TCLK J14 J13 TRST Figure 8. TRST timing 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 27

Peripheral operating requirements and behaviors 6.3.1 MCG specifications Table 15. MCG specifications Symbol Description Min. Typ. Max. Unit Notes f Internal reference frequency (slow clock) — — 32.768 — kHz ints_ft factory trimmed at nominal VDD and 25 °C f Internal reference frequency (slow clock) — user 31.25 — 38.2 kHz ints_t trimmed — over fixed voltage and temperature range of 0–70°C Δ Resolution of trimmed average DCO output — ± 0.3 ± 0.6 %f 1 fdco_res_t dco frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM Δf Total deviation of trimmed average DCO output — ± 4.5 — %f 1 dco_t dco frequency over fixed voltage and temperature range of 0–70°C f Internal reference frequency (fast clock) — — 4 — MHz intf_ft factory trimmed at nominal VDD and 25°C f Internal reference frequency (fast clock) — user 3 — 5 MHz intf_t trimmed at nominal VDD and 25 °C f Loss of external clock minimum frequency — (3/5) x — — kHz loc_low RANGE = 00 f ints_t f Loss of external clock minimum frequency — (16/5) x — — kHz loc_high RANGE = 01, 10, or 11 f ints_t FLL f FLL reference frequency range 31.25 — 39.0625 kHz fll_ref f DCO output Low range (DRS=00) 20 20.97 25 MHz 2, 3 dco frequency range 640 × f fll_ref Mid range (DRS=01) 40 41.94 50 MHz 1280 × f fll_ref Mid-high range (DRS=10) 60 62.91 75 MHz 1920 × f fll_ref High range (DRS=11) 80 83.89 100 MHz 2560 × f fll_ref f DCO output Low range (DRS=00) — 23.99 — MHz 4, 5 dco_t_DMX32 frequency 732 × f fll_ref Mid range (DRS=01) — 47.97 — MHz 1464 × f fll_ref Mid-high range (DRS=10) — 71.99 — MHz 2197 × f fll_ref High range (DRS=11) — 95.98 — MHz 2929 × f fll_ref J FLL period jitter ps cyc_fll — 180 — • f = 48 MHz VCO — 150 — • f = 98 MHz VCO t FLL target frequency acquisition time — — 1 ms 6 fll_acquire Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 28 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 15. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes PLL f VCO operating frequency 48.0 — 100 MHz vco I PLL operating current 7 pll — 1060 — µA • PLL @ 96 MHz (f = 8 MHz, f = osc_hi_1 pll_ref 2 MHz, VDIV multiplier = 48) I PLL operating current 7 pll — 600 — µA • PLL @ 48 MHz (f = 8 MHz, f = osc_hi_1 pll_ref 2 MHz, VDIV multiplier = 24) f PLL reference frequency range 2.0 — 4.0 MHz pll_ref J PLL period jitter (RMS) 8 cyc_pll • f = 48 MHz — 120 — ps vco • f = 100 MHz — 50 — ps vco J PLL accumulated jitter over 1µs (RMS) 8 acc_pll • f = 48 MHz — 1350 — ps vco • f = 100 MHz — 600 — ps vco D Lock entry frequency tolerance ± 1.49 — ± 2.98 % lock D Lock exit frequency tolerance ± 4.47 — ± 5.97 % unl t Lock detector detection time — — 150 × 10-6 s 9 pll_lock + 1075(1/ f ) pll_ref 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δf ) over voltage and temperature should be considered. dco_t 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. Excludes any oscillator currents that are also consuming power while PLL is in operation. 8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 6.3.2 Oscillator electrical specifications This section provides the electrical characteristics of the module. K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 29

Peripheral operating requirements and behaviors 6.3.2.1 Oscillator DC electrical specifications Table 16. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit Notes V Supply voltage 1.71 — 3.6 V DD I Supply current — low-power mode (HGO=0) 1 DDOSC • 32 kHz — 500 — nA • 4 MHz — 200 — μA • 8 MHz (RANGE=01) — 300 — μA • 16 MHz — 950 — μA • 24 MHz — 1.2 — mA • 32 MHz — 1.5 — mA I Supply current — high gain mode (HGO=1) 1 DDOSC • 32 kHz — 25 — μA • 4 MHz — 400 — μA • 8 MHz (RANGE=01) — 500 — μA • 16 MHz — 2.5 — mA • 24 MHz — 3 — mA • 32 MHz — 4 — mA C EXTAL load capacitance — — — 2, 3 x C XTAL load capacitance — — — 2, 3 y R Feedback resistor — low-frequency, low-power — — — MΩ 2, 4 F mode (HGO=0) Feedback resistor — low-frequency, high-gain — 10 — MΩ mode (HGO=1) Feedback resistor — high-frequency, low-power — — — MΩ mode (HGO=0) Feedback resistor — high-frequency, high-gain — 1 — MΩ mode (HGO=1) R Series resistor — low-frequency, low-power — — — kΩ S mode (HGO=0) Series resistor — low-frequency, high-gain mode — 200 — kΩ (HGO=1) Series resistor — high-frequency, low-power — — — kΩ mode (HGO=0) Series resistor — high-frequency, high-gain mode (HGO=1) — 0 — kΩ Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 30 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 16. Oscillator DC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit Notes V 5 Peak-to-peak amplitude of oscillation (oscillator — 0.6 — V pp mode) — low-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator — V — V DD mode) — low-frequency, high-gain mode (HGO=1) Peak-to-peak amplitude of oscillation (oscillator — 0.6 — V mode) — high-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator — V — V DD mode) — high-frequency, high-gain mode (HGO=1) 1. V =3.3 V, Temperature =25 °C DD 2. See crystal or resonator manufacturer's recommendation 3. C ,C can be provided by using either the integrated capacitors or by using external components. x y 4. When low power mode is selected, R is integrated and must not be attached externally. F 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 Oscillator frequency specifications Table 17. Oscillator frequency specifications Symbol Description Min. Typ. Max. Unit Notes f Oscillator crystal or resonator frequency — low 32 — 40 kHz osc_lo frequency mode (MCG_C2[RANGE]=00) f Oscillator crystal or resonator frequency — high 3 — 8 MHz osc_hi_1 frequency mode (low range) (MCG_C2[RANGE]=01) f Oscillator crystal or resonator frequency — high 8 — 32 MHz osc_hi_2 frequency mode (high range) (MCG_C2[RANGE]=1x) f Input clock frequency (external clock mode) — — 50 MHz 1, 2 ec_extal t Input clock duty cycle (external clock mode) 40 50 60 % dc_extal t Crystal startup time — 32 kHz low-frequency, — 750 — ms 3, 4 cst low-power mode (HGO=0) Crystal startup time — 32 kHz low-frequency, — 250 — ms high-gain mode (HGO=1) Crystal startup time — 8 MHz high-frequency — 0.6 — ms (MCG_C2[RANGE]=01), low-power mode (HGO=0) Crystal startup time — 8 MHz high-frequency — 1 — ms (MCG_C2[RANGE]=01), high-gain mode (HGO=1) 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 31

Peripheral operating requirements and behaviors 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. NOTE The 32 kHz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 6.3.3 32 kHz Oscillator Electrical Characteristics This section describes the module electrical characteristics. 6.3.3.1 32 kHz oscillator DC electrical specifications Table 18. 32kHz oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit V Supply voltage 1.71 — 3.6 V BAT R Internal feedback resistor — 100 — MΩ F C Parasitical capacitance of EXTAL32 and XTAL32 — 5 7 pF para V 1 Peak-to-peak amplitude of oscillation — 0.6 — V pp 1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.3.2 32 kHz oscillator frequency specifications Table 19. 32 kHz oscillator frequency specifications Symbol Description Min. Typ. Max. Unit Notes f Oscillator crystal — 32.768 — kHz osc_lo t Crystal start-up time — 1000 — ms 1 start f Externally provided input clock frequency — 32.768 — kHz 2 ec_extal32 v Externally provided input clock amplitude 700 — V mV 2, 3 ec_extal32 BAT 1. Proper PC board layout procedures must be followed to achieve specifications. 2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The oscillator remains enabled and XTAL32 must be left unconnected. 3. The parameter specified is a peak-to-peak value and V and V specifications do not apply. The voltage of the applied IH IL clock must be within the range of V to V . SS BAT 6.4 Memories and memory interfaces K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 32 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 6.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 6.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 20. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit Notes t Longword Program high-voltage time — 7.5 18 μs hvpgm4 t Sector Erase high-voltage time — 13 113 ms 1 hversscr t Erase Block high-voltage time for 256 KB — 416 3616 ms 1 hversblk256k 1. Maximum time based on expectations at cycling end-of-life. 6.4.1.2 Flash timing specifications — commands Table 21. Flash command timing specifications Symbol Description Min. Typ. Max. Unit Notes Read 1s Block execution time t • 256 KB program/data flash — — 1.7 ms rd1blk256k t Read 1s Section execution time (flash sector) — — 60 μs 1 rd1sec2k t Program Check execution time — — 45 μs 1 pgmchk t Read Resource execution time — — 30 μs 1 rdrsrc t Program Longword execution time — 65 145 μs pgm4 Erase Flash Block execution time 2 t • 256 KB program/data flash — 435 3700 ms ersblk256k t Erase Flash Sector execution time — 14 114 ms 2 ersscr Program Section execution time t • 512 bytes flash — 2.4 — ms pgmsec512 t • 1 KB flash — 4.7 — ms pgmsec1k t • 2 KB flash — 9.3 — ms pgmsec2k t Read 1s All Blocks execution time — — 1.8 ms rd1all t Read Once execution time — — 25 μs 1 rdonce t Program Once execution time — 65 — μs pgmonce t Erase All Blocks execution time — 870 7400 ms 2 ersall t Verify Backdoor Access Key execution time — — 30 μs 1 vfykey Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 33

Peripheral operating requirements and behaviors Table 21. Flash command timing specifications (continued) Symbol Description Min. Typ. Max. Unit Notes Swap Control execution time t • control code 0x01 — 200 — μs swapx01 t • control code 0x02 — 70 150 μs swapx02 t • control code 0x04 — 70 150 μs swapx04 t • control code 0x08 — — 30 μs swapx08 Program Partition for EEPROM execution time t • 256 KB FlexNVM — — ms pgmpart64k 450 t pgmpart256k Set FlexRAM Function execution time: t • Control Code 0xFF — 70 — μs setramff t • 32 KB EEPROM backup — 0.8 1.2 ms setram32k t • 64 KB EEPROM backup — 1.3 1.9 ms setram64k t • 256 KB EEPROM backup — 4.5 5.5 ms setram256k Byte-write to FlexRAM for EEPROM operation t Byte-write to erased FlexRAM location execution — 175 260 μs 3 eewr8bers time Byte-write to FlexRAM execution time: t • 32 KB EEPROM backup — 385 1800 μs eewr8b32k t • 64 KB EEPROM backup — 475 2000 μs eewr8b64k t • 128 KB EEPROM backup — 650 2400 μs eewr8b128k t • 256 KB EEPROM backup — 1000 3200 μs eewr8b256k Word-write to FlexRAM for EEPROM operation t Word-write to erased FlexRAM location — 175 260 μs eewr16bers execution time Word-write to FlexRAM execution time: t • 32 KB EEPROM backup — 385 1800 μs eewr16b32k t • 64 KB EEPROM backup — 475 2000 μs eewr16b64k t • 128 KB EEPROM backup — 650 2400 μs eewr16b128k t • 256 KB EEPROM backup — 1000 3200 μs eewr16b256k Longword-write to FlexRAM for EEPROM operation t Longword-write to erased FlexRAM location — 360 540 μs eewr32bers execution time Longword-write to FlexRAM execution time: t • 32 KB EEPROM backup — 630 2050 μs eewr32b32k t • 64 KB EEPROM backup — 810 2250 μs eewr32b64k t • 128 KB EEPROM backup — 1200 2675 μs eewr32b128k t • 256 KB EEPROM backup — 1900 3500 μs eewr32b256k K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 34 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased. 6.4.1.3 Flash high voltage current behaviors Table 22. Flash high voltage current behaviors Symbol Description Min. Typ. Max. Unit I Average current adder during high voltage — 2.5 6.0 mA DD_PGM flash programming operation I Average current adder during high voltage — 1.5 4.0 mA DD_ERS flash erase operation 6.4.1.4 Reliability specifications Table 23. NVM reliability specifications Symbol Description Min. Typ.1 Max. Unit Notes Program Flash t Data retention after up to 10 K cycles 5 50 — years nvmretp10k t Data retention after up to 1 K cycles 20 100 — years nvmretp1k n Cycling endurance 10 K 50 K — cycles 2 nvmcycp Data Flash t Data retention after up to 10 K cycles 5 50 — years nvmretd10k t Data retention after up to 1 K cycles 20 100 — years nvmretd1k n Cycling endurance 10 K 50 K — cycles 2 nvmcycd FlexRAM as EEPROM t Data retention up to 100% of write endurance 5 50 — years nvmretee100 t Data retention up to 10% of write endurance 20 100 — years nvmretee10 Write endurance 3 n • EEPROM backup to FlexRAM ratio = 16 35 K 175 K — writes nvmwree16 n • EEPROM backup to FlexRAM ratio = 128 315 K 1.6 M — writes nvmwree128 n • EEPROM backup to FlexRAM ratio = 512 1.27 M 6.4 M — writes nvmwree512 n • EEPROM backup to FlexRAM ratio = 4096 10 M 50 M — writes nvmwree4k n • EEPROM backup to FlexRAM ratio = 80 M 400 M — writes nvmwree32k 32,768 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40°C ≤ T ≤ 125°C. j 3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and typical values assume all byte-writes to FlexRAM. K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 35

Peripheral operating requirements and behaviors 6.4.1.5 Write endurance to FlexRAM for EEPROM When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the flash memory module to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. EEPROM – 2 × EEESPLIT × EEESIZE Writes_subsystem = × Write_efficiency × n nvmcycd EEESPLIT × EEESIZE where • Writes_subsystem — minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance) • EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with the Program Partition command • EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command • EEESIZE — allocated FlexRAM based on DEPART; entered with the Program Partition command • Write_efficiency — • 0.25 for 8-bit writes to FlexRAM • 0.50 for 16-bit or 32-bit writes to FlexRAM • n — data flash cycling endurance (the following graph assumes 10,000 nvmcycd cycles) K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 36 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Figure 9. EEPROM backup writes to FlexRAM 6.4.2 EzPort Switching Specifications Table 24. EzPort switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V EP1 EZP_CK frequency of operation (all commands except — f /2 MHz SYS READ) EP1a EZP_CK frequency of operation (READ command) — f /8 MHz SYS EP2 EZP_CS negation to next EZP_CS assertion 2 x t — ns EZP_CK EP3 EZP_CS input valid to EZP_CK high (setup) 5 — ns EP4 EZP_CK high to EZP_CS input invalid (hold) 5 — ns EP5 EZP_D input valid to EZP_CK high (setup) 2 — ns EP6 EZP_CK high to EZP_D input invalid (hold) 5 — ns EP7 EZP_CK low to EZP_Q output valid — 16 ns EP8 EZP_CK low to EZP_Q output invalid (hold) 0 — ns EP9 EZP_CS negation to EZP_Q tri-state — 12 ns K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 37

Peripheral operating requirements and behaviors EZP_CK EP3 EP4 EP2 EZP_CS EP9 EP8 EP7 EZP_Q (output) EP5 EP6 EZP_D (input) Figure 10. EzPort Timing Diagram 6.4.3 Flexbus Switching Specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency. The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be derived from these values. Table 25. Flexbus limited voltage range switching specifications Num Description Min. Max. Unit Notes Operating voltage 2.7 3.6 V Frequency of operation — FB_CLK MHz FB1 Clock period 20 — ns FB2 Address, data, and control output valid — 11.5 ns 1 FB3 Address, data, and control output hold 0.5 — ns 1 FB4 Data and FB_TA input setup 8.5 — ns 2 FB5 Data and FB_TA input hold 0.5 — ns 2 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 38 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 2. Specification is valid for all FB_AD[31:0] and FB_TA. Table 26. Flexbus full voltage range switching specifications Num Description Min. Max. Unit Notes Operating voltage 1.71 3.6 V Frequency of operation — FB_CLK MHz FB1 Clock period 1/FB_CLK — ns FB2 Address, data, and control output valid — 13.5 ns 1 FB3 Address, data, and control output hold 0 — ns 1 FB4 Data and FB_TA input setup 13.7 — ns 2 FB5 Data and FB_TA input hold 0.5 — ns 2 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 39

Peripheral operating requirements and behaviors FB1 FB_CLK FB3 FB5 FB_A[Y] Address FB2 FB4 FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 11. FlexBus read timing diagram K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 40 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors FB1 FB_CLK FB2 FB3 FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 12. FlexBus write timing diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 41

Peripheral operating requirements and behaviors 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 27 and Table 28 are achievable on the differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and ADCx_DM3. The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are not direct device pins. Accuracy specifications for these pins are defined in Table 29 and Table 30. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit ADC operating conditions Table 27. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes V Supply voltage Absolute 1.71 — 3.6 V DDA ΔV Supply voltage Delta to V (V - V ) -100 0 +100 mV 2 DDA DD DD DDA ΔV Ground voltage Delta to V (V - V ) -100 0 +100 mV 2 SSA SS SS SSA V ADC reference 1.13 V V V REFH DDA DDA voltage high V ADC reference V V V V REFL SSA SSA SSA voltage low V Input voltage • 16-bit differential mode VREFL — 31/32 * V ADIN VREFH • All other modes VREFL — VREFH C Input capacitance • 16-bit mode — 8 10 pF ADIN • 8-bit / 10-bit / 12-bit — 4 5 modes R Input resistance — 2 5 kΩ ADIN R Analog source 13-bit / 12-bit modes 3 AS resistance f < 4 MHz — — 5 kΩ ADCK f ADC conversion ≤ 13-bit mode 1.0 — 18.0 MHz 4 ADCK clock frequency f ADC conversion 16-bit mode 2.0 — 12.0 MHz 4 ADCK clock frequency C ADC conversion ≤ 13-bit modes 5 rate rate No ADC hardware averaging 20.000 — 818.330 Ksps Continuous conversions enabled, subsequent conversion time Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 42 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 27. 16-bit ADC operating conditions (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes C ADC conversion 16-bit mode 5 rate rate No ADC hardware averaging 37.037 — 461.467 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume V = 3.0 V, Temp = 25 °C, f = 1.0 MHz, unless otherwise stated. Typical values are for DDA ADCK reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The R /C AS AS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED Pad Z CHANNEL SELECT AS leakage due to CIRCUIT ADC SAR R input R ENGINE AS protection ADIN V ADIN C V AS AS R ADIN IINNPPUUTT PPIINN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN Figure 13. ADC input impedance equivalency diagram 6.6.1.2 16-bit ADC electrical characteristics Table 28. 16-bit ADC characteristics (V = V , V = V ) REFH DDA REFL SSA Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes I Supply current 0.215 — 1.7 mA 3 DDA_ADC Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 43

Peripheral operating requirements and behaviors Table 28. 16-bit ADC characteristics (V = V , V = V ) (continued) REFH DDA REFL SSA Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes ADC • ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz tADACK = 1/ asynchronous f clock source • ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz ADACK f ADACK • ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz • ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz Sample Time See Reference Manual chapter for sample times TUE Total unadjusted • 12-bit modes — ±4 ±6.8 LSB4 5 error • <12-bit modes — ±1.4 ±2.1 DNL Differential non- • 12-bit modes — ±0.7 -1.1 to +1.9 LSB4 5 linearity -0.3 to 0.5 • <12-bit modes — ±0.2 INL Integral non- • 12-bit modes — ±1.0 -2.7 to +1.9 LSB4 5 linearity -0.7 to +0.5 • <12-bit modes — ±0.5 E Full-scale error • 12-bit modes — -4 -5.4 LSB4 V = FS ADIN V • <12-bit modes — -1.4 -1.8 DDA 5 E Quantization • 16-bit modes — -1 to 0 — LSB4 Q error • ≤13-bit modes — — ±0.5 ENOB Effective number 16-bit differential mode 6 of bits • Avg = 32 12.8 14.5 — bits • Avg = 4 11.9 13.8 — bits 16-bit single-ended mode • Avg = 32 12.2 13.9 — bits • Avg = 4 11.4 13.1 — bits Signal-to-noise See ENOB SINAD 6.02 × ENOB + 1.76 dB plus distortion THD Total harmonic 16-bit differential mode 7 distortion • Avg = 32 — –94 — dB 16-bit single-ended mode — -85 — dB • Avg = 32 SFDR Spurious free 16-bit differential mode 7 dynamic range • Avg = 32 82 95 — dB 16-bit single-ended mode 78 90 — dB • Avg = 32 Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 44 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 28. 16-bit ADC characteristics (V = V , V = V ) (continued) REFH DDA REFL SSA Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes E Input leakage I × R mV I = IL In AS In error leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor Across the full temperature 1.55 1.62 1.69 mV/°C slope range of the device V Temp sensor 25 °C 706 716 726 mV TEMP25 voltage 1. All accuracy numbers assume the ADC is calibrated with V = V REFH DDA 2. Typical values assume V = 3.0 V, Temp = 25°C, f = 2.0 MHz unless otherwise stated. Typical values are for DDA ADCK reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit must be set, the HSC bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (V - V )/2N REFH REFL 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. Figure 14. Typical ENOB vs. ADC_CLK for 16-bit differential mode K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 45

Peripheral operating requirements and behaviors Figure 15. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 6.6.1.3 16-bit ADC with PGA operating conditions Table 29. 16-bit ADC with PGA operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes V Supply voltage Absolute 1.71 — 3.6 V DDA V PGA ref voltage VREF_OU VREF_OU VREF_OU V 2, 3 REFPGA T T T V Input voltage V — V V ADIN SSA DDA V Input Common V — V V CM SSA DDA Mode range R Differential input Gain = 1, 2, 4, 8 — 128 — kΩ IN+ to IN-4 PGAD impedance Gain = 16, 32 — 64 — Gain = 64 — 32 — R Analog source — 100 — Ω 5 AS resistance T ADC sampling 1.25 — — µs 6 S time Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 46 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 29. 16-bit ADC with PGA operating conditions (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes C ADC conversion ≤ 13 bit modes 18.484 — 450 Ksps 7 rate rate No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 16 bit modes 37.037 — 250 Ksps 8 No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 1. Typical values assume V = 3.0 V, Temp = 25°C, f = 6 MHz unless otherwise stated. Typical values are for DDA ADCK reference only and are not tested in production. 2. ADC must be configured to use the internal voltage reference (VREF_OUT) 3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other than the output of the VREF module, the VREF module must be disabled. 4. For single ended configurations the input impedance of the driven input is R /2 PGAD 5. The analog source resistance (R ), external to MCU, should be kept as minimum as possible. Increased R causes drop AS AS in PGA gain without affecting other performances. This is not dependent on ADC clock frequency. 6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs time should be allowed for F =4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at in 8 MHz ADC clock. 7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1 8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1 6.6.1.4 16-bit ADC with PGA characteristics Table 30. 16-bit ADC with PGA characteristics Symbol Description Conditions Min. Typ.1 Max. Unit Notes I Supply current Low power — 420 644 μA 2 DDA_PGA (ADC_PGA[PGALPb]=0) I Input DC current A 3 DC_PGA Gain =1, V =1.2V, — 1.54 — μA REFPGA V =0.5V CM Gain =64, V =1.2V, — 0.57 — μA REFPGA V =0.1V CM Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 47

Peripheral operating requirements and behaviors Table 30. 16-bit ADC with PGA characteristics (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes G Gain4 • PGAG=0 0.95 1 1.05 RAS < 100Ω • PGAG=1 1.9 2 2.1 • PGAG=2 3.8 4 4.2 • PGAG=3 7.6 8 8.4 • PGAG=4 15.2 16 16.6 • PGAG=5 30.0 31.6 33.2 • PGAG=6 58.8 63.3 67.8 BW Input signal • 16-bit modes — — 4 kHz bandwidth • < 16-bit modes — — 40 kHz PSRR Power supply Gain=1 — -84 — dB V = 3V DDA rejection ratio ±100mV, f = 50Hz, VDDA 60Hz CMRR Common mode • Gain=1 — -84 — dB V = CM rejection ratio 500mVpp, • Gain=64 — -85 — dB f = 50Hz, VCM 100Hz V Input offset — 0.2 — mV Output offset = OFS voltage V *(Gain+1) OFS T Gain switching — — 10 µs 5 GSW settling time E Input leakage All modes I × R mV I = leakage IL In AS In error current (refer to the MCU's voltage and current operating ratings) V Maximum V 6 PP,DIFF differential input signal swing where V = V × 0.583 X REFPGA SNR Signal-to-noise • Gain=1 80 90 — dB 16-bit ratio differential • Gain=64 52 66 — dB mode, Average=32 THD Total harmonic • Gain=1 85 100 — dB 16-bit distortion differential • Gain=64 49 95 — dB mode, Average=32, f =100Hz in SFDR Spurious free • Gain=1 85 105 — dB 16-bit dynamic range differential • Gain=64 53 88 — dB mode, Average=32, f =100Hz in Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 48 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 30. 16-bit ADC with PGA characteristics (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes ENOB Effective number • Gain=1, Average=4 11.6 13.4 — bits 16-bit of bits differential • Gain=64, Average=4 7.2 9.6 — bits mode,f =100Hz in • Gain=1, Average=32 12.8 14.5 — bits • Gain=2, Average=32 11.0 14.3 — bits • Gain=4, Average=32 7.9 13.8 — bits • Gain=8, Average=32 7.3 13.1 — bits • Gain=16, Average=32 6.8 12.5 — bits • Gain=32, Average=32 6.8 11.5 — bits • Gain=64, Average=32 7.5 10.6 — bits SINAD Signal-to-noise See ENOB 6.02 × ENOB + 1.76 dB plus distortion ratio 1. Typical values assume V =3.0V, Temp=25°C, f =6MHz unless otherwise stated. DDA ADCK 2. This current is a PGA module adder, in addition to ADC conversion currents. 3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong function of input common mode voltage (V ) and the PGA gain. CM 4. Gain = 2PGAG 5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored. 6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the PGA reference voltage and gain setting. 6.6.2 CMP and 6-bit DAC electrical specifications Table 31. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit V Supply voltage 1.71 — 3.6 V DD I Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA DDHS I Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA DDLS V Analog input voltage V – 0.3 — V V AIN SS DD V Analog input offset voltage — — 20 mV AIO V Analog comparator hysteresis1 H • CR0[HYSTCTR] = 00 — 5 — mV • CR0[HYSTCTR] = 01 — 10 — mV • CR0[HYSTCTR] = 10 — 20 — mV • CR0[HYSTCTR] = 11 — 30 — mV V Output high V – 0.5 — — V CMPOh DD V Output low — — 0.5 V CMPOl t Propagation delay, high-speed mode (EN=1, 20 50 200 ns DHS PMODE=1) Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 49

Peripheral operating requirements and behaviors Table 31. Comparator and 6-bit DAC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit t Propagation delay, low-speed mode (EN=1, 80 250 600 ns DLS PMODE=0) Analog comparator initialization delay2 — — 40 μs I 6-bit DAC current adder (enabled) — 7 — μA DAC6b INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to V -0.6 V. DD 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = V /64 reference 0.08 0.07 0.06 0.05 HYSTCTR Setting V) s ( eri 00 er 0.04 yst 01 H P 1100 M C 0.03 11 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 50 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 0.18 0.16 0.14 0.12 HYSTCTR Setting V) s ( 0.1 eri 00 er yst 01 H P P 00.0088 1100 M C 11 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 17. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) 6.6.3 12-bit DAC electrical characteristics 6.6.3.1 12-bit DAC operating requirements Table 32. 12-bit DAC operating requirements Symbol Desciption Min. Max. Unit Notes V Supply voltage 1.71 3.6 V DDA V Reference voltage 1.13 3.6 V 1 DACR T Temperature Operating temperature °C A range of the device C Output load capacitance — 100 pF 2 L I Output load current — 1 mA L 1. The DAC reference can be selected to be V or the voltage output of the VREF module (VREF_OUT) DDA 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 51

Peripheral operating requirements and behaviors 6.6.3.2 12-bit DAC operating behaviors Table 33. 12-bit DAC operating behaviors Symbol Description Min. Typ. Max. Unit Notes I Supply current — low-power mode — — 150 μA DDA_DACL P I Supply current — high-speed mode — — 700 μA DDA_DACH P t Full-scale settling time (0x080 to 0xF7F) — — 100 200 μs 1 DACLP low-power mode t Full-scale settling time (0x080 to 0xF7F) — — 15 30 μs 1 DACHP high-power mode t Code-to-code settling time (0xBF8 to 0xC08) — 0.7 1 μs 1 CCDACLP — low-power mode and high-speed mode V DAC output voltage range low — high-speed — — 100 mV dacoutl mode, no load, DAC set to 0x000 V DAC output voltage range high — high- V — V mV dacouth DACR DACR speed mode, no load, DAC set to 0xFFF −100 INL Integral non-linearity error — high speed — — ±8 LSB 2 mode DNL Differential non-linearity error — V > 2 — — ±1 LSB 3 DACR V DNL Differential non-linearity error — V = — — ±1 LSB 4 DACR VREF_OUT V Offset error — ±0.4 ±0.8 %FSR 5 OFFSET E Gain error — ±0.1 ±0.6 %FSR 5 G PSRR Power supply rejection ratio, V ≥ 2.4 V 60 — 90 dB DDA T Temperature coefficient offset voltage — 3.7 — μV/C 6 CO T Temperature coefficient gain error — 0.000421 — %FSR/C GE Rop Output resistance load = 3 kΩ — — 250 Ω SR Slew rate -80h→ F7Fh→ 80h V/μs • High power (SP ) 1.2 1.7 — HP • Low power (SP ) 0.05 0.12 — LP CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth kHz • High power (SP ) 550 — — HP • Low power (SP ) 40 — — LP 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to V −100 mV DACR 3. The DNL is measured for 0 + 100 mV to V −100 mV DACR 4. The DNL is measured for 0 + 100 mV to V −100 mV with V > 2.4 V DACR DDA 5. Calculated by a best fit curve from V + 100 mV to V − 100 mV SS DACR 6. V = 3.0 V, reference select set for V (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to DDA DDA 0x800, temperature range is across the full range of the device K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 52 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Figure 18. Typical INL error vs. digital code K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 53

Peripheral operating requirements and behaviors Figure 19. Offset at half scale vs. temperature 6.6.4 Voltage reference electrical specifications Table 34. VREF full-range operating requirements Symbol Description Min. Max. Unit Notes V Supply voltage 1.71 3.6 V DDA T Temperature Operating temperature °C A range of the device C Output load capacitance 100 nF 1, 2 L 1. C must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external L reference. 2. The load capacitance should not exceed +/-25% of the nominal specified C value over the operating temperature range of L the device. K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 54 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 35. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit Notes V Voltage reference output with factory trim at 1.1915 1.195 1.1977 V out nominal V and temperature=25C DDA V Voltage reference output — factory trim 1.1584 — 1.2376 V out V Voltage reference trim step — 0.5 — mV step V Temperature drift (Vmax -Vmin across the full — — 80 mV tdrift temperature range) I Bandgap only current — — 80 µA 1 bg I Low-power buffer current — — 360 uA 1 lp I High-power buffer current — — 1 mA 1 hp ΔV Load regulation mV 1, 2 LOAD • current = + 1.0 mA — 2 — • current = - 1.0 mA — 5 — T Buffer startup time — — 100 µs stup V Voltage drift (Vmax -Vmin across the full voltage — 2 — mV 1 vdrift range) 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load Table 36. VREF limited-range operating requirements Symbol Description Min. Max. Unit Notes T Temperature 0 50 °C A Table 37. VREF limited-range operating behaviors Symbol Description Min. Max. Unit Notes V Voltage reference output with factory trim 1.173 1.225 V out 6.7 Timers See General switching specifications. 6.8 Communication interfaces K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 55

Peripheral operating requirements and behaviors 6.8.1 Ethernet switching specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 6.8.1.1 MII signal switching specifications The following timing specs meet the requirements for MII style interfaces for a range of transceiver devices. Table 38. MII signal switching specifications Symbol Description Min. Max. Unit — RXCLK frequency — 25 MHz MII1 RXCLK pulse width high 35% 65% RXCLK period MII2 RXCLK pulse width low 35% 65% RXCLK period MII3 RXD[3:0], RXDV, RXER to RXCLK setup 5 — ns MII4 RXCLK to RXD[3:0], RXDV, RXER hold 5 — ns — TXCLK frequency — 25 MHz MII5 TXCLK pulse width high 35% 65% TXCLK period MII6 TXCLK pulse width low 35% 65% TXCLK period MII7 TXCLK to TXD[3:0], TXEN, TXER invalid 2 — ns MII8 TXCLK to TXD[3:0], TXEN, TXER valid — 25 ns MII6 MII5 TXCLK (input) MII8 MII7 TXD[n:0] Valid data TXEN Valid data TXER Valid data Figure 20. MII transmit signal timing diagram K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 56 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors MII2 MII1 RXCLK (input) MII3 MII4 RXD[n:0] Valid data RXDV Valid data RXER Valid data Figure 21. MII receive signal timing diagram 6.8.1.2 RMII signal switching specifications The following timing specs meet the requirements for RMII style interfaces for a range of transceiver devices. Table 39. RMII signal switching specifications Num Description Min. Max. Unit — EXTAL frequency (RMII input clock RMII_CLK) — 50 MHz RMII1 RMII_CLK pulse width high 35% 65% RMII_CLK period RMII2 RMII_CLK pulse width low 35% 65% RMII_CLK period RMII3 RXD[1:0], CRS_DV, RXER to RMII_CLK setup 4 — ns RMII4 RMII_CLK to RXD[1:0], CRS_DV, RXER hold 2 — ns RMII7 RMII_CLK to TXD[1:0], TXEN invalid 4 — ns RMII8 RMII_CLK to TXD[1:0], TXEN valid — 15 ns 6.8.2 USB electrical specifications The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit usb.org. K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 57

Peripheral operating requirements and behaviors 6.8.3 USB DCD electrical specifications Table 40. USB DCD electrical specifications Symbol Description Min. Typ. Max. Unit V USB_DP source voltage (up to 250 μA) 0.5 — 0.7 V DP_SRC V Threshold voltage for logic high 0.8 — 2.0 V LGC I USB_DP source current 7 10 13 μA DP_SRC I USB_DM sink current 50 100 150 μA DM_SINK R D- pulldown resistance for data pin contact detect 14.25 — 24.8 kΩ DM_DWN V Data detect voltage 0.25 0.33 0.4 V DAT_REF 6.8.4 USB VREG electrical specifications Table 41. USB VREG electrical specifications Symbol Description Min. Typ.1 Max. Unit Notes VREGIN Input supply voltage 2.7 — 5.5 V I Quiescent current — Run mode, load current — 120 186 μA DDon equal zero, input supply (VREGIN) > 3.6 V I Quiescent current — Standby mode, load current — 1.27 30 μA DDstby equal zero I Quiescent current — Shutdown mode DDoff — 650 — nA • VREGIN = 5.0 V and temperature=25 °C — — 4 μA • Across operating voltage and temperature I Maximum load current — Run mode — — 120 mA LOADrun I Maximum load current — Standby mode — — 1 mA LOADstby V Regulator output voltage — Input supply Reg33out (VREGIN) > 3.6 V • Run mode 3 3.3 3.6 V • Standby mode 2.1 2.8 3.6 V V Regulator output voltage — Input supply 2.1 — 3.6 V 2 Reg33out (VREGIN) < 3.6 V, pass-through mode C External output capacitor 1.76 2.2 8.16 μF OUT ESR External output capacitor equivalent series 1 — 100 mΩ resistance I Short circuit current — 290 — mA LIM 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I . Load K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 58 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 6.8.5 CAN switching specifications See General switching specifications. 6.8.6 DSPI switching specifications (limited voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 42. Master mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Notes Operating voltage 2.7 3.6 V Frequency of operation — 25 MHz DS1 DSPI_SCK output cycle time 2 x t — ns BUS DS2 DSPI_SCK output high/low time (t /2) − 2 (t /2) + 2 ns SCK SCK DS3 DSPI_PCSn valid to DSPI_SCK delay (t x 2) − — ns 1 BUS 2 DS4 DSPI_SCK to DSPI_PCSn invalid delay (t x 2) − — ns 2 BUS 2 DS5 DSPI_SCK to DSPI_SOUT valid — 8.5 ns DS6 DSPI_SCK to DSPI_SOUT invalid −2 — ns DS7 DSPI_SIN to DSPI_SCK input setup 15 — ns DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DS2 DS1 DS4 DSPI_SCK DS8 (CPOL=0) DS7 DSPI_SIN First data Data Last data DS5 DS6 DSPI_SOUT First data Data Last data Figure 22. DSPI classic SPI timing — master mode K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 59

Peripheral operating requirements and behaviors Table 43. Slave mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation 12.5 MHz DS9 DSPI_SCK input cycle time 4 x t — ns BUS DS10 DSPI_SCK input high/low time (t /2) − 2 (t /2) + 2 ns SCK SCK DS11 DSPI_SCK to DSPI_SOUT valid — 10 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS13 DSPI_SIN to DSPI_SCK input setup 2 — ns DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns DS15 DSPI_SS active to DSPI_SOUT driven — 14 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven — 14 ns DSPI_SS DS10 DS9 DSPI_SCK (CPOL=0) DS15 DS12 DS11 DS16 DSPI_SOUT First data Data Last data DS13 DS14 DSPI_SIN First data Data Last data Figure 23. DSPI classic SPI timing — slave mode 6.8.7 DSPI switching specifications (full voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 44. Master mode DSPI timing (full voltage range) Num Description Min. Max. Unit Notes Operating voltage 1.71 3.6 V 1 Frequency of operation — 12.5 MHz DS1 DSPI_SCK output cycle time 4 x t — ns BUS Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 60 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 44. Master mode DSPI timing (full voltage range) (continued) Num Description Min. Max. Unit Notes DS2 DSPI_SCK output high/low time (t /2) - 4 (t + 4 ns SCK SCK/2) DS3 DSPI_PCSn valid to DSPI_SCK delay (t x 2) − — ns 2 BUS 4 DS4 DSPI_SCK to DSPI_PCSn invalid delay (t x 2) − — ns 3 BUS 4 DS5 DSPI_SCK to DSPI_SOUT valid — 10 ns DS6 DSPI_SCK to DSPI_SOUT invalid -4.5 — ns DS7 DSPI_SIN to DSPI_SCK input setup 20.5 — ns DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns 1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DS2 DS1 DS4 DSPI_SCK DS8 (CPOL=0) DS7 DSPI_SIN First data Data Last data DS5 DS6 DSPI_SOUT First data Data Last data Figure 24. DSPI classic SPI timing — master mode Table 45. Slave mode DSPI timing (full voltage range) Num Description Min. Max. Unit Operating voltage 1.71 3.6 V Frequency of operation — 6.25 MHz DS9 DSPI_SCK input cycle time 8 x t — ns BUS DS10 DSPI_SCK input high/low time (t /2) - 4 (t + 4 ns SCK SCK/2) DS11 DSPI_SCK to DSPI_SOUT valid — 20 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS13 DSPI_SIN to DSPI_SCK input setup 2 — ns DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns DS15 DSPI_SS active to DSPI_SOUT driven — 19 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven — 19 ns K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 61

Peripheral operating requirements and behaviors DSPI_SS DS10 DS9 DSPI_SCK (CPOL=0) DS15 DS12 DS11 DS16 DSPI_SOUT First data Data Last data DS13 DS14 DSPI_SIN First data Data Last data Figure 25. DSPI classic SPI timing — slave mode 6.8.8 Inter-Integrated Circuit Interface (I2C) timing Table 46. I 2C timing Characteristic Symbol Standard Mode Fast Mode Unit Minimum Maximum Minimum Maximum SCL Clock Frequency f 0 100 0 400 kHz SCL Hold time (repeated) START condition. t ; STA 4 — 0.6 — µs HD After this period, the first clock pulse is generated. LOW period of the SCL clock t 4.7 — 1.3 — µs LOW HIGH period of the SCL clock t 4 — 0.6 — µs HIGH Set-up time for a repeated START t ; STA 4.7 — 0.6 — µs SU condition Data hold time for I C bus devices t ; DAT 01 3.452 03 0.91 µs 2 HD Data set-up time t ; DAT 2504 — 1002, 5 — ns SU Rise time of SDA and SCL signals t — 1000 20 +0.1C 6 300 ns r b Fall time of SDA and SCL signals t — 300 20 +0.1C 5 300 ns f b Set-up time for STOP condition t ; STO 4 — 0.6 — µs SU Bus free time between STOP and t 4.7 — 1.3 — µs BUF START condition Pulse width of spikes that must be t N/A N/A 0 50 ns SP suppressed by the input filter 1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 3. Input signal Slew = 10ns and Output Load = 50pf 4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement t ≥ 250 ns must SU; DAT then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t + t rmax SU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 62 Freescale Semiconductor, Inc.

  Peripheral operating requirements and behaviors 6. C = total capacitance of the one bus line in pF. b SDA tSU; DAT tf tf tLOW tr tHD; STA tSP tr tBUF SCL tHD; STA tSU; STA tSU; STO S t t SR P S HD; DAT HIGH Figure 26. Timing definition for fast and standard mode devices on the I2C bus 6.8.9 UART switching specifications See General switching specifications. 6.8.10 SDHC specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. Table 47. SDHC switching specifications Num Symbol Description Min. Max. Unit Card input clock SD1 fpp Clock frequency (low speed) 0 400 kHz fpp Clock frequency (SD\SDIO full speed\high speed) 0 25\50 MHz fpp Clock frequency (MMC full speed\high speed) 0 20\50 MHz f Clock frequency (identification mode) 0 400 kHz OD SD2 t Clock low time 7 — ns WL SD3 t Clock high time 7 — ns WH SD4 t Clock rise time — 3 ns TLH SD5 t Clock fall time — 3 ns THL SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD6 t SDHC output delay (output valid) -5 8.3 ns OD SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD7 t SDHC input setup time 5 — ns ISU SD8 t SDHC input hold time 0 — ns IH K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 63

Peripheral operating requirements and behaviors SD3 SD2 SD1 SDHC_CLK SD6 Output SDHC_CMD Output SDHC_DAT[3:0] SD7 SD8 Input SDHC_CMD Input SDHC_DAT[3:0] Figure 27. SDHC timing 6.8.11 I2S switching specifications This section provides the AC timings for the I2S in master (clocks driven) and slave modes (clocks input). All timings are given for non-inverted serial clock polarity (TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0, RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync (I2S_FS) shown in the figures below. Table 48. I2S master mode timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V S1 I2S_MCLK cycle time 2 x t ns SYS S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_BCLK cycle time 5 x t — ns SYS S4 I2S_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_BCLK to I2S_FS output valid — 15 ns S6 I2S_BCLK to I2S_FS output invalid -2.5 — ns S7 I2S_BCLK to I2S_TXD valid — 15 ns S8 I2S_BCLK to I2S_TXD invalid -3 — ns S9 I2S_RXD/I2S_FS input setup before I2S_BCLK 20 — ns S10 I2S_RXD/I2S_FS input hold after I2S_BCLK 0 — ns K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 64 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_BCLK (output) S4 S4 S5 S6 I2S_FS (output) S9 S10 I2S_FS (input) S7 S7 S8 S8 I2S_TXD S9 S10 I2S_RXD Figure 28. I2S timing — master mode Table 49. I2S slave mode timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V S11 I2S_BCLK cycle time (input) 8 x t — ns SYS S12 I2S_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_FS input setup before I2S_BCLK 10 — ns S14 I2S_FS input hold after I2S_BCLK 3 — ns S15 I2S_BCLK to I2S_TXD/I2S_FS output valid — 20 ns S16 I2S_BCLK to I2S_TXD/I2S_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_BCLK 10 — ns S18 I2S_RXD hold after I2S_BCLK 2 — ns K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 65

Peripheral operating requirements and behaviors S11 S12 I2S_BCLK (input) S12 S15 S16 I2S_FS (output) S13 S14 I2S_FS (input) S15 S15 S16 S16 I2S_TXD S17 S18 I2S_RXD Figure 29. I2S timing — slave modes Table 50. I2S master mode timing (full voltage range) Num Description Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 2 x t ns SYS S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_BCLK cycle time 5 x t — ns SYS S4 I2S_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_BCLK to I2S_FS output valid — 15 ns S6 I2S_BCLK to I2S_FS output invalid -4.3 — ns S7 I2S_BCLK to I2S_TXD valid — 15 ns S8 I2S_BCLK to I2S_TXD invalid -4.6 — ns S9 I2S_RXD/I2S_FS input setup before I2S_BCLK 23.9 — ns S10 I2S_RXD/I2S_FS input hold after I2S_BCLK 0 — ns Table 51. I2S slave mode timing (full voltage range) Num Description Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_BCLK cycle time (input) 8 x t — ns SYS S12 I2S_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_FS input setup before I2S_BCLK 10 — ns S14 I2S_FS input hold after I2S_BCLK 3.5 — ns S15 I2S_BCLK to I2S_TXD/I2S_FS output valid — 28.6 ns S16 I2S_BCLK to I2S_TXD/I2S_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_BCLK 10 — ns S18 I2S_RXD hold after I2S_BCLK 2 — ns K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 66 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 6.9 Human-machine interfaces (HMI) 6.9.1 TSI electrical specifications Table 52. TSI electrical specifications Symbol Description Min. Typ. Max. Unit Notes V Operating voltage 1.71 — 3.6 V DDTSI C Target electrode capacitance range 1 20 500 pF 1 ELE f Reference oscillator frequency — 5.5 12.7 MHz 2 REFmax f Electrode oscillator frequency — 0.5 4.0 MHz 3 ELEmax C Internal reference capacitor 0.5 1 1.2 pF REF V Oscillator delta voltage 100 600 760 mV 4 DELTA I Reference oscillator current source base current μA 3 , 5 REF — 1.133 1.5 • 1uA setting (REFCHRG=0) • 32uA setting (REFCHRG=31) — 36 50 I Electrode oscillator current source base current μA 3 , 6 ELE — 1.133 1.5 • 1uA setting (EXTCHRG=0) • 32uA setting (EXTCHRG=31) — 36 50 Pres5 Electrode capacitance measurement precision — 8.3333 38400 fF/count 7 Pres20 Electrode capacitance measurement precision — 8.3333 38400 fF/count 8 Pres100 Electrode capacitance measurement precision — 8.3333 38400 fF/count 9 MaxSens Maximum sensitivity 0.003 12.5 — fF/count 10 Res Resolution — — 16 bits T Response time @ 20 pF 8 15 25 μs 11 Con20 I Current added in run mode — 55 — μA TSI_RUN I Low power mode current adder — 1.3 2.5 μA 12 TSI_LP 1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. 2. CAPTRM=7, DELVOL=7, and fixed external capacitance of 20 pF. 3. CAPTRM=0, DELVOL=2, and fixed external capacitance of 20 pF. 4. CAPTRM=0, EXTCHRG=9, and fixed external capacitance of 20 pF. 5. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current. 6. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current. 7. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16. 8. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16. 9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16. 10. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes, it is equal to (C ref * I )/( I * PS * NSCN). Sensitivity depends on the configuration used. The typical value listed is based on the following ext ref configuration: Iext = 5 μA, EXTCHRG = 4, PS = 128, NSCN = 2, Iref = 16 μA, REFCHRG = 15, Cref = 1.0 pF. The minimum sensitivity describes the smallest possible capacitance that can be measured by a single count (this is the best sensitivity but is described as a minimum because it’s the smallest number). The minimum sensitivity parameter is based on the following configuration: Iext = 1 μA, EXTCHRG = 0, PS = 128, NSCN = 32, Iref = 32 μA, REFCHRG = 31, Cref= 0.5 pF 11. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1 electrode, DELVOL = 2, EXTCHRG = 15. 12. CAPTRM=7, DELVOL=2, REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window. K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 67

Dimensions 7 Dimensions 7.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 121-pin MAPBGA 98ASA00344D 8 Pinout 8.1 K60 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 121 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort MAP BGA E4 PTE0 ADC1_SE4a ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 I2C1_SDA E3 PTE1/ ADC1_SE5a ADC1_SE5a PTE1/ SPI1_SOUT UART1_RX SDHC0_D0 I2C1_SCL LLWU_P0 LLWU_P0 E2 PTE2/ ADC1_SE6a ADC1_SE6a PTE2/ SPI1_SCK UART1_CTS_b SDHC0_DCLK LLWU_P1 LLWU_P1 F4 PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_b SDHC0_CMD E7 VDD VDD VDD F7 VSS VSS VSS H7 PTE4/ DISABLED PTE4/ SPI1_PCS0 UART3_TX SDHC0_D3 LLWU_P2 LLWU_P2 G4 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 F3 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CTS_b I2S0_MCLK I2S0_CLKIN E6 VDD VDD VDD G7 VSS VSS VSS L6 VSS VSS VSS F1 USB0_DP USB0_DP USB0_DP K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 68 Freescale Semiconductor, Inc.

Pinout 121 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort MAP BGA F2 USB0_DM USB0_DM USB0_DM G1 VOUT33 VOUT33 VOUT33 G2 VREGIN VREGIN VREGIN H1 ADC0_DP1 ADC0_DP1 ADC0_DP1 H2 ADC0_DM1 ADC0_DM1 ADC0_DM1 J1 ADC1_DP1 ADC1_DP1 ADC1_DP1 J2 ADC1_DM1 ADC1_DM1 ADC1_DM1 K1 PGA0_DP/ PGA0_DP/ PGA0_DP/ ADC0_DP0/ ADC0_DP0/ ADC0_DP0/ ADC1_DP3 ADC1_DP3 ADC1_DP3 K2 PGA0_DM/ PGA0_DM/ PGA0_DM/ ADC0_DM0/ ADC0_DM0/ ADC0_DM0/ ADC1_DM3 ADC1_DM3 ADC1_DM3 L1 PGA1_DP/ PGA1_DP/ PGA1_DP/ ADC1_DP0/ ADC1_DP0/ ADC1_DP0/ ADC0_DP3 ADC0_DP3 ADC0_DP3 L2 PGA1_DM/ PGA1_DM/ PGA1_DM/ ADC1_DM0/ ADC1_DM0/ ADC1_DM0/ ADC0_DM3 ADC0_DM3 ADC0_DM3 F5 VDDA VDDA VDDA G5 VREFH VREFH VREFH G6 VREFL VREFL VREFL F6 VSSA VSSA VSSA J3 ADC1_SE16/ ADC1_SE16/ ADC1_SE16/ CMP2_IN2/ CMP2_IN2/ CMP2_IN2/ ADC0_SE22 ADC0_SE22 ADC0_SE22 H3 ADC0_SE16/ ADC0_SE16/ ADC0_SE16/ CMP1_IN2/ CMP1_IN2/ CMP1_IN2/ ADC0_SE21 ADC0_SE21 ADC0_SE21 L3 VREF_OUT/ VREF_OUT/ VREF_OUT/ CMP1_IN5/ CMP1_IN5/ CMP1_IN5/ CMP0_IN5/ CMP0_IN5/ CMP0_IN5/ ADC1_SE18 ADC1_SE18 ADC1_SE18 K5 DAC0_OUT/ DAC0_OUT/ DAC0_OUT/ CMP1_IN3/ CMP1_IN3/ CMP1_IN3/ ADC0_SE23 ADC0_SE23 ADC0_SE23 K4 DAC1_OUT/ DAC1_OUT/ DAC1_OUT/ CMP2_IN3/ CMP2_IN3/ CMP2_IN3/ ADC1_SE23 ADC1_SE23 ADC1_SE23 L4 XTAL32 XTAL32 XTAL32 L5 EXTAL32 EXTAL32 EXTAL32 K6 VBAT VBAT VBAT H5 PTE24 ADC0_SE17 ADC0_SE17 PTE24 CAN1_TX UART4_TX EWM_OUT_b J5 PTE25 ADC0_SE18 ADC0_SE18 PTE25 CAN1_RX UART4_RX EWM_IN H6 PTE26 DISABLED PTE26 UART4_CTS_b ENET_1588_ RTC_CLKOUT USB_CLKIN CLKIN K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 69

Pinout 121 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort MAP BGA J6 PTA0 JTAG_TCLK/ TSI0_CH1 PTA0 UART0_CTS_b FTM0_CH5 JTAG_TCLK/ EZP_CLK SWD_CLK/ SWD_CLK EZP_CLK H8 PTA1 JTAG_TDI/ TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI EZP_DI J7 PTA2 JTAG_TDO/ TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/ EZP_DO TRACE_SWO/ TRACE_SWO EZP_DO H9 PTA3 JTAG_TMS/ TSI0_CH4 PTA3 UART0_RTS_b FTM0_CH0 JTAG_TMS/ SWD_DIO SWD_DIO J8 PTA4/ NMI_b/ TSI0_CH5 PTA4/ FTM0_CH1 NMI_b EZP_CS_b LLWU_P3 EZP_CS_b LLWU_P3 K7 PTA5 DISABLED PTA5 FTM0_CH2 RMII0_RXER/ CMP2_OUT I2S0_RX_BCLK JTAG_TRST MII0_RXER E5 VDD VDD VDD G3 VSS VSS VSS J9 PTA10 DISABLED PTA10 FTM2_CH0 MII0_RXD2 FTM2_QD_ TRACE_D0 PHA J4 PTA11 DISABLED PTA11 FTM2_CH1 MII0_RXCLK FTM2_QD_ PHB K8 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 RMII0_RXD1/ I2S0_TXD FTM1_QD_ MII0_RXD1 PHA L8 PTA13/ CMP2_IN1 CMP2_IN1 PTA13/ CAN0_RX FTM1_CH1 RMII0_RXD0/ I2S0_TX_FS FTM1_QD_ LLWU_P4 LLWU_P4 MII0_RXD0 PHB K9 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX RMII0_CRS_ I2S0_TX_BCLK DV/ MII0_RXDV L9 PTA15 DISABLED PTA15 SPI0_SCK UART0_RX RMII0_TXEN/ I2S0_RXD MII0_TXEN J10 PTA16 DISABLED PTA16 SPI0_SOUT UART0_CTS_b RMII0_TXD0/ I2S0_RX_FS MII0_TXD0 H10 PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_RTS_b RMII0_TXD1/ I2S0_MCLK I2S0_CLKIN MII0_TXD1 L10 VDD VDD VDD K10 VSS VSS VSS L11 PTA18 EXTAL EXTAL PTA18 FTM0_FLT2 FTM_CLKIN0 K11 PTA19 XTAL XTAL PTA19 FTM1_FLT0 FTM_CLKIN1 LPT0_ALT1 J11 RESET_b RESET_b RESET_b H11 PTA29 DISABLED PTA29 MII0_COL FB_A24 G11 PTB0/ ADC0_SE8/ ADC0_SE8/ PTB0/ I2C0_SCL FTM1_CH0 RMII0_MDIO/ FTM1_QD_ LLWU_P5 ADC1_SE8/ ADC1_SE8/ LLWU_P5 MII0_MDIO PHA TSI0_CH0 TSI0_CH0 G10 PTB1 ADC0_SE9/ ADC0_SE9/ PTB1 I2C0_SDA FTM1_CH1 RMII0_MDC/ FTM1_QD_ ADC1_SE9/ ADC1_SE9/ MII0_MDC PHB TSI0_CH6 TSI0_CH6 G9 PTB2 ADC0_SE12/ ADC0_SE12/ PTB2 I2C0_SCL UART0_RTS_b ENET0_1588_ FTM0_FLT3 TSI0_CH7 TSI0_CH7 TMR0 K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 70 Freescale Semiconductor, Inc.

Pinout 121 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort MAP BGA G8 PTB3 ADC0_SE13/ ADC0_SE13/ PTB3 I2C0_SDA UART0_CTS_b ENET0_1588_ FTM0_FLT0 TSI0_CH8 TSI0_CH8 TMR1 F11 PTB6 ADC1_SE12 ADC1_SE12 PTB6 FB_AD23 E11 PTB7 ADC1_SE13 ADC1_SE13 PTB7 FB_AD22 D11 PTB8 PTB8 UART3_RTS_b FB_AD21 E10 PTB9 PTB9 SPI1_PCS1 UART3_CTS_b FB_AD20 D10 PTB10 ADC1_SE14 ADC1_SE14 PTB10 SPI1_PCS0 UART3_RX FB_AD19 FTM0_FLT1 C10 PTB11 ADC1_SE15 ADC1_SE15 PTB11 SPI1_SCK UART3_TX FB_AD18 FTM0_FLT2 B10 PTB16 TSI0_CH9 TSI0_CH9 PTB16 SPI1_SOUT UART0_RX FB_AD17 EWM_IN E9 PTB17 TSI0_CH10 TSI0_CH10 PTB17 SPI1_SIN UART0_TX FB_AD16 EWM_OUT_b D9 PTB18 TSI0_CH11 TSI0_CH11 PTB18 CAN0_TX FTM2_CH0 I2S0_TX_BCLK FB_AD15 FTM2_QD_ PHA C9 PTB19 TSI0_CH12 TSI0_CH12 PTB19 CAN0_RX FTM2_CH1 I2S0_TX_FS FB_OE_b FTM2_QD_ PHB F10 PTB20 PTB20 SPI2_PCS0 FB_AD31 CMP0_OUT F9 PTB21 PTB21 SPI2_SCK FB_AD30 CMP1_OUT F8 PTB22 PTB22 SPI2_SOUT FB_AD29 CMP2_OUT E8 PTB23 PTB23 SPI2_SIN SPI0_PCS5 FB_AD28 B9 PTC0 ADC0_SE14/ ADC0_SE14/ PTC0 SPI0_PCS4 PDB0_EXTRG I2S0_TXD FB_AD14 TSI0_CH13 TSI0_CH13 D8 PTC1/ ADC0_SE15/ ADC0_SE15/ PTC1/ SPI0_PCS3 UART1_RTS_b FTM0_CH0 FB_AD13 LLWU_P6 TSI0_CH14 TSI0_CH14 LLWU_P6 C8 PTC2 ADC0_SE4b/ ADC0_SE4b/ PTC2 SPI0_PCS2 UART1_CTS_b FTM0_CH1 FB_AD12 CMP1_IN0/ CMP1_IN0/ TSI0_CH15 TSI0_CH15 B8 PTC3/ CMP1_IN1 CMP1_IN1 PTC3/ SPI0_PCS1 UART1_RX FTM0_CH2 FB_CLKOUT LLWU_P7 LLWU_P7 A8 PTC4/ PTC4/ SPI0_PCS0 UART1_TX FTM0_CH3 FB_AD11 CMP1_OUT LLWU_P8 LLWU_P8 D7 PTC5/ PTC5/ SPI0_SCK LPT0_ALT2 FB_AD10 CMP0_OUT LLWU_P9 LLWU_P9 C7 PTC6/ CMP0_IN0 CMP0_IN0 PTC6/ SPI0_SOUT PDB0_EXTRG FB_AD9 LLWU_P10 LLWU_P10 B7 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN FB_AD8 A7 PTC8 ADC1_SE4b/ ADC1_SE4b/ PTC8 I2S0_MCLK I2S0_CLKIN FB_AD7 CMP0_IN2 CMP0_IN2 D6 PTC9 ADC1_SE5b/ ADC1_SE5b/ PTC9 I2S0_RX_BCLK FB_AD6 FTM2_FLT0 CMP0_IN3 CMP0_IN3 C6 PTC10 ADC1_SE6b/ ADC1_SE6b/ PTC10 I2C1_SCL I2S0_RX_FS FB_AD5 CMP0_IN4 CMP0_IN4 C5 PTC11/ ADC1_SE7b ADC1_SE7b PTC11/ I2C1_SDA I2S0_RXD FB_RW_b LLWU_P11 LLWU_P11 B6 PTC12 PTC12 UART4_RTS_b FB_AD27 A6 PTC13 PTC13 UART4_CTS_b FB_AD26 A5 PTC14 PTC14 UART4_RX FB_AD25 K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 71

Pinout 121 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort MAP BGA B5 PTC15 PTC15 UART4_TX FB_AD24 D5 PTC16 PTC16 CAN1_RX UART3_RX ENET0_1588_ FB_CS5_b/ TMR0 FB_TSIZ1/ FB_BE23_16_b C4 PTC17 PTC17 CAN1_TX UART3_TX ENET0_1588_ FB_CS4_b/ TMR1 FB_TSIZ0/ FB_BE31_24_b B4 PTC18 PTC18 UART3_RTS_b ENET0_1588_ FB_TBST_b/ TMR2 FB_CS2_b/ FB_BE15_8_b A4 PTC19 PTC19 UART3_CTS_b ENET0_1588_ FB_CS3_b/ FB_TA_b TMR3 FB_BE7_0_b D4 PTD0/ PTD0/ SPI0_PCS0 UART2_RTS_b FB_ALE/ LLWU_P12 LLWU_P12 FB_CS1_b/ FB_TS_b D3 PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK UART2_CTS_b FB_CS0_b C3 PTD2/ PTD2/ SPI0_SOUT UART2_RX FB_AD4 LLWU_P13 LLWU_P13 B3 PTD3 PTD3 SPI0_SIN UART2_TX FB_AD3 A3 PTD4/ PTD4/ SPI0_PCS1 UART0_RTS_b FTM0_CH4 FB_AD2 EWM_IN LLWU_P14 LLWU_P14 A2 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_b FTM0_CH5 FB_AD1 EWM_OUT_b B2 PTD6/ ADC0_SE7b ADC0_SE7b PTD6/ SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 FTM0_FLT0 LLWU_P15 LLWU_P15 A1 PTD7 PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1 A10 PTD8 DISABLED PTD8 I2C0_SCL UART5_RX FB_A16 A9 PTD9 DISABLED PTD9 I2C0_SDA UART5_TX FB_A17 B1 PTD10 DISABLED PTD10 UART5_RTS_b FB_A18 C2 PTD11 DISABLED PTD11 SPI2_PCS0 UART5_CTS_b SDHC0_CLKIN FB_A19 C1 PTD12 DISABLED PTD12 SPI2_SCK SDHC0_D4 FB_A20 D2 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21 D1 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22 E1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23 L7 RESERVED RESERVED RESERVED A11 NC NC NC B11 NC NC NC C11 NC NC NC K3 NC NC NC H4 NC NC NC K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 72 Freescale Semiconductor, Inc.

Revision History 8.2 K60 Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. 1 2 3 4 5 6 7 8 9 10 11 A PTD7 PTD5 PTD4 PTC19 PTC14 PTC13 PTC8 PTC4 PTD9 PTD8 NC A B PTD10 PTD6 PTD3 PTC18 PTC15 PTC12 PTC7 PTC3 PTC0 PTB16 NC B C PTD12 PTD11 PTD2 PTC17 PTC11 PTC10 PTC6 PTC2 PTB19 PTB11 NC C D PTD14 PTD13 PTD1 PTD0 PTC16 PTC9 PTC5 PTC1 PTB18 PTB10 PTB8 D E PTD15 PTE2 PTE1 PTE0 VDD VDD VDD PTB23 PTB17 PTB9 PTB7 E F USB0_DP USB0_DM PTE6 PTE3 VDDA VSSA VSS PTB22 PTB21 PTB20 PTB6 F G VOUT33 VREGIN VSS PTE5 VREFH VREFL VSS PTB3 PTB2 PTB1 PTB0 G ADC0_SE16/ H ADC0_DP1 ADC0_DM1 CMP1_IN2/ NC PTE24 PTE26 PTE4 PTA1 PTA3 PTA17 PTA29 H ADC0_SE21 ADC1_SE16/ J ADC1_DP1 ADC1_DM1 CMP2_IN2/ PTA11 PTE25 PTA0 PTA2 PTA4 PTA10 PTA16 RESET_b J ADC0_SE22 PGA0_DP/ PGA0_DM/ DAC1_OUT/ DAC0_OUT/ K ADC0_DP0/ ADC0_DM0/ NC CMP2_IN3/ CMP1_IN3/ VBAT PTA5 PTA12 PTA14 VSS PTA19 K ADC1_DP3 ADC1_DM3 ADC1_SE23 ADC0_SE23 L AAPDDGCCA101___DDDPPP03// AAPDDGCCA101___DDDMMM03// AVCCDRMMCEPPF110____SOIINNEU155T8/// XTAL32 EXTAL32 VSS RESERVED PTA13 PTA15 VDD PTA18 L 1 2 3 4 5 6 7 8 9 10 11 Figure 30. K60 121 MAPBGA Pinout Diagram 9 Revision History The following table provides a revision history for this document. K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 73

Revision History Table 53. Revision History Rev. No. Date Substantial Changes 1 11/2010 Initial public revision 2 3/2011 Many updates throughout 3 3/2011 Added sections that were inadvertently removed in previous revision 4 3/2011 Reworded I footnote in "Voltage and Current Operating Requirements" table. IC Added paragraph to "Peripheral operating requirements and behaviors" section. Added "JTAG full voltage range electricals" table to the "JTAG electricals" section. 5 6/2011 • Changed supported part numbers per new part number scheme • Changed DC injection current specs in "Voltage and current operating requirements" table • Changed Input leakage current and internal pullup/pulldown resistor specs in "Voltage and current operating behaviors" table • Split Low power stop mode current specs by temperature range in "Power consumption operating behaviors" table • Changed typical I spec in "Power consumption operating behaviors" table DD_VBAT • Added ENET and LPTMR clock specs to "Device clock specifications" table • Changed Minimum external reset pulse width in "General switching specifications" table • Changed PLL operating current in "MCG specifications" table • Added footnote to PLL period jitter in "MCG specifications" table • Changed Supply current in "Oscillator DC electrical specifications" table • Changed Crystal startup time in "Oscillator frequency specifications" table • Changed Operating voltage in "EzPort switching specifications" table • Changed title of "FlexBus switching specifications" table and added Output valid and hold specs • Added "FlexBus full range switching specifications" table • Changed ADC asynchronous clock source specs in "16-bit ADC characteristics" table • Changed Gain spec in "16-bit ADC with PGA characteristics" table • Added typical Input DC current to "16-bit ADC with PGA characteristics" table • Changed Input offset voltage and ENOB notes field in "16-bit ADC with PGA characteristics" table • Changed Analog comparator initialization delay in "Comparator and 6-bit DAC electrical specifications" • Changed Code-to-code settling time, DAC output voltage range low, and Temperature coefficient offset voltage in "12-bit DAC operating behaviors" table • Changed Temperature drift and Load regulation in "VREF full-range operating behaviors" table • Changed Regulator output voltage in "USB VREG electrical specifications" table • Changed I description and specs in "USB VREG electrical specifications" table LIM • Changed DSPI_SCK cycle time specs in "DSPI timing" tables • Changed DSPI_SS specs in "Slave mode DSPI timing (low-speed mode)" table • Changed DSPI_SCK to DSPI_SOUT valid spec in "Slave mode DSPI timing (high- speed mode)" table • Changed Reference oscillator current source base current spec and added Low-power current adder footer in "TSI electrical specifications" table Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 74 Freescale Semiconductor, Inc.

Revision History Table 53. Revision History (continued) Rev. No. Date Substantial Changes 6 01/2012 • Added AC electrical specifications. • Replaced TBDs with silicon data throughout. • In "Power mode transition operating behaviors" table, removed entry times. • Updated "EMC radiated emissions operating behaviors" to remove SAE level and also added data for 144LQFP. • Clarified "EP7" in "EzPort switching specifications" table and "EzPort Timing Diagram". • Added "ENOB vs. ADC_CLK for 16-bit differential and 16-bit single-ended modes" figures. • Updated I numbers in 'Power consumption operating behaviors' section. DD_RUN • Clarified 'Diagram: Typical IDD_RUN operating behavior' section and updated 'Run mode supply current vs. core frequency — all peripheral clocks disabled' figure. • In 'Voltage reference electrical specifications' section, updated C , V , and V L tdrift vdrift values. • In 'USB electrical specifications' section, updated V , I , and 'V DP_SRC DDstby Reg33out values. 7 02/2013 • In "ESD handling ratings", added a note for I . LAT • Updated "Voltage and current operating requirements". • Updated "Voltage and current operating behaviors". • Updated "Power mode transition operating behaviors". • Updated "EMC radiated emissions operating behaviors" to add MAPBGA data. • In "MCG specifications", updated the description of f . ints_t • In "16-bit ADC operating conditions", updated the max spec of V . ADIN • In "16-bit ADC electrical characteristics", updated the temp sensor slope and voltage specs. • Updated "I2C switching specifications". • In "SDHC specifications", removed the operating voltage limits and updated the SD1 and SD6 specs. • In "I2S switching specifications", added separate specification tables for the full operating voltage range. K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. 75

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