Freescale Semiconductor Document Number: K60P144M100SF2V2 Data Sheet: Technical Data Rev. 3, 6/2013 K60P144M100SF2V2 K60 Sub-Family Supports the following: MK60DN256VLQ10, MK60DX256VLQ10, MK60DN512VLQ10, MK60DN256VMD10, MK60DX256VMD10, MK60DN512VMD10 Features • Security and integrity modules • Operating Characteristics – Hardware CRC module to support fast cyclic – Voltage range: 1.71 to 3.6 V redundancy checks – Flash write voltage range: 1.71 to 3.6 V – Hardware random-number generator – Temperature range (ambient): -40 to 105°C – Hardware encryption supporting DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms • Performance – 128-bit unique identification (ID) number per chip – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per • Human-machine interface MHz – Low-power hardware touch sensor interface (TSI) – General-purpose input/output • Memories and memory interfaces – Up to 512 KB program flash memory on non- • Analog modules FlexMemory devices – Two 16-bit SAR ADCs – Up to 256 KB program flash memory on – Programmable gain amplifier (PGA) (up to x64) FlexMemory devices integrated into each ADC – Up to 256 KB FlexNVM on FlexMemory devices – Two 12-bit DACs – 4 KB FlexRAM on FlexMemory devices – Two transimpedance amplifiers – Up to 128 KB RAM – Three analog comparators (CMP) containing a 6-bit – Serial programming interface (EzPort) DAC and programmable reference input – FlexBus external bus interface – Voltage reference • Clocks • Timers – 3 to 32 MHz crystal oscillator – Programmable delay block – 32 kHz crystal oscillator – Eight-channel motor control/general purpose/PWM – Multi-purpose clock generator timer – Two 2-channel quadrature decoder/general purpose • System peripherals timers – Multiple low-power modes to provide power – IEEE 1588 timers optimization based on application requirements – Periodic interrupt timers – Memory protection unit with multi-master – 16-bit low-power timer protection – Carrier modulator transmitter – 16-channel DMA controller, supporting up to 63 – Real-time clock request sources – External watchdog monitor – Software watchdog – Low-leakage wakeup unit Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012–2013 Freescale Semiconductor, Inc.

• Communication interfaces – Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability – USB full-/low-speed On-the-Go controller with on-chip transceiver – Two Controller Area Network (CAN) modules – Three SPI modules – Two I2C modules – Six UART modules – Secure Digital host controller (SDHC) – I2S module K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 2 Freescale Semiconductor, Inc.

Table of Contents 1 Ordering parts...........................................................................5 5.4.2 Thermal attributes...............................................23 1.1 Determining valid orderable parts......................................5 6 Peripheral operating requirements and behaviors....................24 2 Part identification......................................................................5 6.1 Core modules....................................................................24 2.1 Description.........................................................................5 6.1.1 Debug trace timing specifications.......................24 2.2 Format...............................................................................5 6.1.2 JTAG electricals..................................................25 2.3 Fields.................................................................................5 6.2 System modules................................................................28 2.4 Example............................................................................6 6.3 Clock modules...................................................................28 3 Terminology and guidelines......................................................6 6.3.1 MCG specifications.............................................28 3.1 Definition: Operating requirement......................................6 6.3.2 Oscillator electrical specifications.......................30 3.2 Definition: Operating behavior...........................................7 6.3.3 32 kHz oscillator electrical characteristics..........33 3.3 Definition: Attribute............................................................7 6.4 Memories and memory interfaces.....................................33 3.4 Definition: Rating...............................................................8 6.4.1 Flash electrical specifications.............................33 3.5 Result of exceeding a rating..............................................8 6.4.2 EzPort switching specifications...........................38 3.6 Relationship between ratings and operating 6.4.3 Flexbus switching specifications.........................39 requirements......................................................................8 6.5 Security and integrity modules..........................................42 3.7 Guidelines for ratings and operating requirements............9 6.6 Analog...............................................................................42 3.8 Definition: Typical value.....................................................9 6.6.1 ADC electrical specifications..............................42 3.9 Typical value conditions....................................................10 6.6.2 CMP and 6-bit DAC electrical specifications......50 4 Ratings......................................................................................11 6.6.3 12-bit DAC electrical characteristics...................53 4.1 Thermal handling ratings...................................................11 6.6.4 Voltage reference electrical specifications..........56 4.2 Moisture handling ratings..................................................11 6.7 Timers................................................................................57 4.3 ESD handling ratings.........................................................11 6.8 Communication interfaces.................................................57 4.4 Voltage and current operating ratings...............................11 6.8.1 Ethernet switching specifications........................57 5 General.....................................................................................12 6.8.2 USB electrical specifications...............................59 5.1 AC electrical characteristics..............................................12 6.8.3 USB DCD electrical specifications......................59 5.2 Nonswitching electrical specifications...............................12 6.8.4 USB VREG electrical specifications...................60 5.2.1 Voltage and current operating requirements......13 6.8.5 CAN switching specifications..............................60 5.2.2 LVD and POR operating requirements...............14 6.8.6 DSPI switching specifications (limited voltage 5.2.3 Voltage and current operating behaviors............14 range).................................................................61 5.2.4 Power mode transition operating behaviors.......16 6.8.7 DSPI switching specifications (full voltage 5.2.5 Power consumption operating behaviors............17 range).................................................................62 5.2.6 EMC radiated emissions operating behaviors....20 6.8.8 Inter-Integrated Circuit Interface (I2C) timing.....64 5.2.7 Designing with radiated emissions in mind.........21 6.8.9 UART switching specifications............................65 5.2.8 Capacitance attributes........................................21 6.8.10 SDHC specifications...........................................65 5.3 Switching specifications.....................................................21 6.8.11 I2S/SAI switching specifications.........................66 5.3.1 Device clock specifications.................................21 6.9 Human-machine interfaces (HMI)......................................72 5.3.2 General switching specifications.........................22 6.9.1 TSI electrical specifications................................72 5.4 Thermal specifications.......................................................23 7 Dimensions...............................................................................73 5.4.1 Thermal operating requirements.........................23 7.1 Obtaining package dimensions.........................................73 K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 3

8 Pinout........................................................................................73 8.2 K60 pinouts.......................................................................79 8.1 K60 signal multiplexing and pin assignments....................73 9 Revision history.........................................................................81 K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 4 Freescale Semiconductor, Inc.

Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: PK60 and MK60. 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.2 Format Part numbers for this device have the following format: Q K## A M FFF R T PP CC N 2.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow • P = Prequalification K## Kinetis family • K60 A Key attribute • D = Cortex-M4 w/ DSP • F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only • X = Program flash and FlexMemory Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 5

Terminology and guidelines Field Description Values FFF Program flash memory size • 32 = 32 KB • 64 = 64 KB • 128 = 128 KB • 256 = 256 KB • 512 = 512 KB • 1M0 = 1 MB • 2M0 = 2 MB R Silicon revision • Z = Initial • (Blank) = Main • A = Revision after main T Temperature range (°C) • V = –40 to 105 • C = –40 to 85 PP Package identifier • FM = 32 QFN (5 mm x 5 mm) • FT = 48 QFN (7 mm x 7 mm) • LF = 48 LQFP (7 mm x 7 mm) • LH = 64 LQFP (10 mm x 10 mm) • MP = 64 MAPBGA (5 mm x 5 mm) • LK = 80 LQFP (12 mm x 12 mm) • LL = 100 LQFP (14 mm x 14 mm) • MC = 121 MAPBGA (8 mm x 8 mm) • LQ = 144 LQFP (20 mm x 20 mm) • MD = 144 MAPBGA (13 mm x 13 mm) • MJ = 256 MAPBGA (17 mm x 17 mm) CC Maximum CPU frequency (MHz) • 5 = 50 MHz • 7 = 72 MHz • 10 = 100 MHz • 12 = 120 MHz • 15 = 150 MHz N Packaging type • R = Tape and reel • (Blank) = Trays 2.4 Example This is an example part number: MK60DN512ZVMD10 3 Terminology and guidelines 3.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 6 Freescale Semiconductor, Inc.

Terminology and guidelines 3.1.1 Example This is an example of an operating requirement: Symbol Description Min. Max. Unit V 1.0 V core supply 0.9 1.1 V DD voltage 3.2 Definition: Operating behavior An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 Example This is an example of an operating behavior: Symbol Description Min. Max. Unit I Digital I/O weak pullup/ 10 130 µA WP pulldown current 3.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 Example This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: — 7 pF digital pins K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 7

Terminology and guidelines 3.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. 3.4.1 Example This is an example of an operating rating: Symbol Description Min. Max. Unit V 1.0 V core supply –0.3 1.2 V DD voltage 3.5 Result of exceeding a rating 40 m) 30 p p e ( s in tim 20 Tsohoen l ikaesl iah ocohda roafc pteerrimstiacn beengt icnhsi pto f aeixlucreee idn corneea soef sit sra oppidelrya atins g ratings. e ur Fail 10 0 Operating rating Measured characteristic K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 8 Freescale Semiconductor, Inc.

Terminology and guidelines 3.6 Relationship between ratings and operating requirements O perating rating (min.) O perating require m ent (min.) O perating require m ent (m ax.) O perating rating (m ax.) Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - No permanent failure - No permanent failure Expected permanent failure - Possible decreased life - Correct operation - Possible decreased life - Possible incorrect operation - Possible incorrect operation –∞ ∞ Operating (power on) H andling rating (min.) H andling rating (m ax.) Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure –∞ ∞ Handling (power off) 3.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 9

Terminology and guidelines 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit I Digital I/O weak 10 70 130 µA WP pullup/pulldown current 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 T 3500 J 150 °C A) 3000 μ ( 105 °C P O 2500 T S 25 °C _ D ID 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 V (V) DD 3.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit T Ambient temperature 25 °C A V 3.3 V supply voltage 3.3 V DD K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 10 Freescale Semiconductor, Inc.

Ratings 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes T Storage temperature –55 150 °C 1 STG T Solder temperature, lead-free — 260 °C 2 SDR 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.2 Moisture handling ratings Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.3 ESD handling ratings Symbol Description Min. Max. Unit Notes V Electrostatic discharge voltage, human body model -2000 +2000 V 1 HBM V Electrostatic discharge voltage, charged-device model -500 +500 V 2 CDM I Latch-up current at ambient temperature of 105°C -100 +100 mA 3 LAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 4.4 Voltage and current operating ratings K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 11

General Symbol Description Min. Max. Unit V Digital supply voltage –0.3 3.8 V DD I Digital supply current — 185 mA DD V Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 5.5 V DIO V Analog1, RESET, EXTAL, and XTAL input voltage –0.3 V + 0.3 V AIO DD I Maximum current single pin limit (applies to all digital pins) –25 25 mA D V Analog supply voltage V – 0.3 V + 0.3 V DDA DD DD V USB_DP input voltage –0.3 3.63 V USB_DP V USB_DM input voltage –0.3 3.63 V USB_DM VREGIN USB regulator input –0.3 6.0 V V RTC battery supply voltage –0.3 3.8 V BAT 1. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 5 General 5.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Figure 1. Input signal measurement reference All digital I/O switching characteristics assume: 1. output pins • have C =30pF loads, L • are configured for fast slew rate (PORTx_PCRn[SRE]=0), and • are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins • have their passive filter disabled (PORTx_PCRn[PFE]=0) K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 12 Freescale Semiconductor, Inc.

General 5.2 Nonswitching electrical specifications 5.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit Notes V Supply voltage 1.71 3.6 V DD V Analog supply voltage 1.71 3.6 V DDA V – V V -to-V differential voltage –0.1 0.1 V DD DDA DD DDA V – V V -to-V differential voltage –0.1 0.1 V SS SSA SS SSA V RTC battery supply voltage 1.71 3.6 V BAT V Input high voltage IH • 2.7 V ≤ V ≤ 3.6 V 0.7 × V — V DD DD • 1.7 V ≤ V ≤ 2.7 V 0.75 × V — V DD DD V Input low voltage IL • 2.7 V ≤ V ≤ 3.6 V — 0.35 × V V DD DD • 1.7 V ≤ V ≤ 2.7 V — 0.3 × V V DD DD V Input hysteresis 0.06 × V — V HYS DD I Digital pin negative DC injection current — single pin 1 ICDIO -5 — mA • V < V -0.3V IN SS I Analog2, EXTAL, and XTAL pin DC injection current — 3 ICAIO single pin mA • V < V -0.3V (Negative current injection) -5 — IN SS • V > V +0.3V (Positive current injection) — +5 IN DD I Contiguous pin DC injection current —regional limit, ICcont includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins -25 — mA • Negative current injection — +25 • Positive current injection V Open drain pullup voltage level V V V 4 ODPU DD DD V V voltage required to retain RAM 1.2 — V RAM DD V V voltage required to retain the VBAT register file V — V RFVBAT BAT POR_VBAT 1. All 5 V tolerant digital I/O pins are internally clamped to V through an ESD protection diode. There is no diode SS connection to V . If V is less than V , a current limiting resistor is required. The negative DC injection current DD IN DIO_MIN limiting resistor is calculated as R=(V -V )/|I |. DIO_MIN IN ICDIO 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and XTAL are analog pins. 3. All analog pins are internally clamped to V and V through ESD protection diodes. If V is less than V or greater SS DD IN AIO_MIN than V , a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as AIO_MAX R=(V -V )/|I |. The positive injection current limiting resistor is calculated as R=(V -V )/|I |. Select the AIO_MIN IN ICAIO IN AIO_MAX ICAIO larger of these two calculated resistances if the pin is exposed to positive and negative injection currents. 4. Open drain outputs must be pulled to VDD. K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 13

General 5.2.2 LVD and POR operating requirements Table 2. V supply LVD and POR operating requirements DD Symbol Description Min. Typ. Max. Unit Notes V Falling VDD POR detect voltage 0.8 1.1 1.5 V POR V Falling low-voltage detect threshold — high 2.48 2.56 2.64 V LVDH range (LVDV=01) Low-voltage warning thresholds — high range 1 V • Level 1 falling (LVWV=00) 2.62 2.70 2.78 V LVW1H V • Level 2 falling (LVWV=01) 2.72 2.80 2.88 V LVW2H V • Level 3 falling (LVWV=10) 2.82 2.90 2.98 V LVW3H V • Level 4 falling (LVWV=11) 2.92 3.00 3.08 V LVW4H V Low-voltage inhibit reset/recover hysteresis — — ±80 — mV HYSH high range V Falling low-voltage detect threshold — low range 1.54 1.60 1.66 V LVDL (LVDV=00) Low-voltage warning thresholds — low range 1 V • Level 1 falling (LVWV=00) 1.74 1.80 1.86 V LVW1L V • Level 2 falling (LVWV=01) 1.84 1.90 1.96 V LVW2L V • Level 3 falling (LVWV=10) 1.94 2.00 2.06 V LVW3L V • Level 4 falling (LVWV=11) 2.04 2.10 2.16 V LVW4L V Low-voltage inhibit reset/recover hysteresis — — ±60 — mV HYSL low range V Bandgap voltage reference 0.97 1.00 1.03 V BG t Internal low power oscillator period — factory 900 1000 1100 μs LPO trimmed 1. Rising thresholds are falling threshold + hysteresis voltage Table 3. VBAT power operating requirements Symbol Description Min. Typ. Max. Unit Notes V Falling VBAT supply POR detect voltage 0.8 1.1 1.5 V POR_VBAT K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 14 Freescale Semiconductor, Inc.

General 5.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol Description Min. Typ.1 Max. Unit Notes V Output high voltage — high drive strength OH • 2.7 V ≤ V ≤ 3.6 V, I = -9mA V – 0.5 — — V DD OH DD • 1.71 V ≤ V ≤ 2.7 V, I = -3mA V – 0.5 — — V DD OH DD Output high voltage — low drive strength • 2.7 V ≤ V ≤ 3.6 V, I = -2mA V – 0.5 — — V DD OH DD • 1.71 V ≤ V ≤ 2.7 V, I = -0.6mA V – 0.5 — — V DD OH DD I Output high current total for all ports — — 100 mA OHT V Output low voltage — high drive strength 2 OL • 2.7 V ≤ V ≤ 3.6 V, I = 10mA — — 0.5 V DD OL • 1.71 V ≤ V ≤ 2.7 V, I = 5mA — — 0.5 V DD OL Output low voltage — low drive strength • 2.7 V ≤ V ≤ 3.6 V, I = 2mA — — 0.5 V DD OL • 1.71 V ≤ V ≤ 2.7 V, I = 1mA — — 0.5 V DD OL I Output low current total for all ports — — 100 mA OLT I Input leakage current, analog pins and digital 3, 4 INA pins configured as analog inputs • V ≤ V ≤ V SS IN DD • All pins except EXTAL32, XTAL32, — 0.002 0.5 μA EXTAL, XTAL — 0.004 1.5 μA • EXTAL (PTA18) and XTAL (PTA19) — 0.075 10 μA • EXTAL32, XTAL32 I Input leakage current, digital pins 4, 5 IND • V ≤ V ≤ V SS IN IL • All digital pins — 0.002 0.5 μA • V = V IN DD — 0.002 0.5 μA • All digital pins except PTD7 — 0.004 1 μA • PTD7 I Input leakage current, digital pins 4, 5, 6 IND • V < V < V IL IN DD • V = 3.6 V — 18 26 μA DD • V = 3.0 V — 12 49 μA DD • V = 2.5 V — 8 13 μA DD • V = 1.7 V — 3 6 μA DD Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 15

General Table 4. Voltage and current operating behaviors (continued) Symbol Description Min. Typ.1 Max. Unit Notes I Input leakage current, digital pins 4, 5 IND • V < V < 5.5 V — 1 50 μA DD IN Z Input impedance examples, digital pins 4, 7 IND • V = 3.6 V — — 48 kΩ DD • V = 3.0 V — — 55 kΩ DD • V = 2.5 V — — 57 kΩ DD • V = 1.7 V — — 85 kΩ DD R Internal pullup resistors 20 35 50 kΩ 8 PU R Internal pulldown resistors 20 35 50 kΩ 9 PD 1. Typical values characterized at 25°C and VDD = 3.6 V unless otherwise noted. 2. Open drain outputs must be pulled to V . DD 3. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 4. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL. 5. Internal pull-up/pull-down resistors disabled. 6. Characterized, not tested in production. 7. Examples calculated using V relation, V , and max I : Z =V /I . This is the impedance needed to pull a high IL DD IND IND IL IND signal to a level below V due to leakage when V < V < V . These examples assume signal source low = 0 V. IL IL IN DD 8. Measured at V supply voltage = V min and Vinput = V DD DD SS 9. Measured at V supply voltage = V min and Vinput = V DD DD DD I IND Digital input Z IND + – Source 5.2.4 Power mode transition operating behaviors All specifications except t , and VLLSx→RUN recovery times in the following table POR assume this clock configuration: • CPU and system clocks = 100 MHz • Bus clock = 50 MHz • FlexBus clock = 50 MHz • Flash clock = 25 MHz • MCG mode: FEI K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 16 Freescale Semiconductor, Inc.

General Table 5. Power mode transition operating behaviors Symbol Description Min. Max. Unit Notes t After a POR event, amount of time from the point V 1 POR DD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. μs — 300 • V slew rate ≥ 5.7 kV/s DD — 1.7 V / (V • V slew rate < 5.7 kV/s DD DD slew rate) — 130 μs • VLLS1 → RUN — 92 μs • VLLS2 → RUN — 92 μs • VLLS3 → RUN — 5.9 μs • LLS → RUN — 5.0 μs • VLPS → RUN — 5.0 μs • STOP → RUN 1. Normal boot (FTFL_OPT[LPBOOT]=1) 5.2.5 Power consumption operating behaviors Table 6. Power consumption operating behaviors Symbol Description Min. Typ. Max. Unit Notes I Analog supply current — — See note mA 1 DDA I Run mode current — all peripheral clocks 2 DD_RUN disabled, code executing from flash — 37 63 mA • @ 1.8V — 38 64 mA • @ 3.0V I Run mode current — all peripheral clocks 3, 4 DD_RUN enabled, code executing from flash — 46 77 mA • @ 1.8V • @ 3.0V — 47 63 mA • @ 25°C — 58 79 mA • @ 125°C I Wait mode high frequency current at 3.0 V — all — 20 — mA 2 DD_WAIT peripheral clocks disabled I Wait mode reduced frequency current at 3.0 V — — 9 — mA 5 DD_WAIT all peripheral clocks disabled I Very-low-power run mode current at 3.0 V — all — 1.12 — mA 6 DD_VLPR peripheral clocks disabled Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 17

General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes I Very-low-power run mode current at 3.0 V — all — 1.71 — mA 7 DD_VLPR peripheral clocks enabled I Very-low-power wait mode current at 3.0 V — all — 0.77 — mA 8 DD_VLPW peripheral clocks disabled I Stop mode current at 3.0 V DD_STOP • @ –40 to 25°C — 0.74 1.41 mA • @ 70°C — 2.45 11.5 mA • @ 105°C — 6.61 30 mA I Very-low-power stop mode current at 3.0 V DD_VLPS • @ –40 to 25°C — 83 435 μA • @ 70°C — 425 2000 μA • @ 105°C — 1280 4000 μA I Low leakage stop mode current at 3.0 V 9 DD_LLS • @ –40 to 25°C — 4.58 19.9 μA • @ 70°C — 30.6 105 μA • @ 105°C — 137 500 μA I Very low-leakage stop mode 3 current at 3.0 V 9 DD_VLLS3 • @ –40 to 25°C — 3.0 23 μA • @ 70°C — 18.6 43 μA • @ 105°C — 84.9 230 μA I Very low-leakage stop mode 2 current at 3.0 V DD_VLLS2 • @ –40 to 25°C — 2.2 5.4 μA • @ 70°C — 9.3 35 μA • @ 105°C — 41.4 128 μA I Very low-leakage stop mode 1 current at 3.0 V DD_VLLS1 • @ –40 to 25°C — 2.1 9 μA • @ 70°C — 7.6 28 μA • @ 105°C — 33.5 95.5 μA I Average current with RTC and 32kHz disabled at DD_VBAT 3.0 V • @ –40 to 25°C — 0.19 0.22 μA • @ 70°C — 0.49 0.64 μA • @ 105°C — 2.2 3.2 μA Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 18 Freescale Semiconductor, Inc.

General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes I Average current when CPU is not accessing RTC 10 DD_VBAT registers • @ 1.8V • @ –40 to 25°C — 0.57 0.67 μA • @ 70°C — 0.90 1.2 μA • @ 105°C — 2.4 3.5 μA • @ 3.0V • @ –40 to 25°C — 0.67 0.94 μA • @ 70°C — 1.0 1.4 μA • @ 105°C — 2.7 3.9 μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral clocks disabled. 3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled. 4. Max values are measured with CPU executing DSP instructions. 5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode. 6. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 7. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 9. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA. 10. Includes 32kHz oscillator current and RTC operation. 5.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: • MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater than 50 MHz frequencies. • USB regulator disabled • No GPIOs toggled • Code execution from flash with cache enabled • For the ALLOFF curve, all peripheral clocks are disabled except FTFL K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 19

General Figure 2. Run mode supply current vs. core frequency 5.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors for 144LQFP and 144MAPBGA Symbol Description Frequency 144LQFP 144MAPBGA Unit Notes band (MHz) V Radiated emissions voltage, band 1 0.15–50 23 12 dBμV 1, 2 RE1 V Radiated emissions voltage, band 2 50–150 27 24 dBμV RE2 V Radiated emissions voltage, band 3 150–500 28 27 dBμV RE3 V Radiated emissions voltage, band 4 500–1000 14 11 dBμV RE4 V IEC level 0.15–1000 K K — 2, 3 RE_IEC 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 20 Freescale Semiconductor, Inc.

General 2. V = 3.3 V, T = 25 °C, f = 12 MHz (crystal), f = 96 MHz, f = 48 MHz DD A OSC SYS BUS 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 5.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for “EMC design.” 5.2.8 Capacitance attributes Table 8. Capacitance attributes Symbol Description Min. Max. Unit C Input capacitance: analog pins — 7 pF IN_A C Input capacitance: digital pins — 7 pF IN_D 5.3 Switching specifications 5.3.1 Device clock specifications Table 9. Device clock specifications Symbol Description Min. Max. Unit Notes Normal run mode f System and core clock — 100 MHz SYS f System and core clock when Full Speed USB in 20 — MHz SYS_USB operation f System and core clock when ethernet in operation MHz ENET • 10 Mbps 5 — • 100 Mbps 50 — f Bus clock — 50 MHz BUS FB_CLK FlexBus clock — 50 MHz f Flash clock — 25 MHz FLASH f LPTMR clock — 25 MHz LPTMR VLPR mode1 f System and core clock — 4 MHz SYS Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 21

General Table 9. Device clock specifications (continued) Symbol Description Min. Max. Unit Notes f Bus clock — 4 MHz BUS FB_CLK FlexBus clock — 4 MHz f Flash clock — 1 MHz FLASH f External reference clock — 16 MHz ERCLK f LPTMR clock — 25 MHz LPTMR_pin f LPTMR external reference clock — 16 MHz LPTMR_ERCLK f FlexCAN external reference clock — 8 MHz FlexCAN_ERCLK f I2S master clock — 12.5 MHz I2S_MCLK f I2S bit clock — 4 MHz I2S_BCLK 1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. 5.3.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, UART, CAN, CMT, IEEE 1588 timer, and I2C signals. Table 10. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter 1.5 — Bus clock 1, 2 disabled) — Synchronous path cycles GPIO pin interrupt pulse width (digital glitch filter 100 — ns 3 disabled, analog filter enabled) — Asynchronous path GPIO pin interrupt pulse width (digital glitch filter 16 — ns 3 disabled, analog filter disabled) — Asynchronous path External reset pulse width (digital glitch filter disabled) 100 — ns 3 Mode select (EZP_CS) hold time after reset 2 — Bus clock deassertion cycles Port rise and fall time (high drive strength) 4 • Slew disabled • 1.71 ≤ V ≤ 2.7V — 12 ns DD • 2.7 ≤ V ≤ 3.6V — 6 ns DD • Slew enabled • 1.71 ≤ V ≤ 2.7V — 36 ns DD • 2.7 ≤ V ≤ 3.6V — 24 ns DD Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 22 Freescale Semiconductor, Inc.

General Table 10. General switching specifications (continued) Symbol Description Min. Max. Unit Notes Port rise and fall time (low drive strength) 5 • Slew disabled • 1.71 ≤ V ≤ 2.7V — 12 ns DD • 2.7 ≤ V ≤ 3.6V — 6 ns DD • Slew enabled • 1.71 ≤ V ≤ 2.7V — 36 ns DD • 2.7 ≤ V ≤ 3.6V — 24 ns DD 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75 pF load 5. 15 pF load 5.4 Thermal specifications 5.4.1 Thermal operating requirements Table 11. Thermal operating requirements Symbol Description Min. Max. Unit T Die junction temperature –40 125 °C J T Ambient temperature –40 105 °C A 5.4.2 Thermal attributes Board type Symbol Description 144 LQFP 144 Unit Notes MAPBGA Single-layer R Thermal 45 48 °C/W 1 θJA (1s) resistance, junction to ambient (natural convection) Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 23

Peripheral operating requirements and behaviors Board type Symbol Description 144 LQFP 144 Unit Notes MAPBGA Four-layer R Thermal 36 29 °C/W 1 θJA (2s2p) resistance, junction to ambient (natural convection) Single-layer R Thermal 36 38 °C/W 1 θJMA (1s) resistance, junction to ambient (200 ft./ min. air speed) Four-layer R Thermal 30 25 °C/W 1 θJMA (2s2p) resistance, junction to ambient (200 ft./ min. air speed) — R Thermal 24 16 °C/W 2 θJB resistance, junction to board — R Thermal 9 9 °C/W 3 θJC resistance, junction to case — Ψ Thermal 2 2 °C/W 4 JT characterization parameter, junction to package top outside center (natural convection) 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). 6 Peripheral operating requirements and behaviors 6.1 Core modules K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 24 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 6.1.1 Debug trace timing specifications Table 12. Debug trace operating behaviors Symbol Description Min. Max. Unit T Clock period Frequency dependent MHz cyc T Low pulse width 2 — ns wl T High pulse width 2 — ns wh T Clock and data rise time — 3 ns r T Clock and data fall time — 3 ns f T Data setup 3 — ns s T Data hold 2 — ns h Figure 3. TRACE_CLKOUT specifications TRACE_CLKOUT Ts Th Ts Th TRACE_D[3:0] Figure 4. Trace data specifications 6.1.2 JTAG electricals Table 13. JTAG limited voltage range electricals Symbol Description Min. Max. Unit Operating voltage 2.7 3.6 V J1 TCLK frequency of operation MHz • Boundary Scan 0 10 • JTAG and CJTAG 0 25 • Serial Wire Debug 0 50 J2 TCLK cycle period 1/J1 — ns Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 25

Peripheral operating requirements and behaviors Table 13. JTAG limited voltage range electricals (continued) Symbol Description Min. Max. Unit J3 TCLK clock pulse width • Boundary Scan 50 — ns • JTAG and CJTAG 20 — ns • Serial Wire Debug 10 — ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 17 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns Table 14. JTAG full voltage range electricals Symbol Description Min. Max. Unit Operating voltage 1.71 3.6 V J1 TCLK frequency of operation MHz • Boundary Scan 0 10 • JTAG and CJTAG 0 20 • Serial Wire Debug 0 40 J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width • Boundary Scan 50 — ns • JTAG and CJTAG 25 — ns • Serial Wire Debug 12.5 — ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns J11 TCLK low to TDO data valid — 22.1 ns J12 TCLK low to TDO high-Z — 22.1 ns Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 26 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 14. JTAG full voltage range electricals (continued) Symbol Description Min. Max. Unit J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns J2 J3 J3 TCLK (input) J4 J4 Figure 5. Test clock input timing TCLK J5 J6 Data inputs Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 6. Boundary scan (JTAG) timing K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 27

Peripheral operating requirements and behaviors TCLK J9 J10 TDI/TMS Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 7. Test Access Port timing TCLK J14 J13 TRST Figure 8. TRST timing 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 28 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 6.3.1 MCG specifications Table 15. MCG specifications Symbol Description Min. Typ. Max. Unit Notes f Internal reference frequency (slow clock) — — 32.768 — kHz ints_ft factory trimmed at nominal VDD and 25 °C f Internal reference frequency (slow clock) — user 31.25 — 39.0625 kHz ints_t trimmed Δ Resolution of trimmed average DCO output — ± 0.3 ± 0.6 %f 1 fdco_res_t dco frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM Δf Resolution of trimmed average DCO output — ± 0.2 ± 0.5 %f 1 dco_res_t dco frequency at fixed voltage and temperature — using SCTRIM only Δf Total deviation of trimmed average DCO output — +0.5/-0.7 ± 3 %f 1, dco_t dco frequency over voltage and temperature Δf Total deviation of trimmed average DCO output — ± 0.3 ± 3 %f 1 dco_t dco frequency over fixed voltage and temperature range of 0–70°C f Internal reference frequency (fast clock) — — 4 — MHz intf_ft factory trimmed at nominal VDD and 25°C f Internal reference frequency (fast clock) — user 3 — 5 MHz intf_t trimmed at nominal VDD and 25 °C f Loss of external clock minimum frequency — (3/5) x — — kHz loc_low RANGE = 00 f ints_t f Loss of external clock minimum frequency — (16/5) x — — kHz loc_high RANGE = 01, 10, or 11 f ints_t FLL f FLL reference frequency range 31.25 — 39.0625 kHz fll_ref f DCO output Low range (DRS=00) 20 20.97 25 MHz 2, 3 dco frequency range 640 × f fll_ref Mid range (DRS=01) 40 41.94 50 MHz 1280 × f fll_ref Mid-high range (DRS=10) 60 62.91 75 MHz 1920 × f fll_ref High range (DRS=11) 80 83.89 100 MHz 2560 × f fll_ref f DCO output Low range (DRS=00) — 23.99 — MHz 4, 5 dco_t_DMX32 frequency 732 × f fll_ref Mid range (DRS=01) — 47.97 — MHz 1464 × f fll_ref Mid-high range (DRS=10) — 71.99 — MHz 2197 × f fll_ref High range (DRS=11) — 95.98 — MHz 2929 × f fll_ref Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 29

Peripheral operating requirements and behaviors Table 15. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes J FLL period jitter ps cyc_fll — 180 — • f = 48 MHz DCO — 150 — • f = 98 MHz DCO t FLL target frequency acquisition time — — 1 ms 6 fll_acquire PLL f VCO operating frequency 48.0 — 100 MHz vco I PLL operating current 7 pll — 1060 — µA • PLL @ 96 MHz (f = 8 MHz, f = osc_hi_1 pll_ref 2 MHz, VDIV multiplier = 48) I PLL operating current 7 pll — 600 — µA • PLL @ 48 MHz (f = 8 MHz, f = osc_hi_1 pll_ref 2 MHz, VDIV multiplier = 24) f PLL reference frequency range 2.0 — 4.0 MHz pll_ref J PLL period jitter (RMS) 8 cyc_pll • f = 48 MHz — 120 — ps vco • f = 100 MHz — 50 — ps vco J PLL accumulated jitter over 1µs (RMS) 8 acc_pll • f = 48 MHz — 1350 — ps vco • f = 100 MHz — 600 — ps vco D Lock entry frequency tolerance ± 1.49 — ± 2.98 % lock D Lock exit frequency tolerance ± 4.47 — ± 5.97 % unl t Lock detector detection time — — 150 × 10-6 s 9 pll_lock + 1075(1/ f ) pll_ref 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δf ) over voltage and temperature should be considered. dco_t 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. Excludes any oscillator currents that are also consuming power while PLL is in operation. 8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 6.3.2 Oscillator electrical specifications This section provides the electrical characteristics of the module. K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 30 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 6.3.2.1 Oscillator DC electrical specifications Table 16. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit Notes V Supply voltage 1.71 — 3.6 V DD I Supply current — low-power mode (HGO=0) 1 DDOSC • 32 kHz — 500 — nA • 4 MHz — 200 — μA • 8 MHz (RANGE=01) — 300 — μA • 16 MHz — 950 — μA • 24 MHz — 1.2 — mA • 32 MHz — 1.5 — mA I Supply current — high gain mode (HGO=1) 1 DDOSC • 32 kHz — 25 — μA • 4 MHz — 400 — μA • 8 MHz (RANGE=01) — 500 — μA • 16 MHz — 2.5 — mA • 24 MHz — 3 — mA • 32 MHz — 4 — mA C EXTAL load capacitance — — — 2, 3 x C XTAL load capacitance — — — 2, 3 y R Feedback resistor — low-frequency, low-power — — — MΩ 2, 4 F mode (HGO=0) Feedback resistor — low-frequency, high-gain — 10 — MΩ mode (HGO=1) Feedback resistor — high-frequency, low-power — — — MΩ mode (HGO=0) Feedback resistor — high-frequency, high-gain — 1 — MΩ mode (HGO=1) R Series resistor — low-frequency, low-power — — — kΩ S mode (HGO=0) Series resistor — low-frequency, high-gain mode — 200 — kΩ (HGO=1) Series resistor — high-frequency, low-power — — — kΩ mode (HGO=0) Series resistor — high-frequency, high-gain mode (HGO=1) — 0 — kΩ Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 31

Peripheral operating requirements and behaviors Table 16. Oscillator DC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit Notes V 5 Peak-to-peak amplitude of oscillation (oscillator — 0.6 — V pp mode) — low-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator — V — V DD mode) — low-frequency, high-gain mode (HGO=1) Peak-to-peak amplitude of oscillation (oscillator — 0.6 — V mode) — high-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator — V — V DD mode) — high-frequency, high-gain mode (HGO=1) 1. V =3.3 V, Temperature =25 °C DD 2. See crystal or resonator manufacturer's recommendation 3. C ,C can be provided by using either the integrated capacitors or by using external components. x y 4. When low power mode is selected, R is integrated and must not be attached externally. F 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 Oscillator frequency specifications Table 17. Oscillator frequency specifications Symbol Description Min. Typ. Max. Unit Notes f Oscillator crystal or resonator frequency — low 32 — 40 kHz osc_lo frequency mode (MCG_C2[RANGE]=00) f Oscillator crystal or resonator frequency — high 3 — 8 MHz osc_hi_1 frequency mode (low range) (MCG_C2[RANGE]=01) f Oscillator crystal or resonator frequency — high 8 — 32 MHz osc_hi_2 frequency mode (high range) (MCG_C2[RANGE]=1x) f Input clock frequency (external clock mode) — — 50 MHz 1, 2 ec_extal t Input clock duty cycle (external clock mode) 40 50 60 % dc_extal t Crystal startup time — 32 kHz low-frequency, — 750 — ms 3, 4 cst low-power mode (HGO=0) Crystal startup time — 32 kHz low-frequency, — 250 — ms high-gain mode (HGO=1) Crystal startup time — 8 MHz high-frequency — 0.6 — ms (MCG_C2[RANGE]=01), low-power mode (HGO=0) Crystal startup time — 8 MHz high-frequency — 1 — ms (MCG_C2[RANGE]=01), high-gain mode (HGO=1) 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 32 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. NOTE The 32 kHz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 6.3.3 32 kHz oscillator electrical characteristics This section describes the module electrical characteristics. 6.3.3.1 32 kHz oscillator DC electrical specifications Table 18. 32kHz oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit V Supply voltage 1.71 — 3.6 V BAT R Internal feedback resistor — 100 — MΩ F C Parasitical capacitance of EXTAL32 and XTAL32 — 5 7 pF para V 1 Peak-to-peak amplitude of oscillation — 0.6 — V pp 1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.3.2 32 kHz oscillator frequency specifications Table 19. 32 kHz oscillator frequency specifications Symbol Description Min. Typ. Max. Unit Notes f Oscillator crystal — 32.768 — kHz osc_lo t Crystal start-up time — 1000 — ms 1 start f Externally provided input clock frequency — 32.768 — kHz 2 ec_extal32 v Externally provided input clock amplitude 700 — V mV 2, 3 ec_extal32 BAT 1. Proper PC board layout procedures must be followed to achieve specifications. 2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The oscillator remains enabled and XTAL32 must be left unconnected. 3. The parameter specified is a peak-to-peak value and V and V specifications do not apply. The voltage of the applied IH IL clock must be within the range of V to V . SS BAT 6.4 Memories and memory interfaces K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 33

Peripheral operating requirements and behaviors 6.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 6.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 20. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit Notes t Longword Program high-voltage time — 7.5 18 μs hvpgm4 t Sector Erase high-voltage time — 13 113 ms 1 hversscr t Erase Block high-voltage time for 256 KB — 104 904 ms 1 hversblk256k 1. Maximum time based on expectations at cycling end-of-life. 6.4.1.2 Flash timing specifications — commands Table 21. Flash command timing specifications Symbol Description Min. Typ. Max. Unit Notes Read 1s Block execution time t • 256 KB program/data flash — — 1.7 ms rd1blk256k t Read 1s Section execution time (flash sector) — — 60 μs 1 rd1sec2k t Program Check execution time — — 45 μs 1 pgmchk t Read Resource execution time — — 30 μs 1 rdrsrc t Program Longword execution time — 65 145 μs pgm4 Erase Flash Block execution time 2 t • 256 KB program/data flash — 122 985 ms ersblk256k t Erase Flash Sector execution time — 14 114 ms 2 ersscr Program Section execution time t • 512 bytes flash — 2.4 — ms pgmsec512 t • 1 KB flash — 4.7 — ms pgmsec1k t • 2 KB flash — 9.3 — ms pgmsec2k t Read 1s All Blocks execution time — — 1.8 ms rd1all t Read Once execution time — — 25 μs 1 rdonce t Program Once execution time — 65 — μs pgmonce t Erase All Blocks execution time — 250 2000 ms 2 ersall t Verify Backdoor Access Key execution time — — 30 μs 1 vfykey Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 34 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 21. Flash command timing specifications (continued) Symbol Description Min. Typ. Max. Unit Notes Swap Control execution time t • control code 0x01 — 200 — μs swapx01 t • control code 0x02 — 70 150 μs swapx02 t • control code 0x04 — 70 150 μs swapx04 t • control code 0x08 — — 30 μs swapx08 Program Partition for EEPROM execution time t • 64 KB FlexNVM — 138 — ms pgmpart64k t • 256 KB FlexNVM — 145 — ms pgmpart256k Set FlexRAM Function execution time: t • Control Code 0xFF — 70 — μs setramff t • 32 KB EEPROM backup — 0.8 1.2 ms setram32k t • 64 KB EEPROM backup — 1.3 1.9 ms setram64k t • 256 KB EEPROM backup — 4.5 5.5 ms setram256k Byte-write to FlexRAM for EEPROM operation t Byte-write to erased FlexRAM location execution — 175 260 μs 3 eewr8bers time Byte-write to FlexRAM execution time: t • 32 KB EEPROM backup — 385 1800 μs eewr8b32k t • 64 KB EEPROM backup — 475 2000 μs eewr8b64k t • 128 KB EEPROM backup — 650 2400 μs eewr8b128k t • 256 KB EEPROM backup — 1000 3200 μs eewr8b256k Word-write to FlexRAM for EEPROM operation t Word-write to erased FlexRAM location — 175 260 μs eewr16bers execution time Word-write to FlexRAM execution time: t • 32 KB EEPROM backup — 385 1800 μs eewr16b32k t • 64 KB EEPROM backup — 475 2000 μs eewr16b64k t • 128 KB EEPROM backup — 650 2400 μs eewr16b128k t • 256 KB EEPROM backup — 1000 3200 μs eewr16b256k Longword-write to FlexRAM for EEPROM operation t Longword-write to erased FlexRAM location — 360 540 μs eewr32bers execution time Longword-write to FlexRAM execution time: t • 32 KB EEPROM backup — 630 2050 μs eewr32b32k t • 64 KB EEPROM backup — 810 2250 μs eewr32b64k t • 128 KB EEPROM backup — 1200 2675 μs eewr32b128k t • 256 KB EEPROM backup — 1900 3500 μs eewr32b256k K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 35

Peripheral operating requirements and behaviors 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased. 6.4.1.3 Flash high voltage current behaviors Table 22. Flash high voltage current behaviors Symbol Description Min. Typ. Max. Unit I Average current adder during high voltage — 2.5 6.0 mA DD_PGM flash programming operation I Average current adder during high voltage — 1.5 4.0 mA DD_ERS flash erase operation 6.4.1.4 Reliability specifications Table 23. NVM reliability specifications Symbol Description Min. Typ.1 Max. Unit Notes Program Flash t Data retention after up to 10 K cycles 5 50 — years nvmretp10k t Data retention after up to 1 K cycles 20 100 — years nvmretp1k n Cycling endurance 10 K 50 K — cycles 2 nvmcycp Data Flash t Data retention after up to 10 K cycles 5 50 — years nvmretd10k t Data retention after up to 1 K cycles 20 100 — years nvmretd1k n Cycling endurance 10 K 50 K — cycles 2 nvmcycd FlexRAM as EEPROM t Data retention up to 100% of write endurance 5 50 — years nvmretee100 t Data retention up to 10% of write endurance 20 100 — years nvmretee10 Write endurance 3 n • EEPROM backup to FlexRAM ratio = 16 35 K 175 K — writes nvmwree16 n • EEPROM backup to FlexRAM ratio = 128 315 K 1.6 M — writes nvmwree128 n • EEPROM backup to FlexRAM ratio = 512 1.27 M 6.4 M — writes nvmwree512 n • EEPROM backup to FlexRAM ratio = 4096 10 M 50 M — writes nvmwree4k n • EEPROM backup to FlexRAM ratio = 80 M 400 M — writes nvmwree32k 32,768 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40°C ≤ T ≤ 125°C. j 3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and typical values assume all byte-writes to FlexRAM. K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 36 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 6.4.1.5 Write endurance to FlexRAM for EEPROM When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the flash memory module to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. EEPROM – 2 × EEESPLIT × EEESIZE Writes_subsystem = × Write_efficiency × n nvmcycd EEESPLIT × EEESIZE where • Writes_subsystem — minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance) • EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with the Program Partition command • EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command • EEESIZE — allocated FlexRAM based on DEPART; entered with the Program Partition command • Write_efficiency — • 0.25 for 8-bit writes to FlexRAM • 0.50 for 16-bit or 32-bit writes to FlexRAM • n — data flash cycling endurance (the following graph assumes 10,000 nvmcycd cycles) K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 37

Peripheral operating requirements and behaviors Figure 9. EEPROM backup writes to FlexRAM 6.4.2 EzPort switching specifications Table 24. EzPort switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V EP1 EZP_CK frequency of operation (all commands except — f /2 MHz SYS READ) EP1a EZP_CK frequency of operation (READ command) — f /8 MHz SYS EP2 EZP_CS negation to next EZP_CS assertion 2 x t — ns EZP_CK EP3 EZP_CS input valid to EZP_CK high (setup) 5 — ns EP4 EZP_CK high to EZP_CS input invalid (hold) 5 — ns EP5 EZP_D input valid to EZP_CK high (setup) 2 — ns EP6 EZP_CK high to EZP_D input invalid (hold) 5 — ns EP7 EZP_CK low to EZP_Q output valid — 16 ns EP8 EZP_CK low to EZP_Q output invalid (hold) 0 — ns EP9 EZP_CS negation to EZP_Q tri-state — 12 ns K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 38 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors EZP_CK EP4 EP2 EP3 EZP_CS EP9 EP7 EP8 EZP_Q (output) EP5 EP6 EZP_D (input) Figure 10. EzPort Timing Diagram 6.4.3 Flexbus switching specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency. The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be derived from these values. Table 25. Flexbus limited voltage range switching specifications Num Description Min. Max. Unit Notes Operating voltage 2.7 3.6 V Frequency of operation — FB_CLK MHz FB1 Clock period 20 — ns FB2 Address, data, and control output valid — 11.5 ns 1 FB3 Address, data, and control output hold 0.5 — ns 1 FB4 Data and FB_TA input setup 8.5 — ns 2 FB5 Data and FB_TA input hold 0.5 — ns 2 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 39

Peripheral operating requirements and behaviors 2. Specification is valid for all FB_AD[31:0] and FB_TA. Table 26. Flexbus full voltage range switching specifications Num Description Min. Max. Unit Notes Operating voltage 1.71 3.6 V Frequency of operation — FB_CLK MHz FB1 Clock period 1/FB_CLK — ns FB2 Address, data, and control output valid — 13.5 ns 1 FB3 Address, data, and control output hold 0 — ns 1 FB4 Data and FB_TA input setup 13.7 — ns 2 FB5 Data and FB_TA input hold 0.5 — ns 2 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 40 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors FB1 FB_CLK FB3 FB5 FB_A[Y] Address FB2 FB4 FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 11. FlexBus read timing diagram K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 41

Peripheral operating requirements and behaviors FB1 FB_CLK FB2 FB3 FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 12. FlexBus write timing diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 42 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 27 and Table 28 are achievable on the differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and ADCx_DM3. The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are not direct device pins. Accuracy specifications for these pins are defined in Table 29 and Table 30. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit ADC operating conditions Table 27. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes V Supply voltage Absolute 1.71 — 3.6 V DDA ΔV Supply voltage Delta to V (V – V ) -100 0 +100 mV 2 DDA DD DD DDA ΔV Ground voltage Delta to V (V – V ) -100 0 +100 mV 2 SSA SS SS SSA V ADC reference 1.13 V V V REFH DDA DDA voltage high V ADC reference V V V V REFL SSA SSA SSA voltage low V Input voltage • 16-bit differential mode VREFL — 31/32 * V ADIN VREFH • All other modes VREFL — VREFH C Input capacitance • 16-bit mode — 8 10 pF ADIN • 8-bit / 10-bit / 12-bit — 4 5 modes R Input resistance — 2 5 kΩ ADIN R Analog source 13-bit / 12-bit modes 3 AS resistance f < 4 MHz — — 5 kΩ ADCK f ADC conversion ≤ 13-bit mode 1.0 — 18.0 MHz 4 ADCK clock frequency f ADC conversion 16-bit mode 2.0 — 12.0 MHz 4 ADCK clock frequency C ADC conversion ≤ 13-bit modes 5 rate rate No ADC hardware averaging 20.000 — 818.330 Ksps Continuous conversions enabled, subsequent conversion time Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 43

Peripheral operating requirements and behaviors Table 27. 16-bit ADC operating conditions (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes C ADC conversion 16-bit mode 5 rate rate No ADC hardware averaging 37.037 — 461.467 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume V = 3.0 V, Temp = 25 °C, f = 1.0 MHz, unless otherwise stated. Typical values are for DDA ADCK reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The R /C AS AS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED Pad Z CHANNEL SELECT AS leakage due to CIRCUIT ADC SAR R input R ENGINE AS protection ADIN V ADIN C V AS AS R ADIN IINNPPUUTT PPIINN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN Figure 13. ADC input impedance equivalency diagram 6.6.1.2 16-bit ADC electrical characteristics Table 28. 16-bit ADC characteristics (V = V , V = V ) REFH DDA REFL SSA Symbol Description Conditions1. Min. Typ.2 Max. Unit Notes I Supply current 0.215 — 1.7 mA 3 DDA_ADC Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 44 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 28. 16-bit ADC characteristics (V = V , V = V ) (continued) REFH DDA REFL SSA Symbol Description Conditions1. Min. Typ.2 Max. Unit Notes ADC • ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz tADACK = 1/ asynchronous f clock source • ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz ADACK f ADACK • ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz • ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz Sample Time See Reference Manual chapter for sample times TUE Total unadjusted • 12-bit modes — ±4 ±6.8 LSB4 5 error • <12-bit modes — ±1.4 ±2.1 DNL Differential non- • 12-bit modes — ±0.7 -1.1 to +1.9 LSB4 5 linearity -0.3 to 0.5 • <12-bit modes — ±0.2 INL Integral non- • 12-bit modes — ±1.0 -2.7 to +1.9 LSB4 5 linearity -0.7 to +0.5 • <12-bit modes — ±0.5 E Full-scale error • 12-bit modes — -4 -5.4 LSB4 V = FS ADIN V • <12-bit modes — -1.4 -1.8 DDA 5 E Quantization • 16-bit modes — -1 to 0 — LSB4 Q error • ≤13-bit modes — — ±0.5 ENOB Effective number 16-bit differential mode 6 of bits • Avg = 32 12.8 14.5 — bits • Avg = 4 11.9 13.8 — bits 16-bit single-ended mode • Avg = 32 12.2 13.9 — bits • Avg = 4 11.4 13.1 — bits Signal-to-noise See ENOB SINAD 6.02 × ENOB + 1.76 dB plus distortion THD Total harmonic 16-bit differential mode 7 distortion • Avg = 32 — –94 — dB 16-bit single-ended mode — -85 — dB • Avg = 32 SFDR Spurious free 16-bit differential mode 7 dynamic range • Avg = 32 82 95 — dB 16-bit single-ended mode 78 90 — dB • Avg = 32 Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 45

Peripheral operating requirements and behaviors Table 28. 16-bit ADC characteristics (V = V , V = V ) (continued) REFH DDA REFL SSA Symbol Description Conditions1. Min. Typ.2 Max. Unit Notes E Input leakage I × R mV I = IL In AS In error leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor Across the full temperature 1.55 1.62 1.69 mV/°C slope range of the device V Temp sensor 25 °C 706 716 726 mV TEMP25 voltage 1. All accuracy numbers assume the ADC is calibrated with V = V REFH DDA 2. Typical values assume V = 3.0 V, Temp = 25 °C, f = 2.0 MHz unless otherwise stated. Typical values are for DDA ADCK reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (V - V )/2N REFH REFL 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. Figure 14. Typical ENOB vs. ADC_CLK for 16-bit differential mode K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 46 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Figure 15. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 6.6.1.3 16-bit ADC with PGA operating conditions Table 29. 16-bit ADC with PGA operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes V Supply voltage Absolute 1.71 — 3.6 V DDA V PGA ref voltage VREF_OU VREF_OU VREF_OU V 2, 3 REFPGA T T T V Input voltage V — V V ADIN SSA DDA V Input Common V — V V CM SSA DDA Mode range R Differential input Gain = 1, 2, 4, 8 — 128 — kΩ IN+ to IN-4 PGAD impedance Gain = 16, 32 — 64 — Gain = 64 — 32 — R Analog source — 100 — Ω 5 AS resistance T ADC sampling 1.25 — — µs 6 S time Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 47

Peripheral operating requirements and behaviors Table 29. 16-bit ADC with PGA operating conditions (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes C ADC conversion ≤ 13 bit modes 18.484 — 450 Ksps 7 rate rate No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 16 bit modes 37.037 — 250 Ksps 8 No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 1. Typical values assume V = 3.0 V, Temp = 25°C, f = 6 MHz unless otherwise stated. Typical values are for DDA ADCK reference only and are not tested in production. 2. ADC must be configured to use the internal voltage reference (VREF_OUT) 3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other than the output of the VREF module, the VREF module must be disabled. 4. For single ended configurations the input impedance of the driven input is R /2 PGAD 5. The analog source resistance (R ), external to MCU, should be kept as minimum as possible. Increased R causes drop AS AS in PGA gain without affecting other performances. This is not dependent on ADC clock frequency. 6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs time should be allowed for F =4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at in 8 MHz ADC clock. 7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1 8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1 6.6.1.4 16-bit ADC with PGA characteristics with Chop enabled (ADC_PGA[PGACHPb] =0) Table 30. 16-bit ADC with PGA characteristics Symbol Description Conditions Min. Typ.1 Max. Unit Notes I Supply current Low power — 420 644 μA 2 DDA_PGA (ADC_PGA[PGALPb]=0) I Input DC current A 3 DC_PGA Gain =1, V =1.2V, — 1.54 — μA REFPGA V =0.5V CM Gain =64, V =1.2V, — 0.57 — μA REFPGA V =0.1V CM Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 48 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 30. 16-bit ADC with PGA characteristics (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes G Gain4 • PGAG=0 0.95 1 1.05 RAS < 100Ω • PGAG=1 1.9 2 2.1 • PGAG=2 3.8 4 4.2 • PGAG=3 7.6 8 8.4 • PGAG=4 15.2 16 16.6 • PGAG=5 30.0 31.6 33.2 • PGAG=6 58.8 63.3 67.8 BW Input signal • 16-bit modes — — 4 kHz bandwidth • < 16-bit modes — — 40 kHz PSRR Power supply Gain=1 — -84 — dB V = 3V DDA rejection ratio ±100mV, f = 50Hz, VDDA 60Hz CMRR Common mode • Gain=1 — -84 — dB V = CM rejection ratio 500mVpp, • Gain=64 — -85 — dB f = 50Hz, VCM 100Hz V Input offset — 0.2 — mV Output offset = OFS voltage V *(Gain+1) OFS T Gain switching — — 10 µs 5 GSW settling time dG/dT Gain drift over full • Gain=1 — 6 10 ppm/°C temperature range • Gain=64 — 31 42 ppm/°C dG/dV Gain drift over • Gain=1 — 0.07 0.21 %/V V from 1.71 DDA DDA supply voltage • Gain=64 to 3.6V — 0.14 0.31 %/V E Input leakage All modes I × R mV I = leakage IL In AS In error current (refer to the MCU's voltage and current operating ratings) V Maximum V 6 PP,DIFF differential input signal swing where V = V × 0.583 X REFPGA SNR Signal-to-noise • Gain=1 80 90 — dB 16-bit ratio differential • Gain=64 52 66 — dB mode, Average=32 THD Total harmonic • Gain=1 85 100 — dB 16-bit distortion differential • Gain=64 49 95 — dB mode, Average=32, f =100Hz in Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 49

Peripheral operating requirements and behaviors Table 30. 16-bit ADC with PGA characteristics (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes SFDR Spurious free • Gain=1 85 105 — dB 16-bit dynamic range differential • Gain=64 53 88 — dB mode, Average=32, f =100Hz in ENOB Effective number • Gain=1, Average=4 11.6 13.4 — bits 16-bit of bits differential • Gain=1, Average=8 8.0 13.6 — bits mode,f =100Hz in • Gain=64, Average=4 7.2 9.6 — bits • Gain=64, Average=8 6.3 9.6 — bits • Gain=1, Average=32 12.8 14.5 — bits • Gain=2, Average=32 11.0 14.3 — bits • Gain=4, Average=32 7.9 13.8 — bits • Gain=8, Average=32 7.3 13.1 — bits • Gain=16, Average=32 6.8 12.5 — bits • Gain=32, Average=32 6.8 11.5 — bits • Gain=64, Average=32 7.5 10.6 — bits SINAD Signal-to-noise See ENOB 6.02 × ENOB + 1.76 dB plus distortion ratio 1. Typical values assume V =3.0V, Temp=25°C, f =6MHz unless otherwise stated. DDA ADCK 2. This current is a PGA module adder, in addition to ADC conversion currents. 3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong function of input common mode voltage (V ) and the PGA gain. CM 4. Gain = 2PGAG 5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored. 6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the PGA reference voltage and gain setting. 6.6.2 CMP and 6-bit DAC electrical specifications Table 31. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit V Supply voltage 1.71 — 3.6 V DD I Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA DDHS I Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA DDLS V Analog input voltage V – 0.3 — V V AIN SS DD V Analog input offset voltage — — 20 mV AIO Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 50 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 31. Comparator and 6-bit DAC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit V Analog comparator hysteresis1 H • CR0[HYSTCTR] = 00 — 5 — mV • CR0[HYSTCTR] = 01 — 10 — mV • CR0[HYSTCTR] = 10 — 20 — mV • CR0[HYSTCTR] = 11 — 30 — mV V Output high V – 0.5 — — V CMPOh DD V Output low — — 0.5 V CMPOl t Propagation delay, high-speed mode (EN=1, 20 50 200 ns DHS PMODE=1) t Propagation delay, low-speed mode (EN=1, 80 250 600 ns DLS PMODE=0) Analog comparator initialization delay2 — — 40 μs I 6-bit DAC current adder (enabled) — 7 — μA DAC6b INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to V -0.6 V. DD 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = V /64 reference K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 51

Peripheral operating requirements and behaviors 0.08 0.07 0.06 0.05 HYSTCTR Setting V) s ( eri 00 er 0.04 yst 01 H P 1100 M C 0.03 11 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 52 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 0.18 0.16 0.14 0.12 HYSTCTR Setting V) s ( 0.1 eri 00 er yst 01 H P P 00.0088 1100 M C 11 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 17. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) 6.6.3 12-bit DAC electrical characteristics 6.6.3.1 12-bit DAC operating requirements Table 32. 12-bit DAC operating requirements Symbol Desciption Min. Max. Unit Notes V Supply voltage 1.71 3.6 V DDA V Reference voltage 1.13 3.6 V 1 DACR T Temperature Operating temperature °C A range of the device C Output load capacitance — 100 pF 2 L I Output load current — 1 mA L 1. The DAC reference can be selected to be V or the voltage output of the VREF module (VREF_OUT) DDA 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 53

Peripheral operating requirements and behaviors 6.6.3.2 12-bit DAC operating behaviors Table 33. 12-bit DAC operating behaviors Symbol Description Min. Typ. Max. Unit Notes I Supply current — low-power mode — — 330 μA DDA_DACL P I Supply current — high-speed mode — — 1200 μA DDA_DACH P t Full-scale settling time (0x080 to 0xF7F) — — 100 200 μs 1 DACLP low-power mode t Full-scale settling time (0x080 to 0xF7F) — — 15 30 μs 1 DACHP high-power mode t Code-to-code settling time (0xBF8 to 0xC08) — 0.7 1 μs 1 CCDACLP — low-power mode and high-speed mode V DAC output voltage range low — high-speed — — 100 mV dacoutl mode, no load, DAC set to 0x000 V DAC output voltage range high — high- V — V mV dacouth DACR DACR speed mode, no load, DAC set to 0xFFF −100 INL Integral non-linearity error — high speed — — ±8 LSB 2 mode DNL Differential non-linearity error — V > 2 — — ±1 LSB 3 DACR V DNL Differential non-linearity error — V = — — ±1 LSB 4 DACR VREF_OUT V Offset error — ±0.4 ±0.8 %FSR 5 OFFSET E Gain error — ±0.1 ±0.6 %FSR 5 G PSRR Power supply rejection ratio, V > = 2.4 V 60 — 90 dB DDA T Temperature coefficient offset voltage — 3.7 — μV/C 6 CO T Temperature coefficient gain error — 0.000421 — %FSR/C GE Rop Output resistance load = 3 kΩ — — 250 Ω SR Slew rate -80h→ F7Fh→ 80h V/μs • High power (SP ) 1.2 1.7 — HP • Low power (SP ) 0.05 0.12 — LP CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth kHz • High power (SP ) 550 — — HP • Low power (SP ) 40 — — LP 1. Settling within ±1 LSB 2. The INL is measured for 0+100mV to V −100 mV DACR 3. The DNL is measured for 0+100 mV to V −100 mV DACR 4. The DNL is measured for 0+100mV to V −100 mV with V > 2.4V DACR DDA 5. Calculated by a best fit curve from V +100 mV to V −100 mV SS DACR 6. VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC set to 0x800, Temp range from -40C to 105C K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 54 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Figure 18. Typical INL error vs. digital code K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 55

Peripheral operating requirements and behaviors Figure 19. Offset at half scale vs. temperature 6.6.4 Voltage reference electrical specifications Table 34. VREF full-range operating requirements Symbol Description Min. Max. Unit Notes V Supply voltage 1.71 3.6 V DDA T Temperature Operating temperature °C A range of the device C Output load capacitance 100 nF 1, 2 L 1. C must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external L reference. 2. The load capacitance should not exceed +/-25% of the nominal specified C value over the operating temperature range of L the device. K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 56 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 35. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit Notes V Voltage reference output with factory trim at 1.1915 1.195 1.1977 V out nominal V and temperature=25C DDA V Voltage reference output — factory trim 1.1584 — 1.2376 V out V Voltage reference output — user trim 1.193 — 1.197 V out V Voltage reference trim step — 0.5 — mV step V Temperature drift (Vmax -Vmin across the full — — 80 mV tdrift temperature range) I Bandgap only current — — 80 µA 1 bg I Low-power buffer current — — 360 uA 1 lp I High-power buffer current — — 1 mA 1 hp ΔV Load regulation µV 1, 2 LOAD • current = ± 1.0 mA — 200 — T Buffer startup time — — 100 µs stup V Voltage drift (Vmax -Vmin across the full voltage — 2 — mV 1 vdrift range) 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load Table 36. VREF limited-range operating requirements Symbol Description Min. Max. Unit Notes T Temperature 0 50 °C A Table 37. VREF limited-range operating behaviors Symbol Description Min. Max. Unit Notes V Voltage reference output with factory trim 1.173 1.225 V out 6.7 Timers See General switching specifications. 6.8 Communication interfaces K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 57

Peripheral operating requirements and behaviors 6.8.1 Ethernet switching specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 6.8.1.1 MII signal switching specifications The following timing specs meet the requirements for MII style interfaces for a range of transceiver devices. Table 38. MII signal switching specifications Symbol Description Min. Max. Unit — RXCLK frequency — 25 MHz MII1 RXCLK pulse width high 35% 65% RXCLK period MII2 RXCLK pulse width low 35% 65% RXCLK period MII3 RXD[3:0], RXDV, RXER to RXCLK setup 5 — ns MII4 RXCLK to RXD[3:0], RXDV, RXER hold 5 — ns — TXCLK frequency — 25 MHz MII5 TXCLK pulse width high 35% 65% TXCLK period MII6 TXCLK pulse width low 35% 65% TXCLK period MII7 TXCLK to TXD[3:0], TXEN, TXER invalid 2 — ns MII8 TXCLK to TXD[3:0], TXEN, TXER valid — 25 ns MII6 MII5 TXCLK (input) MII8 MII7 TXD[n:0] Valid data TXEN Valid data TXER Valid data Figure 20. MII transmit signal timing diagram K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 58 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors MII2 MII1 RXCLK (input) MII3 MII4 RXD[n:0] Valid data RXDV Valid data RXER Valid data Figure 21. MII receive signal timing diagram 6.8.1.2 RMII signal switching specifications The following timing specs meet the requirements for RMII style interfaces for a range of transceiver devices. Table 39. RMII signal switching specifications Num Description Min. Max. Unit — EXTAL frequency (RMII input clock RMII_CLK) — 50 MHz RMII1 RMII_CLK pulse width high 35% 65% RMII_CLK period RMII2 RMII_CLK pulse width low 35% 65% RMII_CLK period RMII3 RXD[1:0], CRS_DV, RXER to RMII_CLK setup 4 — ns RMII4 RMII_CLK to RXD[1:0], CRS_DV, RXER hold 2 — ns RMII7 RMII_CLK to TXD[1:0], TXEN invalid 4 — ns RMII8 RMII_CLK to TXD[1:0], TXEN valid — 15 ns 6.8.2 USB electrical specifications The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit usb.org. K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 59

Peripheral operating requirements and behaviors 6.8.3 USB DCD electrical specifications Table 40. USB DCD electrical specifications Symbol Description Min. Typ. Max. Unit V USB_DP source voltage (up to 250 μA) 0.5 — 0.7 V DP_SRC V Threshold voltage for logic high 0.8 — 2.0 V LGC I USB_DP source current 7 10 13 μA DP_SRC I USB_DM sink current 50 100 150 μA DM_SINK R D- pulldown resistance for data pin contact detect 14.25 — 24.8 kΩ DM_DWN V Data detect voltage 0.25 0.33 0.4 V DAT_REF 6.8.4 USB VREG electrical specifications Table 41. USB VREG electrical specifications Symbol Description Min. Typ.1 Max. Unit Notes VREGIN Input supply voltage 2.7 — 5.5 V I Quiescent current — Run mode, load current — 120 186 μA DDon equal zero, input supply (VREGIN) > 3.6 V I Quiescent current — Standby mode, load current — 1.1 10 μA DDstby equal zero I Quiescent current — Shutdown mode DDoff — 650 — nA • VREGIN = 5.0 V and temperature=25 °C — — 4 μA • Across operating voltage and temperature I Maximum load current — Run mode — — 120 mA LOADrun I Maximum load current — Standby mode — — 1 mA LOADstby V Regulator output voltage — Input supply Reg33out (VREGIN) > 3.6 V • Run mode 3 3.3 3.6 V • Standby mode 2.1 2.8 3.6 V V Regulator output voltage — Input supply 2.1 — 3.6 V 2 Reg33out (VREGIN) < 3.6 V, pass-through mode C External output capacitor 1.76 2.2 8.16 μF OUT ESR External output capacitor equivalent series 1 — 100 mΩ resistance I Short circuit current — 290 — mA LIM 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I . Load K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 60 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 6.8.5 CAN switching specifications See General switching specifications. 6.8.6 DSPI switching specifications (limited voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 42. Master mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Notes Operating voltage 2.7 3.6 V Frequency of operation — 25 MHz DS1 DSPI_SCK output cycle time 2 x t — ns BUS DS2 DSPI_SCK output high/low time (t /2) − 2 (t /2) + 2 ns SCK SCK DS3 DSPI_PCSn valid to DSPI_SCK delay (t x 2) − — ns 1 BUS 2 DS4 DSPI_SCK to DSPI_PCSn invalid delay (t x 2) − — ns 2 BUS 2 DS5 DSPI_SCK to DSPI_SOUT valid — 8 ns DS6 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS7 DSPI_SIN to DSPI_SCK input setup 14 — ns DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DS2 DS1 DS4 DSPI_SCK DS8 (CPOL=0) DS7 DSPI_SIN First data Data Last data DS5 DS6 DSPI_SOUT First data Data Last data Figure 22. DSPI classic SPI timing — master mode K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 61

Peripheral operating requirements and behaviors Table 43. Slave mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation 12.5 MHz DS9 DSPI_SCK input cycle time 4 x t — ns BUS DS10 DSPI_SCK input high/low time (t /2) − 2 (t /2) + 2 ns SCK SCK DS11 DSPI_SCK to DSPI_SOUT valid — 20 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS13 DSPI_SIN to DSPI_SCK input setup 2 — ns DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns DS15 DSPI_SS active to DSPI_SOUT driven — 14 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven — 14 ns DSPI_SS DS10 DS9 DSPI_SCK (CPOL=0) DS15 DS12 DS11 DS16 DSPI_SOUT First data Data Last data DS13 DS14 DSPI_SIN First data Data Last data Figure 23. DSPI classic SPI timing — slave mode 6.8.7 DSPI switching specifications (full voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 44. Master mode DSPI timing (full voltage range) Num Description Min. Max. Unit Notes Operating voltage 1.71 3.6 V 1 Frequency of operation — 12.5 MHz DS1 DSPI_SCK output cycle time 4 x t — ns BUS Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 62 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 44. Master mode DSPI timing (full voltage range) (continued) Num Description Min. Max. Unit Notes DS2 DSPI_SCK output high/low time (t /2) - 4 (t + 4 ns SCK SCK/2) DS3 DSPI_PCSn valid to DSPI_SCK delay (t x 2) − — ns 2 BUS 4 DS4 DSPI_SCK to DSPI_PCSn invalid delay (t x 2) − — ns 3 BUS 4 DS5 DSPI_SCK to DSPI_SOUT valid — 8.5 ns DS6 DSPI_SCK to DSPI_SOUT invalid -1.2 — ns DS7 DSPI_SIN to DSPI_SCK input setup 19.1 — ns DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns 1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DS2 DS1 DS4 DSPI_SCK DS8 (CPOL=0) DS7 DSPI_SIN First data Data Last data DS5 DS6 DSPI_SOUT First data Data Last data Figure 24. DSPI classic SPI timing — master mode Table 45. Slave mode DSPI timing (full voltage range) Num Description Min. Max. Unit Operating voltage 1.71 3.6 V Frequency of operation — 6.25 MHz DS9 DSPI_SCK input cycle time 8 x t — ns BUS DS10 DSPI_SCK input high/low time (t /2) - 4 (t + 4 ns SCK SCK/2) DS11 DSPI_SCK to DSPI_SOUT valid — 24 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS13 DSPI_SIN to DSPI_SCK input setup 3.2 — ns DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns DS15 DSPI_SS active to DSPI_SOUT driven — 19 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven — 19 ns K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 63

Peripheral operating requirements and behaviors DSPI_SS DS10 DS9 DSPI_SCK (CPOL=0) DS15 DS12 DS11 DS16 DSPI_SOUT First data Data Last data DS13 DS14 DSPI_SIN First data Data Last data Figure 25. DSPI classic SPI timing — slave mode 6.8.8 Inter-Integrated Circuit Interface (I2C) timing Table 46. I 2C timing Characteristic Symbol Standard Mode Fast Mode Unit Minimum Maximum Minimum Maximum SCL Clock Frequency f 0 100 0 400 kHz SCL Hold time (repeated) START condition. t ; STA 4 — 0.6 — µs HD After this period, the first clock pulse is generated. LOW period of the SCL clock t 4.7 — 1.3 — µs LOW HIGH period of the SCL clock t 4 — 0.6 — µs HIGH Set-up time for a repeated START t ; STA 4.7 — 0.6 — µs SU condition Data hold time for I C bus devices t ; DAT 01 3.452 03 0.91 µs 2 HD Data set-up time t ; DAT 2504 — 1002, 5 — ns SU Rise time of SDA and SCL signals t — 1000 20 +0.1C 6 300 ns r b Fall time of SDA and SCL signals t — 300 20 +0.1C 5 300 ns f b Set-up time for STOP condition t ; STO 4 — 0.6 — µs SU Bus free time between STOP and t 4.7 — 1.3 — µs BUF START condition Pulse width of spikes that must be t N/A N/A 0 50 ns SP suppressed by the input filter 1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 3. Input signal Slew = 10 ns and Output Load = 50 pF 4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement t ≥ 250 ns must SU; DAT then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t + t rmax SU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 64 Freescale Semiconductor, Inc.

  Peripheral operating requirements and behaviors 6. C = total capacitance of the one bus line in pF. b SDA tSU; DAT tf tf tLOW tr tHD; STA tSP tr tBUF SCL tHD; STA tSU; STA tSU; STO S t t SR P S HD; DAT HIGH Figure 26. Timing definition for fast and standard mode devices on the I2C bus 6.8.9 UART switching specifications See General switching specifications. 6.8.10 SDHC specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. Table 47. SDHC switching specifications Num Symbol Description Min. Max. Unit Operating voltage 1.71 3.6 V Card input clock SD1 fpp Clock frequency (low speed) 0 400 kHz fpp Clock frequency (SD\SDIO full speed\high speed) 0 25\50 MHz fpp Clock frequency (MMC full speed\high speed) 0 20\50 MHz f Clock frequency (identification mode) 0 400 kHz OD SD2 t Clock low time 7 — ns WL SD3 t Clock high time 7 — ns WH SD4 t Clock rise time — 3 ns TLH SD5 t Clock fall time — 3 ns THL SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD6 t SDHC output delay (output valid) -5 8.3 ns OD SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD7 t SDHC input setup time 5 — ns ISU SD8 t SDHC input hold time 0 — ns IH K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 65

Peripheral operating requirements and behaviors SD3 SD2 SD1 SDHC_CLK SD6 Output SDHC_CMD Output SDHC_DAT[3:0] SD7 SD8 Input SDHC_CMD Input SDHC_DAT[3:0] Figure 27. SDHC timing 6.8.11 I2S/SAI switching specifications This section provides the AC timing for the I2S/SAI module in master mode (clocks are driven) and slave mode (clocks are input). All timing is given for noninverted serial clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the frame sync (FS) signal shown in the following figures. 6.8.11.1 Normal Run, Wait and Stop mode performance over a limited operating voltage range This section provides the operating performance over a limited operating voltage for the device in Normal Run, Wait and Stop modes. Table 48. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage range) Num. Characteristic Min. Max. Unit Operating voltage 2.7 3.6 V S1 I2S_MCLK cycle time 40 — ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 — ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ — 15 ns I2S_RX_FS output valid Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 66 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 48. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage range) (continued) Num. Characteristic Min. Max. Unit S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ 0 — ns I2S_RX_FS output invalid S7 I2S_TX_BCLK to I2S_TXD valid — 15 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns S9 I2S_RXD/I2S_RX_FS input setup before 15 — ns I2S_RX_BCLK S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ S4 I2S_RX_BCLK (output) S4 S5 S6 I2S_TX_FS/ I2S_RX_FS (output) S9 S10 I2S_TX_FS/ I2S_RX_FS (input) S7 S7 S8 S8 I2S_TXD S9 S10 I2S_RXD Figure 28. I2S/SAI timing — master modes Table 49. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage range) Num. Characteristic Min. Max. Unit Operating voltage 2.7 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 — ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% MCLK period (input) S13 I2S_TX_FS/I2S_RX_FS input setup before 4.5 — ns I2S_TX_BCLK/I2S_RX_BCLK S14 I2S_TX_FS/I2S_RX_FS input hold after 2 — ns I2S_TX_BCLK/I2S_RX_BCLK S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid ns — 21 • Multiple SAI Synchronous mode • All other modes — 15 Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 67

Peripheral operating requirements and behaviors Table 49. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage range) (continued) Num. Characteristic Min. Max. Unit S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_RX_BCLK 4.5 — ns S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 — 25 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear S11 S12 I2S_TX_BCLK/ S12 I2S_RX_BCLK (input) S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 S14 I2S_TX_FS/ I2S_RX_FS (input) S15 S19 S15 S16 S16 I2S_TXD S17 S18 I2S_RXD Figure 29. I2S/SAI timing — slave modes 6.8.11.2 Normal Run, Wait and Stop mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes. Table 50. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 40 — ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 — ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ — 15 ns I2S_RX_FS output valid S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ -1.0 — ns I2S_RX_FS output invalid Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 68 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 50. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage range) (continued) Num. Characteristic Min. Max. Unit S7 I2S_TX_BCLK to I2S_TXD valid — 15 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns S9 I2S_RXD/I2S_RX_FS input setup before 20.5 — ns I2S_RX_BCLK S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ S4 I2S_RX_BCLK (output) S4 S5 S6 I2S_TX_FS/ I2S_RX_FS (output) S9 S10 I2S_TX_FS/ I2S_RX_FS (input) S7 S7 S8 S8 I2S_TXD S9 S10 I2S_RXD Figure 30. I2S/SAI timing — master modes Table 51. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 — ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% MCLK period (input) S13 I2S_TX_FS/I2S_RX_FS input setup before 5.8 — ns I2S_TX_BCLK/I2S_RX_BCLK S14 I2S_TX_FS/I2S_RX_FS input hold after 2 — ns I2S_TX_BCLK/I2S_RX_BCLK S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid ns — 24 • Multiple SAI Synchronous mode • All other modes — 20.6 S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 69

Peripheral operating requirements and behaviors Table 51. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage range) (continued) Num. Characteristic Min. Max. Unit S17 I2S_RXD setup before I2S_RX_BCLK 5.8 — ns S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 — 25 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear S11 S12 I2S_TX_BCLK/ S12 I2S_RX_BCLK (input) S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 S14 I2S_TX_FS/ I2S_RX_FS (input) S15 S19 S15 S16 S16 I2S_TXD S17 S18 I2S_RXD Figure 31. I2S/SAI timing — slave modes 6.8.11.3 VLPR, VLPW, and VLPS mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes. Table 52. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 62.5 — ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 — ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ — 45 ns I2S_RX_FS output valid S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ 0 — ns I2S_RX_FS output invalid S7 I2S_TX_BCLK to I2S_TXD valid — 45 ns Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 70 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 52. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) (continued) Num. Characteristic Min. Max. Unit S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns S9 I2S_RXD/I2S_RX_FS input setup before 45 — ns I2S_RX_BCLK S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ S4 I2S_RX_BCLK (output) S4 S5 S6 I2S_TX_FS/ I2S_RX_FS (output) S9 S10 I2S_TX_FS/ I2S_RX_FS (input) S7 S7 S8 S8 I2S_TXD S9 S10 I2S_RXD Figure 32. I2S/SAI timing — master modes Table 53. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 — ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% MCLK period (input) S13 I2S_TX_FS/I2S_RX_FS input setup before 30 — ns I2S_TX_BCLK/I2S_RX_BCLK S14 I2S_TX_FS/I2S_RX_FS input hold after 3 — ns I2S_TX_BCLK/I2S_RX_BCLK S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 63 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_RX_BCLK 30 — ns S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 — 72 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 71

Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ S12 I2S_RX_BCLK (input) S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 S14 I2S_TX_FS/ I2S_RX_FS (input) S15 S19 S15 S16 S16 I2S_TXD S17 S18 I2S_RXD Figure 33. I2S/SAI timing — slave modes 6.9 Human-machine interfaces (HMI) 6.9.1 TSI electrical specifications Table 54. TSI electrical specifications Symbol Description Min. Typ. Max. Unit Notes V Operating voltage 1.71 — 3.6 V DDTSI C Target electrode capacitance range 1 20 500 pF 1 ELE f Reference oscillator frequency — 8 15 MHz 2, 3 REFmax f Electrode oscillator frequency — 1 1.8 MHz 2, 4 ELEmax C Internal reference capacitor — 1 — pF REF V Oscillator delta voltage — 500 — mV 2, 5 DELTA I Reference oscillator current source base current μA 2, 6 REF — 2 3 • 2 μA setting (REFCHRG = 0) • 32 μA setting (REFCHRG = 15) — 36 50 I Electrode oscillator current source base current μA 2, 7 ELE — 2 3 • 2 μA setting (EXTCHRG = 0) • 32 μA setting (EXTCHRG = 15) — 36 50 Pres5 Electrode capacitance measurement precision — 8.3333 38400 fF/count 8 Pres20 Electrode capacitance measurement precision — 8.3333 38400 fF/count 9 Pres100 Electrode capacitance measurement precision — 8.3333 38400 fF/count 10 MaxSens Maximum sensitivity 0.008 1.46 — fF/count 11 Res Resolution — — 16 bits T Response time @ 20 pF 8 15 25 μs 12 Con20 I Current added in run mode — 55 — μA TSI_RUN I Low power mode current adder — 1.3 2.5 μA 13 TSI_LP K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 72 Freescale Semiconductor, Inc.

Dimensions 1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. 2. Fixed external capacitance of 20 pF. 3. REFCHRG = 2, EXTCHRG=0. 4. REFCHRG = 0, EXTCHRG = 10. 5. V = 3.0 V. DD 6. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current. 7. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current. 8. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16. 9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16. 10. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16. 11. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity depends on the configuration used. The documented values are provided as examples calculated for a specific configuration of operating conditions using the following equation: (C * I )/( I * PS * NSCN) ref ext ref The typical value is calculated with the following configuration: Iext = 6 μA (EXTCHRG = 2), PS = 128, NSCN = 2, Iref = 16 μA (REFCHRG = 7), Cref = 1.0 pF The minimum value is calculated with the following configuration: Iext = 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 μA (REFCHRG = 15), Cref = 0.5 pF The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be measured by a single count. 12. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1 electrode, EXTCHRG = 7. 13. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window. 7 Dimensions 7.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 144-pin LQFP 98ASS23177W 144-pin MAPBGA 98ASA00222D 8 Pinout K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 73

Pinout 8.1 K60 signal multiplexing and pin assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 144 144 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort LQFP MAP BGA — L5 RTC_ RTC_ RTC_ WAKEUP_B WAKEUP_B WAKEUP_B — M5 NC NC NC — A10 NC NC NC — B10 NC NC NC — C10 NC NC NC 1 D3 PTE0 ADC1_SE4a ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 I2C1_SDA RTC_CLKOUT 2 D2 PTE1/ ADC1_SE5a ADC1_SE5a PTE1/ SPI1_SOUT UART1_RX SDHC0_D0 I2C1_SCL SPI1_SIN LLWU_P0 LLWU_P0 3 D1 PTE2/ ADC1_SE6a ADC1_SE6a PTE2/ SPI1_SCK UART1_CTS_ SDHC0_DCLK LLWU_P1 LLWU_P1 b 4 E4 PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_ SDHC0_CMD SPI1_SOUT b 5 E5 VDD VDD VDD 6 F6 VSS VSS VSS 7 E3 PTE4/ DISABLED PTE4/ SPI1_PCS0 UART3_TX SDHC0_D3 LLWU_P2 LLWU_P2 8 E2 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 9 E1 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CTS_ I2S0_MCLK USB_SOF_ b OUT 10 F4 PTE7 DISABLED PTE7 UART3_RTS_ I2S0_RXD0 b 11 F3 PTE8 DISABLED PTE8 I2S0_RXD1 UART5_TX I2S0_RX_FS 12 F2 PTE9 DISABLED PTE9 I2S0_TXD1 UART5_RX I2S0_RX_ BCLK 13 F1 PTE10 DISABLED PTE10 UART5_CTS_ I2S0_TXD0 b 14 G4 PTE11 DISABLED PTE11 UART5_RTS_ I2S0_TX_FS b 15 G3 PTE12 DISABLED PTE12 I2S0_TX_ BCLK 16 E6 VDD VDD VDD 17 F7 VSS VSS VSS 18 H3 VSS VSS VSS 19 H1 USB0_DP USB0_DP USB0_DP 20 H2 USB0_DM USB0_DM USB0_DM 21 G1 VOUT33 VOUT33 VOUT33 22 G2 VREGIN VREGIN VREGIN K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 74 Freescale Semiconductor, Inc.

Pinout 144 144 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort LQFP MAP BGA 23 J1 ADC0_DP1 ADC0_DP1 ADC0_DP1 24 J2 ADC0_DM1 ADC0_DM1 ADC0_DM1 25 K1 ADC1_DP1 ADC1_DP1 ADC1_DP1 26 K2 ADC1_DM1 ADC1_DM1 ADC1_DM1 27 L1 PGA0_DP/ PGA0_DP/ PGA0_DP/ ADC0_DP0/ ADC0_DP0/ ADC0_DP0/ ADC1_DP3 ADC1_DP3 ADC1_DP3 28 L2 PGA0_DM/ PGA0_DM/ PGA0_DM/ ADC0_DM0/ ADC0_DM0/ ADC0_DM0/ ADC1_DM3 ADC1_DM3 ADC1_DM3 29 M1 PGA1_DP/ PGA1_DP/ PGA1_DP/ ADC1_DP0/ ADC1_DP0/ ADC1_DP0/ ADC0_DP3 ADC0_DP3 ADC0_DP3 30 M2 PGA1_DM/ PGA1_DM/ PGA1_DM/ ADC1_DM0/ ADC1_DM0/ ADC1_DM0/ ADC0_DM3 ADC0_DM3 ADC0_DM3 31 H5 VDDA VDDA VDDA 32 G5 VREFH VREFH VREFH 33 G6 VREFL VREFL VREFL 34 H6 VSSA VSSA VSSA 35 K3 ADC1_SE16/ ADC1_SE16/ ADC1_SE16/ CMP2_IN2/ CMP2_IN2/ CMP2_IN2/ ADC0_SE22 ADC0_SE22 ADC0_SE22 36 J3 ADC0_SE16/ ADC0_SE16/ ADC0_SE16/ CMP1_IN2/ CMP1_IN2/ CMP1_IN2/ ADC0_SE21 ADC0_SE21 ADC0_SE21 37 M3 VREF_OUT/ VREF_OUT/ VREF_OUT/ CMP1_IN5/ CMP1_IN5/ CMP1_IN5/ CMP0_IN5/ CMP0_IN5/ CMP0_IN5/ ADC1_SE18 ADC1_SE18 ADC1_SE18 38 L3 DAC0_OUT/ DAC0_OUT/ DAC0_OUT/ CMP1_IN3/ CMP1_IN3/ CMP1_IN3/ ADC0_SE23 ADC0_SE23 ADC0_SE23 39 L4 DAC1_OUT/ DAC1_OUT/ DAC1_OUT/ CMP0_IN4/ CMP0_IN4/ CMP0_IN4/ CMP2_IN3/ CMP2_IN3/ CMP2_IN3/ ADC1_SE23 ADC1_SE23 ADC1_SE23 40 M7 XTAL32 XTAL32 XTAL32 41 M6 EXTAL32 EXTAL32 EXTAL32 42 L6 VBAT VBAT VBAT 43 — VDD VDD VDD 44 — VSS VSS VSS 45 M4 PTE24 ADC0_SE17 ADC0_SE17 PTE24 CAN1_TX UART4_TX EWM_OUT_b 46 K5 PTE25 ADC0_SE18 ADC0_SE18 PTE25 CAN1_RX UART4_RX EWM_IN 47 K4 PTE26 DISABLED PTE26 ENET_1588_ UART4_CTS_ RTC_CLKOUT USB_CLKIN CLKIN b K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 75

Pinout 144 144 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort LQFP MAP BGA 48 J4 PTE27 DISABLED PTE27 UART4_RTS_ b 49 H4 PTE28 DISABLED PTE28 50 J5 PTA0 JTAG_TCLK/ TSI0_CH1 PTA0 UART0_CTS_ FTM0_CH5 JTAG_TCLK/ EZP_CLK SWD_CLK/ b/ SWD_CLK EZP_CLK UART0_COL_ b 51 J6 PTA1 JTAG_TDI/ TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI EZP_DI 52 K6 PTA2 JTAG_TDO/ TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/ EZP_DO TRACE_SWO/ TRACE_SWO EZP_DO 53 K7 PTA3 JTAG_TMS/ TSI0_CH4 PTA3 UART0_RTS_ FTM0_CH0 JTAG_TMS/ SWD_DIO b SWD_DIO 54 L7 PTA4/ NMI_b/ TSI0_CH5 PTA4/ FTM0_CH1 NMI_b EZP_CS_b LLWU_P3 EZP_CS_b LLWU_P3 55 M8 PTA5 DISABLED PTA5 USB_CLKIN FTM0_CH2 RMII0_RXER/ CMP2_OUT I2S0_TX_ JTAG_TRST_ MII0_RXER BCLK b 56 E7 VDD VDD VDD 57 G7 VSS VSS VSS 58 J7 PTA6 DISABLED PTA6 FTM0_CH3 TRACE_ CLKOUT 59 J8 PTA7 ADC0_SE10 ADC0_SE10 PTA7 FTM0_CH4 TRACE_D3 60 K8 PTA8 ADC0_SE11 ADC0_SE11 PTA8 FTM1_CH0 FTM1_QD_ TRACE_D2 PHA 61 L8 PTA9 DISABLED PTA9 FTM1_CH1 MII0_RXD3 FTM1_QD_ TRACE_D1 PHB 62 M9 PTA10 DISABLED PTA10 FTM2_CH0 MII0_RXD2 FTM2_QD_ TRACE_D0 PHA 63 L9 PTA11 DISABLED PTA11 FTM2_CH1 MII0_RXCLK FTM2_QD_ PHB 64 K9 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 RMII0_RXD1/ I2S0_TXD0 FTM1_QD_ MII0_RXD1 PHA 65 J9 PTA13/ CMP2_IN1 CMP2_IN1 PTA13/ CAN0_RX FTM1_CH1 RMII0_RXD0/ I2S0_TX_FS FTM1_QD_ LLWU_P4 LLWU_P4 MII0_RXD0 PHB 66 L10 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX RMII0_CRS_ I2S0_RX_ I2S0_TXD1 DV/ BCLK MII0_RXDV 67 L11 PTA15 DISABLED PTA15 SPI0_SCK UART0_RX RMII0_TXEN/ I2S0_RXD0 MII0_TXEN 68 K10 PTA16 DISABLED PTA16 SPI0_SOUT UART0_CTS_ RMII0_TXD0/ I2S0_RX_FS I2S0_RXD1 b/ MII0_TXD0 UART0_COL_ b 69 K11 PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_RTS_ RMII0_TXD1/ I2S0_MCLK b MII0_TXD1 70 E8 VDD VDD VDD K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 76 Freescale Semiconductor, Inc.

Pinout 144 144 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort LQFP MAP BGA 71 G8 VSS VSS VSS 72 M12 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2 FTM_CLKIN0 73 M11 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0 FTM_CLKIN1 LPTMR0_ ALT1 74 L12 RESET_b RESET_b RESET_b 75 K12 PTA24 DISABLED PTA24 MII0_TXD2 FB_A29 76 J12 PTA25 DISABLED PTA25 MII0_TXCLK FB_A28 77 J11 PTA26 DISABLED PTA26 MII0_TXD3 FB_A27 78 J10 PTA27 DISABLED PTA27 MII0_CRS FB_A26 79 H12 PTA28 DISABLED PTA28 MII0_TXER FB_A25 80 H11 PTA29 DISABLED PTA29 MII0_COL FB_A24 81 H10 PTB0/ ADC0_SE8/ ADC0_SE8/ PTB0/ I2C0_SCL FTM1_CH0 RMII0_MDIO/ FTM1_QD_ LLWU_P5 ADC1_SE8/ ADC1_SE8/ LLWU_P5 MII0_MDIO PHA TSI0_CH0 TSI0_CH0 82 H9 PTB1 ADC0_SE9/ ADC0_SE9/ PTB1 I2C0_SDA FTM1_CH1 RMII0_MDC/ FTM1_QD_ ADC1_SE9/ ADC1_SE9/ MII0_MDC PHB TSI0_CH6 TSI0_CH6 83 G12 PTB2 ADC0_SE12/ ADC0_SE12/ PTB2 I2C0_SCL UART0_RTS_ ENET0_1588_ FTM0_FLT3 TSI0_CH7 TSI0_CH7 b TMR0 84 G11 PTB3 ADC0_SE13/ ADC0_SE13/ PTB3 I2C0_SDA UART0_CTS_ ENET0_1588_ FTM0_FLT0 TSI0_CH8 TSI0_CH8 b/ TMR1 UART0_COL_ b 85 G10 PTB4 ADC1_SE10 ADC1_SE10 PTB4 ENET0_1588_ FTM1_FLT0 TMR2 86 G9 PTB5 ADC1_SE11 ADC1_SE11 PTB5 ENET0_1588_ FTM2_FLT0 TMR3 87 F12 PTB6 ADC1_SE12 ADC1_SE12 PTB6 FB_AD23 88 F11 PTB7 ADC1_SE13 ADC1_SE13 PTB7 FB_AD22 89 F10 PTB8 DISABLED PTB8 UART3_RTS_ FB_AD21 b 90 F9 PTB9 DISABLED PTB9 SPI1_PCS1 UART3_CTS_ FB_AD20 b 91 E12 PTB10 ADC1_SE14 ADC1_SE14 PTB10 SPI1_PCS0 UART3_RX FB_AD19 FTM0_FLT1 92 E11 PTB11 ADC1_SE15 ADC1_SE15 PTB11 SPI1_SCK UART3_TX FB_AD18 FTM0_FLT2 93 H7 VSS VSS VSS 94 F5 VDD VDD VDD 95 E10 PTB16 TSI0_CH9 TSI0_CH9 PTB16 SPI1_SOUT UART0_RX FB_AD17 EWM_IN 96 E9 PTB17 TSI0_CH10 TSI0_CH10 PTB17 SPI1_SIN UART0_TX FB_AD16 EWM_OUT_b 97 D12 PTB18 TSI0_CH11 TSI0_CH11 PTB18 CAN0_TX FTM2_CH0 I2S0_TX_ FB_AD15 FTM2_QD_ BCLK PHA 98 D11 PTB19 TSI0_CH12 TSI0_CH12 PTB19 CAN0_RX FTM2_CH1 I2S0_TX_FS FB_OE_b FTM2_QD_ PHB 99 D10 PTB20 DISABLED PTB20 SPI2_PCS0 FB_AD31 CMP0_OUT 100 D9 PTB21 DISABLED PTB21 SPI2_SCK FB_AD30 CMP1_OUT K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 77

Pinout 144 144 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort LQFP MAP BGA 101 C12 PTB22 DISABLED PTB22 SPI2_SOUT FB_AD29 CMP2_OUT 102 C11 PTB23 DISABLED PTB23 SPI2_SIN SPI0_PCS5 FB_AD28 103 B12 PTC0 ADC0_SE14/ ADC0_SE14/ PTC0 SPI0_PCS4 PDB0_EXTRG FB_AD14 I2S0_TXD1 TSI0_CH13 TSI0_CH13 104 B11 PTC1/ ADC0_SE15/ ADC0_SE15/ PTC1/ SPI0_PCS3 UART1_RTS_ FTM0_CH0 FB_AD13 I2S0_TXD0 LLWU_P6 TSI0_CH14 TSI0_CH14 LLWU_P6 b 105 A12 PTC2 ADC0_SE4b/ ADC0_SE4b/ PTC2 SPI0_PCS2 UART1_CTS_ FTM0_CH1 FB_AD12 I2S0_TX_FS CMP1_IN0/ CMP1_IN0/ b TSI0_CH15 TSI0_CH15 106 A11 PTC3/ CMP1_IN1 CMP1_IN1 PTC3/ SPI0_PCS1 UART1_RX FTM0_CH2 CLKOUT I2S0_TX_ LLWU_P7 LLWU_P7 BCLK 107 H8 VSS VSS VSS 108 — VDD VDD VDD 109 A9 PTC4/ DISABLED PTC4/ SPI0_PCS0 UART1_TX FTM0_CH3 FB_AD11 CMP1_OUT LLWU_P8 LLWU_P8 110 D8 PTC5/ DISABLED PTC5/ SPI0_SCK LPTMR0_ I2S0_RXD0 FB_AD10 CMP0_OUT LLWU_P9 LLWU_P9 ALT2 111 C8 PTC6/ CMP0_IN0 CMP0_IN0 PTC6/ SPI0_SOUT PDB0_EXTRG I2S0_RX_ FB_AD9 I2S0_MCLK LLWU_P10 LLWU_P10 BCLK 112 B8 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_SOF_ I2S0_RX_FS FB_AD8 OUT 113 A8 PTC8 ADC1_SE4b/ ADC1_SE4b/ PTC8 I2S0_MCLK FB_AD7 CMP0_IN2 CMP0_IN2 114 D7 PTC9 ADC1_SE5b/ ADC1_SE5b/ PTC9 I2S0_RX_ FB_AD6 FTM2_FLT0 CMP0_IN3 CMP0_IN3 BCLK 115 C7 PTC10 ADC1_SE6b ADC1_SE6b PTC10 I2C1_SCL I2S0_RX_FS FB_AD5 116 B7 PTC11/ ADC1_SE7b ADC1_SE7b PTC11/ I2C1_SDA I2S0_RXD1 FB_RW_b LLWU_P11 LLWU_P11 117 A7 PTC12 DISABLED PTC12 UART4_RTS_ FB_AD27 b 118 D6 PTC13 DISABLED PTC13 UART4_CTS_ FB_AD26 b 119 C6 PTC14 DISABLED PTC14 UART4_RX FB_AD25 120 B6 PTC15 DISABLED PTC15 UART4_TX FB_AD24 121 — VSS VSS VSS 122 — VDD VDD VDD 123 A6 PTC16 DISABLED PTC16 CAN1_RX UART3_RX ENET0_1588_ FB_CS5_b/ TMR0 FB_TSIZ1/ FB_BE23_16_ b 124 D5 PTC17 DISABLED PTC17 CAN1_TX UART3_TX ENET0_1588_ FB_CS4_b/ TMR1 FB_TSIZ0/ FB_BE31_24_ b 125 C5 PTC18 DISABLED PTC18 UART3_RTS_ ENET0_1588_ FB_TBST_b/ b TMR2 FB_CS2_b/ FB_BE15_8_b K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 78 Freescale Semiconductor, Inc.

Pinout 144 144 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort LQFP MAP BGA 126 B5 PTC19 DISABLED PTC19 UART3_CTS_ ENET0_1588_ FB_CS3_b/ FB_TA_b b TMR3 FB_BE7_0_b 127 A5 PTD0/ DISABLED PTD0/ SPI0_PCS0 UART2_RTS_ FB_ALE/ LLWU_P12 LLWU_P12 b FB_CS1_b/ FB_TS_b 128 D4 PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK UART2_CTS_ FB_CS0_b b 129 C4 PTD2/ DISABLED PTD2/ SPI0_SOUT UART2_RX FB_AD4 LLWU_P13 LLWU_P13 130 B4 PTD3 DISABLED PTD3 SPI0_SIN UART2_TX FB_AD3 131 A4 PTD4/ DISABLED PTD4/ SPI0_PCS1 UART0_RTS_ FTM0_CH4 FB_AD2 EWM_IN LLWU_P14 LLWU_P14 b 132 A3 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_ FTM0_CH5 FB_AD1 EWM_OUT_b b/ UART0_COL_ b 133 A2 PTD6/ ADC0_SE7b ADC0_SE7b PTD6/ SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 FTM0_FLT0 LLWU_P15 LLWU_P15 134 M10 VSS VSS VSS 135 F8 VDD VDD VDD 136 A1 PTD7 DISABLED PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1 137 C9 PTD8 DISABLED PTD8 I2C0_SCL UART5_RX FB_A16 138 B9 PTD9 DISABLED PTD9 I2C0_SDA UART5_TX FB_A17 139 B3 PTD10 DISABLED PTD10 UART5_RTS_ FB_A18 b 140 B2 PTD11 DISABLED PTD11 SPI2_PCS0 UART5_CTS_ SDHC0_ FB_A19 b CLKIN 141 B1 PTD12 DISABLED PTD12 SPI2_SCK SDHC0_D4 FB_A20 142 C3 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21 143 C2 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22 144 C1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23 8.2 K60 pinouts The figure below shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 79

Pinout 1 5 4 3 2 1 0 1 1 1 1 P 1 9 8 P P P P _ P P P _ _ _ _ U _ _ _ U U U U W U U U W W W W L W W W L L L L L L L L D15 D14 D13 D12 D11 D10 D9 D8 D7 D S D6/L D5 D4/L D3 D2/L D1 D0/L C19 C18 C17 C16 D S C15 C14 C13 C12 C11/ C10 C9 C8 C7 C6/L C5/L C4/L T T T T T T T T T D S T T T T T T T T T T T D S T T T T T T T T T T T T P P P P P P P P P V V P P P P P P P P P P P V V P P P P P P P P P P P P PTE0 1 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109108 VDD PTE1/LLWU_P0 2 107 VSS PTE2/LLWU_P1 3 106 PTC3/LLWU_P7 PTE3 4 105 PTC2 VDD 5 104 PTC1/LLWU_P6 VSS 6 103 PTC0 PTE4/LLWU_P2 7 102 PTB23 PTE5 8 101 PTB22 PTE6 9 100 PTB21 PTE7 10 99 PTB20 PTE8 11 98 PTB19 PTE9 12 97 PTB18 PTE10 13 96 PTB17 PTE11 14 95 PTB16 PTE12 15 94 VDD VDD 16 93 VSS VSS 17 92 PTB11 VSS 18 91 PTB10 USB0_DP 19 90 PTB9 USB0_DM 20 89 PTB8 VOUT33 21 88 PTB7 VREGIN 22 87 PTB6 ADC0_DP1 23 86 PTB5 ADC0_DM1 24 85 PTB4 ADC1_DP1 25 84 PTB3 ADC1_DM1 26 83 PTB2 PGA0_DP/ADC0_DP0/ADC1_DP3 27 82 PTB1 PGA0_DM/ADC0_DM0/ADC1_DM3 28 81 PTB0/LLWU_P5 PGA1_DP/ADC1_DP0/ADC0_DP3 29 80 PTA29 PGA1_DM/ADC1_DM0/ADC0_DM3 30 79 PTA28 VDDA 31 78 PTA27 VREFH 32 77 PTA26 VREFL 33 76 PTA25 VSSA 34 75 PTA24 ADC1_SE16/CMP2_IN2/ADC0_SE22 35 74 RESET_b ADC0_SE16/CMP1_IN2/ADC0_SE21 36 73 PTA19 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 P0_IN5/ADC1_SE18 P1_IN3/ADC0_SE23 P2_IN3/ADC1_SE23 XTAL32 EXTAL32 VBAT VDD VSS PTE24 PTE25 PTE26 PTE27 PTE28 PTA0 PTA1 PTA2 PTA3 PTA4/LLWU_P3 PTA5 VDD VSS PTA6 PTA7 PTA8 PTA9 PTA10 PTA11 PTA12 PTA13/LLWU_P4 PTA14 PTA15 PTA16 PTA17 VDD VSS PTA18 M M M C C C N5/ UT/ N4/ MP1_I C0_O MP0_I T/C DA T/C U U O O EF_ C1_ R A V D Figure 34. K60 144 LQFP Pinout Diagram K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 80 Freescale Semiconductor, Inc.

Revision history 1 2 3 4 5 6 7 8 9 10 11 12 A PTD7 LLWPTUD_6P/15 PTD5 LLWPTUD_4P/14 LLWPTUD_0P/12 PTC16 PTC12 PTC8 LLPWTUC_4P/8 NC LLPWTUC_3P/7 PTC2 A B PTD12 PTD11 PTD10 PTD3 PTC19 PTC15 PTC11/ PTC7 PTD9 NC PTC1/ PTC0 B LLWU_P11 LLWU_P6 C PTD15 PTD14 PTD13 PTD2/ PTC18 PTC14 PTC10 PTC6/ PTD8 NC PTB23 PTB22 C LLWU_P13 LLWU_P10 D PTE2/ PTE1/ PTE0 PTD1 PTC17 PTC13 PTC9 PTC5/ PTB21 PTB20 PTB19 PTB18 D LLWU_P1 LLWU_P0 LLWU_P9 E PTE6 PTE5 PTE4/ PTE3 VDD VDD VDD VDD PTB17 PTB16 PTB11 PTB10 E LLWU_P2 F PTE10 PTE9 PTE8 PTE7 VDD VSS VSS VDD PTB9 PTB8 PTB7 PTB6 F G VOUT33 VREGIN PTE12 PTE11 VREFH VREFL VSS VSS PTB5 PTB4 PTB3 PTB2 G H USB0_DP USB0_DM VSS PTE28 VDDA VSSA VSS VSS PTB1 PTB0/ PTA29 PTA28 H LLWU_P5 ADC0_SE16/ J ADC0_DP1 ADC0_DM1 CMP1_IN2/ PTE27 PTA0 PTA1 PTA6 PTA7 PTA13/ PTA27 PTA26 PTA25 J LLWU_P4 ADC0_SE21 ADC1_SE16/ K ADC1_DP1 ADC1_DM1 CMP2_IN2/ PTE26 PTE25 PTA2 PTA3 PTA8 PTA12 PTA16 PTA17 PTA24 K ADC0_SE22 DAC1_OUT/ PGA0_DP/ PGA0_DM/ DAC0_OUT/ L ADC0_DP0/ ADC0_DM0/ CMP1_IN3/ CCMMPP02__IINN43// _WARKTECUP_B VBAT LLPWTUA_4P/3 PTA9 PTA11 PTA14 PTA15 RESET_b L ADC1_DP3 ADC1_DM3 ADC0_SE23 ADC1_SE23 VREF_OUT/ PGA1_DP/ PGA1_DM/ M ADC1_DP0/ ADC1_DM0/ CMP1_IN5/ PTE24 NC EXTAL32 XTAL32 PTA5 PTA10 VSS PTA19 PTA18 M CMP0_IN5/ ADC0_DP3 ADC0_DM3 ADC1_SE18 1 2 3 4 5 6 7 8 9 10 11 12 Figure 35. K60 144 MAPBGA Pinout Diagram 9 Revision history The following table provides a revision history for this document. Table 55. Revision history Rev. No. Date Substantial Changes 1 6/2012 Initial public revision Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 81

Revision history Table 55. Revision history (continued) Rev. No. Date Substantial Changes 2 12/2012 Replaced TBDs throughout. 3 6/2013 • In ESD handling ratings, added a note for ILAT. • Updated "Voltage and current operating requirements" Table 1. • Updated I data for V row in "Voltage and current operating behaviors" Table 4. OL OL • Updated wakeup times and t value in "Power mode transition operating behaviors" POR Table 5. • In "EMC radiated emissions operating behaviors . . ." Table 7, added a column for 144MAPBGA. • In "16-bit ADC operating conditions" Table 27, updated the max spec of VADIN. • In "16-bit ADC electrical characteristics" Table 28, updated the temp sensor slope and voltage specs. • Updated Inter-Integrated Circuit Interface (I2C) timing. • In SDHC specifications, added operating voltage row. K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 82 Freescale Semiconductor, Inc.

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