Freescale Semiconductor Document Number: K10P32M50SF0 Data Sheet: Technical Data Rev. 4 5/2012 K10P32M50SF0 K10 Sub-Family Supports the following: MK10DN32VFM5, MK10DX32VFM5, MK10DN64VFM5, MK10DX64VFM5, MK10DN128VFM5, MK10DX128VFM5 Features • Security and integrity modules • Operating Characteristics – Hardware CRC module to support fast cyclic – Voltage range: 1.71 to 3.6 V redundancy checks – Flash write voltage range: 1.71 to 3.6 V – 128-bit unique identification (ID) number per chip – Temperature range (ambient): -40 to 105°C • Analog modules • Performance – 16-bit SAR ADC – Up to 50 MHz ARM Cortex-M4 core with DSP – Two analog comparators (CMP) containing a 6-bit instructions delivering 1.25 Dhrystone MIPS per DAC and programmable reference input MHz • Timers • Memories and memory interfaces – Programmable delay block – Up to 128 KB program flash. – Eight-channel motor control/general purpose/PWM – Up to 32 KB FlexNVM on FlexMemory devices timer – 2 KB FlexRAM on FlexMemory devices – Two-channel quadrature decoder/general purpose – Up to 16 KB RAM timer – Serial programming interface (EzPort) – Periodic interrupt timers – 16-bit low-power timer • Clocks – Carrier modulator transmitter – 3 to 32 MHz crystal oscillator – Real-time clock – 32 kHz crystal oscillator – Multi-purpose clock generator • Communication interfaces – SPI module • System peripherals – I2C module – Multiple low-power modes to provide power – Three UART modules optimization based on application requirements – I2S module – 4-channel DMA controller, supporting up to 41 request sources – External watchdog monitor – Software watchdog – Low-leakage wakeup unit Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2011–2012 Freescale Semiconductor, Inc.

Table of Contents 1 Ordering parts...........................................................................3 5.3.2 General switching specifications...........................20 1.1 Determining valid orderable parts......................................3 5.4 Thermal specifications.......................................................21 2 Part identification......................................................................3 5.4.1 Thermal operating requirements...........................21 2.1 Description.........................................................................3 5.4.2 Thermal attributes.................................................21 2.2 Format...............................................................................3 6 Peripheral operating requirements and behaviors....................22 2.3 Fields.................................................................................3 6.1 Core modules....................................................................22 2.4 Example............................................................................4 6.1.1 JTAG electricals....................................................22 3 Terminology and guidelines......................................................4 6.2 System modules................................................................25 3.1 Definition: Operating requirement......................................4 6.3 Clock modules...................................................................25 3.2 Definition: Operating behavior...........................................5 6.3.1 MCG specifications...............................................25 3.3 Definition: Attribute............................................................5 6.3.2 Oscillator electrical specifications.........................27 3.4 Definition: Rating...............................................................6 6.3.3 32 kHz Oscillator Electrical Characteristics...........29 3.5 Result of exceeding a rating..............................................6 6.4 Memories and memory interfaces.....................................30 3.6 Relationship between ratings and operating 6.4.1 Flash electrical specifications................................30 requirements......................................................................6 6.4.2 EzPort Switching Specifications............................34 3.7 Guidelines for ratings and operating requirements............7 6.5 Security and integrity modules..........................................35 3.8 Definition: Typical value.....................................................7 6.6 Analog...............................................................................35 3.9 Typical value conditions....................................................8 6.6.1 ADC electrical specifications.................................35 4 Ratings......................................................................................9 6.6.2 CMP and 6-bit DAC electrical specifications.........40 4.1 Thermal handling ratings...................................................9 6.7 Timers................................................................................43 4.2 Moisture handling ratings..................................................9 6.8 Communication interfaces.................................................43 4.3 ESD handling ratings.........................................................9 6.8.1 DSPI switching specifications (limited voltage 4.4 Voltage and current operating ratings...............................9 range)....................................................................43 5 General.....................................................................................10 6.8.2 DSPI switching specifications (full voltage range).45 5.1 AC electrical characteristics..............................................10 6.8.3 I2C switching specifications..................................47 5.2 Nonswitching electrical specifications...............................10 6.8.4 UART switching specifications..............................47 5.2.1 Voltage and current operating requirements.........10 6.8.5 I2S/SAI Switching Specifications..........................47 5.2.2 LVD and POR operating requirements.................11 6.9 Human-machine interfaces (HMI)......................................51 5.2.3 Voltage and current operating behaviors..............12 6.9.1 TSI electrical specifications...................................51 5.2.4 Power mode transition operating behaviors..........13 7 Dimensions...............................................................................53 5.2.5 Power consumption operating behaviors..............14 7.1 Obtaining package dimensions.........................................53 5.2.6 EMC radiated emissions operating behaviors.......18 8 Pinout........................................................................................53 5.2.7 Designing with radiated emissions in mind...........19 8.1 K10 Signal Multiplexing and Pin Assignments..................53 5.2.8 Capacitance attributes..........................................19 8.2 K10 Pinouts.......................................................................54 5.3 Switching specifications.....................................................19 9 Revision History........................................................................55 5.3.1 Device clock specifications...................................19 K10 Sub-Family Data Sheet, Rev. 4 5/2012. 2 Freescale Semiconductor, Inc.

Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers: PK10 and MK10 . 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.2 Format Part numbers for this device have the following format: Q K## A M FFF R T PP CC N 2.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow • P = Prequalification K## Kinetis family • K10 A Key attribute • D = Cortex-M4 w/ DSP • F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only • X = Program flash and FlexMemory Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 3

Terminology and guidelines Field Description Values FFF Program flash memory size • 32 = 32 KB • 64 = 64 KB • 128 = 128 KB • 256 = 256 KB • 512 = 512 KB • 1M0 = 1 MB R Silicon revision • Z = Initial • (Blank) = Main • A = Revision after main T Temperature range (°C) • V = –40 to 105 • C = –40 to 85 PP Package identifier • FM = 32 QFN (5 mm x 5 mm) • FT = 48 QFN (7 mm x 7 mm) • LF = 48 LQFP (7 mm x 7 mm) • LH = 64 LQFP (10 mm x 10 mm) • MP = 64 MAPBGA (5 mm x 5 mm) • LK = 80 LQFP (12 mm x 12 mm) • MB = 81 MAPBGA (8 mm x 8 mm) • LL = 100 LQFP (14 mm x 14 mm) • ML = 104 MAPBGA (8 mm x 8 mm) • MC = 121 MAPBGA (8 mm x 8 mm) • LQ = 144 LQFP (20 mm x 20 mm) • MD = 144 MAPBGA (13 mm x 13 mm) • MJ = 256 MAPBGA (17 mm x 17 mm) CC Maximum CPU frequency (MHz) • 5 = 50 MHz • 7 = 72 MHz • 10 = 100 MHz • 12 = 120 MHz • 15 = 150 MHz N Packaging type • R = Tape and reel • (Blank) = Trays 2.4 Example This is an example part number: MK10DN32VFM5 3 Terminology and guidelines K10 Sub-Family Data Sheet, Rev. 4 5/2012. 4 Freescale Semiconductor, Inc.

Terminology and guidelines 3.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 3.1.1 Example This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol Description Min. Max. Unit V 1.0 V core supply 0.9 1.1 V DD voltage 3.2 Definition: Operating behavior An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 Example This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol Description Min. Max. Unit I Digital I/O weak pullup/ 10 130 µA WP pulldown current 3.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 5

Terminology and guidelines 3.3.1 Example This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: — 7 pF digital pins 3.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. 3.4.1 Example This is an example of an operating rating: Symbol Description Min. Max. Unit V 1.0 V core supply –0.3 1.2 V DD voltage 3.5 Result of exceeding a rating 40 m) 30 p p e ( s in tim 20 Tsohoen l ikaesl iah ocohda roafc pteerrimstiacn beengt icnhsi pto f aeixlucreee idn corneea soef sit sra oppidelrya atins g ratings. e ur Fail 10 0 Operating rating Measured characteristic K10 Sub-Family Data Sheet, Rev. 4 5/2012. 6 Freescale Semiconductor, Inc.

Terminology and guidelines 3.6 Relationship between ratings and operating requirements O perating rating (min.) O perating require m ent (min.) O perating require m ent (m ax.) O perating rating (m ax.) Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - No permanent failure - No permanent failure Expected permanent failure - Possible decreased life - Correct operation - Possible decreased life - Possible incorrect operation - Possible incorrect operation –∞ ∞ Operating (power on) H andling rating (min.) H andling rating (m ax.) Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure –∞ ∞ Handling (power off) 3.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 7

Terminology and guidelines 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit I Digital I/O weak 10 70 130 µA WP pullup/pulldown current 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 T 3500 J 150 °C A) 3000 μ ( 105 °C P O 2500 T S 25 °C _ D ID 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 V (V) DD 3.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit T Ambient temperature 25 °C A V 3.3 V supply voltage 3.3 V DD K10 Sub-Family Data Sheet, Rev. 4 5/2012. 8 Freescale Semiconductor, Inc.

Ratings 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes T Storage temperature –55 150 °C 1 STG T Solder temperature, lead-free — 260 °C 2 SDR 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.2 Moisture handling ratings Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.3 ESD handling ratings Symbol Description Min. Max. Unit Notes V Electrostatic discharge voltage, human body model -2000 +2000 V 1 HBM V Electrostatic discharge voltage, charged-device model -500 +500 V 2 CDM I Latch-up current at ambient temperature of 105°C -100 +100 mA LAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 4.4 Voltage and current operating ratings Symbol Description Min. Max. Unit V Digital supply voltage –0.3 3.8 V DD Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 9

General Symbol Description Min. Max. Unit I Digital supply current — 155 mA DD V Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 V + 0.3 V DIO DD VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V I Maximum current single pin limit (applies to all port pins) –25 25 mA D V Analog supply voltage V – 0.3 V + 0.3 V DDA DD DD V RTC battery supply voltage –0.3 3.8 V BAT 1. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 5 General 5.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Figure 1. Input signal measurement reference All digital I/O switching characteristics assume: 1. output pins • have C =30pF loads, L • are configured for fast slew rate (PORTx_PCRn[SRE]=0), and • are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins • have their passive filter disabled (PORTx_PCRn[PFE]=0) 5.2 Nonswitching electrical specifications K10 Sub-Family Data Sheet, Rev. 4 5/2012. 10 Freescale Semiconductor, Inc.

General 5.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit Notes V Supply voltage 1.71 3.6 V DD V Analog supply voltage 1.71 3.6 V DDA V – V V -to-V differential voltage –0.1 0.1 V DD DDA DD DDA V – V V -to-V differential voltage –0.1 0.1 V SS SSA SS SSA V RTC battery supply voltage 1.71 3.6 V BAT V Input high voltage IH • 2.7 V ≤ V ≤ 3.6 V 0.7 × V — V DD DD • 1.7 V ≤ V ≤ 2.7 V 0.75 × V — V DD DD V Input low voltage IL • 2.7 V ≤ V ≤ 3.6 V — 0.35 × V V DD DD • 1.7 V ≤ V ≤ 2.7 V — 0.3 × V V DD DD V Input hysteresis 0.06 × V — V HYS DD I I/O pin DC injection current — single pin 1 ICIO • V < V -0.3V (Negative current injection) mA IN SS -3 — • V > V +0.3V (Positive current injection) IN DD — +3 I Contiguous pin DC injection current —regional limit, ICcont includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins -25 — mA • Negative current injection — +25 • Positive current injection V V voltage required to retain RAM 1.2 — V RAM DD V V voltage required to retain the VBAT register file V — V RFVBAT BAT POR_VBAT 1. All analog pins are internally clamped to V and V through ESD protection diodes. If V is greater than V SS DD IN AIO_MIN (=V -0.3V) and V is less than V (=V +0.3V) is observed, then there is no need to provide current limiting SS IN AIO_MAX DD resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(V -V )/|I |. The positive injection current limiting resistor is AIO_MIN IN IC calcualted as R=(V -V )/|I |. Select the larger of these two calculated resistances. IN AIO_MAX IC 5.2.2 LVD and POR operating requirements Table 2. V supply LVD and POR operating requirements DD Symbol Description Min. Typ. Max. Unit Notes V Falling VDD POR detect voltage 0.8 1.1 1.5 V POR Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 11

General Table 2. V supply LVD and POR operating requirements (continued) DD Symbol Description Min. Typ. Max. Unit Notes V Falling low-voltage detect threshold — high 2.48 2.56 2.64 V LVDH range (LVDV=01) Low-voltage warning thresholds — high range 1 V • Level 1 falling (LVWV=00) 2.62 2.70 2.78 V LVW1H V • Level 2 falling (LVWV=01) 2.72 2.80 2.88 V LVW2H V • Level 3 falling (LVWV=10) 2.82 2.90 2.98 V LVW3H • Level 4 falling (LVWV=11) 2.92 3.00 3.08 V V LVW4H V Low-voltage inhibit reset/recover hysteresis — — ±80 — mV HYSH high range V Falling low-voltage detect threshold — low range 1.54 1.60 1.66 V LVDL (LVDV=00) Low-voltage warning thresholds — low range 1 V • Level 1 falling (LVWV=00) 1.74 1.80 1.86 V LVW1L V • Level 2 falling (LVWV=01) 1.84 1.90 1.96 V LVW2L V • Level 3 falling (LVWV=10) 1.94 2.00 2.06 V LVW3L • Level 4 falling (LVWV=11) 2.04 2.10 2.16 V V LVW4L V Low-voltage inhibit reset/recover hysteresis — — ±60 — mV HYSL low range V Bandgap voltage reference 0.97 1.00 1.03 V BG t Internal low power oscillator period — factory 900 1000 1100 μs LPO trimmed 1. Rising thresholds are falling threshold + hysteresis voltage Table 3. VBAT power operating requirements Symbol Description Min. Typ. Max. Unit Notes V Falling VBAT supply POR detect voltage 0.8 1.1 1.5 V POR_VBAT K10 Sub-Family Data Sheet, Rev. 4 5/2012. 12 Freescale Semiconductor, Inc.

General 5.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol Description Min. Max. Unit Notes V Output high voltage — high drive strength OH • 2.7 V ≤ V ≤ 3.6 V, I = - 9 mA V – 0.5 — V DD OH DD • 1.71 V ≤ V ≤ 2.7 V, I = -3 mA V – 0.5 — V DD OH DD Output high voltage — low drive strength • 2.7 V ≤ V ≤ 3.6 V, I = -2 mA V – 0.5 — V DD OH DD • 1.71 V ≤ V ≤ 2.7 V, I = -0.6 mA V – 0.5 — V DD OH DD I Output high current total for all ports — 100 mA OHT V Output low voltage — high drive strength OL • 2.7 V ≤ V ≤ 3.6 V, I = 9 mA — 0.5 V DD OL • 1.71 V ≤ V ≤ 2.7 V, I = 3 mA — 0.5 V DD OL Output low voltage — low drive strength • 2.7 V ≤ V ≤ 3.6 V, I = 2 mA — 0.5 V DD OL • 1.71 V ≤ V ≤ 2.7 V, I = 0.6 mA — 0.5 V DD OL I Output low current total for all ports — 100 mA OLT I Input leakage current (per pin) IN • @ full temperature range — 1.0 μA 1 • @ 25 °C — 0.1 μA I Hi-Z (off-state) leakage current (per pin) — 1 μA OZ I Total Hi-Z (off-state) leakage current (all input pins) — 4 μA OZ R Internal pullup resistors 22 50 kΩ 2 PU R Internal pulldown resistors 22 50 kΩ 3 PD 1. Tested by ganged leakage method 2. Measured at Vinput = V SS 3. Measured at Vinput = V DD 5.2.4 Power mode transition operating behaviors All specifications except t , and VLLSx→RUN recovery times in the following table POR assume this clock configuration: • CPU and system clocks = 50 MHz • Bus clock = 50 MHz • Flash clock = 25 MHz K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 13

General Table 5. Power mode transition operating behaviors Symbol Description Min. Max. Unit Notes t After a POR event, amount of time from the point V — 300 μs 1 POR DD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. — 130 μs • VLLS0 → RUN — 130 μs • VLLS1 → RUN — 70 μs • VLLS2 → RUN — 70 μs • VLLS3 → RUN — 6 μs • LLS → RUN — 5.2 μs • VLPS → RUN — 5.2 μs • STOP → RUN 1. Normal boot (FTFL_OPT[LPBOOT]=1) 5.2.5 Power consumption operating behaviors Table 6. Power consumption operating behaviors Symbol Description Min. Typ. Max. Unit Notes I Analog supply current — — See note mA 1 DDA I Run mode current — all peripheral clocks 2 DD_RUN disabled, code executing from flash — 13.7 15.1 mA • @ 1.8V — 13.9 15.3 mA • @ 3.0V I Run mode current — all peripheral clocks 3, 4 DD_RUN enabled, code executing from flash — 16.1 18.2 mA • @ 1.8V • @ 3.0V — 16.3 17.7 mA • @ 25°C — 16.7 18.4 mA • @ 125°C I Wait mode high frequency current at 3.0 V — all — 7.5 8.4 mA 2 DD_WAIT peripheral clocks disabled I Wait mode reduced frequency current at 3.0 V — 5.6 6.4 mA 5 DD_WAIT — all peripheral clocks disabled Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 14 Freescale Semiconductor, Inc.

General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes I Very-low-power run mode current at 3.0 V — all — 867 — μA 6 DD_VLPR peripheral clocks disabled I Very-low-power run mode current at 3.0 V — all — 1.1 — mA 7 DD_VLPR peripheral clocks enabled I Very-low-power wait mode current at 3.0 V — 509 — μA 8 DD_VLPW I Stop mode current at 3.0 V DD_STOP • @ –40 to 25°C — 310 426 μA • @ 70°C — 384 458 μA • @ 105°C — 629 1100 μA I Very-low-power stop mode current at 3.0 V DD_VLPS • @ –40 to 25°C — 3.5 22.6 μA • @ 70°C — 20.7 52.9 μA • @ 105°C — 85 220 μA I Low leakage stop mode current at 3.0 V DD_LLS • @ –40 to 25°C — 2.1 3.7 μA • @ 70°C — 7.7 43.1 μA • @ 105°C — 32.2 68 μA I Very low-leakage stop mode 3 current at 3.0 V DD_VLLS3 • @ –40 to 25°C — 1.5 2.9 μA • @ 70°C — 4.8 22.5 μA • @ 105°C — 20 37.8 μA I Very low-leakage stop mode 2 current at 3.0 V DD_VLLS2 • @ –40 to 25°C — 1.4 2.8 μA • @ 70°C — 4.1 19.2 μA • @ 105°C — 17.3 32.4 μA I Very low-leakage stop mode 1 current at 3.0 V DD_VLLS1 • @ –40 to 25°C — 0.678 1.3 μA • @ 70°C — 2.8 13.6 μA • @ 105°C — 13.6 24.5 μA I Very low-leakage stop mode 0 current at 3.0 V DD_VLLS0 with POR detect circuit enabled — 0.367 1.0 μA • @ –40 to 25°C — 2.4 13.3 μA • @ 70°C — 13.2 24.1 μA • @ 105°C Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 15

General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes I Very low-leakage stop mode 0 current at 3.0 V DD_VLLS0 with POR detect circuit disabled — 0.176 0.859 μA • @ –40 to 25°C — 2.2 13.1 μA • @ 70°C — 13 23.9 μA • @ 105°C I Average current with RTC and 32kHz disabled at DD_VBAT 3.0 V • @ –40 to 25°C — 0.19 0.22 μA • @ 70°C — 0.49 0.64 μA • @ 105°C — 2.2 3.2 μA I Average current when CPU is not accessing 9 DD_VBAT RTC registers • @ 1.8V • @ –40 to 25°C — 0.57 0.67 μA • @ 70°C — 0.90 1.2 μA • @ 105°C — 2.4 3.5 μA • @ 3.0V • @ –40 to 25°C — 0.67 0.94 μA • @ 70°C — 1.0 1.4 μA • @ 105°C — 2.7 3.9 μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 50MHz core and system clock, 25MHz bus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral clocks disabled. 3. 50MHz core and system clock, 25MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, and peripherals are in active operation. 4. Max values are measured with CPU executing DSP instructions 5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz flash clock. MCG configured for FEI mode. 6. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 7. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 9. Includes 32kHz oscillator current and RTC operation. 5.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: • MCG in FBE mode • No GPIOs toggled • Code execution from flash with cache enabled • For the ALLOFF curve, all peripheral clocks are disabled except FTFL K10 Sub-Family Data Sheet, Rev. 4 5/2012. 16 Freescale Semiconductor, Inc.

General Figure 2. Run mode supply current vs. core frequency K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 17

General Figure 3. VLPR mode supply current vs. core frequency 5.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors for 64LQFP Symbol Description Frequency Typ. Unit Notes band (MHz) V Radiated emissions voltage, band 1 0.15–50 19 dBμV 1 , 2 RE1 V Radiated emissions voltage, band 2 50–150 21 dBμV RE2 V Radiated emissions voltage, band 3 150–500 19 dBμV RE3 V Radiated emissions voltage, band 4 500–1000 11 dBμV RE4 V IEC level 0.15–1000 L — 2, 3 RE_IEC 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported K10 Sub-Family Data Sheet, Rev. 4 5/2012. 18 Freescale Semiconductor, Inc.

General emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. V = 3.3 V, T = 25 °C, f = 12 MHz (crystal), f = 48 MHz, f = 48MHz DD A OSC SYS BUS 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 5.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to http://www.freescale.com. 2. Perform a keyword search for “EMC design.” 5.2.8 Capacitance attributes Table 8. Capacitance attributes Symbol Description Min. Max. Unit C Input capacitance: analog pins — 7 pF IN_A C Input capacitance: digital pins — 7 pF IN_D 5.3 Switching specifications 5.3.1 Device clock specifications Table 9. Device clock specifications Symbol Description Min. Max. Unit Notes Normal run mode f System and core clock — 50 MHz SYS f Bus clock — 50 MHz BUS f Flash clock — 25 MHz FLASH f LPTMR clock — 25 MHz LPTMR VLPR mode1 f System and core clock — 4 MHz SYS f Bus clock — 4 MHz BUS f Flash clock — 1 MHz FLASH f External reference clock — 16 MHz ERCLK Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 19

General Table 9. Device clock specifications (continued) Symbol Description Min. Max. Unit Notes f LPTMR clock — 25 MHz LPTMR_pin f LPTMR external reference clock — 16 MHz LPTMR_ERCLK f I2S master clock — 12.5 MHz I2S_MCLK f I2S bit clock — 4 MHz I2S_BCLK 1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. 5.3.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, UART, CMT, and I2C signals. Table 10. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter 1.5 — Bus clock 1, 2 disabled) — Synchronous path cycles GPIO pin interrupt pulse width (digital glitch filter 100 — ns 3 disabled, analog filter enabled) — Asynchronous path GPIO pin interrupt pulse width (digital glitch filter 50 — ns 3 disabled, analog filter disabled) — Asynchronous path External reset pulse width (digital glitch filter disabled) 100 — ns 3 Mode select (EZP_CS) hold time after reset 2 — Bus clock deassertion cycles Port rise and fall time (high drive strength) 4 • Slew disabled • 1.71 ≤ V ≤ 2.7V — 13 ns DD • 2.7 ≤ V ≤ 3.6V — ns DD • Slew enabled 7 • 1.71 ≤ V ≤ 2.7V — ns DD — 36 ns • 2.7 ≤ V ≤ 3.6V DD 24 Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 20 Freescale Semiconductor, Inc.

General Table 10. General switching specifications (continued) Symbol Description Min. Max. Unit Notes Port rise and fall time (low drive strength) 5 • Slew disabled • 1.71 ≤ V ≤ 2.7V — 12 ns DD • 2.7 ≤ V ≤ 3.6V — 6 ns DD • Slew enabled • 1.71 ≤ V ≤ 2.7V — 36 ns DD — 24 ns • 2.7 ≤ V ≤ 3.6V DD 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75pF load 5. 15pF load 5.4 Thermal specifications 5.4.1 Thermal operating requirements Table 11. Thermal operating requirements Symbol Description Min. Max. Unit T Die junction temperature –40 125 °C J T Ambient temperature –40 105 °C A 5.4.2 Thermal attributes Board type Symbol Description 32 QFN Unit Notes Single-layer (1s) R Thermal 94 °C/W 1, 2 θJA resistance, junction to ambient (natural convection) Four-layer (2s2p) R Thermal 32 °C/W 1, 3 θJA resistance, junction to ambient (natural convection) Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 21

Peripheral operating requirements and behaviors Board type Symbol Description 32 QFN Unit Notes Single-layer (1s) R Thermal 78 °C/W 1,3 θJMA resistance, junction to ambient (200 ft./ min. air speed) Four-layer (2s2p) R Thermal 27 °C/W , θJMA resistance, junction to ambient (200 ft./ min. air speed) — R Thermal 12 °C/W 5 θJB resistance, junction to board — R Thermal 1.5 °C/W 6 θJC resistance, junction to case — Ψ Thermal 6 °C/W 7 JT characterization parameter, junction to package top outside center (natural convection) 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air) with the single layer board horizontal. For the LQFP, the board meets the JESD51-3 specification. For the MAPBGA, the board meets the JESD51-9 specification. 3. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental Conditions—Forced Convection (Moving Air) with the board horizontal. 5. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package. 6. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 7. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). 6 Peripheral operating requirements and behaviors 6.1 Core modules 6.1.1 JTAG electricals Table 12. JTAG voltage range electricals Symbol Description Min. Max. Unit Operating voltage 2.7 5.5 V Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 22 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 12. JTAG voltage range electricals (continued) Symbol Description Min. Max. Unit J1 TCLK frequency of operation MHz • JTAG — 10 • CJTAG — 5 J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width • JTAG 100 — ns • CJTAG 200 — ns ns J4 TCLK rise and fall times — 1 ns J5 TMS input data setup time to TCLK rise ns 53 — • JTAG • CJTAG 112 — J6 TDI input data setup time to TCLK rise 8 — ns J7 TMS input data hold time after TCLK rise ns 3.4 — • JTAG • CJTAG 3.4 — J8 TDI input data hold time after TCLK rise 3.4 — ns J9 TCLK low to TMS data valid ns — 48 • JTAG • CJTAG — 85 J10 TCLK low to TDO data valid — 48 ns J11 Output data hold/invalid time after clock edge1 — 3 ns 1. They are common for JTAG and CJTAG. Input transition = 1 ns and Output load = 50pf J2 J3 J3 TCLK (input) J4 J4 Figure 4. Test clock input timing K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 23

Peripheral operating requirements and behaviors TCLK J5 J6 Data inputs Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 5. Boundary scan (JTAG) timing TCLK J9 J10 TDI/TMS Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 6. Test Access Port timing K10 Sub-Family Data Sheet, Rev. 4 5/2012. 24 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors TCLK J14 J13 TRST Figure 7. TRST timing 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules 6.3.1 MCG specifications Table 13. MCG specifications Symbol Description Min. Typ. Max. Unit Notes f Internal reference frequency (slow clock) — — 32.768 — kHz ints_ft factory trimmed at nominal VDD and 25 °C f Internal reference frequency (slow clock) — user 31.25 — 39.0625 kHz ints_t trimmed Δ Resolution of trimmed average DCO output — ± 0.3 ± 0.6 %f 1 fdco_res_t dco frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM Δf Total deviation of trimmed average DCO output — +0.5/-0.7 ± 3 %f 1 dco_t dco frequency over voltage and temperature Δf Total deviation of trimmed average DCO output — ± 0.3 — %f 1 dco_t dco frequency over fixed voltage and temperature range of 0–70°C f Internal reference frequency (fast clock) — — 4 — MHz intf_ft factory trimmed at nominal VDD and 25°C f Internal reference frequency (fast clock) — user 3 — 5 MHz intf_t trimmed at nominal VDD and 25 °C f Loss of external clock minimum frequency — (3/5) x — — kHz loc_low RANGE = 00 f ints_t f Loss of external clock minimum frequency — (16/5) x — — kHz loc_high RANGE = 01, 10, or 11 f ints_t FLL Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 25

Peripheral operating requirements and behaviors Table 13. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes f FLL reference frequency range 31.25 — 39.0625 kHz fll_ref f DCO output Low range (DRS=00) 20 20.97 25 MHz 2, 3 dco frequency range 640 × f fll_ref Mid range (DRS=01) 40 41.94 50 MHz 1280 × f fll_ref Mid-high range (DRS=10) 60 62.91 75 MHz 1920 × f fll_ref High range (DRS=11) 80 83.89 100 MHz 2560 × f fll_ref f DCO output Low range (DRS=00) — 23.99 — MHz 4, 5 dco_t_DMX3 frequency 2 732 × f fll_ref Mid range (DRS=01) — 47.97 — MHz 1464 × f fll_ref Mid-high range (DRS=10) — 71.99 — MHz 2197 × f fll_ref High range (DRS=11) — 95.98 — MHz 2929 × f fll_ref J FLL period jitter ps cyc_fll — 180 — • f = 48 MHz VCO — 150 — • f = 98 MHz VCO t FLL target frequency acquisition time — — 1 ms 6 fll_acquire PLL f VCO operating frequency 48.0 — 100 MHz vco I PLL operating current 7 pll — 1060 — µA • PLL @ 96 MHz (f = 8 MHz, f = osc_hi_1 pll_ref 2 MHz, VDIV multiplier = 48) I PLL operating current 7 pll — 600 — µA • PLL @ 48 MHz (f = 8 MHz, f = osc_hi_1 pll_ref 2 MHz, VDIV multiplier = 24) f PLL reference frequency range 2.0 — 4.0 MHz pll_ref J PLL period jitter (RMS) 8 cyc_pll • f = 48 MHz — 120 — ps vco • f = 100 MHz — 50 — ps vco Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 26 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 13. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes J PLL accumulated jitter over 1µs (RMS) 8 acc_pll • f = 48 MHz — 1350 — ps vco • f = 100 MHz — 600 — ps vco D Lock entry frequency tolerance ± 1.49 — ± 2.98 % lock D Lock exit frequency tolerance ± 4.47 — ± 5.97 % unl tpll_lock Lock detector detection time — — 150 × 10-6 s 9 + 1075(1/ f ) pll_ref 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δf ) over voltage and temperature should be considered. dco_t 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. Excludes any oscillator currents that are also consuming power while PLL is in operation. 8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 6.3.2 Oscillator electrical specifications This section provides the electrical characteristics of the module. 6.3.2.1 Oscillator DC electrical specifications Table 14. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit Notes V Supply voltage 1.71 — 3.6 V DD I Supply current — low-power mode (HGO=0) 1 DDOSC • 32 kHz — 500 — nA • 4 MHz — 200 — μA • 8 MHz (RANGE=01) — 300 — μA • 16 MHz — 950 — μA • 24 MHz — 1.2 — mA • 32 MHz — 1.5 — mA Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 27

Peripheral operating requirements and behaviors Table 14. Oscillator DC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit Notes I Supply current — high gain mode (HGO=1) 1 DDOSC • 32 kHz — 25 — μA • 4 MHz — 400 — μA • 8 MHz (RANGE=01) — 500 — μA • 16 MHz — 2.5 — mA • 24 MHz — 3 — mA • 32 MHz — 4 — mA C EXTAL load capacitance — — — 2, 3 x C XTAL load capacitance — — — 2, 3 y R Feedback resistor — low-frequency, low-power — — — MΩ 2, 4 F mode (HGO=0) Feedback resistor — low-frequency, high-gain — 10 — MΩ mode (HGO=1) Feedback resistor — high-frequency, low-power — — — MΩ mode (HGO=0) Feedback resistor — high-frequency, high-gain — 1 — MΩ mode (HGO=1) R Series resistor — low-frequency, low-power — — — kΩ S mode (HGO=0) Series resistor — low-frequency, high-gain mode — 200 — kΩ (HGO=1) Series resistor — high-frequency, low-power — — — kΩ mode (HGO=0) Series resistor — high-frequency, high-gain mode (HGO=1) — 0 — kΩ V 5 Peak-to-peak amplitude of oscillation (oscillator — 0.6 — V pp mode) — low-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator — V — V DD mode) — low-frequency, high-gain mode (HGO=1) Peak-to-peak amplitude of oscillation (oscillator — 0.6 — V mode) — high-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator — V — V DD mode) — high-frequency, high-gain mode (HGO=1) 1. V =3.3 V, Temperature =25 °C DD 2. See crystal or resonator manufacturer's recommendation 3. C ,C can be provided by using either the integrated capacitors or by using external components. x y 4. When low power mode is selected, R is integrated and must not be attached externally. F K10 Sub-Family Data Sheet, Rev. 4 5/2012. 28 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 Oscillator frequency specifications Table 15. Oscillator frequency specifications Symbol Description Min. Typ. Max. Unit Notes f Oscillator crystal or resonator frequency — low 32 — 40 kHz osc_lo frequency mode (MCG_C2[RANGE]=00) f Oscillator crystal or resonator frequency — high 3 — 8 MHz osc_hi_1 frequency mode (low range) (MCG_C2[RANGE]=01) f Oscillator crystal or resonator frequency — high 8 — 32 MHz osc_hi_2 frequency mode (high range) (MCG_C2[RANGE]=1x) f Input clock frequency (external clock mode) — — 50 MHz 1, 2 ec_extal t Input clock duty cycle (external clock mode) 40 50 60 % dc_extal t Crystal startup time — 32 kHz low-frequency, — 750 — ms 3, 4 cst low-power mode (HGO=0) Crystal startup time — 32 kHz low-frequency, — 250 — ms high-gain mode (HGO=1) Crystal startup time — 8 MHz high-frequency — 0.6 — ms (MCG_C2[RANGE]=01), low-power mode (HGO=0) Crystal startup time — 8 MHz high-frequency — 1 — ms (MCG_C2[RANGE]=01), high-gain mode (HGO=1) 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 6.3.3 32 kHz Oscillator Electrical Characteristics This section describes the module electrical characteristics. 6.3.3.1 32 kHz oscillator DC electrical specifications Table 16. 32kHz oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit V Supply voltage 1.71 — 3.6 V BAT R Internal feedback resistor — 100 — MΩ F Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 29

Peripheral operating requirements and behaviors Table 16. 32kHz oscillator DC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit C Parasitical capacitance of EXTAL32 and XTAL32 — 5 7 pF para V 1 Peak-to-peak amplitude of oscillation — 0.6 — V pp 1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.3.2 32kHz oscillator frequency specifications Table 17. 32kHz oscillator frequency specifications Symbol Description Min. Typ. Max. Unit Notes fosc_lo Oscillator crystal — 32.768 — kHz tstart Crystal start-up time — 1000 — ms 1 fec_extal32 Externally provided input clock frequency — 32.768 — kHz 2 vec_extal32 Externally provided input clock amplitude 700 — VBAT mV 2, 3 1. Proper PC board layout procedures must be followed to achieve specifications. 2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The oscillator remains enabled and XTAL32 must be left unconnected. 3. The parameter specified is a peak-to-peak value and V and V specifications do not apply. The voltage of the applied IH IL clock must be within the range of V to V . SS BAT 6.4 Memories and memory interfaces 6.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 6.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 18. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit Notes t Longword Program high-voltage time — 7.5 18 μs hvpgm4 t Sector Erase high-voltage time — 13 113 ms 1 hversscr t Erase Block high-voltage time for 32 KB — 52 452 ms 1 hversblk32k t Erase Block high-voltage time for 128 KB — 52 452 ms 1 hversblk128k 1. Maximum time based on expectations at cycling end-of-life. K10 Sub-Family Data Sheet, Rev. 4 5/2012. 30 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 6.4.1.2 Flash timing specifications — commands Table 19. Flash command timing specifications Symbol Description Min. Typ. Max. Unit Notes Read 1s Block execution time t • 32 KB data flash — — 0.5 ms rd1blk32k t • 128 KB program flash — — 1.7 ms rd1blk128k t Read 1s Section execution time (flash sector) — — 60 μs 1 rd1sec1k t Program Check execution time — — 45 μs 1 pgmchk t Read Resource execution time — — 30 μs 1 rdrsrc t Program Longword execution time — 65 145 μs pgm4 Erase Flash Block execution time 2 t • 32 KB data flash — 55 465 ms ersblk32k t • 128 KB program flash — 61 495 ms ersblk128k t Erase Flash Sector execution time — 14 114 ms 2 ersscr Program Section execution time t • 512 B flash — 4.7 — ms pgmsec512 t • 1 KB flash — 9.3 — ms pgmsec1k t Read 1s All Blocks execution time — — 1.8 ms rd1all t Read Once execution time — — 25 μs 1 rdonce t Program Once execution time — 65 — μs pgmonce t Erase All Blocks execution time — 115 1000 ms 2 ersall t Verify Backdoor Access Key execution time — — 30 μs 1 vfykey Program Partition for EEPROM execution time t • 32 KB FlexNVM — 70 — ms pgmpart32k Set FlexRAM Function execution time: t • Control Code 0xFF — 50 — μs setramff t • 8 KB EEPROM backup — 0.3 0.5 ms setram8k t • 32 KB EEPROM backup — 0.7 1.0 ms setram32k Byte-write to FlexRAM for EEPROM operation t Byte-write to erased FlexRAM location execution — 175 260 μs 3 eewr8bers time Byte-write to FlexRAM execution time: t • 8 KB EEPROM backup — 340 1700 μs eewr8b8k t • 16 KB EEPROM backup — 385 1800 μs eewr8b16k t • 32 KB EEPROM backup — 475 2000 μs eewr8b32k Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 31

Peripheral operating requirements and behaviors Table 19. Flash command timing specifications (continued) Symbol Description Min. Typ. Max. Unit Notes Word-write to FlexRAM for EEPROM operation t Word-write to erased FlexRAM location — 175 260 μs eewr16bers execution time Word-write to FlexRAM execution time: t • 8 KB EEPROM backup — 340 1700 μs eewr16b8k t • 16 KB EEPROM backup — 385 1800 μs eewr16b16k t • 32 KB EEPROM backup — 475 2000 μs eewr16b32k Longword-write to FlexRAM for EEPROM operation t Longword-write to erased FlexRAM location — 360 540 μs eewr32bers execution time Longword-write to FlexRAM execution time: t • 8 KB EEPROM backup — 545 1950 μs eewr32b8k t • 16 KB EEPROM backup — 630 2050 μs eewr32b16k t • 32 KB EEPROM backup — 810 2250 μs eewr32b32k 1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased. 6.4.1.3 Flash high voltage current behaviors Table 20. Flash high voltage current behaviors Symbol Description Min. Typ. Max. Unit I Average current adder during high voltage — 2.5 6.0 mA DD_PGM flash programming operation I Average current adder during high voltage — 1.5 4.0 mA DD_ERS flash erase operation 6.4.1.4 Reliability specifications Table 21. NVM reliability specifications Symbol Description Min. Typ.1 Max. Unit Notes Program Flash t Data retention after up to 10 K cycles 5 50 — years nvmretp10k t Data retention after up to 1 K cycles 20 100 — years nvmretp1k n Cycling endurance 10 K 50 K — cycles 2 nvmcycp Data Flash t Data retention after up to 10 K cycles 5 50 — years nvmretd10k Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 32 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 21. NVM reliability specifications (continued) Symbol Description Min. Typ.1 Max. Unit Notes t Data retention after up to 1 K cycles 20 100 — years nvmretd1k n Cycling endurance 10 K 50 K — cycles 2 nvmcycd FlexRAM as EEPROM t Data retention up to 100% of write endurance 5 50 — years nvmretee100 t Data retention up to 10% of write endurance 20 100 — years nvmretee10 Write endurance 3 n • EEPROM backup to FlexRAM ratio = 16 35 K 175 K — writes nvmwree16 n • EEPROM backup to FlexRAM ratio = 128 315 K 1.6 M — writes nvmwree128 n • EEPROM backup to FlexRAM ratio = 512 1.27 M 6.4 M — writes nvmwree512 • EEPROM backup to FlexRAM ratio = 4096 10 M 50 M — writes n nvmwree4k • EEPROM backup to FlexRAM ratio = 8192 20 M 100 M — writes n nvmwree8k 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40°C ≤ T ≤ 125°C. j 3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup. Minimum and typical values assume all byte-writes to FlexRAM. 6.4.1.5 Write endurance to FlexRAM for EEPROM When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the flash memory module to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. EEPROM – 2 × EEESIZE Writes_FlexRAM = × Write_efficiency × n nvmcycd EEESIZE where • Writes_FlexRAM — minimum number of writes to each FlexRAM location K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 33

Peripheral operating requirements and behaviors • EEPROM — allocated FlexNVM based on DEPART; entered with the Program Partition command • EEESIZE — allocated FlexRAM based on DEPART; entered with the Program Partition command • Write_efficiency — • 0.25 for 8-bit writes to FlexRAM • 0.50 for 16-bit or 32-bit writes to FlexRAM • n — data flash cycling endurance (the following graph assumes 10,000 nvmcycd cycles) Figure 8. EEPROM backup writes to FlexRAM 6.4.2 EzPort Switching Specifications Table 22. EzPort switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 34 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 22. EzPort switching specifications (continued) Num Description Min. Max. Unit EP1 EZP_CK frequency of operation (all commands except — f /2 MHz SYS READ) EP1a EZP_CK frequency of operation (READ command) — f /8 MHz SYS EP2 EZP_CS negation to next EZP_CS assertion 2 x t — ns EZP_CK EP3 EZP_CS input valid to EZP_CK high (setup) 5 — ns EP4 EZP_CK high to EZP_CS input invalid (hold) 5 — ns EP5 EZP_D input valid to EZP_CK high (setup) 2 — ns EP6 EZP_CK high to EZP_D input invalid (hold) 5 — ns EP7 EZP_CK low to EZP_Q output valid — 17 ns EP8 EZP_CK low to EZP_Q output invalid (hold) 0 — ns EP9 EZP_CS negation to EZP_Q tri-state — 12 ns EZP_CK EP3 EP4 EP2 EZP_CS EP9 EP8 EP7 EZP_Q (output) EP5 EP6 EZP_D (input) Figure 9. EzPort Timing Diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 35

Peripheral operating requirements and behaviors 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 23 and Table 24 are achievable on the differential pins ADCx_DP0, ADCx_DM0. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit ADC operating conditions Table 23. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes V Supply voltage Absolute 1.71 — 3.6 V DDA ΔV Supply voltage Delta to V (V - -100 0 +100 mV 2 DDA DD DD V ) DDA ΔV Ground voltage Delta to V (V - -100 0 +100 mV 2 SSA SS SS V ) SSA V ADC reference 1.13 V V V REFH DDA DDA voltage high V Reference V V V V REFL SSA SSA SSA voltage low V Input voltage V — V V ADIN REFL REFH C Input • 16 bit modes — 8 10 pF ADIN capacitance • 8/10/12 bit — 4 5 modes R Input resistance — 2 5 kΩ ADIN R Analog source 12 bit modes 3 AS resistance f < 4MHz — — 5 kΩ ADCK f ADC conversion ≤ bit modes 4 ADCK clock frequency 1.0 — 18.0 MHz f ADC conversion 16 bit modes 4 ADCK clock frequency 2.0 — 12.0 MHz C ADC conversion ≤ bit modes 5 rate rate No ADC hardware 20.000 — 818.330 Ksps averaging Continuous conversions enabled, subsequent conversion time Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 36 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 23. 16-bit ADC operating conditions (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes C ADC conversion 16 bit modes 5 rate rate No ADC hardware 37.037 — 461.467 Ksps averaging Continuous conversions enabled, subsequent conversion time 1. Typical values assume V = 3.0 V, Temp = 25°C, f = 1.0 MHz unless otherwise stated. Typical values are for DDA ADCK reference only and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the best results. The results in this datasheet were derived from a system which has <8 Ω analog source resistance. The R / AS C time constant should be kept to <1ns. AS 4. To use the maximum ADC conversion clock frequency, the ADHSC bit should be set and the ADLPC bit should be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool: http://cache.freescale.com/ files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1 SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED Pad Z CHANNEL SELECT AS leakage due to CIRCUIT ADC SAR R input R ENGINE AS protection ADIN V ADIN C V AS AS R ADIN IINNPPUUTT PPIINN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN Figure 10. ADC input impedance equivalency diagram 6.6.1.2 16-bit ADC electrical characteristics Table 24. 16-bit ADC characteristics (V = V , V = V ) REFH DDA REFL SSA Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes I Supply current 0.215 — 1.7 mA 3 DDA_ADC Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 37

Peripheral operating requirements and behaviors Table 24. 16-bit ADC characteristics (V = V , V = V ) (continued) REFH DDA REFL SSA Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes ADC • ADLPC=1, ADHSC=0 1.2 2.4 3.9 MHz tADACK = 1/ asynchronous f clock source • ADLPC=1, ADHSC=1 3.0 4.0 7.3 MHz ADACK f ADACK • ADLPC=0, ADHSC=0 2.4 5.2 6.1 MHz • ADLPC=0, ADHSC=1 4.4 6.2 9.5 MHz Sample Time See Reference Manual chapter for sample times TUE Total unadjusted • 12 bit modes — ±4 ±6.8 LSB4 5 error • <12 bit modes — ±1.4 ±2.1 DNL Differential non- • 12 bit modes — ±0.7 -1.1 to LSB4 5 linearity +1.9 -0.3 to 0.5 • <12 bit modes — ±0.2 INL Integral non- • 12 bit modes — ±1.0 -2.7 to LSB4 5 linearity +1.9 -0.7 to • <12 bit modes — ±0.5 +0.5 EFS Full-scale error • 12 bit modes — -4 -5.4 LSB4 VADIN = V • <12 bit modes — -1.4 -1.8 DDA 5 EQ Quantization • 16 bit modes — -1 to 0 — LSB4 error • bit modes — — ±0.5 ENOB Effective number 16 bit differential mode 6 of bits • Avg=32 12.8 14.5 — bits • Avg=4 11.9 13.8 — bits 16 bit single-ended mode • Avg=32 12.2 13.9 — bits • Avg=4 11.4 13.1 — bits Signal-to-noise See ENOB SINAD 6.02 × ENOB + 1.76 dB plus distortion THD Total harmonic 16 bit differential mode 7 distortion • Avg=32 — –94 — dB 16 bit single-ended mode — -85 — dB • Avg=32 Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 38 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 24. 16-bit ADC characteristics (V = V , V = V ) (continued) REFH DDA REFL SSA Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes SFDR Spurious free 16 bit differential mode 7 dynamic range • Avg=32 82 95 — dB 16 bit single-ended mode 78 90 — dB • Avg=32 E Input leakage I × R mV I = IL In AS In error leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor –40°C to 105°C — 1.715 — mV/°C slope V Temp sensor 25°C — 719 — mV TEMP25 voltage 1. All accuracy numbers assume the ADC is calibrated with V = V REFH DDA 2. Typical values assume V = 3.0 V, Temp = 25°C, f = 2.0 MHz unless otherwise stated. Typical values are for DDA ADCK reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock speed. 4. 1 LSB = (V - V )/2N REFH REFL 5. ADC conversion clock <16MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock <12MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock <12MHz. K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 39

Peripheral operating requirements and behaviors Figure 11. Typical ENOB vs. ADC_CLK for 16-bit differential mode Figure 12. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode K10 Sub-Family Data Sheet, Rev. 4 5/2012. 40 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 6.6.2 CMP and 6-bit DAC electrical specifications Table 25. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit V Supply voltage 1.71 — 3.6 V DD I Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA DDHS I Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA DDLS V Analog input voltage V – 0.3 — V V AIN SS DD V Analog input offset voltage — — 20 mV AIO VH Analog comparator hysteresis1 • CR0[HYSTCTR] = 00 — 5 — mV • CR0[HYSTCTR] = 01 — 10 — mV • CR0[HYSTCTR] = 10 — 20 — mV • CR0[HYSTCTR] = 11 — 30 — mV V Output high V – 0.5 — — V CMPOh DD V Output low — — 0.5 V CMPOl t Propagation delay, high-speed mode (EN=1, 20 50 200 ns DHS PMODE=1) t Propagation delay, low-speed mode (EN=1, 80 250 600 ns DLS PMODE=0) Analog comparator initialization delay2 — — 40 μs I 6-bit DAC current adder (enabled) — 7 — μA DAC6b INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to V -0.6V. DD 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = V /64 reference K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 41

Peripheral operating requirements and behaviors 0.08 0.07 0.06 0.05 HYSTCTR Setting V) s ( eri 00 er 0.04 yst 01 H P 1100 M C 0.03 11 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 13. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K10 Sub-Family Data Sheet, Rev. 4 5/2012. 42 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors 0.18 0.16 0.14 0.12 HYSTCTR Setting V) s ( 0.1 eri 00 er yst 01 H P P 00.0088 1100 M C 11 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 14. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) 6.7 Timers See General switching specifications. 6.8 Communication interfaces K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 43

Peripheral operating requirements and behaviors 6.8.1 DSPI switching specifications (limited voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 26. Master mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Notes Operating voltage 2.7 3.6 V Frequency of operation — 25 MHz DS1 DSPI_SCK output cycle time 2 x t — ns BUS DS2 DSPI_SCK output high/low time (t /2) − 2 (t /2) + 2 ns SCK SCK DS3 DSPI_PCSn valid to DSPI_SCK delay (t x 2) − — ns 1 BUS 2 DS4 DSPI_SCK to DSPI_PCSn invalid delay (t x 2) − — ns 2 BUS 2 DS5 DSPI_SCK to DSPI_SOUT valid — 8 ns DS6 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS7 DSPI_SIN to DSPI_SCK input setup 14 — ns DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DS2 DS1 DS4 DSPI_SCK DS8 (CPOL=0) DS7 DSPI_SIN First data Data Last data DS5 DS6 DSPI_SOUT First data Data Last data Figure 15. DSPI classic SPI timing — master mode Table 27. Slave mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation 12.5 MHz Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 44 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 27. Slave mode DSPI timing (limited voltage range) (continued) Num Description Min. Max. Unit DS9 DSPI_SCK input cycle time 4 x t — ns BUS DS10 DSPI_SCK input high/low time (t /2) − 2 (t /2) + 2 ns SCK SCK DS11 DSPI_SCK to DSPI_SOUT valid — 20 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS13 DSPI_SIN to DSPI_SCK input setup 2 — ns DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns DS15 DSPI_SS active to DSPI_SOUT driven — 14 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven — 14 ns DSPI_SS DS10 DS9 DSPI_SCK (CPOL=0) DS15 DS12 DS11 DS16 DSPI_SOUT First data Data Last data DS13 DS14 DSPI_SIN First data Data Last data Figure 16. DSPI classic SPI timing — slave mode 6.8.2 DSPI switching specifications (full voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 28. Master mode DSPI timing (full voltage range) Num Description Min. Max. Unit Notes Operating voltage 1.71 3.6 V 1 Frequency of operation — 12.5 MHz DS1 DSPI_SCK output cycle time 4 x t — ns BUS DS2 DSPI_SCK output high/low time (t /2) - 4 (t + 4 ns SCK SCK/2) Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 45

Peripheral operating requirements and behaviors Table 28. Master mode DSPI timing (full voltage range) (continued) Num Description Min. Max. Unit Notes DS3 DSPI_PCSn valid to DSPI_SCK delay (t x 2) − — ns 2 BUS 4 DS4 DSPI_SCK to DSPI_PCSn invalid delay (t x 2) − — ns 3 BUS 4 DS5 DSPI_SCK to DSPI_SOUT valid — 8.5 ns DS6 DSPI_SCK to DSPI_SOUT invalid -1.2 — ns DS7 DSPI_SIN to DSPI_SCK input setup 19.1 — ns DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns 1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DS2 DS1 DS4 DSPI_SCK DS8 (CPOL=0) DS7 DSPI_SIN First data Data Last data DS5 DS6 DSPI_SOUT First data Data Last data Figure 17. DSPI classic SPI timing — master mode Table 29. Slave mode DSPI timing (full voltage range) Num Description Min. Max. Unit Operating voltage 1.71 3.6 V Frequency of operation — 6.25 MHz DS9 DSPI_SCK input cycle time 8 x t — ns BUS DS10 DSPI_SCK input high/low time (t /2) - 4 (t + 4 ns SCK SCK/2) DS11 DSPI_SCK to DSPI_SOUT valid — 24 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS13 DSPI_SIN to DSPI_SCK input setup 3.2 — ns DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns DS15 DSPI_SS active to DSPI_SOUT driven — 19 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven — 19 ns K10 Sub-Family Data Sheet, Rev. 4 5/2012. 46 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors DSPI_SS DS10 DS9 DSPI_SCK (CPOL=0) DS15 DS12 DS11 DS16 DSPI_SOUT First data Data Last data DS13 DS14 DSPI_SIN First data Data Last data Figure 18. DSPI classic SPI timing — slave mode 6.8.3 I2C switching specifications See General switching specifications. 6.8.4 UART switching specifications See General switching specifications. 6.8.5 I2S/SAI Switching Specifications This section provides the AC timing for the I2S/SAI module in master mode (clocks are driven) and slave mode (clocks are input). All timing is given for noninverted serial clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the frame sync (FS) signal shown in the following figures. K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 47

Peripheral operating requirements and behaviors 6.8.5.1 Normal Run, Wait and Stop mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes. Table 30. I2S/SAI master mode timing Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 40 — ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 — ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ — 15 ns I2S_RX_FS output valid S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ 0 — ns I2S_RX_FS output invalid S7 I2S_TX_BCLK to I2S_TXD valid — 15 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns S9 I2S_RXD/I2S_RX_FS input setup before 25 — ns I2S_RX_BCLK S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ S4 I2S_RX_BCLK (output) S4 S5 S6 I2S_TX_FS/ I2S_RX_FS (output) S9 S10 I2S_TX_FS/ I2S_RX_FS (input) S7 S7 S8 S8 I2S_TXD S9 S10 I2S_RXD Figure 19. I2S/SAI timing — master modes K10 Sub-Family Data Sheet, Rev. 4 5/2012. 48 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 31. I2S/SAI slave mode timing Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 — ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% MCLK period (input) S13 I2S_TX_FS/I2S_RX_FS input setup before 10 — ns I2S_TX_BCLK/I2S_RX_BCLK S14 I2S_TX_FS/I2S_RX_FS input hold after 2 — ns I2S_TX_BCLK/I2S_RX_BCLK S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 29 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_RX_BCLK 10 — ns S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 — 21 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear S11 S12 I2S_TX_BCLK/ S12 I2S_RX_BCLK (input) S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 S14 I2S_TX_FS/ I2S_RX_FS (input) S15 S19 S15 S16 S16 I2S_TXD S17 S18 I2S_RXD Figure 20. I2S/SAI timing — slave modes 6.8.5.2 VLPR, VLPW, and VLPS mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes. K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 49

Peripheral operating requirements and behaviors Table 32. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 62.5 — ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 — ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ — 45 ns I2S_RX_FS output valid S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ 0 — ns I2S_RX_FS output invalid S7 I2S_TX_BCLK to I2S_TXD valid — 45 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns S9 I2S_RXD/I2S_RX_FS input setup before 45 — ns I2S_RX_BCLK S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ S4 I2S_RX_BCLK (output) S4 S5 S6 I2S_TX_FS/ I2S_RX_FS (output) S9 S10 I2S_TX_FS/ I2S_RX_FS (input) S7 S7 S8 S8 I2S_TXD S9 S10 I2S_RXD Figure 21. I2S/SAI timing — master modes Table 33. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 — ns Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 50 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors Table 33. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) (continued) Num. Characteristic Min. Max. Unit S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% MCLK period (input) S13 I2S_TX_FS/I2S_RX_FS input setup before 30 — ns I2S_TX_BCLK/I2S_RX_BCLK S14 I2S_TX_FS/I2S_RX_FS input hold after 3 — ns I2S_TX_BCLK/I2S_RX_BCLK S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 63 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_RX_BCLK 30 — ns S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 — 72 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear S11 S12 I2S_TX_BCLK/ S12 I2S_RX_BCLK (input) S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 S14 I2S_TX_FS/ I2S_RX_FS (input) S15 S19 S15 S16 S16 I2S_TXD S17 S18 I2S_RXD Figure 22. I2S/SAI timing — slave modes 6.9 Human-machine interfaces (HMI) 6.9.1 TSI electrical specifications Table 34. TSI electrical specifications Symbol Description Min. Typ. Max. Unit Notes V Operating voltage 1.71 — 3.6 V DDTSI C Target electrode capacitance range 1 20 500 pF 1 ELE Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 51

Peripheral operating requirements and behaviors Table 34. TSI electrical specifications (continued) Symbol Description Min. Typ. Max. Unit Notes f Reference oscillator frequency — 8 15 MHz 2, 3 REFmax f Electrode oscillator frequency — 1 1.8 MHz 2, 4 ELEmax C Internal reference capacitor — 1 — pF REF V Oscillator delta voltage — 500 — mV 2, 5 DELTA I Reference oscillator current source base current μA 2, 6 REF — 2 3 • 2 μA setting (REFCHRG = 0) • 32 μA setting (REFCHRG = 15) — 36 50 I Electrode oscillator current source base current μA 2, 7 ELE — 2 3 • 2 μA setting (EXTCHRG = 0) • 32 μA setting (EXTCHRG = 15) — 36 50 Pres5 Electrode capacitance measurement precision — 8.3333 38400 fF/count 8 Pres20 Electrode capacitance measurement precision — 8.3333 38400 fF/count 9 Pres100 Electrode capacitance measurement precision — 8.3333 38400 fF/count 10 MaxSens Maximum sensitivity 0.008 1.46 — fF/count 11 Res Resolution — — 16 bits T Response time @ 20 pF 8 15 25 μs 12 Con20 I Current added in run mode — 55 — μA TSI_RUN I Low power mode current adder — 1.3 2.5 μA 13 TSI_LP 1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. 2. Fixed external capacitance of 20 pF. 3. REFCHRG = 2, EXTCHRG=0. 4. REFCHRG = 0, EXTCHRG = 10. 5. V = 3.0 V. DD 6. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current. 7. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current. 8. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16. 9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16. 10. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16. 11. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity depends on the configuration used. The documented values are provided as examples calculated for a specific configuration of operating conditions using the following equation: (C * I )/( I * PS * NSCN) ref ext ref The typical value is calculated with the following configuration: Iext = 6 μA (EXTCHRG = 2), PS = 128, NSCN = 2, Iref = 16 μA (REFCHRG = 7), Cref = 1.0 pF The minimum value is calculated with the following configuration: Iext = 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 μA (REFCHRG = 15), Cref = 0.5 pF The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be measured by a single count. 12. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1 electrode, EXTCHRG = 7. 13. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window. K10 Sub-Family Data Sheet, Rev. 4 5/2012. 52 Freescale Semiconductor, Inc.

Dimensions 7 Dimensions 7.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to http://www.freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 32-pin QFN 98ARE10566D 8 Pinout 8.1 K10 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 32 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort QFN 1 VDD VDD VDD 2 VSS VSS VSS 3 PTE16 ADC0_SE4a ADC0_SE4a PTE16 SPI0_PCS0 UART2_TX FTM_CLKIN0 FTM0_FLT3 4 PTE17 ADC0_SE5a ADC0_SE5a PTE17 SPI0_SCK UART2_RX FTM_CLKIN1 LPTMR0_ALT3 5 PTE18 ADC0_SE6a ADC0_SE6a PTE18 SPI0_SOUT UART2_CTS_b I2C0_SDA 6 PTE19 ADC0_SE7a ADC0_SE7a PTE19 SPI0_SIN UART2_RTS_b I2C0_SCL 7 VDDA VDDA VDDA 8 VSSA VSSA VSSA 9 XTAL32 XTAL32 XTAL32 10 EXTAL32 EXTAL32 EXTAL32 11 VBAT VBAT VBAT 12 PTA0 JTAG_TCLK/ TSI0_CH1 PTA0 UART0_CTS_ FTM0_CH5 JTAG_TCLK/ EZP_CLK SWD_CLK/ b/ SWD_CLK EZP_CLK UART0_COL_b 13 PTA1 JTAG_TDI/ TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI EZP_DI K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 53

Pinout 32 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort QFN 14 PTA2 JTAG_TDO/ TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/ EZP_DO TRACE_SWO/ TRACE_SWO EZP_DO 15 PTA3 JTAG_TMS/ TSI0_CH4 PTA3 UART0_RTS_b FTM0_CH0 JTAG_TMS/ SWD_DIO SWD_DIO 16 PTA4/ NMI_b/ TSI0_CH5 PTA4/ FTM0_CH1 NMI_b EZP_CS_b LLWU_P3 EZP_CS_b LLWU_P3 17 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2 FTM_CLKIN0 18 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0 FTM_CLKIN1 LPTMR0_ALT1 19 RESET_b RESET_b RESET_b 20 PTB0/ ADC0_SE8/ ADC0_SE8/ PTB0/ I2C0_SCL FTM1_CH0 FTM1_QD_ LLWU_P5 TSI0_CH0 TSI0_CH0 LLWU_P5 PHA 21 PTB1 ADC0_SE9/ ADC0_SE9/ PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_ TSI0_CH6 TSI0_CH6 PHB 22 PTC1/ ADC0_SE15/ ADC0_SE15/ PTC1/ SPI0_PCS3 UART1_RTS_b FTM0_CH0 I2S0_TXD0 LLWU_P6 TSI0_CH14 TSI0_CH14 LLWU_P6 23 PTC2 ADC0_SE4b/ ADC0_SE4b/ PTC2 SPI0_PCS2 UART1_CTS_b FTM0_CH1 I2S0_TX_FS CMP1_IN0/ CMP1_IN0/ TSI0_CH15 TSI0_CH15 24 PTC3/ CMP1_IN1 CMP1_IN1 PTC3/ SPI0_PCS1 UART1_RX FTM0_CH2 I2S0_TX_BCLK LLWU_P7 LLWU_P7 25 PTC4/ DISABLED PTC4/ SPI0_PCS0 UART1_TX FTM0_CH3 CMP1_OUT LLWU_P8 LLWU_P8 26 PTC5/ DISABLED PTC5/ SPI0_SCK LPTMR0_ALT2 I2S0_RXD0 CMP0_OUT LLWU_P9 LLWU_P9 27 PTC6/ CMP0_IN0 CMP0_IN0 PTC6/ SPI0_SOUT PDB0_EXTRG I2S0_RX_BCLK I2S0_MCLK LLWU_P10 LLWU_P10 28 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN I2S0_RX_FS 29 PTD4/ DISABLED PTD4/ SPI0_PCS1 UART0_RTS_b FTM0_CH4 EWM_IN LLWU_P14 LLWU_P14 30 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_ FTM0_CH5 EWM_OUT_b b/ UART0_COL_b 31 PTD6/ ADC0_SE7b ADC0_SE7b PTD6/ SPI0_PCS3 UART0_RX FTM0_CH6 FTM0_FLT0 LLWU_P15 LLWU_P15 32 PTD7 DISABLED PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1 8.2 K10 Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. K10 Sub-Family Data Sheet, Rev. 4 5/2012. 54 Freescale Semiconductor, Inc.

Revision History 5 4 0 1 1 1 9 8 P P P P P _ _ _ _ _ U U U U U W W W W W L L L L L L L L L L 7 6/ 5 4/ 7 6/ 5/ 4/ D D D D C C C C T T T T T T T T P P P P P P P P 2 1 0 9 8 7 6 5 3 3 3 2 2 2 2 2 VDD 1 24 PTC3/LLWU_P7 VSS 2 23 PTC2 PTE16 3 22 PTC1/LLWU_P6 PTE17 4 21 PTB1 PTE18 5 20 PTB0/LLWU_P5 PTE19 6 19 RESET_b VDDA 7 18 PTA19 VSSA 8 17 PTA18 0 1 2 3 4 5 6 9 1 1 1 1 1 1 1 2 2 T 0 1 2 3 3 3 3 A A A A A P L L B T T T T _ A A V P P P P U T T W X X E L L 4/ A T P Figure 23. K10 32 QFN Pinout Diagram 9 Revision History The following table provides a revision history for this document. Table 35. Revision History Rev. No. Date Substantial Changes 2 2/2012 Initial public release 3 4/2012 • Replaced TBDs throughout. • Updated "Power mode transition operating behaviors" table. • Updated "Power consumption operating behaviors" table. • For "Diagram: Typical IDD_RUN operating behavior" section, added "VLPR mode supply current vs. core frequency" figure. • Updated "EMC radiated emissions operating behaviors" section. • Updated "Thermal operating requirements" section. • Updated "MCG specifications" table. • Updated "VREF full-range operating behaviors" table. • Updated "I2S/SAI Switching Specifications" section. • Updated "TSI electrical specifications" table. Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 55

Revision History Table 35. Revision History (continued) Rev. No. Date Substantial Changes 4 5/2012 • For the "32kHz oscillator frequency specifications", added specifications for an externally driven clock. • Renamed section "Flash current and power specfications" to section "Flash high voltage current behaviors" and improved the specifications. • For the "VREF full-range operating behaviors" table, removed the Ac (aging coefficient) specification. • Corrected the following DSPI switching specifications: tightened DS5, DS6, and DS7; relaxed DS11 and DS13. • Removed references to USB as non-applicable. • For the "TSI electrical specifications", changed and clarified the example calculations for the MaxSens specification. K10 Sub-Family Data Sheet, Rev. 4 5/2012. 56 Freescale Semiconductor, Inc.

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